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v3d: Use ldunif instructions for uniforms.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (vir_in_nonuniform_control_flow(c)) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
309 config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert((result.file == QFILE_TEMP &&
358 last_inst && last_inst == c->defs[result.index]));
359
360 if (dest->is_ssa) {
361 assert(chan < dest->ssa.num_components);
362
363 struct qreg *qregs;
364 struct hash_entry *entry =
365 _mesa_hash_table_search(c->def_ht, &dest->ssa);
366
367 if (entry)
368 qregs = entry->data;
369 else
370 qregs = ntq_init_ssa_def(c, &dest->ssa);
371
372 qregs[chan] = result;
373 } else {
374 nir_register *reg = dest->reg.reg;
375 assert(dest->reg.base_offset == 0);
376 assert(reg->num_array_elems == 0);
377 struct hash_entry *entry =
378 _mesa_hash_table_search(c->def_ht, reg);
379 struct qreg *qregs = entry->data;
380
381 /* Insert a MOV if the source wasn't an SSA def in the
382 * previous instruction.
383 */
384 if ((vir_in_nonuniform_control_flow(c) &&
385 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 }
409 }
410 }
411
412 struct qreg
413 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
414 {
415 struct hash_entry *entry;
416 if (src.is_ssa) {
417 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
418 assert(i < src.ssa->num_components);
419 } else {
420 nir_register *reg = src.reg.reg;
421 entry = _mesa_hash_table_search(c->def_ht, reg);
422 assert(reg->num_array_elems == 0);
423 assert(src.reg.base_offset == 0);
424 assert(i < reg->num_components);
425 }
426
427 struct qreg *qregs = entry->data;
428 return qregs[i];
429 }
430
431 static struct qreg
432 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
433 unsigned src)
434 {
435 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
436 unsigned chan = ffs(instr->dest.write_mask) - 1;
437 struct qreg r = ntq_get_src(c, instr->src[src].src,
438 instr->src[src].swizzle[chan]);
439
440 assert(!instr->src[src].abs);
441 assert(!instr->src[src].negate);
442
443 return r;
444 };
445
446 static struct qreg
447 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
448 {
449 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
450 }
451
452 static void
453 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
454 {
455 unsigned unit = instr->texture_index;
456 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
457 int dest_size = nir_tex_instr_dest_size(instr);
458
459 struct qreg lod = c->undef;
460 if (lod_index != -1)
461 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
462
463 for (int i = 0; i < dest_size; i++) {
464 assert(i < 3);
465 enum quniform_contents contents;
466
467 if (instr->is_array && i == dest_size - 1)
468 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
469 else
470 contents = QUNIFORM_TEXTURE_WIDTH + i;
471
472 struct qreg size = vir_uniform(c, contents, unit);
473
474 switch (instr->sampler_dim) {
475 case GLSL_SAMPLER_DIM_1D:
476 case GLSL_SAMPLER_DIM_2D:
477 case GLSL_SAMPLER_DIM_MS:
478 case GLSL_SAMPLER_DIM_3D:
479 case GLSL_SAMPLER_DIM_CUBE:
480 /* Don't minify the array size. */
481 if (!(instr->is_array && i == dest_size - 1)) {
482 size = ntq_minify(c, size, lod);
483 }
484 break;
485
486 case GLSL_SAMPLER_DIM_RECT:
487 /* There's no LOD field for rects */
488 break;
489
490 default:
491 unreachable("Bad sampler type");
492 }
493
494 ntq_store_dest(c, &instr->dest, i, size);
495 }
496 }
497
498 static void
499 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
500 {
501 unsigned unit = instr->texture_index;
502
503 /* Since each texture sampling op requires uploading uniforms to
504 * reference the texture, there's no HW support for texture size and
505 * you just upload uniforms containing the size.
506 */
507 switch (instr->op) {
508 case nir_texop_query_levels:
509 ntq_store_dest(c, &instr->dest, 0,
510 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
511 return;
512 case nir_texop_txs:
513 ntq_emit_txs(c, instr);
514 return;
515 default:
516 break;
517 }
518
519 if (c->devinfo->ver >= 40)
520 v3d40_vir_emit_tex(c, instr);
521 else
522 v3d33_vir_emit_tex(c, instr);
523 }
524
525 static struct qreg
526 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
527 {
528 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
529 if (is_cos)
530 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
531
532 struct qreg periods = vir_FROUND(c, input);
533 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
534 return vir_XOR(c, sin_output, vir_SHL(c,
535 vir_FTOIN(c, periods),
536 vir_uniform_ui(c, -1)));
537 }
538
539 static struct qreg
540 ntq_fsign(struct v3d_compile *c, struct qreg src)
541 {
542 struct qreg t = vir_get_temp(c);
543
544 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
545 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
546 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
547 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
548 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
549 return vir_MOV(c, t);
550 }
551
552 static void
553 emit_fragcoord_input(struct v3d_compile *c, int attr)
554 {
555 c->inputs[attr * 4 + 0] = vir_FXCD(c);
556 c->inputs[attr * 4 + 1] = vir_FYCD(c);
557 c->inputs[attr * 4 + 2] = c->payload_z;
558 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
559 }
560
561 static struct qreg
562 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
563 uint8_t swizzle, int array_index)
564 {
565 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
566 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
567
568 struct qreg vary;
569 if (c->devinfo->ver >= 41) {
570 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
571 c->undef, c->undef);
572 ldvary->qpu.sig.ldvary = true;
573 vary = vir_emit_def(c, ldvary);
574 } else {
575 vir_NOP(c)->qpu.sig.ldvary = true;
576 vary = r3;
577 }
578
579 /* For gl_PointCoord input or distance along a line, we'll be called
580 * with no nir_variable, and we don't count toward VPM size so we
581 * don't track an input slot.
582 */
583 if (!var) {
584 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
585 }
586
587 int i = c->num_inputs++;
588 c->input_slots[i] =
589 v3d_slot_from_slot_and_component(var->data.location +
590 array_index, swizzle);
591
592 switch (var->data.interpolation) {
593 case INTERP_MODE_NONE:
594 /* If a gl_FrontColor or gl_BackColor input has no interp
595 * qualifier, then if we're using glShadeModel(GL_FLAT) it
596 * needs to be flat shaded.
597 */
598 switch (var->data.location + array_index) {
599 case VARYING_SLOT_COL0:
600 case VARYING_SLOT_COL1:
601 case VARYING_SLOT_BFC0:
602 case VARYING_SLOT_BFC1:
603 if (c->fs_key->shade_model_flat) {
604 BITSET_SET(c->flat_shade_flags, i);
605 vir_MOV_dest(c, c->undef, vary);
606 return vir_MOV(c, r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary,
609 c->payload_w), r5);
610 }
611 default:
612 break;
613 }
614 /* FALLTHROUGH */
615 case INTERP_MODE_SMOOTH:
616 if (var->data.centroid) {
617 BITSET_SET(c->centroid_flags, i);
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w_centroid), r5);
620 } else {
621 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
622 }
623 case INTERP_MODE_NOPERSPECTIVE:
624 BITSET_SET(c->noperspective_flags, i);
625 return vir_FADD(c, vir_MOV(c, vary), r5);
626 case INTERP_MODE_FLAT:
627 BITSET_SET(c->flat_shade_flags, i);
628 vir_MOV_dest(c, c->undef, vary);
629 return vir_MOV(c, r5);
630 default:
631 unreachable("Bad interp mode");
632 }
633 }
634
635 static void
636 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
637 int array_index)
638 {
639 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
640 int chan = var->data.location_frac + i;
641 c->inputs[attr * 4 + chan] =
642 emit_fragment_varying(c, var, chan, array_index);
643 }
644 }
645
646 static void
647 add_output(struct v3d_compile *c,
648 uint32_t decl_offset,
649 uint8_t slot,
650 uint8_t swizzle)
651 {
652 uint32_t old_array_size = c->outputs_array_size;
653 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
654 decl_offset + 1);
655
656 if (old_array_size != c->outputs_array_size) {
657 c->output_slots = reralloc(c,
658 c->output_slots,
659 struct v3d_varying_slot,
660 c->outputs_array_size);
661 }
662
663 c->output_slots[decl_offset] =
664 v3d_slot_from_slot_and_component(slot, swizzle);
665 }
666
667 static void
668 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
669 {
670 unsigned array_id = c->num_ubo_ranges++;
671 if (array_id >= c->ubo_ranges_array_size) {
672 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
673 array_id + 1);
674 c->ubo_ranges = reralloc(c, c->ubo_ranges,
675 struct v3d_ubo_range,
676 c->ubo_ranges_array_size);
677 c->ubo_range_used = reralloc(c, c->ubo_range_used,
678 bool,
679 c->ubo_ranges_array_size);
680 }
681
682 c->ubo_ranges[array_id].dst_offset = 0;
683 c->ubo_ranges[array_id].src_offset = start;
684 c->ubo_ranges[array_id].size = size;
685 c->ubo_range_used[array_id] = false;
686 }
687
688 /**
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
692 */
693 static bool
694 ntq_emit_comparison(struct v3d_compile *c,
695 nir_alu_instr *compare_instr,
696 enum v3d_qpu_cond *out_cond)
697 {
698 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
699 struct qreg src1;
700 if (nir_op_infos[compare_instr->op].num_inputs > 1)
701 src1 = ntq_get_alu_src(c, compare_instr, 1);
702 bool cond_invert = false;
703 struct qreg nop = vir_nop_reg();
704
705 switch (compare_instr->op) {
706 case nir_op_feq32:
707 case nir_op_seq:
708 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
709 break;
710 case nir_op_ieq32:
711 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
712 break;
713
714 case nir_op_fne32:
715 case nir_op_sne:
716 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719 case nir_op_ine32:
720 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
721 cond_invert = true;
722 break;
723
724 case nir_op_fge32:
725 case nir_op_sge:
726 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ige32:
729 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732 case nir_op_uge32:
733 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
734 cond_invert = true;
735 break;
736
737 case nir_op_slt:
738 case nir_op_flt32:
739 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
740 break;
741 case nir_op_ilt32:
742 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
743 break;
744 case nir_op_ult32:
745 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
746 break;
747
748 case nir_op_i2b32:
749 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
750 cond_invert = true;
751 break;
752
753 case nir_op_f2b32:
754 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
755 cond_invert = true;
756 break;
757
758 default:
759 return false;
760 }
761
762 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
763
764 return true;
765 }
766
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
769 */
770 static struct nir_alu_instr *
771 ntq_get_alu_parent(nir_src src)
772 {
773 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
774 return NULL;
775 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
776 if (!instr)
777 return NULL;
778
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
781 * src.
782 */
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 if (!instr->src[i].src.is_ssa)
785 return NULL;
786 }
787
788 return instr;
789 }
790
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
794 {
795 nir_alu_instr *compare = ntq_get_alu_parent(src);
796 if (!compare)
797 goto out;
798
799 enum v3d_qpu_cond cond;
800 if (ntq_emit_comparison(c, compare, &cond))
801 return cond;
802
803 out:
804 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
805 V3D_QPU_PF_PUSHZ);
806 return V3D_QPU_COND_IFNA;
807 }
808
809 static void
810 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
811 {
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr->dest.saturate);
814
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
818 */
819 if (instr->op == nir_op_vec2 ||
820 instr->op == nir_op_vec3 ||
821 instr->op == nir_op_vec4) {
822 struct qreg srcs[4];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
824 srcs[i] = ntq_get_src(c, instr->src[i].src,
825 instr->src[i].swizzle[0]);
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
827 ntq_store_dest(c, &instr->dest.dest, i,
828 vir_MOV(c, srcs[i]));
829 return;
830 }
831
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src[nir_op_infos[instr->op].num_inputs];
834 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
835 src[i] = ntq_get_alu_src(c, instr, i);
836 }
837
838 struct qreg result;
839
840 switch (instr->op) {
841 case nir_op_fmov:
842 case nir_op_imov:
843 result = vir_MOV(c, src[0]);
844 break;
845
846 case nir_op_fneg:
847 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
848 break;
849 case nir_op_ineg:
850 result = vir_NEG(c, src[0]);
851 break;
852
853 case nir_op_fmul:
854 result = vir_FMUL(c, src[0], src[1]);
855 break;
856 case nir_op_fadd:
857 result = vir_FADD(c, src[0], src[1]);
858 break;
859 case nir_op_fsub:
860 result = vir_FSUB(c, src[0], src[1]);
861 break;
862 case nir_op_fmin:
863 result = vir_FMIN(c, src[0], src[1]);
864 break;
865 case nir_op_fmax:
866 result = vir_FMAX(c, src[0], src[1]);
867 break;
868
869 case nir_op_f2i32: {
870 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
871 if (src0_alu && src0_alu->op == nir_op_fround_even) {
872 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
873 } else {
874 result = vir_FTOIZ(c, src[0]);
875 }
876 break;
877 }
878
879 case nir_op_f2u32:
880 result = vir_FTOUZ(c, src[0]);
881 break;
882 case nir_op_i2f32:
883 result = vir_ITOF(c, src[0]);
884 break;
885 case nir_op_u2f32:
886 result = vir_UTOF(c, src[0]);
887 break;
888 case nir_op_b2f32:
889 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
890 break;
891 case nir_op_b2i32:
892 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
893 break;
894
895 case nir_op_iadd:
896 result = vir_ADD(c, src[0], src[1]);
897 break;
898 case nir_op_ushr:
899 result = vir_SHR(c, src[0], src[1]);
900 break;
901 case nir_op_isub:
902 result = vir_SUB(c, src[0], src[1]);
903 break;
904 case nir_op_ishr:
905 result = vir_ASR(c, src[0], src[1]);
906 break;
907 case nir_op_ishl:
908 result = vir_SHL(c, src[0], src[1]);
909 break;
910 case nir_op_imin:
911 result = vir_MIN(c, src[0], src[1]);
912 break;
913 case nir_op_umin:
914 result = vir_UMIN(c, src[0], src[1]);
915 break;
916 case nir_op_imax:
917 result = vir_MAX(c, src[0], src[1]);
918 break;
919 case nir_op_umax:
920 result = vir_UMAX(c, src[0], src[1]);
921 break;
922 case nir_op_iand:
923 result = vir_AND(c, src[0], src[1]);
924 break;
925 case nir_op_ior:
926 result = vir_OR(c, src[0], src[1]);
927 break;
928 case nir_op_ixor:
929 result = vir_XOR(c, src[0], src[1]);
930 break;
931 case nir_op_inot:
932 result = vir_NOT(c, src[0]);
933 break;
934
935 case nir_op_ufind_msb:
936 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
937 break;
938
939 case nir_op_imul:
940 result = vir_UMUL(c, src[0], src[1]);
941 break;
942
943 case nir_op_seq:
944 case nir_op_sne:
945 case nir_op_sge:
946 case nir_op_slt: {
947 enum v3d_qpu_cond cond;
948 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
949 assert(ok);
950 result = vir_MOV(c, vir_SEL(c, cond,
951 vir_uniform_f(c, 1.0),
952 vir_uniform_f(c, 0.0)));
953 break;
954 }
955
956 case nir_op_i2b32:
957 case nir_op_f2b32:
958 case nir_op_feq32:
959 case nir_op_fne32:
960 case nir_op_fge32:
961 case nir_op_flt32:
962 case nir_op_ieq32:
963 case nir_op_ine32:
964 case nir_op_ige32:
965 case nir_op_uge32:
966 case nir_op_ilt32:
967 case nir_op_ult32: {
968 enum v3d_qpu_cond cond;
969 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
970 assert(ok);
971 result = vir_MOV(c, vir_SEL(c, cond,
972 vir_uniform_ui(c, ~0),
973 vir_uniform_ui(c, 0)));
974 break;
975 }
976
977 case nir_op_b32csel:
978 result = vir_MOV(c,
979 vir_SEL(c,
980 ntq_emit_bool_to_cond(c, instr->src[0].src),
981 src[1], src[2]));
982 break;
983
984 case nir_op_fcsel:
985 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
986 V3D_QPU_PF_PUSHZ);
987 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
988 src[1], src[2]));
989 break;
990
991 case nir_op_frcp:
992 result = vir_RECIP(c, src[0]);
993 break;
994 case nir_op_frsq:
995 result = vir_RSQRT(c, src[0]);
996 break;
997 case nir_op_fexp2:
998 result = vir_EXP(c, src[0]);
999 break;
1000 case nir_op_flog2:
1001 result = vir_LOG(c, src[0]);
1002 break;
1003
1004 case nir_op_fceil:
1005 result = vir_FCEIL(c, src[0]);
1006 break;
1007 case nir_op_ffloor:
1008 result = vir_FFLOOR(c, src[0]);
1009 break;
1010 case nir_op_fround_even:
1011 result = vir_FROUND(c, src[0]);
1012 break;
1013 case nir_op_ftrunc:
1014 result = vir_FTRUNC(c, src[0]);
1015 break;
1016
1017 case nir_op_fsin:
1018 result = ntq_fsincos(c, src[0], false);
1019 break;
1020 case nir_op_fcos:
1021 result = ntq_fsincos(c, src[0], true);
1022 break;
1023
1024 case nir_op_fsign:
1025 result = ntq_fsign(c, src[0]);
1026 break;
1027
1028 case nir_op_fabs: {
1029 result = vir_FMOV(c, src[0]);
1030 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1031 break;
1032 }
1033
1034 case nir_op_iabs:
1035 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1036 break;
1037
1038 case nir_op_fddx:
1039 case nir_op_fddx_coarse:
1040 case nir_op_fddx_fine:
1041 result = vir_FDX(c, src[0]);
1042 break;
1043
1044 case nir_op_fddy:
1045 case nir_op_fddy_coarse:
1046 case nir_op_fddy_fine:
1047 result = vir_FDY(c, src[0]);
1048 break;
1049
1050 case nir_op_uadd_carry:
1051 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1052 V3D_QPU_PF_PUSHC);
1053 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1054 vir_uniform_ui(c, ~0),
1055 vir_uniform_ui(c, 0)));
1056 break;
1057
1058 case nir_op_pack_half_2x16_split:
1059 result = vir_VFPACK(c, src[0], src[1]);
1060 break;
1061
1062 case nir_op_unpack_half_2x16_split_x:
1063 result = vir_FMOV(c, src[0]);
1064 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1065 break;
1066
1067 case nir_op_unpack_half_2x16_split_y:
1068 result = vir_FMOV(c, src[0]);
1069 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1070 break;
1071
1072 default:
1073 fprintf(stderr, "unknown NIR ALU inst: ");
1074 nir_print_instr(&instr->instr, stderr);
1075 fprintf(stderr, "\n");
1076 abort();
1077 }
1078
1079 /* We have a scalar result, so the instruction should only have a
1080 * single channel written to.
1081 */
1082 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1083 ntq_store_dest(c, &instr->dest.dest,
1084 ffs(instr->dest.write_mask) - 1, result);
1085 }
1086
1087 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1088 * specifier. They come from a register that's preloaded with 0xffffffff
1089 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1090 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1091 */
1092 #define TLB_TYPE_F16_COLOR (3 << 6)
1093 #define TLB_TYPE_I32_COLOR (1 << 6)
1094 #define TLB_TYPE_F32_COLOR (0 << 6)
1095 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1096 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1097 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1098 #define TLB_F16_SWAP_HI_LO (1 << 1)
1099 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1100 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1101 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1102
1103 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1104 * flag is set.
1105 */
1106 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1107 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1108 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1109 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1110 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1111
1112 /* Stencil is a single 32-bit write. */
1113 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1114
1115 static void
1116 emit_frag_end(struct v3d_compile *c)
1117 {
1118 /* XXX
1119 if (c->output_sample_mask_index != -1) {
1120 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1121 }
1122 */
1123
1124 bool has_any_tlb_color_write = false;
1125 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1126 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1127 has_any_tlb_color_write = true;
1128 }
1129
1130 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1131 struct nir_variable *var = c->output_color_var[0];
1132 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1133
1134 vir_SETMSF_dest(c, vir_nop_reg(),
1135 vir_AND(c,
1136 vir_MSF(c),
1137 vir_FTOC(c, color[3])));
1138 }
1139
1140 if (c->output_position_index != -1) {
1141 struct qinst *inst = vir_MOV_dest(c,
1142 vir_reg(QFILE_TLBU, 0),
1143 c->outputs[c->output_position_index]);
1144 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1145
1146 if (c->devinfo->ver >= 42) {
1147 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1148 TLB_SAMPLE_MODE_PER_PIXEL);
1149 } else
1150 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1151
1152 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1153 tlb_specifier |
1154 0xffffff00);
1155 c->writes_z = true;
1156 } else if (c->s->info.fs.uses_discard ||
1157 !c->s->info.fs.early_fragment_tests ||
1158 c->fs_key->sample_alpha_to_coverage ||
1159 !has_any_tlb_color_write) {
1160 /* Emit passthrough Z if it needed to be delayed until shader
1161 * end due to potential discards.
1162 *
1163 * Since (single-threaded) fragment shaders always need a TLB
1164 * write, emit passthrouh Z if we didn't have any color
1165 * buffers and flag us as potentially discarding, so that we
1166 * can use Z as the TLB write.
1167 */
1168 c->s->info.fs.uses_discard = true;
1169
1170 struct qinst *inst = vir_MOV_dest(c,
1171 vir_reg(QFILE_TLBU, 0),
1172 vir_nop_reg());
1173 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1174
1175 if (c->devinfo->ver >= 42) {
1176 /* The spec says the PER_PIXEL flag is ignored for
1177 * invariant writes, but the simulator demands it.
1178 */
1179 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1180 TLB_SAMPLE_MODE_PER_PIXEL);
1181 } else {
1182 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1183 }
1184
1185 inst->uniform = vir_get_uniform_index(c,
1186 QUNIFORM_CONSTANT,
1187 tlb_specifier |
1188 0xffffff00);
1189 c->writes_z = true;
1190 }
1191
1192 /* XXX: Performance improvement: Merge Z write and color writes TLB
1193 * uniform setup
1194 */
1195
1196 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1197 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1198 continue;
1199
1200 nir_variable *var = c->output_color_var[rt];
1201 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1202 int num_components = glsl_get_vector_elements(var->type);
1203 uint32_t conf = 0xffffff00;
1204 struct qinst *inst;
1205
1206 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1207 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1208
1209 if (c->fs_key->swap_color_rb & (1 << rt))
1210 num_components = MAX2(num_components, 3);
1211
1212 assert(num_components != 0);
1213 switch (glsl_get_base_type(var->type)) {
1214 case GLSL_TYPE_UINT:
1215 case GLSL_TYPE_INT:
1216 /* The F32 vs I32 distinction was dropped in 4.2. */
1217 if (c->devinfo->ver < 42)
1218 conf |= TLB_TYPE_I32_COLOR;
1219 else
1220 conf |= TLB_TYPE_F32_COLOR;
1221 conf |= ((num_components - 1) <<
1222 TLB_VEC_SIZE_MINUS_1_SHIFT);
1223
1224 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1225 inst->uniform = vir_get_uniform_index(c,
1226 QUNIFORM_CONSTANT,
1227 conf);
1228
1229 for (int i = 1; i < num_components; i++) {
1230 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1231 color[i]);
1232 }
1233 break;
1234
1235 default: {
1236 struct qreg r = color[0];
1237 struct qreg g = color[1];
1238 struct qreg b = color[2];
1239 struct qreg a = color[3];
1240
1241 if (c->fs_key->f32_color_rb & (1 << rt)) {
1242 conf |= TLB_TYPE_F32_COLOR;
1243 conf |= ((num_components - 1) <<
1244 TLB_VEC_SIZE_MINUS_1_SHIFT);
1245 } else {
1246 conf |= TLB_TYPE_F16_COLOR;
1247 conf |= TLB_F16_SWAP_HI_LO;
1248 if (num_components >= 3)
1249 conf |= TLB_VEC_SIZE_4_F16;
1250 else
1251 conf |= TLB_VEC_SIZE_2_F16;
1252 }
1253
1254 if (c->fs_key->swap_color_rb & (1 << rt)) {
1255 r = color[2];
1256 b = color[0];
1257 }
1258
1259 if (c->fs_key->sample_alpha_to_one)
1260 a = vir_uniform_f(c, 1.0);
1261
1262 if (c->fs_key->f32_color_rb & (1 << rt)) {
1263 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1264 inst->uniform = vir_get_uniform_index(c,
1265 QUNIFORM_CONSTANT,
1266 conf);
1267
1268 if (num_components >= 2)
1269 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1270 if (num_components >= 3)
1271 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1272 if (num_components >= 4)
1273 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1274 } else {
1275 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1276 if (conf != ~0) {
1277 inst->dst.file = QFILE_TLBU;
1278 inst->uniform = vir_get_uniform_index(c,
1279 QUNIFORM_CONSTANT,
1280 conf);
1281 }
1282
1283 if (num_components >= 3)
1284 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1285 }
1286 break;
1287 }
1288 }
1289 }
1290 }
1291
1292 static void
1293 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1294 {
1295 if (c->devinfo->ver >= 40) {
1296 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1297 } else {
1298 /* XXX: v3d33_vir_vpm_write_setup(c); */
1299 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1300 }
1301 }
1302
1303 static void
1304 emit_vert_end(struct v3d_compile *c)
1305 {
1306 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1307 */
1308 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1309 vir_VPMWT(c);
1310 }
1311
1312 void
1313 v3d_optimize_nir(struct nir_shader *s)
1314 {
1315 bool progress;
1316
1317 do {
1318 progress = false;
1319
1320 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1321 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1322 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1323 NIR_PASS(progress, s, nir_copy_prop);
1324 NIR_PASS(progress, s, nir_opt_remove_phis);
1325 NIR_PASS(progress, s, nir_opt_dce);
1326 NIR_PASS(progress, s, nir_opt_dead_cf);
1327 NIR_PASS(progress, s, nir_opt_cse);
1328 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1329 NIR_PASS(progress, s, nir_opt_algebraic);
1330 NIR_PASS(progress, s, nir_opt_constant_folding);
1331 NIR_PASS(progress, s, nir_opt_undef);
1332 } while (progress);
1333
1334 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1335 }
1336
1337 static int
1338 driver_location_compare(const void *in_a, const void *in_b)
1339 {
1340 const nir_variable *const *a = in_a;
1341 const nir_variable *const *b = in_b;
1342
1343 return (*a)->data.driver_location - (*b)->data.driver_location;
1344 }
1345
1346 static struct qreg
1347 ntq_emit_vpm_read(struct v3d_compile *c,
1348 uint32_t *num_components_queued,
1349 uint32_t *remaining,
1350 uint32_t vpm_index)
1351 {
1352 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1353
1354 if (c->devinfo->ver >= 40 ) {
1355 return vir_LDVPMV_IN(c,
1356 vir_uniform_ui(c,
1357 (*num_components_queued)++));
1358 }
1359
1360 if (*num_components_queued != 0) {
1361 (*num_components_queued)--;
1362 return vir_MOV(c, vpm);
1363 }
1364
1365 uint32_t num_components = MIN2(*remaining, 32);
1366
1367 v3d33_vir_vpm_read_setup(c, num_components);
1368
1369 *num_components_queued = num_components - 1;
1370 *remaining -= num_components;
1371
1372 return vir_MOV(c, vpm);
1373 }
1374
1375 static void
1376 ntq_setup_vpm_inputs(struct v3d_compile *c)
1377 {
1378 /* Figure out how many components of each vertex attribute the shader
1379 * uses. Each variable should have been split to individual
1380 * components and unused ones DCEed. The vertex fetcher will load
1381 * from the start of the attribute to the number of components we
1382 * declare we need in c->vattr_sizes[].
1383 */
1384 nir_foreach_variable(var, &c->s->inputs) {
1385 /* No VS attribute array support. */
1386 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1387
1388 unsigned loc = var->data.driver_location;
1389 int start_component = var->data.location_frac;
1390 int num_components = glsl_get_components(var->type);
1391
1392 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1393 start_component + num_components);
1394 }
1395
1396 unsigned num_components = 0;
1397 uint32_t vpm_components_queued = 0;
1398 bool uses_iid = c->s->info.system_values_read &
1399 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1400 bool uses_vid = c->s->info.system_values_read &
1401 (1ull << SYSTEM_VALUE_VERTEX_ID);
1402 num_components += uses_iid;
1403 num_components += uses_vid;
1404
1405 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1406 num_components += c->vattr_sizes[i];
1407
1408 if (uses_iid) {
1409 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1410 &num_components, ~0);
1411 }
1412
1413 if (uses_vid) {
1414 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1415 &num_components, ~0);
1416 }
1417
1418 /* The actual loads will happen directly in nir_intrinsic_load_input
1419 * on newer versions.
1420 */
1421 if (c->devinfo->ver >= 40)
1422 return;
1423
1424 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1425 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1426 (loc + 1) * 4);
1427
1428 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1429 c->inputs[loc * 4 + i] =
1430 ntq_emit_vpm_read(c,
1431 &vpm_components_queued,
1432 &num_components,
1433 loc * 4 + i);
1434
1435 }
1436 }
1437
1438 if (c->devinfo->ver >= 40) {
1439 assert(vpm_components_queued == num_components);
1440 } else {
1441 assert(vpm_components_queued == 0);
1442 assert(num_components == 0);
1443 }
1444 }
1445
1446 static void
1447 ntq_setup_fs_inputs(struct v3d_compile *c)
1448 {
1449 unsigned num_entries = 0;
1450 unsigned num_components = 0;
1451 nir_foreach_variable(var, &c->s->inputs) {
1452 num_entries++;
1453 num_components += glsl_get_components(var->type);
1454 }
1455
1456 nir_variable *vars[num_entries];
1457
1458 unsigned i = 0;
1459 nir_foreach_variable(var, &c->s->inputs)
1460 vars[i++] = var;
1461
1462 /* Sort the variables so that we emit the input setup in
1463 * driver_location order. This is required for VPM reads, whose data
1464 * is fetched into the VPM in driver_location (TGSI register index)
1465 * order.
1466 */
1467 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1468
1469 for (unsigned i = 0; i < num_entries; i++) {
1470 nir_variable *var = vars[i];
1471 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1472 unsigned loc = var->data.driver_location;
1473
1474 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1475 (loc + array_len) * 4);
1476
1477 if (var->data.location == VARYING_SLOT_POS) {
1478 emit_fragcoord_input(c, loc);
1479 } else if (var->data.location == VARYING_SLOT_PNTC ||
1480 (var->data.location >= VARYING_SLOT_VAR0 &&
1481 (c->fs_key->point_sprite_mask &
1482 (1 << (var->data.location -
1483 VARYING_SLOT_VAR0))))) {
1484 c->inputs[loc * 4 + 0] = c->point_x;
1485 c->inputs[loc * 4 + 1] = c->point_y;
1486 } else {
1487 for (int j = 0; j < array_len; j++)
1488 emit_fragment_input(c, loc + j, var, j);
1489 }
1490 }
1491 }
1492
1493 static void
1494 ntq_setup_outputs(struct v3d_compile *c)
1495 {
1496 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1497 return;
1498
1499 nir_foreach_variable(var, &c->s->outputs) {
1500 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1501 unsigned loc = var->data.driver_location * 4;
1502
1503 assert(array_len == 1);
1504 (void)array_len;
1505
1506 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1507 add_output(c, loc + var->data.location_frac + i,
1508 var->data.location,
1509 var->data.location_frac + i);
1510 }
1511
1512 switch (var->data.location) {
1513 case FRAG_RESULT_COLOR:
1514 c->output_color_var[0] = var;
1515 c->output_color_var[1] = var;
1516 c->output_color_var[2] = var;
1517 c->output_color_var[3] = var;
1518 break;
1519 case FRAG_RESULT_DATA0:
1520 case FRAG_RESULT_DATA1:
1521 case FRAG_RESULT_DATA2:
1522 case FRAG_RESULT_DATA3:
1523 c->output_color_var[var->data.location -
1524 FRAG_RESULT_DATA0] = var;
1525 break;
1526 case FRAG_RESULT_DEPTH:
1527 c->output_position_index = loc;
1528 break;
1529 case FRAG_RESULT_SAMPLE_MASK:
1530 c->output_sample_mask_index = loc;
1531 break;
1532 }
1533 }
1534 }
1535
1536 static void
1537 ntq_setup_uniforms(struct v3d_compile *c)
1538 {
1539 nir_foreach_variable(var, &c->s->uniforms) {
1540 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1541 false);
1542 unsigned vec4_size = 4 * sizeof(float);
1543
1544 if (var->data.mode != nir_var_uniform)
1545 continue;
1546
1547 declare_uniform_range(c, var->data.driver_location * vec4_size,
1548 vec4_count * vec4_size);
1549
1550 }
1551 }
1552
1553 /**
1554 * Sets up the mapping from nir_register to struct qreg *.
1555 *
1556 * Each nir_register gets a struct qreg per 32-bit component being stored.
1557 */
1558 static void
1559 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1560 {
1561 foreach_list_typed(nir_register, nir_reg, node, list) {
1562 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1563 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1564 array_len *
1565 nir_reg->num_components);
1566
1567 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1568
1569 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1570 qregs[i] = vir_get_temp(c);
1571 }
1572 }
1573
1574 static void
1575 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1576 {
1577 /* XXX perf: Experiment with using immediate loads to avoid having
1578 * these end up in the uniform stream. Watch out for breaking the
1579 * small immediates optimization in the process!
1580 */
1581 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1582 for (int i = 0; i < instr->def.num_components; i++)
1583 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1584
1585 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1586 }
1587
1588 static void
1589 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1590 {
1591 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1592
1593 /* VIR needs there to be *some* value, so pick 0 (same as for
1594 * ntq_setup_registers().
1595 */
1596 for (int i = 0; i < instr->def.num_components; i++)
1597 qregs[i] = vir_uniform_ui(c, 0);
1598 }
1599
1600 static void
1601 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1602 {
1603 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1604 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1605 unsigned image_index = var->data.driver_location;
1606 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1607 bool is_array = glsl_sampler_type_is_array(sampler_type);
1608
1609 ntq_store_dest(c, &instr->dest, 0,
1610 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1611 if (instr->num_components > 1) {
1612 ntq_store_dest(c, &instr->dest, 1,
1613 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1614 image_index));
1615 }
1616 if (instr->num_components > 2) {
1617 ntq_store_dest(c, &instr->dest, 2,
1618 vir_uniform(c,
1619 is_array ?
1620 QUNIFORM_IMAGE_ARRAY_SIZE :
1621 QUNIFORM_IMAGE_DEPTH,
1622 image_index));
1623 }
1624 }
1625
1626 static void
1627 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1628 {
1629 unsigned offset;
1630
1631 switch (instr->intrinsic) {
1632 case nir_intrinsic_load_uniform:
1633 if (nir_src_is_const(instr->src[0])) {
1634 int offset = (nir_intrinsic_base(instr) +
1635 nir_src_as_uint(instr->src[0]));
1636 assert(offset % 4 == 0);
1637 /* We need dwords */
1638 offset = offset / 4;
1639 for (int i = 0; i < instr->num_components; i++) {
1640 ntq_store_dest(c, &instr->dest, i,
1641 vir_uniform(c, QUNIFORM_UNIFORM,
1642 offset + i));
1643 }
1644 } else {
1645 ntq_emit_tmu_general(c, instr, false);
1646 }
1647 break;
1648
1649 case nir_intrinsic_load_ubo:
1650 ntq_emit_tmu_general(c, instr, false);
1651 break;
1652
1653 case nir_intrinsic_ssbo_atomic_add:
1654 case nir_intrinsic_ssbo_atomic_imin:
1655 case nir_intrinsic_ssbo_atomic_umin:
1656 case nir_intrinsic_ssbo_atomic_imax:
1657 case nir_intrinsic_ssbo_atomic_umax:
1658 case nir_intrinsic_ssbo_atomic_and:
1659 case nir_intrinsic_ssbo_atomic_or:
1660 case nir_intrinsic_ssbo_atomic_xor:
1661 case nir_intrinsic_ssbo_atomic_exchange:
1662 case nir_intrinsic_ssbo_atomic_comp_swap:
1663 case nir_intrinsic_load_ssbo:
1664 case nir_intrinsic_store_ssbo:
1665 ntq_emit_tmu_general(c, instr, false);
1666 break;
1667
1668 case nir_intrinsic_shared_atomic_add:
1669 case nir_intrinsic_shared_atomic_imin:
1670 case nir_intrinsic_shared_atomic_umin:
1671 case nir_intrinsic_shared_atomic_imax:
1672 case nir_intrinsic_shared_atomic_umax:
1673 case nir_intrinsic_shared_atomic_and:
1674 case nir_intrinsic_shared_atomic_or:
1675 case nir_intrinsic_shared_atomic_xor:
1676 case nir_intrinsic_shared_atomic_exchange:
1677 case nir_intrinsic_shared_atomic_comp_swap:
1678 case nir_intrinsic_load_shared:
1679 case nir_intrinsic_store_shared:
1680 ntq_emit_tmu_general(c, instr, true);
1681 break;
1682
1683 case nir_intrinsic_image_deref_load:
1684 case nir_intrinsic_image_deref_store:
1685 case nir_intrinsic_image_deref_atomic_add:
1686 case nir_intrinsic_image_deref_atomic_min:
1687 case nir_intrinsic_image_deref_atomic_max:
1688 case nir_intrinsic_image_deref_atomic_and:
1689 case nir_intrinsic_image_deref_atomic_or:
1690 case nir_intrinsic_image_deref_atomic_xor:
1691 case nir_intrinsic_image_deref_atomic_exchange:
1692 case nir_intrinsic_image_deref_atomic_comp_swap:
1693 v3d40_vir_emit_image_load_store(c, instr);
1694 break;
1695
1696 case nir_intrinsic_get_buffer_size:
1697 ntq_store_dest(c, &instr->dest, 0,
1698 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1699 nir_src_as_uint(instr->src[0])));
1700 break;
1701
1702 case nir_intrinsic_load_user_clip_plane:
1703 for (int i = 0; i < instr->num_components; i++) {
1704 ntq_store_dest(c, &instr->dest, i,
1705 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1706 nir_intrinsic_ucp_id(instr) *
1707 4 + i));
1708 }
1709 break;
1710
1711 case nir_intrinsic_load_viewport_x_scale:
1712 ntq_store_dest(c, &instr->dest, 0,
1713 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1714 break;
1715
1716 case nir_intrinsic_load_viewport_y_scale:
1717 ntq_store_dest(c, &instr->dest, 0,
1718 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1719 break;
1720
1721 case nir_intrinsic_load_viewport_z_scale:
1722 ntq_store_dest(c, &instr->dest, 0,
1723 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1724 break;
1725
1726 case nir_intrinsic_load_viewport_z_offset:
1727 ntq_store_dest(c, &instr->dest, 0,
1728 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1729 break;
1730
1731 case nir_intrinsic_load_alpha_ref_float:
1732 ntq_store_dest(c, &instr->dest, 0,
1733 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1734 break;
1735
1736 case nir_intrinsic_load_sample_mask_in:
1737 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1738 break;
1739
1740 case nir_intrinsic_load_helper_invocation:
1741 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1742 ntq_store_dest(c, &instr->dest, 0,
1743 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1744 vir_uniform_ui(c, ~0),
1745 vir_uniform_ui(c, 0))));
1746 break;
1747
1748 case nir_intrinsic_load_front_face:
1749 /* The register contains 0 (front) or 1 (back), and we need to
1750 * turn it into a NIR bool where true means front.
1751 */
1752 ntq_store_dest(c, &instr->dest, 0,
1753 vir_ADD(c,
1754 vir_uniform_ui(c, -1),
1755 vir_REVF(c)));
1756 break;
1757
1758 case nir_intrinsic_load_instance_id:
1759 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1760 break;
1761
1762 case nir_intrinsic_load_vertex_id:
1763 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1764 break;
1765
1766 case nir_intrinsic_load_input:
1767 offset = (nir_intrinsic_base(instr) +
1768 nir_src_as_uint(instr->src[0]));
1769 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1770 c->devinfo->ver >= 40) {
1771 /* Emit the LDVPM directly now, rather than at the top
1772 * of the shader like we did for V3D 3.x (which needs
1773 * vpmsetup when not just taking the next offset).
1774 *
1775 * Note that delaying like this may introduce stalls,
1776 * as LDVPMV takes a minimum of 1 instruction but may
1777 * be slower if the VPM unit is busy with another QPU.
1778 */
1779 int index = 0;
1780 if (c->s->info.system_values_read &
1781 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1782 index++;
1783 }
1784 if (c->s->info.system_values_read &
1785 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1786 index++;
1787 }
1788 for (int i = 0; i < offset; i++)
1789 index += c->vattr_sizes[i];
1790 index += nir_intrinsic_component(instr);
1791 for (int i = 0; i < instr->num_components; i++) {
1792 struct qreg vpm_offset =
1793 vir_uniform_ui(c, index++);
1794 ntq_store_dest(c, &instr->dest, i,
1795 vir_LDVPMV_IN(c, vpm_offset));
1796 }
1797 } else {
1798 for (int i = 0; i < instr->num_components; i++) {
1799 int comp = nir_intrinsic_component(instr) + i;
1800 ntq_store_dest(c, &instr->dest, i,
1801 vir_MOV(c, c->inputs[offset * 4 +
1802 comp]));
1803 }
1804 }
1805 break;
1806
1807 case nir_intrinsic_store_output:
1808 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1809 offset = ((nir_intrinsic_base(instr) +
1810 nir_src_as_uint(instr->src[1])) * 4 +
1811 nir_intrinsic_component(instr));
1812 for (int i = 0; i < instr->num_components; i++) {
1813 c->outputs[offset + i] =
1814 vir_MOV(c,
1815 ntq_get_src(c,
1816 instr->src[0], i));
1817 }
1818 } else {
1819 assert(instr->num_components == 1);
1820
1821 vir_VPM_WRITE(c,
1822 ntq_get_src(c, instr->src[0], 0),
1823 nir_intrinsic_base(instr));
1824 }
1825 break;
1826
1827 case nir_intrinsic_image_deref_size:
1828 ntq_emit_image_size(c, instr);
1829 break;
1830
1831 case nir_intrinsic_discard:
1832 if (vir_in_nonuniform_control_flow(c)) {
1833 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1834 V3D_QPU_PF_PUSHZ);
1835 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1836 vir_uniform_ui(c, 0)),
1837 V3D_QPU_COND_IFA);
1838 } else {
1839 vir_SETMSF_dest(c, vir_nop_reg(),
1840 vir_uniform_ui(c, 0));
1841 }
1842 break;
1843
1844 case nir_intrinsic_discard_if: {
1845 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1846
1847 if (vir_in_nonuniform_control_flow(c)) {
1848 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1849 c->execute);
1850 if (cond == V3D_QPU_COND_IFA) {
1851 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1852 } else {
1853 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1854 cond = V3D_QPU_COND_IFA;
1855 }
1856 }
1857
1858 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1859 vir_uniform_ui(c, 0)), cond);
1860
1861 break;
1862 }
1863
1864 case nir_intrinsic_memory_barrier:
1865 case nir_intrinsic_memory_barrier_atomic_counter:
1866 case nir_intrinsic_memory_barrier_buffer:
1867 case nir_intrinsic_memory_barrier_image:
1868 case nir_intrinsic_memory_barrier_shared:
1869 /* We don't do any instruction scheduling of these NIR
1870 * instructions between each other, so we just need to make
1871 * sure that the TMU operations before the barrier are flushed
1872 * before the ones after the barrier. That is currently
1873 * handled by having a THRSW in each of them and a LDTMU
1874 * series or a TMUWT after.
1875 */
1876 break;
1877
1878 case nir_intrinsic_barrier:
1879 /* Emit a TSY op to get all invocations in the workgroup
1880 * (actually supergroup) to block until the last invocation
1881 * reaches the TSY op.
1882 */
1883 if (c->devinfo->ver >= 42) {
1884 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1885 V3D_QPU_WADDR_SYNCB));
1886 } else {
1887 struct qinst *sync =
1888 vir_BARRIERID_dest(c,
1889 vir_reg(QFILE_MAGIC,
1890 V3D_QPU_WADDR_SYNCU));
1891 sync->uniform =
1892 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1893 0xffffff00 |
1894 V3D_TSY_WAIT_INC_CHECK);
1895
1896 }
1897
1898 /* The blocking of a TSY op only happens at the next thread
1899 * switch. No texturing may be outstanding at the time of a
1900 * TSY blocking operation.
1901 */
1902 vir_emit_thrsw(c);
1903 break;
1904
1905 case nir_intrinsic_load_num_work_groups:
1906 for (int i = 0; i < 3; i++) {
1907 ntq_store_dest(c, &instr->dest, i,
1908 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1909 i));
1910 }
1911 break;
1912
1913 case nir_intrinsic_load_local_invocation_index:
1914 ntq_store_dest(c, &instr->dest, 0,
1915 vir_SHR(c, c->cs_payload[1],
1916 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1917 break;
1918
1919 case nir_intrinsic_load_work_group_id:
1920 ntq_store_dest(c, &instr->dest, 0,
1921 vir_AND(c, c->cs_payload[0],
1922 vir_uniform_ui(c, 0xffff)));
1923 ntq_store_dest(c, &instr->dest, 1,
1924 vir_SHR(c, c->cs_payload[0],
1925 vir_uniform_ui(c, 16)));
1926 ntq_store_dest(c, &instr->dest, 2,
1927 vir_AND(c, c->cs_payload[1],
1928 vir_uniform_ui(c, 0xffff)));
1929 break;
1930
1931 default:
1932 fprintf(stderr, "Unknown intrinsic: ");
1933 nir_print_instr(&instr->instr, stderr);
1934 fprintf(stderr, "\n");
1935 break;
1936 }
1937 }
1938
1939 /* Clears (activates) the execute flags for any channels whose jump target
1940 * matches this block.
1941 *
1942 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1943 * enabling?
1944 *
1945 * XXX perf: For uniform control flow, we should be able to skip c->execute
1946 * handling entirely.
1947 */
1948 static void
1949 ntq_activate_execute_for_block(struct v3d_compile *c)
1950 {
1951 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
1952 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1953 V3D_QPU_PF_PUSHZ);
1954
1955 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1956 }
1957
1958 static void
1959 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1960 {
1961 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1962 bool empty_else_block =
1963 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1964 exec_list_is_empty(&nir_else_block->instr_list));
1965
1966 struct qblock *then_block = vir_new_block(c);
1967 struct qblock *after_block = vir_new_block(c);
1968 struct qblock *else_block;
1969 if (empty_else_block)
1970 else_block = after_block;
1971 else
1972 else_block = vir_new_block(c);
1973
1974 /* Set up the flags for the IF condition (taking the THEN branch). */
1975 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1976
1977 /* Jump to ELSE. */
1978 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1979 V3D_QPU_BRANCH_COND_ALLNA :
1980 V3D_QPU_BRANCH_COND_ALLA);
1981 vir_link_blocks(c->cur_block, else_block);
1982 vir_link_blocks(c->cur_block, then_block);
1983
1984 /* Process the THEN block. */
1985 vir_set_emit_block(c, then_block);
1986 ntq_emit_cf_list(c, &if_stmt->then_list);
1987
1988 if (!empty_else_block) {
1989 /* At the end of the THEN block, jump to ENDIF */
1990 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
1991 vir_link_blocks(c->cur_block, after_block);
1992
1993 /* Emit the else block. */
1994 vir_set_emit_block(c, else_block);
1995 ntq_activate_execute_for_block(c);
1996 ntq_emit_cf_list(c, &if_stmt->else_list);
1997 }
1998
1999 vir_link_blocks(c->cur_block, after_block);
2000
2001 vir_set_emit_block(c, after_block);
2002 }
2003
2004 static void
2005 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2006 {
2007 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2008 bool empty_else_block =
2009 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2010 exec_list_is_empty(&nir_else_block->instr_list));
2011
2012 struct qblock *then_block = vir_new_block(c);
2013 struct qblock *after_block = vir_new_block(c);
2014 struct qblock *else_block;
2015 if (empty_else_block)
2016 else_block = after_block;
2017 else
2018 else_block = vir_new_block(c);
2019
2020 bool was_uniform_control_flow = false;
2021 if (!vir_in_nonuniform_control_flow(c)) {
2022 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2023 was_uniform_control_flow = true;
2024 }
2025
2026 /* Set up the flags for the IF condition (taking the THEN branch). */
2027 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2028
2029 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2030 * was previously active (execute Z) for updating the exec flags.
2031 */
2032 if (was_uniform_control_flow) {
2033 cond = v3d_qpu_cond_invert(cond);
2034 } else {
2035 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2036 if (cond == V3D_QPU_COND_IFA) {
2037 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2038 } else {
2039 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2040 cond = V3D_QPU_COND_IFA;
2041 }
2042 }
2043
2044 vir_MOV_cond(c, cond,
2045 c->execute,
2046 vir_uniform_ui(c, else_block->index));
2047
2048 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2049 * through.
2050 */
2051 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2052 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2053 vir_link_blocks(c->cur_block, else_block);
2054 vir_link_blocks(c->cur_block, then_block);
2055
2056 /* Process the THEN block. */
2057 vir_set_emit_block(c, then_block);
2058 ntq_emit_cf_list(c, &if_stmt->then_list);
2059
2060 if (!empty_else_block) {
2061 /* Handle the end of the THEN block. First, all currently
2062 * active channels update their execute flags to point to
2063 * ENDIF
2064 */
2065 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2066 V3D_QPU_PF_PUSHZ);
2067 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2068 vir_uniform_ui(c, after_block->index));
2069
2070 /* If everything points at ENDIF, then jump there immediately. */
2071 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2072 c->execute,
2073 vir_uniform_ui(c, after_block->index)),
2074 V3D_QPU_PF_PUSHZ);
2075 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2076 vir_link_blocks(c->cur_block, after_block);
2077 vir_link_blocks(c->cur_block, else_block);
2078
2079 vir_set_emit_block(c, else_block);
2080 ntq_activate_execute_for_block(c);
2081 ntq_emit_cf_list(c, &if_stmt->else_list);
2082 }
2083
2084 vir_link_blocks(c->cur_block, after_block);
2085
2086 vir_set_emit_block(c, after_block);
2087 if (was_uniform_control_flow)
2088 c->execute = c->undef;
2089 else
2090 ntq_activate_execute_for_block(c);
2091 }
2092
2093 static void
2094 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2095 {
2096 bool was_in_control_flow = c->in_control_flow;
2097 c->in_control_flow = true;
2098 if (!vir_in_nonuniform_control_flow(c) &&
2099 nir_src_is_dynamically_uniform(nif->condition)) {
2100 ntq_emit_uniform_if(c, nif);
2101 } else {
2102 ntq_emit_nonuniform_if(c, nif);
2103 }
2104 c->in_control_flow = was_in_control_flow;
2105 }
2106
2107 static void
2108 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2109 {
2110 switch (jump->type) {
2111 case nir_jump_break:
2112 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2113 V3D_QPU_PF_PUSHZ);
2114 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2115 vir_uniform_ui(c, c->loop_break_block->index));
2116 break;
2117
2118 case nir_jump_continue:
2119 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2120 V3D_QPU_PF_PUSHZ);
2121 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2122 vir_uniform_ui(c, c->loop_cont_block->index));
2123 break;
2124
2125 case nir_jump_return:
2126 unreachable("All returns shouold be lowered\n");
2127 }
2128 }
2129
2130 static void
2131 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2132 {
2133 switch (instr->type) {
2134 case nir_instr_type_deref:
2135 /* ignored, will be walked by the intrinsic using it. */
2136 break;
2137
2138 case nir_instr_type_alu:
2139 ntq_emit_alu(c, nir_instr_as_alu(instr));
2140 break;
2141
2142 case nir_instr_type_intrinsic:
2143 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2144 break;
2145
2146 case nir_instr_type_load_const:
2147 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2148 break;
2149
2150 case nir_instr_type_ssa_undef:
2151 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2152 break;
2153
2154 case nir_instr_type_tex:
2155 ntq_emit_tex(c, nir_instr_as_tex(instr));
2156 break;
2157
2158 case nir_instr_type_jump:
2159 ntq_emit_jump(c, nir_instr_as_jump(instr));
2160 break;
2161
2162 default:
2163 fprintf(stderr, "Unknown NIR instr type: ");
2164 nir_print_instr(instr, stderr);
2165 fprintf(stderr, "\n");
2166 abort();
2167 }
2168 }
2169
2170 static void
2171 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2172 {
2173 nir_foreach_instr(instr, block) {
2174 ntq_emit_instr(c, instr);
2175 }
2176 }
2177
2178 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2179
2180 static void
2181 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2182 {
2183 bool was_in_control_flow = c->in_control_flow;
2184 c->in_control_flow = true;
2185
2186 bool was_uniform_control_flow = false;
2187 if (!vir_in_nonuniform_control_flow(c)) {
2188 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2189 was_uniform_control_flow = true;
2190 }
2191
2192 struct qblock *save_loop_cont_block = c->loop_cont_block;
2193 struct qblock *save_loop_break_block = c->loop_break_block;
2194
2195 c->loop_cont_block = vir_new_block(c);
2196 c->loop_break_block = vir_new_block(c);
2197
2198 vir_link_blocks(c->cur_block, c->loop_cont_block);
2199 vir_set_emit_block(c, c->loop_cont_block);
2200 ntq_activate_execute_for_block(c);
2201
2202 ntq_emit_cf_list(c, &loop->body);
2203
2204 /* Re-enable any previous continues now, so our ANYA check below
2205 * works.
2206 *
2207 * XXX: Use the .ORZ flags update, instead.
2208 */
2209 vir_set_pf(vir_XOR_dest(c,
2210 vir_nop_reg(),
2211 c->execute,
2212 vir_uniform_ui(c, c->loop_cont_block->index)),
2213 V3D_QPU_PF_PUSHZ);
2214 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2215
2216 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2217
2218 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2219 /* Pixels that were not dispatched or have been discarded should not
2220 * contribute to looping again.
2221 */
2222 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2223 vir_link_blocks(c->cur_block, c->loop_cont_block);
2224 vir_link_blocks(c->cur_block, c->loop_break_block);
2225
2226 vir_set_emit_block(c, c->loop_break_block);
2227 if (was_uniform_control_flow)
2228 c->execute = c->undef;
2229 else
2230 ntq_activate_execute_for_block(c);
2231
2232 c->loop_break_block = save_loop_break_block;
2233 c->loop_cont_block = save_loop_cont_block;
2234
2235 c->loops++;
2236
2237 c->in_control_flow = was_in_control_flow;
2238 }
2239
2240 static void
2241 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2242 {
2243 fprintf(stderr, "FUNCTIONS not handled.\n");
2244 abort();
2245 }
2246
2247 static void
2248 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2249 {
2250 foreach_list_typed(nir_cf_node, node, node, list) {
2251 switch (node->type) {
2252 case nir_cf_node_block:
2253 ntq_emit_block(c, nir_cf_node_as_block(node));
2254 break;
2255
2256 case nir_cf_node_if:
2257 ntq_emit_if(c, nir_cf_node_as_if(node));
2258 break;
2259
2260 case nir_cf_node_loop:
2261 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2262 break;
2263
2264 case nir_cf_node_function:
2265 ntq_emit_function(c, nir_cf_node_as_function(node));
2266 break;
2267
2268 default:
2269 fprintf(stderr, "Unknown NIR node type\n");
2270 abort();
2271 }
2272 }
2273 }
2274
2275 static void
2276 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2277 {
2278 ntq_setup_registers(c, &impl->registers);
2279 ntq_emit_cf_list(c, &impl->body);
2280 }
2281
2282 static void
2283 nir_to_vir(struct v3d_compile *c)
2284 {
2285 switch (c->s->info.stage) {
2286 case MESA_SHADER_FRAGMENT:
2287 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2288 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2289 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2290
2291 /* XXX perf: We could set the "disable implicit point/line
2292 * varyings" field in the shader record and not emit these, if
2293 * they're not going to be used.
2294 */
2295 if (c->fs_key->is_points) {
2296 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2297 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2298 } else if (c->fs_key->is_lines) {
2299 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2300 }
2301 break;
2302 case MESA_SHADER_COMPUTE:
2303 /* Set up the TSO for barriers, assuming we do some. */
2304 if (c->devinfo->ver < 42) {
2305 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2306 V3D_QPU_WADDR_SYNC));
2307 }
2308
2309 if (c->s->info.system_values_read &
2310 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2311 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2312 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2313 }
2314 if ((c->s->info.system_values_read &
2315 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2316 c->s->info.cs.shared_size) {
2317 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2318 }
2319
2320 /* Set up the division between gl_LocalInvocationIndex and
2321 * wg_in_mem in the payload reg.
2322 */
2323 int wg_size = (c->s->info.cs.local_size[0] *
2324 c->s->info.cs.local_size[1] *
2325 c->s->info.cs.local_size[2]);
2326 c->local_invocation_index_bits =
2327 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2328 assert(c->local_invocation_index_bits <= 8);
2329
2330 if (c->s->info.cs.shared_size) {
2331 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2332 vir_uniform_ui(c, 16));
2333 if (c->s->info.cs.local_size[0] != 1 ||
2334 c->s->info.cs.local_size[1] != 1 ||
2335 c->s->info.cs.local_size[2] != 1) {
2336 int wg_bits = (16 -
2337 c->local_invocation_index_bits);
2338 int wg_mask = (1 << wg_bits) - 1;
2339 wg_in_mem = vir_AND(c, wg_in_mem,
2340 vir_uniform_ui(c, wg_mask));
2341 }
2342 struct qreg shared_per_wg =
2343 vir_uniform_ui(c, c->s->info.cs.shared_size);
2344
2345 c->cs_shared_offset =
2346 vir_ADD(c,
2347 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2348 vir_UMUL(c, wg_in_mem, shared_per_wg));
2349 }
2350 break;
2351 default:
2352 break;
2353 }
2354
2355 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2356 ntq_setup_fs_inputs(c);
2357 else
2358 ntq_setup_vpm_inputs(c);
2359
2360 ntq_setup_outputs(c);
2361 ntq_setup_uniforms(c);
2362 ntq_setup_registers(c, &c->s->registers);
2363
2364 /* Find the main function and emit the body. */
2365 nir_foreach_function(function, c->s) {
2366 assert(strcmp(function->name, "main") == 0);
2367 assert(function->impl);
2368 ntq_emit_impl(c, function->impl);
2369 }
2370 }
2371
2372 const nir_shader_compiler_options v3d_nir_options = {
2373 .lower_all_io_to_temps = true,
2374 .lower_extract_byte = true,
2375 .lower_extract_word = true,
2376 .lower_bfm = true,
2377 .lower_bitfield_insert_to_shifts = true,
2378 .lower_bitfield_extract_to_shifts = true,
2379 .lower_bitfield_reverse = true,
2380 .lower_bit_count = true,
2381 .lower_cs_local_id_from_index = true,
2382 .lower_ffract = true,
2383 .lower_pack_unorm_2x16 = true,
2384 .lower_pack_snorm_2x16 = true,
2385 .lower_pack_unorm_4x8 = true,
2386 .lower_pack_snorm_4x8 = true,
2387 .lower_unpack_unorm_4x8 = true,
2388 .lower_unpack_snorm_4x8 = true,
2389 .lower_pack_half_2x16 = true,
2390 .lower_unpack_half_2x16 = true,
2391 .lower_fdiv = true,
2392 .lower_find_lsb = true,
2393 .lower_ffma = true,
2394 .lower_flrp32 = true,
2395 .lower_fpow = true,
2396 .lower_fsat = true,
2397 .lower_fsqrt = true,
2398 .lower_ifind_msb = true,
2399 .lower_isign = true,
2400 .lower_ldexp = true,
2401 .lower_mul_high = true,
2402 .lower_wpos_pntc = true,
2403 .native_integers = true,
2404 };
2405
2406 /**
2407 * When demoting a shader down to single-threaded, removes the THRSW
2408 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2409 * program end).
2410 */
2411 static void
2412 vir_remove_thrsw(struct v3d_compile *c)
2413 {
2414 vir_for_each_block(block, c) {
2415 vir_for_each_inst_safe(inst, block) {
2416 if (inst->qpu.sig.thrsw)
2417 vir_remove_instruction(c, inst);
2418 }
2419 }
2420
2421 c->last_thrsw = NULL;
2422 }
2423
2424 void
2425 vir_emit_last_thrsw(struct v3d_compile *c)
2426 {
2427 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2428 * switching, so disable threads if we didn't do any TMU ops (each of
2429 * which would have emitted a THRSW).
2430 */
2431 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2432 c->threads = 1;
2433 if (c->last_thrsw)
2434 vir_remove_thrsw(c);
2435 return;
2436 }
2437
2438 /* If we're threaded and the last THRSW was in conditional code, then
2439 * we need to emit another one so that we can flag it as the last
2440 * thrsw.
2441 */
2442 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2443 assert(c->devinfo->ver >= 41);
2444 vir_emit_thrsw(c);
2445 }
2446
2447 /* If we're threaded, then we need to mark the last THRSW instruction
2448 * so we can emit a pair of them at QPU emit time.
2449 *
2450 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2451 * post-last-THRSW state, so we can skip this.
2452 */
2453 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2454 assert(c->devinfo->ver >= 41);
2455 vir_emit_thrsw(c);
2456 }
2457
2458 if (c->last_thrsw)
2459 c->last_thrsw->is_last_thrsw = true;
2460 }
2461
2462 /* There's a flag in the shader for "center W is needed for reasons other than
2463 * non-centroid varyings", so we just walk the program after VIR optimization
2464 * to see if it's used. It should be harmless to set even if we only use
2465 * center W for varyings.
2466 */
2467 static void
2468 vir_check_payload_w(struct v3d_compile *c)
2469 {
2470 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2471 return;
2472
2473 vir_for_each_inst_inorder(inst, c) {
2474 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2475 if (inst->src[i].file == QFILE_REG &&
2476 inst->src[i].index == 0) {
2477 c->uses_center_w = true;
2478 return;
2479 }
2480 }
2481 }
2482
2483 }
2484
2485 void
2486 v3d_nir_to_vir(struct v3d_compile *c)
2487 {
2488 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2489 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2490 fprintf(stderr, "%s prog %d/%d NIR:\n",
2491 vir_get_stage_name(c),
2492 c->program_id, c->variant_id);
2493 nir_print_shader(c->s, stderr);
2494 }
2495
2496 nir_to_vir(c);
2497
2498 /* Emit the last THRSW before STVPM and TLB writes. */
2499 vir_emit_last_thrsw(c);
2500
2501 switch (c->s->info.stage) {
2502 case MESA_SHADER_FRAGMENT:
2503 emit_frag_end(c);
2504 break;
2505 case MESA_SHADER_VERTEX:
2506 emit_vert_end(c);
2507 break;
2508 default:
2509 unreachable("bad stage");
2510 }
2511
2512 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2513 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2514 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2515 vir_get_stage_name(c),
2516 c->program_id, c->variant_id);
2517 vir_dump(c);
2518 fprintf(stderr, "\n");
2519 }
2520
2521 vir_optimize(c);
2522
2523 vir_check_payload_w(c);
2524
2525 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2526 * We used that on that platform to pipeline TMU writes and reduce the
2527 * number of thread switches, as well as try (mostly successfully) to
2528 * reduce maximum register pressure to allow more threads. We should
2529 * do something of that sort for V3D -- either instruction scheduling
2530 * here, or delay the the THRSW and LDTMUs from our texture
2531 * instructions until the results are needed.
2532 */
2533
2534 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2535 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2536 fprintf(stderr, "%s prog %d/%d VIR:\n",
2537 vir_get_stage_name(c),
2538 c->program_id, c->variant_id);
2539 vir_dump(c);
2540 fprintf(stderr, "\n");
2541 }
2542
2543 /* Attempt to allocate registers for the temporaries. If we fail,
2544 * reduce thread count and try again.
2545 */
2546 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2547 struct qpu_reg *temp_registers;
2548 while (true) {
2549 bool spilled;
2550 temp_registers = v3d_register_allocate(c, &spilled);
2551 if (spilled)
2552 continue;
2553
2554 if (temp_registers)
2555 break;
2556
2557 if (c->threads == min_threads) {
2558 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2559 c->threads);
2560 vir_dump(c);
2561 c->failed = true;
2562 return;
2563 }
2564
2565 c->threads /= 2;
2566
2567 if (c->threads == 1)
2568 vir_remove_thrsw(c);
2569 }
2570
2571 if (c->spill_size &&
2572 (V3D_DEBUG & (V3D_DEBUG_VIR |
2573 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2574 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2575 vir_get_stage_name(c),
2576 c->program_id, c->variant_id);
2577 vir_dump(c);
2578 fprintf(stderr, "\n");
2579 }
2580
2581 v3d_vir_to_qpu(c, temp_registers);
2582 }