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v3d: Add support for matrix inputs to the FS.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 static void
70 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
71
72 static void
73 resize_qreg_array(struct v3d_compile *c,
74 struct qreg **regs,
75 uint32_t *size,
76 uint32_t decl_size)
77 {
78 if (*size >= decl_size)
79 return;
80
81 uint32_t old_size = *size;
82 *size = MAX2(*size * 2, decl_size);
83 *regs = reralloc(c, *regs, struct qreg, *size);
84 if (!*regs) {
85 fprintf(stderr, "Malloc failure\n");
86 abort();
87 }
88
89 for (uint32_t i = old_size; i < *size; i++)
90 (*regs)[i] = c->undef;
91 }
92
93 void
94 vir_emit_thrsw(struct v3d_compile *c)
95 {
96 if (c->threads == 1)
97 return;
98
99 /* Always thread switch after each texture operation for now.
100 *
101 * We could do better by batching a bunch of texture fetches up and
102 * then doing one thread switch and collecting all their results
103 * afterward.
104 */
105 c->last_thrsw = vir_NOP(c);
106 c->last_thrsw->qpu.sig.thrsw = true;
107 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
108 }
109
110 /**
111 * Implements indirect uniform loads through the TMU general memory access
112 * interface.
113 */
114 static void
115 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr)
116 {
117 uint32_t tmu_op = GENERAL_TMU_READ_OP_READ;
118 bool has_index = instr->intrinsic == nir_intrinsic_load_ubo;
119 int offset_src = 0 + has_index;
120
121 struct qreg offset;
122 if (instr->intrinsic == nir_intrinsic_load_uniform) {
123 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
124
125 /* Find what variable in the default uniform block this
126 * uniform load is coming from.
127 */
128 uint32_t base = nir_intrinsic_base(instr);
129 int i;
130 struct v3d_ubo_range *range = NULL;
131 for (i = 0; i < c->num_ubo_ranges; i++) {
132 range = &c->ubo_ranges[i];
133 if (base >= range->src_offset &&
134 base < range->src_offset + range->size) {
135 break;
136 }
137 }
138 /* The driver-location-based offset always has to be within a
139 * declared uniform range.
140 */
141 assert(i != c->num_ubo_ranges);
142 if (!c->ubo_range_used[i]) {
143 c->ubo_range_used[i] = true;
144 range->dst_offset = c->next_ubo_dst_offset;
145 c->next_ubo_dst_offset += range->size;
146 }
147
148 base = base - range->src_offset + range->dst_offset;
149
150 if (base != 0)
151 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
152 } else {
153 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
154 * 1 (0 is gallium's constant buffer 0).
155 */
156 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
157 nir_src_as_uint(instr->src[0]) + 1);
158 }
159
160 uint32_t config = (0xffffff00 |
161 tmu_op |
162 GENERAL_TMU_LOOKUP_PER_PIXEL);
163 if (instr->num_components == 1) {
164 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
165 } else {
166 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
167 instr->num_components - 2);
168 }
169
170 struct qreg dest;
171 if (config == ~0)
172 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
173 else
174 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
175
176 struct qinst *tmu;
177 if (nir_src_is_const(instr->src[offset_src]) &&
178 nir_src_as_uint(instr->src[offset_src]) == 0) {
179 tmu = vir_MOV_dest(c, dest, offset);
180 } else {
181 tmu = vir_ADD_dest(c, dest,
182 offset,
183 ntq_get_src(c, instr->src[offset_src], 0));
184 }
185
186 if (config != ~0) {
187 tmu->src[vir_get_implicit_uniform_src(tmu)] =
188 vir_uniform_ui(c, config);
189 }
190
191 vir_emit_thrsw(c);
192
193 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
194 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
195 }
196
197 static struct qreg *
198 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
199 {
200 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
201 def->num_components);
202 _mesa_hash_table_insert(c->def_ht, def, qregs);
203 return qregs;
204 }
205
206 /**
207 * This function is responsible for getting VIR results into the associated
208 * storage for a NIR instruction.
209 *
210 * If it's a NIR SSA def, then we just set the associated hash table entry to
211 * the new result.
212 *
213 * If it's a NIR reg, then we need to update the existing qreg assigned to the
214 * NIR destination with the incoming value. To do that without introducing
215 * new MOVs, we require that the incoming qreg either be a uniform, or be
216 * SSA-defined by the previous VIR instruction in the block and rewritable by
217 * this function. That lets us sneak ahead and insert the SF flag beforehand
218 * (knowing that the previous instruction doesn't depend on flags) and rewrite
219 * its destination to be the NIR reg's destination
220 */
221 void
222 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
223 struct qreg result)
224 {
225 struct qinst *last_inst = NULL;
226 if (!list_empty(&c->cur_block->instructions))
227 last_inst = (struct qinst *)c->cur_block->instructions.prev;
228
229 assert(result.file == QFILE_UNIF ||
230 (result.file == QFILE_TEMP &&
231 last_inst && last_inst == c->defs[result.index]));
232
233 if (dest->is_ssa) {
234 assert(chan < dest->ssa.num_components);
235
236 struct qreg *qregs;
237 struct hash_entry *entry =
238 _mesa_hash_table_search(c->def_ht, &dest->ssa);
239
240 if (entry)
241 qregs = entry->data;
242 else
243 qregs = ntq_init_ssa_def(c, &dest->ssa);
244
245 qregs[chan] = result;
246 } else {
247 nir_register *reg = dest->reg.reg;
248 assert(dest->reg.base_offset == 0);
249 assert(reg->num_array_elems == 0);
250 struct hash_entry *entry =
251 _mesa_hash_table_search(c->def_ht, reg);
252 struct qreg *qregs = entry->data;
253
254 /* Insert a MOV if the source wasn't an SSA def in the
255 * previous instruction.
256 */
257 if (result.file == QFILE_UNIF) {
258 result = vir_MOV(c, result);
259 last_inst = c->defs[result.index];
260 }
261
262 /* We know they're both temps, so just rewrite index. */
263 c->defs[last_inst->dst.index] = NULL;
264 last_inst->dst.index = qregs[chan].index;
265
266 /* If we're in control flow, then make this update of the reg
267 * conditional on the execution mask.
268 */
269 if (c->execute.file != QFILE_NULL) {
270 last_inst->dst.index = qregs[chan].index;
271
272 /* Set the flags to the current exec mask.
273 */
274 c->cursor = vir_before_inst(last_inst);
275 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
276 c->cursor = vir_after_inst(last_inst);
277
278 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
279 last_inst->cond_is_exec_mask = true;
280 }
281 }
282 }
283
284 struct qreg
285 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
286 {
287 struct hash_entry *entry;
288 if (src.is_ssa) {
289 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
290 assert(i < src.ssa->num_components);
291 } else {
292 nir_register *reg = src.reg.reg;
293 entry = _mesa_hash_table_search(c->def_ht, reg);
294 assert(reg->num_array_elems == 0);
295 assert(src.reg.base_offset == 0);
296 assert(i < reg->num_components);
297 }
298
299 struct qreg *qregs = entry->data;
300 return qregs[i];
301 }
302
303 static struct qreg
304 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
305 unsigned src)
306 {
307 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
308 unsigned chan = ffs(instr->dest.write_mask) - 1;
309 struct qreg r = ntq_get_src(c, instr->src[src].src,
310 instr->src[src].swizzle[chan]);
311
312 assert(!instr->src[src].abs);
313 assert(!instr->src[src].negate);
314
315 return r;
316 };
317
318 static struct qreg
319 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
320 {
321 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
322 }
323
324 static void
325 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
326 {
327 unsigned unit = instr->texture_index;
328 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
329 int dest_size = nir_tex_instr_dest_size(instr);
330
331 struct qreg lod = c->undef;
332 if (lod_index != -1)
333 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
334
335 for (int i = 0; i < dest_size; i++) {
336 assert(i < 3);
337 enum quniform_contents contents;
338
339 if (instr->is_array && i == dest_size - 1)
340 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
341 else
342 contents = QUNIFORM_TEXTURE_WIDTH + i;
343
344 struct qreg size = vir_uniform(c, contents, unit);
345
346 switch (instr->sampler_dim) {
347 case GLSL_SAMPLER_DIM_1D:
348 case GLSL_SAMPLER_DIM_2D:
349 case GLSL_SAMPLER_DIM_MS:
350 case GLSL_SAMPLER_DIM_3D:
351 case GLSL_SAMPLER_DIM_CUBE:
352 /* Don't minify the array size. */
353 if (!(instr->is_array && i == dest_size - 1)) {
354 size = ntq_minify(c, size, lod);
355 }
356 break;
357
358 case GLSL_SAMPLER_DIM_RECT:
359 /* There's no LOD field for rects */
360 break;
361
362 default:
363 unreachable("Bad sampler type");
364 }
365
366 ntq_store_dest(c, &instr->dest, i, size);
367 }
368 }
369
370 static void
371 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
372 {
373 unsigned unit = instr->texture_index;
374
375 /* Since each texture sampling op requires uploading uniforms to
376 * reference the texture, there's no HW support for texture size and
377 * you just upload uniforms containing the size.
378 */
379 switch (instr->op) {
380 case nir_texop_query_levels:
381 ntq_store_dest(c, &instr->dest, 0,
382 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
383 return;
384 case nir_texop_txs:
385 ntq_emit_txs(c, instr);
386 return;
387 default:
388 break;
389 }
390
391 if (c->devinfo->ver >= 40)
392 v3d40_vir_emit_tex(c, instr);
393 else
394 v3d33_vir_emit_tex(c, instr);
395 }
396
397 static struct qreg
398 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
399 {
400 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
401 if (is_cos)
402 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
403
404 struct qreg periods = vir_FROUND(c, input);
405 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
406 return vir_XOR(c, sin_output, vir_SHL(c,
407 vir_FTOIN(c, periods),
408 vir_uniform_ui(c, -1)));
409 }
410
411 static struct qreg
412 ntq_fsign(struct v3d_compile *c, struct qreg src)
413 {
414 struct qreg t = vir_get_temp(c);
415
416 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
417 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
418 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
419 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
420 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
421 return vir_MOV(c, t);
422 }
423
424 static struct qreg
425 ntq_isign(struct v3d_compile *c, struct qreg src)
426 {
427 struct qreg t = vir_get_temp(c);
428
429 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
430 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
431 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
432 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
433 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
434 return vir_MOV(c, t);
435 }
436
437 static void
438 emit_fragcoord_input(struct v3d_compile *c, int attr)
439 {
440 c->inputs[attr * 4 + 0] = vir_FXCD(c);
441 c->inputs[attr * 4 + 1] = vir_FYCD(c);
442 c->inputs[attr * 4 + 2] = c->payload_z;
443 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
444 }
445
446 static struct qreg
447 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
448 uint8_t swizzle, int array_index)
449 {
450 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
451 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
452
453 struct qreg vary;
454 if (c->devinfo->ver >= 41) {
455 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
456 c->undef, c->undef);
457 ldvary->qpu.sig.ldvary = true;
458 vary = vir_emit_def(c, ldvary);
459 } else {
460 vir_NOP(c)->qpu.sig.ldvary = true;
461 vary = r3;
462 }
463
464 /* For gl_PointCoord input or distance along a line, we'll be called
465 * with no nir_variable, and we don't count toward VPM size so we
466 * don't track an input slot.
467 */
468 if (!var) {
469 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
470 }
471
472 int i = c->num_inputs++;
473 c->input_slots[i] =
474 v3d_slot_from_slot_and_component(var->data.location +
475 array_index, swizzle);
476
477 switch (var->data.interpolation) {
478 case INTERP_MODE_NONE:
479 /* If a gl_FrontColor or gl_BackColor input has no interp
480 * qualifier, then if we're using glShadeModel(GL_FLAT) it
481 * needs to be flat shaded.
482 */
483 switch (var->data.location + array_index) {
484 case VARYING_SLOT_COL0:
485 case VARYING_SLOT_COL1:
486 case VARYING_SLOT_BFC0:
487 case VARYING_SLOT_BFC1:
488 if (c->fs_key->shade_model_flat) {
489 BITSET_SET(c->flat_shade_flags, i);
490 vir_MOV_dest(c, c->undef, vary);
491 return vir_MOV(c, r5);
492 } else {
493 return vir_FADD(c, vir_FMUL(c, vary,
494 c->payload_w), r5);
495 }
496 default:
497 break;
498 }
499 /* FALLTHROUGH */
500 case INTERP_MODE_SMOOTH:
501 if (var->data.centroid) {
502 BITSET_SET(c->centroid_flags, i);
503 return vir_FADD(c, vir_FMUL(c, vary,
504 c->payload_w_centroid), r5);
505 } else {
506 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
507 }
508 case INTERP_MODE_NOPERSPECTIVE:
509 BITSET_SET(c->noperspective_flags, i);
510 return vir_FADD(c, vir_MOV(c, vary), r5);
511 case INTERP_MODE_FLAT:
512 BITSET_SET(c->flat_shade_flags, i);
513 vir_MOV_dest(c, c->undef, vary);
514 return vir_MOV(c, r5);
515 default:
516 unreachable("Bad interp mode");
517 }
518 }
519
520 static void
521 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
522 int array_index)
523 {
524 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
525 int chan = var->data.location_frac + i;
526 c->inputs[attr * 4 + chan] =
527 emit_fragment_varying(c, var, chan, array_index);
528 }
529 }
530
531 static void
532 add_output(struct v3d_compile *c,
533 uint32_t decl_offset,
534 uint8_t slot,
535 uint8_t swizzle)
536 {
537 uint32_t old_array_size = c->outputs_array_size;
538 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
539 decl_offset + 1);
540
541 if (old_array_size != c->outputs_array_size) {
542 c->output_slots = reralloc(c,
543 c->output_slots,
544 struct v3d_varying_slot,
545 c->outputs_array_size);
546 }
547
548 c->output_slots[decl_offset] =
549 v3d_slot_from_slot_and_component(slot, swizzle);
550 }
551
552 static void
553 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
554 {
555 unsigned array_id = c->num_ubo_ranges++;
556 if (array_id >= c->ubo_ranges_array_size) {
557 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
558 array_id + 1);
559 c->ubo_ranges = reralloc(c, c->ubo_ranges,
560 struct v3d_ubo_range,
561 c->ubo_ranges_array_size);
562 c->ubo_range_used = reralloc(c, c->ubo_range_used,
563 bool,
564 c->ubo_ranges_array_size);
565 }
566
567 c->ubo_ranges[array_id].dst_offset = 0;
568 c->ubo_ranges[array_id].src_offset = start;
569 c->ubo_ranges[array_id].size = size;
570 c->ubo_range_used[array_id] = false;
571 }
572
573 /**
574 * If compare_instr is a valid comparison instruction, emits the
575 * compare_instr's comparison and returns the sel_instr's return value based
576 * on the compare_instr's result.
577 */
578 static bool
579 ntq_emit_comparison(struct v3d_compile *c,
580 nir_alu_instr *compare_instr,
581 enum v3d_qpu_cond *out_cond)
582 {
583 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
584 struct qreg src1;
585 if (nir_op_infos[compare_instr->op].num_inputs > 1)
586 src1 = ntq_get_alu_src(c, compare_instr, 1);
587 bool cond_invert = false;
588 struct qreg nop = vir_reg(QFILE_NULL, 0);
589
590 switch (compare_instr->op) {
591 case nir_op_feq32:
592 case nir_op_seq:
593 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
594 break;
595 case nir_op_ieq32:
596 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
597 break;
598
599 case nir_op_fne32:
600 case nir_op_sne:
601 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
602 cond_invert = true;
603 break;
604 case nir_op_ine32:
605 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
606 cond_invert = true;
607 break;
608
609 case nir_op_fge32:
610 case nir_op_sge:
611 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
612 break;
613 case nir_op_ige32:
614 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
615 cond_invert = true;
616 break;
617 case nir_op_uge32:
618 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
619 cond_invert = true;
620 break;
621
622 case nir_op_slt:
623 case nir_op_flt32:
624 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
625 break;
626 case nir_op_ilt32:
627 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
628 break;
629 case nir_op_ult32:
630 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
631 break;
632
633 default:
634 return false;
635 }
636
637 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
638
639 return true;
640 }
641
642 /* Finds an ALU instruction that generates our src value that could
643 * (potentially) be greedily emitted in the consuming instruction.
644 */
645 static struct nir_alu_instr *
646 ntq_get_alu_parent(nir_src src)
647 {
648 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
649 return NULL;
650 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
651 if (!instr)
652 return NULL;
653
654 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
655 * moving emission of the ALU instr down past another write of the
656 * src.
657 */
658 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
659 if (!instr->src[i].src.is_ssa)
660 return NULL;
661 }
662
663 return instr;
664 }
665
666 /**
667 * Attempts to fold a comparison generating a boolean result into the
668 * condition code for selecting between two values, instead of comparing the
669 * boolean result against 0 to generate the condition code.
670 */
671 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
672 struct qreg *src)
673 {
674 nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src);
675 if (!compare)
676 goto out;
677
678 enum v3d_qpu_cond cond;
679 if (ntq_emit_comparison(c, compare, &cond))
680 return vir_MOV(c, vir_SEL(c, cond, src[1], src[2]));
681
682 out:
683 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
684 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
685 }
686
687
688 static void
689 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
690 {
691 /* This should always be lowered to ALU operations for V3D. */
692 assert(!instr->dest.saturate);
693
694 /* Vectors are special in that they have non-scalarized writemasks,
695 * and just take the first swizzle channel for each argument in order
696 * into each writemask channel.
697 */
698 if (instr->op == nir_op_vec2 ||
699 instr->op == nir_op_vec3 ||
700 instr->op == nir_op_vec4) {
701 struct qreg srcs[4];
702 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
703 srcs[i] = ntq_get_src(c, instr->src[i].src,
704 instr->src[i].swizzle[0]);
705 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
706 ntq_store_dest(c, &instr->dest.dest, i,
707 vir_MOV(c, srcs[i]));
708 return;
709 }
710
711 /* General case: We can just grab the one used channel per src. */
712 struct qreg src[nir_op_infos[instr->op].num_inputs];
713 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
714 src[i] = ntq_get_alu_src(c, instr, i);
715 }
716
717 struct qreg result;
718
719 switch (instr->op) {
720 case nir_op_fmov:
721 case nir_op_imov:
722 result = vir_MOV(c, src[0]);
723 break;
724
725 case nir_op_fneg:
726 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
727 break;
728 case nir_op_ineg:
729 result = vir_NEG(c, src[0]);
730 break;
731
732 case nir_op_fmul:
733 result = vir_FMUL(c, src[0], src[1]);
734 break;
735 case nir_op_fadd:
736 result = vir_FADD(c, src[0], src[1]);
737 break;
738 case nir_op_fsub:
739 result = vir_FSUB(c, src[0], src[1]);
740 break;
741 case nir_op_fmin:
742 result = vir_FMIN(c, src[0], src[1]);
743 break;
744 case nir_op_fmax:
745 result = vir_FMAX(c, src[0], src[1]);
746 break;
747
748 case nir_op_f2i32:
749 result = vir_FTOIZ(c, src[0]);
750 break;
751 case nir_op_f2u32:
752 result = vir_FTOUZ(c, src[0]);
753 break;
754 case nir_op_i2f32:
755 result = vir_ITOF(c, src[0]);
756 break;
757 case nir_op_u2f32:
758 result = vir_UTOF(c, src[0]);
759 break;
760 case nir_op_b2f32:
761 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
762 break;
763 case nir_op_b2i32:
764 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
765 break;
766 case nir_op_i2b32:
767 case nir_op_f2b32:
768 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
769 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
770 vir_uniform_ui(c, ~0),
771 vir_uniform_ui(c, 0)));
772 break;
773
774 case nir_op_iadd:
775 result = vir_ADD(c, src[0], src[1]);
776 break;
777 case nir_op_ushr:
778 result = vir_SHR(c, src[0], src[1]);
779 break;
780 case nir_op_isub:
781 result = vir_SUB(c, src[0], src[1]);
782 break;
783 case nir_op_ishr:
784 result = vir_ASR(c, src[0], src[1]);
785 break;
786 case nir_op_ishl:
787 result = vir_SHL(c, src[0], src[1]);
788 break;
789 case nir_op_imin:
790 result = vir_MIN(c, src[0], src[1]);
791 break;
792 case nir_op_umin:
793 result = vir_UMIN(c, src[0], src[1]);
794 break;
795 case nir_op_imax:
796 result = vir_MAX(c, src[0], src[1]);
797 break;
798 case nir_op_umax:
799 result = vir_UMAX(c, src[0], src[1]);
800 break;
801 case nir_op_iand:
802 result = vir_AND(c, src[0], src[1]);
803 break;
804 case nir_op_ior:
805 result = vir_OR(c, src[0], src[1]);
806 break;
807 case nir_op_ixor:
808 result = vir_XOR(c, src[0], src[1]);
809 break;
810 case nir_op_inot:
811 result = vir_NOT(c, src[0]);
812 break;
813
814 case nir_op_ufind_msb:
815 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
816 break;
817
818 case nir_op_imul:
819 result = vir_UMUL(c, src[0], src[1]);
820 break;
821
822 case nir_op_seq:
823 case nir_op_sne:
824 case nir_op_sge:
825 case nir_op_slt: {
826 enum v3d_qpu_cond cond;
827 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
828 assert(ok);
829 result = vir_MOV(c, vir_SEL(c, cond,
830 vir_uniform_f(c, 1.0),
831 vir_uniform_f(c, 0.0)));
832 break;
833 }
834
835 case nir_op_feq32:
836 case nir_op_fne32:
837 case nir_op_fge32:
838 case nir_op_flt32:
839 case nir_op_ieq32:
840 case nir_op_ine32:
841 case nir_op_ige32:
842 case nir_op_uge32:
843 case nir_op_ilt32:
844 case nir_op_ult32: {
845 enum v3d_qpu_cond cond;
846 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
847 assert(ok);
848 result = vir_MOV(c, vir_SEL(c, cond,
849 vir_uniform_ui(c, ~0),
850 vir_uniform_ui(c, 0)));
851 break;
852 }
853
854 case nir_op_b32csel:
855 result = ntq_emit_bcsel(c, instr, src);
856 break;
857 case nir_op_fcsel:
858 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
859 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
860 src[1], src[2]));
861 break;
862
863 case nir_op_frcp:
864 result = vir_RECIP(c, src[0]);
865 break;
866 case nir_op_frsq:
867 result = vir_RSQRT(c, src[0]);
868 break;
869 case nir_op_fexp2:
870 result = vir_EXP(c, src[0]);
871 break;
872 case nir_op_flog2:
873 result = vir_LOG(c, src[0]);
874 break;
875
876 case nir_op_fceil:
877 result = vir_FCEIL(c, src[0]);
878 break;
879 case nir_op_ffloor:
880 result = vir_FFLOOR(c, src[0]);
881 break;
882 case nir_op_fround_even:
883 result = vir_FROUND(c, src[0]);
884 break;
885 case nir_op_ftrunc:
886 result = vir_FTRUNC(c, src[0]);
887 break;
888 case nir_op_ffract:
889 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
890 break;
891
892 case nir_op_fsin:
893 result = ntq_fsincos(c, src[0], false);
894 break;
895 case nir_op_fcos:
896 result = ntq_fsincos(c, src[0], true);
897 break;
898
899 case nir_op_fsign:
900 result = ntq_fsign(c, src[0]);
901 break;
902 case nir_op_isign:
903 result = ntq_isign(c, src[0]);
904 break;
905
906 case nir_op_fabs: {
907 result = vir_FMOV(c, src[0]);
908 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
909 break;
910 }
911
912 case nir_op_iabs:
913 result = vir_MAX(c, src[0],
914 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
915 break;
916
917 case nir_op_fddx:
918 case nir_op_fddx_coarse:
919 case nir_op_fddx_fine:
920 result = vir_FDX(c, src[0]);
921 break;
922
923 case nir_op_fddy:
924 case nir_op_fddy_coarse:
925 case nir_op_fddy_fine:
926 result = vir_FDY(c, src[0]);
927 break;
928
929 case nir_op_uadd_carry:
930 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
931 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
932 vir_uniform_ui(c, ~0),
933 vir_uniform_ui(c, 0)));
934 break;
935
936 case nir_op_pack_half_2x16_split:
937 result = vir_VFPACK(c, src[0], src[1]);
938 break;
939
940 case nir_op_unpack_half_2x16_split_x:
941 /* XXX perf: It would be good to be able to merge this unpack
942 * with whatever uses our result.
943 */
944 result = vir_FMOV(c, src[0]);
945 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
946 break;
947
948 case nir_op_unpack_half_2x16_split_y:
949 result = vir_FMOV(c, src[0]);
950 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
951 break;
952
953 default:
954 fprintf(stderr, "unknown NIR ALU inst: ");
955 nir_print_instr(&instr->instr, stderr);
956 fprintf(stderr, "\n");
957 abort();
958 }
959
960 /* We have a scalar result, so the instruction should only have a
961 * single channel written to.
962 */
963 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
964 ntq_store_dest(c, &instr->dest.dest,
965 ffs(instr->dest.write_mask) - 1, result);
966 }
967
968 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
969 * specifier. They come from a register that's preloaded with 0xffffffff
970 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
971 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
972 */
973 #define TLB_TYPE_F16_COLOR (3 << 6)
974 #define TLB_TYPE_I32_COLOR (1 << 6)
975 #define TLB_TYPE_F32_COLOR (0 << 6)
976 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
977 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
978 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
979 #define TLB_F16_SWAP_HI_LO (1 << 1)
980 #define TLB_VEC_SIZE_4_F16 (1 << 0)
981 #define TLB_VEC_SIZE_2_F16 (0 << 0)
982 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
983
984 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
985 * flag is set.
986 */
987 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
988 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
989 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
990 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
991 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
992
993 /* Stencil is a single 32-bit write. */
994 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
995
996 static void
997 emit_frag_end(struct v3d_compile *c)
998 {
999 /* XXX
1000 if (c->output_sample_mask_index != -1) {
1001 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1002 }
1003 */
1004
1005 bool has_any_tlb_color_write = false;
1006 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1007 if (c->output_color_var[rt])
1008 has_any_tlb_color_write = true;
1009 }
1010
1011 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1012 struct nir_variable *var = c->output_color_var[0];
1013 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1014
1015 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1016 vir_AND(c,
1017 vir_MSF(c),
1018 vir_FTOC(c, color[3])));
1019 }
1020
1021 if (c->output_position_index != -1) {
1022 struct qinst *inst = vir_MOV_dest(c,
1023 vir_reg(QFILE_TLBU, 0),
1024 c->outputs[c->output_position_index]);
1025 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1026
1027 if (c->devinfo->ver >= 42) {
1028 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1029 TLB_SAMPLE_MODE_PER_PIXEL);
1030 } else
1031 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1032
1033 inst->src[vir_get_implicit_uniform_src(inst)] =
1034 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1035 } else if (c->s->info.fs.uses_discard ||
1036 c->fs_key->sample_alpha_to_coverage ||
1037 !has_any_tlb_color_write) {
1038 /* Emit passthrough Z if it needed to be delayed until shader
1039 * end due to potential discards.
1040 *
1041 * Since (single-threaded) fragment shaders always need a TLB
1042 * write, emit passthrouh Z if we didn't have any color
1043 * buffers and flag us as potentially discarding, so that we
1044 * can use Z as the TLB write.
1045 */
1046 c->s->info.fs.uses_discard = true;
1047
1048 struct qinst *inst = vir_MOV_dest(c,
1049 vir_reg(QFILE_TLBU, 0),
1050 vir_reg(QFILE_NULL, 0));
1051 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1052
1053 if (c->devinfo->ver >= 42) {
1054 /* The spec says the PER_PIXEL flag is ignored for
1055 * invariant writes, but the simulator demands it.
1056 */
1057 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1058 TLB_SAMPLE_MODE_PER_PIXEL);
1059 } else {
1060 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1061 }
1062
1063 inst->src[vir_get_implicit_uniform_src(inst)] =
1064 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1065 }
1066
1067 /* XXX: Performance improvement: Merge Z write and color writes TLB
1068 * uniform setup
1069 */
1070
1071 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1072 if (!c->output_color_var[rt])
1073 continue;
1074
1075 nir_variable *var = c->output_color_var[rt];
1076 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1077 int num_components = glsl_get_vector_elements(var->type);
1078 uint32_t conf = 0xffffff00;
1079 struct qinst *inst;
1080
1081 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1082 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1083
1084 if (c->fs_key->swap_color_rb & (1 << rt))
1085 num_components = MAX2(num_components, 3);
1086
1087 assert(num_components != 0);
1088 switch (glsl_get_base_type(var->type)) {
1089 case GLSL_TYPE_UINT:
1090 case GLSL_TYPE_INT:
1091 /* The F32 vs I32 distinction was dropped in 4.2. */
1092 if (c->devinfo->ver < 42)
1093 conf |= TLB_TYPE_I32_COLOR;
1094 else
1095 conf |= TLB_TYPE_F32_COLOR;
1096 conf |= ((num_components - 1) <<
1097 TLB_VEC_SIZE_MINUS_1_SHIFT);
1098
1099 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1100 inst->src[vir_get_implicit_uniform_src(inst)] =
1101 vir_uniform_ui(c, conf);
1102
1103 for (int i = 1; i < num_components; i++) {
1104 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1105 color[i]);
1106 }
1107 break;
1108
1109 default: {
1110 struct qreg r = color[0];
1111 struct qreg g = color[1];
1112 struct qreg b = color[2];
1113 struct qreg a = color[3];
1114
1115 if (c->fs_key->f32_color_rb & (1 << rt)) {
1116 conf |= TLB_TYPE_F32_COLOR;
1117 conf |= ((num_components - 1) <<
1118 TLB_VEC_SIZE_MINUS_1_SHIFT);
1119 } else {
1120 conf |= TLB_TYPE_F16_COLOR;
1121 conf |= TLB_F16_SWAP_HI_LO;
1122 if (num_components >= 3)
1123 conf |= TLB_VEC_SIZE_4_F16;
1124 else
1125 conf |= TLB_VEC_SIZE_2_F16;
1126 }
1127
1128 if (c->fs_key->swap_color_rb & (1 << rt)) {
1129 r = color[2];
1130 b = color[0];
1131 }
1132
1133 if (c->fs_key->sample_alpha_to_one)
1134 a = vir_uniform_f(c, 1.0);
1135
1136 if (c->fs_key->f32_color_rb & (1 << rt)) {
1137 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1138 inst->src[vir_get_implicit_uniform_src(inst)] =
1139 vir_uniform_ui(c, conf);
1140
1141 if (num_components >= 2)
1142 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1143 if (num_components >= 3)
1144 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1145 if (num_components >= 4)
1146 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1147 } else {
1148 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1149 if (conf != ~0) {
1150 inst->dst.file = QFILE_TLBU;
1151 inst->src[vir_get_implicit_uniform_src(inst)] =
1152 vir_uniform_ui(c, conf);
1153 }
1154
1155 if (num_components >= 3)
1156 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1157 }
1158 break;
1159 }
1160 }
1161 }
1162 }
1163
1164 static void
1165 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1166 {
1167 if (c->devinfo->ver >= 40) {
1168 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1169 *vpm_index = *vpm_index + 1;
1170 } else {
1171 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1172 }
1173
1174 c->num_vpm_writes++;
1175 }
1176
1177 static void
1178 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1179 uint32_t *vpm_index)
1180 {
1181 for (int i = 0; i < 2; i++) {
1182 struct qreg coord = c->outputs[c->output_position_index + i];
1183 coord = vir_FMUL(c, coord,
1184 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1185 0));
1186 coord = vir_FMUL(c, coord, rcp_w);
1187 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1188 }
1189
1190 }
1191
1192 static void
1193 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1194 {
1195 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1196 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1197
1198 struct qreg z = c->outputs[c->output_position_index + 2];
1199 z = vir_FMUL(c, z, zscale);
1200 z = vir_FMUL(c, z, rcp_w);
1201 z = vir_FADD(c, z, zoffset);
1202 vir_VPM_WRITE(c, z, vpm_index);
1203 }
1204
1205 static void
1206 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1207 {
1208 vir_VPM_WRITE(c, rcp_w, vpm_index);
1209 }
1210
1211 static void
1212 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1213 {
1214 struct qreg point_size;
1215
1216 if (c->output_point_size_index != -1)
1217 point_size = c->outputs[c->output_point_size_index];
1218 else
1219 point_size = vir_uniform_f(c, 1.0);
1220
1221 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1222 * BCM21553).
1223 */
1224 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1225
1226 vir_VPM_WRITE(c, point_size, vpm_index);
1227 }
1228
1229 static void
1230 emit_vpm_write_setup(struct v3d_compile *c)
1231 {
1232 if (c->devinfo->ver >= 40)
1233 return;
1234
1235 v3d33_vir_vpm_write_setup(c);
1236 }
1237
1238 /**
1239 * Sets up c->outputs[c->output_position_index] for the vertex shader
1240 * epilogue, if an output vertex position wasn't specified in the user's
1241 * shader. This may be the case for transform feedback with rasterizer
1242 * discard enabled.
1243 */
1244 static void
1245 setup_default_position(struct v3d_compile *c)
1246 {
1247 if (c->output_position_index != -1)
1248 return;
1249
1250 c->output_position_index = c->outputs_array_size;
1251 for (int i = 0; i < 4; i++) {
1252 add_output(c,
1253 c->output_position_index + i,
1254 VARYING_SLOT_POS, i);
1255 }
1256 }
1257
1258 static void
1259 emit_vert_end(struct v3d_compile *c)
1260 {
1261 setup_default_position(c);
1262
1263 uint32_t vpm_index = 0;
1264 struct qreg rcp_w = vir_RECIP(c,
1265 c->outputs[c->output_position_index + 3]);
1266
1267 emit_vpm_write_setup(c);
1268
1269 if (c->vs_key->is_coord) {
1270 for (int i = 0; i < 4; i++)
1271 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1272 &vpm_index);
1273 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1274 if (c->vs_key->per_vertex_point_size) {
1275 emit_point_size_write(c, &vpm_index);
1276 /* emit_rcp_wc_write(c, rcp_w); */
1277 }
1278 /* XXX: Z-only rendering */
1279 if (0)
1280 emit_zs_write(c, rcp_w, &vpm_index);
1281 } else {
1282 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1283 emit_zs_write(c, rcp_w, &vpm_index);
1284 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1285 if (c->vs_key->per_vertex_point_size)
1286 emit_point_size_write(c, &vpm_index);
1287 }
1288
1289 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1290 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1291 int j;
1292
1293 for (j = 0; j < c->num_outputs; j++) {
1294 struct v3d_varying_slot output = c->output_slots[j];
1295
1296 if (!memcmp(&input, &output, sizeof(input))) {
1297 vir_VPM_WRITE(c, c->outputs[j],
1298 &vpm_index);
1299 break;
1300 }
1301 }
1302 /* Emit padding if we didn't find a declared VS output for
1303 * this FS input.
1304 */
1305 if (j == c->num_outputs)
1306 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1307 &vpm_index);
1308 }
1309
1310 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1311 */
1312 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1313 vir_VPMWT(c);
1314 }
1315
1316 void
1317 v3d_optimize_nir(struct nir_shader *s)
1318 {
1319 bool progress;
1320
1321 do {
1322 progress = false;
1323
1324 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1325 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1326 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1327 NIR_PASS(progress, s, nir_copy_prop);
1328 NIR_PASS(progress, s, nir_opt_remove_phis);
1329 NIR_PASS(progress, s, nir_opt_dce);
1330 NIR_PASS(progress, s, nir_opt_dead_cf);
1331 NIR_PASS(progress, s, nir_opt_cse);
1332 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1333 NIR_PASS(progress, s, nir_opt_algebraic);
1334 NIR_PASS(progress, s, nir_opt_constant_folding);
1335 NIR_PASS(progress, s, nir_opt_undef);
1336 } while (progress);
1337
1338 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1339 }
1340
1341 static int
1342 driver_location_compare(const void *in_a, const void *in_b)
1343 {
1344 const nir_variable *const *a = in_a;
1345 const nir_variable *const *b = in_b;
1346
1347 return (*a)->data.driver_location - (*b)->data.driver_location;
1348 }
1349
1350 static struct qreg
1351 ntq_emit_vpm_read(struct v3d_compile *c,
1352 uint32_t *num_components_queued,
1353 uint32_t *remaining,
1354 uint32_t vpm_index)
1355 {
1356 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1357
1358 if (c->devinfo->ver >= 40 ) {
1359 return vir_LDVPMV_IN(c,
1360 vir_uniform_ui(c,
1361 (*num_components_queued)++));
1362 }
1363
1364 if (*num_components_queued != 0) {
1365 (*num_components_queued)--;
1366 c->num_inputs++;
1367 return vir_MOV(c, vpm);
1368 }
1369
1370 uint32_t num_components = MIN2(*remaining, 32);
1371
1372 v3d33_vir_vpm_read_setup(c, num_components);
1373
1374 *num_components_queued = num_components - 1;
1375 *remaining -= num_components;
1376 c->num_inputs++;
1377
1378 return vir_MOV(c, vpm);
1379 }
1380
1381 static void
1382 ntq_setup_vpm_inputs(struct v3d_compile *c)
1383 {
1384 /* Figure out how many components of each vertex attribute the shader
1385 * uses. Each variable should have been split to individual
1386 * components and unused ones DCEed. The vertex fetcher will load
1387 * from the start of the attribute to the number of components we
1388 * declare we need in c->vattr_sizes[].
1389 */
1390 nir_foreach_variable(var, &c->s->inputs) {
1391 /* No VS attribute array support. */
1392 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1393
1394 unsigned loc = var->data.driver_location;
1395 int start_component = var->data.location_frac;
1396 int num_components = glsl_get_components(var->type);
1397
1398 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1399 start_component + num_components);
1400 }
1401
1402 unsigned num_components = 0;
1403 uint32_t vpm_components_queued = 0;
1404 bool uses_iid = c->s->info.system_values_read &
1405 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1406 bool uses_vid = c->s->info.system_values_read &
1407 (1ull << SYSTEM_VALUE_VERTEX_ID);
1408 num_components += uses_iid;
1409 num_components += uses_vid;
1410
1411 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1412 num_components += c->vattr_sizes[i];
1413
1414 if (uses_iid) {
1415 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1416 &num_components, ~0);
1417 }
1418
1419 if (uses_vid) {
1420 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1421 &num_components, ~0);
1422 }
1423
1424 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1425 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1426 (loc + 1) * 4);
1427
1428 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1429 c->inputs[loc * 4 + i] =
1430 ntq_emit_vpm_read(c,
1431 &vpm_components_queued,
1432 &num_components,
1433 loc * 4 + i);
1434
1435 }
1436 }
1437
1438 if (c->devinfo->ver >= 40) {
1439 assert(vpm_components_queued == num_components);
1440 } else {
1441 assert(vpm_components_queued == 0);
1442 assert(num_components == 0);
1443 }
1444 }
1445
1446 static void
1447 ntq_setup_fs_inputs(struct v3d_compile *c)
1448 {
1449 unsigned num_entries = 0;
1450 unsigned num_components = 0;
1451 nir_foreach_variable(var, &c->s->inputs) {
1452 num_entries++;
1453 num_components += glsl_get_components(var->type);
1454 }
1455
1456 nir_variable *vars[num_entries];
1457
1458 unsigned i = 0;
1459 nir_foreach_variable(var, &c->s->inputs)
1460 vars[i++] = var;
1461
1462 /* Sort the variables so that we emit the input setup in
1463 * driver_location order. This is required for VPM reads, whose data
1464 * is fetched into the VPM in driver_location (TGSI register index)
1465 * order.
1466 */
1467 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1468
1469 for (unsigned i = 0; i < num_entries; i++) {
1470 nir_variable *var = vars[i];
1471 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1472 unsigned loc = var->data.driver_location;
1473
1474 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1475 (loc + array_len) * 4);
1476
1477 if (var->data.location == VARYING_SLOT_POS) {
1478 emit_fragcoord_input(c, loc);
1479 } else if (var->data.location == VARYING_SLOT_PNTC ||
1480 (var->data.location >= VARYING_SLOT_VAR0 &&
1481 (c->fs_key->point_sprite_mask &
1482 (1 << (var->data.location -
1483 VARYING_SLOT_VAR0))))) {
1484 c->inputs[loc * 4 + 0] = c->point_x;
1485 c->inputs[loc * 4 + 1] = c->point_y;
1486 } else {
1487 for (int j = 0; j < array_len; j++)
1488 emit_fragment_input(c, loc + j, var, j);
1489 }
1490 }
1491 }
1492
1493 static void
1494 ntq_setup_outputs(struct v3d_compile *c)
1495 {
1496 nir_foreach_variable(var, &c->s->outputs) {
1497 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1498 unsigned loc = var->data.driver_location * 4;
1499
1500 assert(array_len == 1);
1501 (void)array_len;
1502
1503 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1504 add_output(c, loc + var->data.location_frac + i,
1505 var->data.location,
1506 var->data.location_frac + i);
1507 }
1508
1509 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1510 switch (var->data.location) {
1511 case FRAG_RESULT_COLOR:
1512 c->output_color_var[0] = var;
1513 c->output_color_var[1] = var;
1514 c->output_color_var[2] = var;
1515 c->output_color_var[3] = var;
1516 break;
1517 case FRAG_RESULT_DATA0:
1518 case FRAG_RESULT_DATA1:
1519 case FRAG_RESULT_DATA2:
1520 case FRAG_RESULT_DATA3:
1521 c->output_color_var[var->data.location -
1522 FRAG_RESULT_DATA0] = var;
1523 break;
1524 case FRAG_RESULT_DEPTH:
1525 c->output_position_index = loc;
1526 break;
1527 case FRAG_RESULT_SAMPLE_MASK:
1528 c->output_sample_mask_index = loc;
1529 break;
1530 }
1531 } else {
1532 switch (var->data.location) {
1533 case VARYING_SLOT_POS:
1534 c->output_position_index = loc;
1535 break;
1536 case VARYING_SLOT_PSIZ:
1537 c->output_point_size_index = loc;
1538 break;
1539 }
1540 }
1541 }
1542 }
1543
1544 static void
1545 ntq_setup_uniforms(struct v3d_compile *c)
1546 {
1547 nir_foreach_variable(var, &c->s->uniforms) {
1548 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1549 false);
1550 unsigned vec4_size = 4 * sizeof(float);
1551
1552 declare_uniform_range(c, var->data.driver_location * vec4_size,
1553 vec4_count * vec4_size);
1554
1555 }
1556 }
1557
1558 /**
1559 * Sets up the mapping from nir_register to struct qreg *.
1560 *
1561 * Each nir_register gets a struct qreg per 32-bit component being stored.
1562 */
1563 static void
1564 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1565 {
1566 foreach_list_typed(nir_register, nir_reg, node, list) {
1567 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1568 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1569 array_len *
1570 nir_reg->num_components);
1571
1572 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1573
1574 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1575 qregs[i] = vir_get_temp(c);
1576 }
1577 }
1578
1579 static void
1580 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1581 {
1582 /* XXX perf: Experiment with using immediate loads to avoid having
1583 * these end up in the uniform stream. Watch out for breaking the
1584 * small immediates optimization in the process!
1585 */
1586 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1587 for (int i = 0; i < instr->def.num_components; i++)
1588 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1589
1590 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1591 }
1592
1593 static void
1594 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1595 {
1596 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1597
1598 /* VIR needs there to be *some* value, so pick 0 (same as for
1599 * ntq_setup_registers().
1600 */
1601 for (int i = 0; i < instr->def.num_components; i++)
1602 qregs[i] = vir_uniform_ui(c, 0);
1603 }
1604
1605 static void
1606 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1607 {
1608 unsigned offset;
1609
1610 switch (instr->intrinsic) {
1611 case nir_intrinsic_load_uniform:
1612 if (nir_src_is_const(instr->src[0])) {
1613 int offset = (nir_intrinsic_base(instr) +
1614 nir_src_as_uint(instr->src[0]));
1615 assert(offset % 4 == 0);
1616 /* We need dwords */
1617 offset = offset / 4;
1618 for (int i = 0; i < instr->num_components; i++) {
1619 ntq_store_dest(c, &instr->dest, i,
1620 vir_uniform(c, QUNIFORM_UNIFORM,
1621 offset + i));
1622 }
1623 } else {
1624 ntq_emit_tmu_general(c, instr);
1625 }
1626 break;
1627
1628 case nir_intrinsic_load_ubo:
1629 ntq_emit_tmu_general(c, instr);
1630 break;
1631
1632 case nir_intrinsic_load_user_clip_plane:
1633 for (int i = 0; i < instr->num_components; i++) {
1634 ntq_store_dest(c, &instr->dest, i,
1635 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1636 nir_intrinsic_ucp_id(instr) *
1637 4 + i));
1638 }
1639 break;
1640
1641 case nir_intrinsic_load_alpha_ref_float:
1642 ntq_store_dest(c, &instr->dest, 0,
1643 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1644 break;
1645
1646 case nir_intrinsic_load_sample_mask_in:
1647 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1648 break;
1649
1650 case nir_intrinsic_load_helper_invocation:
1651 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1652 ntq_store_dest(c, &instr->dest, 0,
1653 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1654 vir_uniform_ui(c, ~0),
1655 vir_uniform_ui(c, 0))));
1656 break;
1657
1658 case nir_intrinsic_load_front_face:
1659 /* The register contains 0 (front) or 1 (back), and we need to
1660 * turn it into a NIR bool where true means front.
1661 */
1662 ntq_store_dest(c, &instr->dest, 0,
1663 vir_ADD(c,
1664 vir_uniform_ui(c, -1),
1665 vir_REVF(c)));
1666 break;
1667
1668 case nir_intrinsic_load_instance_id:
1669 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1670 break;
1671
1672 case nir_intrinsic_load_vertex_id:
1673 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1674 break;
1675
1676 case nir_intrinsic_load_input:
1677 for (int i = 0; i < instr->num_components; i++) {
1678 offset = (nir_intrinsic_base(instr) +
1679 nir_src_as_uint(instr->src[0]));
1680 int comp = nir_intrinsic_component(instr) + i;
1681 ntq_store_dest(c, &instr->dest, i,
1682 vir_MOV(c, c->inputs[offset * 4 + comp]));
1683 }
1684 break;
1685
1686 case nir_intrinsic_store_output:
1687 offset = ((nir_intrinsic_base(instr) +
1688 nir_src_as_uint(instr->src[1])) * 4 +
1689 nir_intrinsic_component(instr));
1690
1691 for (int i = 0; i < instr->num_components; i++) {
1692 c->outputs[offset + i] =
1693 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1694 }
1695 c->num_outputs = MAX2(c->num_outputs,
1696 offset + instr->num_components);
1697 break;
1698
1699 case nir_intrinsic_discard:
1700 if (c->execute.file != QFILE_NULL) {
1701 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1702 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1703 vir_uniform_ui(c, 0)),
1704 V3D_QPU_COND_IFA);
1705 } else {
1706 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1707 vir_uniform_ui(c, 0));
1708 }
1709 break;
1710
1711 case nir_intrinsic_discard_if: {
1712 /* true (~0) if we're discarding */
1713 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1714
1715 if (c->execute.file != QFILE_NULL) {
1716 /* execute == 0 means the channel is active. Invert
1717 * the condition so that we can use zero as "executing
1718 * and discarding."
1719 */
1720 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1721 V3D_QPU_PF_PUSHZ);
1722 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1723 vir_uniform_ui(c, 0)),
1724 V3D_QPU_COND_IFA);
1725 } else {
1726 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1727 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1728 vir_uniform_ui(c, 0)),
1729 V3D_QPU_COND_IFNA);
1730 }
1731
1732 break;
1733 }
1734
1735 default:
1736 fprintf(stderr, "Unknown intrinsic: ");
1737 nir_print_instr(&instr->instr, stderr);
1738 fprintf(stderr, "\n");
1739 break;
1740 }
1741 }
1742
1743 /* Clears (activates) the execute flags for any channels whose jump target
1744 * matches this block.
1745 *
1746 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1747 * enabling?
1748 *
1749 * XXX perf: For uniform control flow, we should be able to skip c->execute
1750 * handling entirely.
1751 */
1752 static void
1753 ntq_activate_execute_for_block(struct v3d_compile *c)
1754 {
1755 vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0),
1756 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1757 V3D_QPU_PF_PUSHZ);
1758
1759 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1760 }
1761
1762 static void
1763 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1764 {
1765 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1766 bool empty_else_block =
1767 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1768 exec_list_is_empty(&nir_else_block->instr_list));
1769
1770 struct qblock *then_block = vir_new_block(c);
1771 struct qblock *after_block = vir_new_block(c);
1772 struct qblock *else_block;
1773 if (empty_else_block)
1774 else_block = after_block;
1775 else
1776 else_block = vir_new_block(c);
1777
1778 /* Set up the flags for the IF condition (taking the THEN branch). */
1779 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
1780 enum v3d_qpu_cond cond;
1781 if (!if_condition_alu ||
1782 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
1783 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
1784 V3D_QPU_PF_PUSHZ);
1785 cond = V3D_QPU_COND_IFNA;
1786 }
1787
1788 /* Jump to ELSE. */
1789 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1790 V3D_QPU_BRANCH_COND_ALLNA :
1791 V3D_QPU_BRANCH_COND_ALLA);
1792 vir_link_blocks(c->cur_block, else_block);
1793 vir_link_blocks(c->cur_block, then_block);
1794
1795 /* Process the THEN block. */
1796 vir_set_emit_block(c, then_block);
1797 ntq_emit_cf_list(c, &if_stmt->then_list);
1798
1799 if (!empty_else_block) {
1800 /* At the end of the THEN block, jump to ENDIF */
1801 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
1802 vir_link_blocks(c->cur_block, after_block);
1803
1804 /* Emit the else block. */
1805 vir_set_emit_block(c, else_block);
1806 ntq_activate_execute_for_block(c);
1807 ntq_emit_cf_list(c, &if_stmt->else_list);
1808 }
1809
1810 vir_link_blocks(c->cur_block, after_block);
1811
1812 vir_set_emit_block(c, after_block);
1813 }
1814
1815 static void
1816 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
1817 {
1818 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1819 bool empty_else_block =
1820 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1821 exec_list_is_empty(&nir_else_block->instr_list));
1822
1823 struct qblock *then_block = vir_new_block(c);
1824 struct qblock *after_block = vir_new_block(c);
1825 struct qblock *else_block;
1826 if (empty_else_block)
1827 else_block = after_block;
1828 else
1829 else_block = vir_new_block(c);
1830
1831 bool was_top_level = false;
1832 if (c->execute.file == QFILE_NULL) {
1833 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1834 was_top_level = true;
1835 }
1836
1837 /* Set up the flags for the IF condition (taking the THEN branch). */
1838 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
1839 enum v3d_qpu_cond cond;
1840 if (!if_condition_alu ||
1841 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
1842 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
1843 V3D_QPU_PF_PUSHZ);
1844 cond = V3D_QPU_COND_IFNA;
1845 }
1846
1847 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
1848 * was previously active (execute Z) for updating the exec flags.
1849 */
1850 if (was_top_level) {
1851 cond = v3d_qpu_cond_invert(cond);
1852 } else {
1853 struct qinst *inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0),
1854 c->execute);
1855 if (cond == V3D_QPU_COND_IFA) {
1856 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
1857 } else {
1858 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
1859 cond = V3D_QPU_COND_IFA;
1860 }
1861 }
1862
1863 vir_MOV_cond(c, cond,
1864 c->execute,
1865 vir_uniform_ui(c, else_block->index));
1866
1867 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1868 * through.
1869 */
1870 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1871 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1872 vir_link_blocks(c->cur_block, else_block);
1873 vir_link_blocks(c->cur_block, then_block);
1874
1875 /* Process the THEN block. */
1876 vir_set_emit_block(c, then_block);
1877 ntq_emit_cf_list(c, &if_stmt->then_list);
1878
1879 if (!empty_else_block) {
1880 /* Handle the end of the THEN block. First, all currently
1881 * active channels update their execute flags to point to
1882 * ENDIF
1883 */
1884 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1885 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1886 vir_uniform_ui(c, after_block->index));
1887
1888 /* If everything points at ENDIF, then jump there immediately. */
1889 vir_PF(c, vir_XOR(c, c->execute,
1890 vir_uniform_ui(c, after_block->index)),
1891 V3D_QPU_PF_PUSHZ);
1892 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1893 vir_link_blocks(c->cur_block, after_block);
1894 vir_link_blocks(c->cur_block, else_block);
1895
1896 vir_set_emit_block(c, else_block);
1897 ntq_activate_execute_for_block(c);
1898 ntq_emit_cf_list(c, &if_stmt->else_list);
1899 }
1900
1901 vir_link_blocks(c->cur_block, after_block);
1902
1903 vir_set_emit_block(c, after_block);
1904 if (was_top_level)
1905 c->execute = c->undef;
1906 else
1907 ntq_activate_execute_for_block(c);
1908 }
1909
1910 static void
1911 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
1912 {
1913 if (c->execute.file == QFILE_NULL &&
1914 nir_src_is_dynamically_uniform(nif->condition)) {
1915 ntq_emit_uniform_if(c, nif);
1916 } else {
1917 ntq_emit_nonuniform_if(c, nif);
1918 }
1919 }
1920
1921 static void
1922 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1923 {
1924 switch (jump->type) {
1925 case nir_jump_break:
1926 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1927 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1928 vir_uniform_ui(c, c->loop_break_block->index));
1929 break;
1930
1931 case nir_jump_continue:
1932 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1933 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1934 vir_uniform_ui(c, c->loop_cont_block->index));
1935 break;
1936
1937 case nir_jump_return:
1938 unreachable("All returns shouold be lowered\n");
1939 }
1940 }
1941
1942 static void
1943 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1944 {
1945 switch (instr->type) {
1946 case nir_instr_type_alu:
1947 ntq_emit_alu(c, nir_instr_as_alu(instr));
1948 break;
1949
1950 case nir_instr_type_intrinsic:
1951 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1952 break;
1953
1954 case nir_instr_type_load_const:
1955 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1956 break;
1957
1958 case nir_instr_type_ssa_undef:
1959 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1960 break;
1961
1962 case nir_instr_type_tex:
1963 ntq_emit_tex(c, nir_instr_as_tex(instr));
1964 break;
1965
1966 case nir_instr_type_jump:
1967 ntq_emit_jump(c, nir_instr_as_jump(instr));
1968 break;
1969
1970 default:
1971 fprintf(stderr, "Unknown NIR instr type: ");
1972 nir_print_instr(instr, stderr);
1973 fprintf(stderr, "\n");
1974 abort();
1975 }
1976 }
1977
1978 static void
1979 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1980 {
1981 nir_foreach_instr(instr, block) {
1982 ntq_emit_instr(c, instr);
1983 }
1984 }
1985
1986 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1987
1988 static void
1989 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1990 {
1991 bool was_top_level = false;
1992 if (c->execute.file == QFILE_NULL) {
1993 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1994 was_top_level = true;
1995 }
1996
1997 struct qblock *save_loop_cont_block = c->loop_cont_block;
1998 struct qblock *save_loop_break_block = c->loop_break_block;
1999
2000 c->loop_cont_block = vir_new_block(c);
2001 c->loop_break_block = vir_new_block(c);
2002
2003 vir_link_blocks(c->cur_block, c->loop_cont_block);
2004 vir_set_emit_block(c, c->loop_cont_block);
2005 ntq_activate_execute_for_block(c);
2006
2007 ntq_emit_cf_list(c, &loop->body);
2008
2009 /* Re-enable any previous continues now, so our ANYA check below
2010 * works.
2011 *
2012 * XXX: Use the .ORZ flags update, instead.
2013 */
2014 vir_PF(c, vir_XOR(c,
2015 c->execute,
2016 vir_uniform_ui(c, c->loop_cont_block->index)),
2017 V3D_QPU_PF_PUSHZ);
2018 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2019
2020 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2021
2022 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2023 /* Pixels that were not dispatched or have been discarded should not
2024 * contribute to looping again.
2025 */
2026 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2027 vir_link_blocks(c->cur_block, c->loop_cont_block);
2028 vir_link_blocks(c->cur_block, c->loop_break_block);
2029
2030 vir_set_emit_block(c, c->loop_break_block);
2031 if (was_top_level)
2032 c->execute = c->undef;
2033 else
2034 ntq_activate_execute_for_block(c);
2035
2036 c->loop_break_block = save_loop_break_block;
2037 c->loop_cont_block = save_loop_cont_block;
2038
2039 c->loops++;
2040 }
2041
2042 static void
2043 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2044 {
2045 fprintf(stderr, "FUNCTIONS not handled.\n");
2046 abort();
2047 }
2048
2049 static void
2050 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2051 {
2052 foreach_list_typed(nir_cf_node, node, node, list) {
2053 switch (node->type) {
2054 case nir_cf_node_block:
2055 ntq_emit_block(c, nir_cf_node_as_block(node));
2056 break;
2057
2058 case nir_cf_node_if:
2059 ntq_emit_if(c, nir_cf_node_as_if(node));
2060 break;
2061
2062 case nir_cf_node_loop:
2063 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2064 break;
2065
2066 case nir_cf_node_function:
2067 ntq_emit_function(c, nir_cf_node_as_function(node));
2068 break;
2069
2070 default:
2071 fprintf(stderr, "Unknown NIR node type\n");
2072 abort();
2073 }
2074 }
2075 }
2076
2077 static void
2078 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2079 {
2080 ntq_setup_registers(c, &impl->registers);
2081 ntq_emit_cf_list(c, &impl->body);
2082 }
2083
2084 static void
2085 nir_to_vir(struct v3d_compile *c)
2086 {
2087 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2088 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2089 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2090 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2091
2092 /* XXX perf: We could set the "disable implicit point/line
2093 * varyings" field in the shader record and not emit these, if
2094 * they're not going to be used.
2095 */
2096 if (c->fs_key->is_points) {
2097 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2098 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2099 } else if (c->fs_key->is_lines) {
2100 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2101 }
2102 }
2103
2104 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2105 ntq_setup_fs_inputs(c);
2106 else
2107 ntq_setup_vpm_inputs(c);
2108
2109 ntq_setup_outputs(c);
2110 ntq_setup_uniforms(c);
2111 ntq_setup_registers(c, &c->s->registers);
2112
2113 /* Find the main function and emit the body. */
2114 nir_foreach_function(function, c->s) {
2115 assert(strcmp(function->name, "main") == 0);
2116 assert(function->impl);
2117 ntq_emit_impl(c, function->impl);
2118 }
2119 }
2120
2121 const nir_shader_compiler_options v3d_nir_options = {
2122 .lower_all_io_to_temps = true,
2123 .lower_extract_byte = true,
2124 .lower_extract_word = true,
2125 .lower_bfm = true,
2126 .lower_bitfield_insert_to_shifts = true,
2127 .lower_bitfield_extract_to_shifts = true,
2128 .lower_bitfield_reverse = true,
2129 .lower_bit_count = true,
2130 .lower_pack_unorm_2x16 = true,
2131 .lower_pack_snorm_2x16 = true,
2132 .lower_pack_unorm_4x8 = true,
2133 .lower_pack_snorm_4x8 = true,
2134 .lower_unpack_unorm_4x8 = true,
2135 .lower_unpack_snorm_4x8 = true,
2136 .lower_pack_half_2x16 = true,
2137 .lower_unpack_half_2x16 = true,
2138 .lower_fdiv = true,
2139 .lower_find_lsb = true,
2140 .lower_ffma = true,
2141 .lower_flrp32 = true,
2142 .lower_fpow = true,
2143 .lower_fsat = true,
2144 .lower_fsqrt = true,
2145 .lower_ifind_msb = true,
2146 .lower_ldexp = true,
2147 .lower_mul_high = true,
2148 .lower_wpos_pntc = true,
2149 .native_integers = true,
2150 };
2151
2152 /**
2153 * When demoting a shader down to single-threaded, removes the THRSW
2154 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2155 * program end).
2156 */
2157 static void
2158 vir_remove_thrsw(struct v3d_compile *c)
2159 {
2160 vir_for_each_block(block, c) {
2161 vir_for_each_inst_safe(inst, block) {
2162 if (inst->qpu.sig.thrsw)
2163 vir_remove_instruction(c, inst);
2164 }
2165 }
2166
2167 c->last_thrsw = NULL;
2168 }
2169
2170 void
2171 vir_emit_last_thrsw(struct v3d_compile *c)
2172 {
2173 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2174 * switching, so disable threads if we didn't do any TMU ops (each of
2175 * which would have emitted a THRSW).
2176 */
2177 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2178 c->threads = 1;
2179 if (c->last_thrsw)
2180 vir_remove_thrsw(c);
2181 return;
2182 }
2183
2184 /* If we're threaded and the last THRSW was in conditional code, then
2185 * we need to emit another one so that we can flag it as the last
2186 * thrsw.
2187 */
2188 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2189 assert(c->devinfo->ver >= 41);
2190 vir_emit_thrsw(c);
2191 }
2192
2193 /* If we're threaded, then we need to mark the last THRSW instruction
2194 * so we can emit a pair of them at QPU emit time.
2195 *
2196 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2197 * post-last-THRSW state, so we can skip this.
2198 */
2199 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2200 assert(c->devinfo->ver >= 41);
2201 vir_emit_thrsw(c);
2202 }
2203
2204 if (c->last_thrsw)
2205 c->last_thrsw->is_last_thrsw = true;
2206 }
2207
2208 /* There's a flag in the shader for "center W is needed for reasons other than
2209 * non-centroid varyings", so we just walk the program after VIR optimization
2210 * to see if it's used. It should be harmless to set even if we only use
2211 * center W for varyings.
2212 */
2213 static void
2214 vir_check_payload_w(struct v3d_compile *c)
2215 {
2216 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2217 return;
2218
2219 vir_for_each_inst_inorder(inst, c) {
2220 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2221 if (inst->src[i].file == QFILE_REG &&
2222 inst->src[i].index == 0) {
2223 c->uses_center_w = true;
2224 return;
2225 }
2226 }
2227 }
2228
2229 }
2230
2231 void
2232 v3d_nir_to_vir(struct v3d_compile *c)
2233 {
2234 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2235 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2236 fprintf(stderr, "%s prog %d/%d NIR:\n",
2237 vir_get_stage_name(c),
2238 c->program_id, c->variant_id);
2239 nir_print_shader(c->s, stderr);
2240 }
2241
2242 nir_to_vir(c);
2243
2244 /* Emit the last THRSW before STVPM and TLB writes. */
2245 vir_emit_last_thrsw(c);
2246
2247 switch (c->s->info.stage) {
2248 case MESA_SHADER_FRAGMENT:
2249 emit_frag_end(c);
2250 break;
2251 case MESA_SHADER_VERTEX:
2252 emit_vert_end(c);
2253 break;
2254 default:
2255 unreachable("bad stage");
2256 }
2257
2258 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2259 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2260 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2261 vir_get_stage_name(c),
2262 c->program_id, c->variant_id);
2263 vir_dump(c);
2264 fprintf(stderr, "\n");
2265 }
2266
2267 vir_optimize(c);
2268 vir_lower_uniforms(c);
2269
2270 vir_check_payload_w(c);
2271
2272 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2273 * We used that on that platform to pipeline TMU writes and reduce the
2274 * number of thread switches, as well as try (mostly successfully) to
2275 * reduce maximum register pressure to allow more threads. We should
2276 * do something of that sort for V3D -- either instruction scheduling
2277 * here, or delay the the THRSW and LDTMUs from our texture
2278 * instructions until the results are needed.
2279 */
2280
2281 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2282 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2283 fprintf(stderr, "%s prog %d/%d VIR:\n",
2284 vir_get_stage_name(c),
2285 c->program_id, c->variant_id);
2286 vir_dump(c);
2287 fprintf(stderr, "\n");
2288 }
2289
2290 /* Attempt to allocate registers for the temporaries. If we fail,
2291 * reduce thread count and try again.
2292 */
2293 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2294 struct qpu_reg *temp_registers;
2295 while (true) {
2296 bool spilled;
2297 temp_registers = v3d_register_allocate(c, &spilled);
2298 if (spilled)
2299 continue;
2300
2301 if (temp_registers)
2302 break;
2303
2304 if (c->threads == min_threads) {
2305 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2306 c->threads);
2307 vir_dump(c);
2308 c->failed = true;
2309 return;
2310 }
2311
2312 c->threads /= 2;
2313
2314 if (c->threads == 1)
2315 vir_remove_thrsw(c);
2316 }
2317
2318 v3d_vir_to_qpu(c, temp_registers);
2319 }