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v3d: Move the stores for fixed function VS output reads into NIR.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (vir_in_nonuniform_control_flow(c)) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->src[vir_get_implicit_uniform_src(tmu)] =
309 vir_uniform_ui(c, config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert(result.file == QFILE_UNIF ||
358 (result.file == QFILE_TEMP &&
359 last_inst && last_inst == c->defs[result.index]));
360
361 if (dest->is_ssa) {
362 assert(chan < dest->ssa.num_components);
363
364 struct qreg *qregs;
365 struct hash_entry *entry =
366 _mesa_hash_table_search(c->def_ht, &dest->ssa);
367
368 if (entry)
369 qregs = entry->data;
370 else
371 qregs = ntq_init_ssa_def(c, &dest->ssa);
372
373 qregs[chan] = result;
374 } else {
375 nir_register *reg = dest->reg.reg;
376 assert(dest->reg.base_offset == 0);
377 assert(reg->num_array_elems == 0);
378 struct hash_entry *entry =
379 _mesa_hash_table_search(c->def_ht, reg);
380 struct qreg *qregs = entry->data;
381
382 /* Insert a MOV if the source wasn't an SSA def in the
383 * previous instruction.
384 */
385 if (result.file == QFILE_UNIF) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 }
409 }
410 }
411
412 struct qreg
413 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
414 {
415 struct hash_entry *entry;
416 if (src.is_ssa) {
417 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
418 assert(i < src.ssa->num_components);
419 } else {
420 nir_register *reg = src.reg.reg;
421 entry = _mesa_hash_table_search(c->def_ht, reg);
422 assert(reg->num_array_elems == 0);
423 assert(src.reg.base_offset == 0);
424 assert(i < reg->num_components);
425 }
426
427 struct qreg *qregs = entry->data;
428 return qregs[i];
429 }
430
431 static struct qreg
432 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
433 unsigned src)
434 {
435 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
436 unsigned chan = ffs(instr->dest.write_mask) - 1;
437 struct qreg r = ntq_get_src(c, instr->src[src].src,
438 instr->src[src].swizzle[chan]);
439
440 assert(!instr->src[src].abs);
441 assert(!instr->src[src].negate);
442
443 return r;
444 };
445
446 static struct qreg
447 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
448 {
449 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
450 }
451
452 static void
453 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
454 {
455 unsigned unit = instr->texture_index;
456 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
457 int dest_size = nir_tex_instr_dest_size(instr);
458
459 struct qreg lod = c->undef;
460 if (lod_index != -1)
461 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
462
463 for (int i = 0; i < dest_size; i++) {
464 assert(i < 3);
465 enum quniform_contents contents;
466
467 if (instr->is_array && i == dest_size - 1)
468 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
469 else
470 contents = QUNIFORM_TEXTURE_WIDTH + i;
471
472 struct qreg size = vir_uniform(c, contents, unit);
473
474 switch (instr->sampler_dim) {
475 case GLSL_SAMPLER_DIM_1D:
476 case GLSL_SAMPLER_DIM_2D:
477 case GLSL_SAMPLER_DIM_MS:
478 case GLSL_SAMPLER_DIM_3D:
479 case GLSL_SAMPLER_DIM_CUBE:
480 /* Don't minify the array size. */
481 if (!(instr->is_array && i == dest_size - 1)) {
482 size = ntq_minify(c, size, lod);
483 }
484 break;
485
486 case GLSL_SAMPLER_DIM_RECT:
487 /* There's no LOD field for rects */
488 break;
489
490 default:
491 unreachable("Bad sampler type");
492 }
493
494 ntq_store_dest(c, &instr->dest, i, size);
495 }
496 }
497
498 static void
499 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
500 {
501 unsigned unit = instr->texture_index;
502
503 /* Since each texture sampling op requires uploading uniforms to
504 * reference the texture, there's no HW support for texture size and
505 * you just upload uniforms containing the size.
506 */
507 switch (instr->op) {
508 case nir_texop_query_levels:
509 ntq_store_dest(c, &instr->dest, 0,
510 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
511 return;
512 case nir_texop_txs:
513 ntq_emit_txs(c, instr);
514 return;
515 default:
516 break;
517 }
518
519 if (c->devinfo->ver >= 40)
520 v3d40_vir_emit_tex(c, instr);
521 else
522 v3d33_vir_emit_tex(c, instr);
523 }
524
525 static struct qreg
526 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
527 {
528 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
529 if (is_cos)
530 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
531
532 struct qreg periods = vir_FROUND(c, input);
533 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
534 return vir_XOR(c, sin_output, vir_SHL(c,
535 vir_FTOIN(c, periods),
536 vir_uniform_ui(c, -1)));
537 }
538
539 static struct qreg
540 ntq_fsign(struct v3d_compile *c, struct qreg src)
541 {
542 struct qreg t = vir_get_temp(c);
543
544 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
545 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
546 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
547 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
548 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
549 return vir_MOV(c, t);
550 }
551
552 static void
553 emit_fragcoord_input(struct v3d_compile *c, int attr)
554 {
555 c->inputs[attr * 4 + 0] = vir_FXCD(c);
556 c->inputs[attr * 4 + 1] = vir_FYCD(c);
557 c->inputs[attr * 4 + 2] = c->payload_z;
558 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
559 }
560
561 static struct qreg
562 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
563 uint8_t swizzle, int array_index)
564 {
565 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
566 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
567
568 struct qreg vary;
569 if (c->devinfo->ver >= 41) {
570 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
571 c->undef, c->undef);
572 ldvary->qpu.sig.ldvary = true;
573 vary = vir_emit_def(c, ldvary);
574 } else {
575 vir_NOP(c)->qpu.sig.ldvary = true;
576 vary = r3;
577 }
578
579 /* For gl_PointCoord input or distance along a line, we'll be called
580 * with no nir_variable, and we don't count toward VPM size so we
581 * don't track an input slot.
582 */
583 if (!var) {
584 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
585 }
586
587 int i = c->num_inputs++;
588 c->input_slots[i] =
589 v3d_slot_from_slot_and_component(var->data.location +
590 array_index, swizzle);
591
592 switch (var->data.interpolation) {
593 case INTERP_MODE_NONE:
594 /* If a gl_FrontColor or gl_BackColor input has no interp
595 * qualifier, then if we're using glShadeModel(GL_FLAT) it
596 * needs to be flat shaded.
597 */
598 switch (var->data.location + array_index) {
599 case VARYING_SLOT_COL0:
600 case VARYING_SLOT_COL1:
601 case VARYING_SLOT_BFC0:
602 case VARYING_SLOT_BFC1:
603 if (c->fs_key->shade_model_flat) {
604 BITSET_SET(c->flat_shade_flags, i);
605 vir_MOV_dest(c, c->undef, vary);
606 return vir_MOV(c, r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary,
609 c->payload_w), r5);
610 }
611 default:
612 break;
613 }
614 /* FALLTHROUGH */
615 case INTERP_MODE_SMOOTH:
616 if (var->data.centroid) {
617 BITSET_SET(c->centroid_flags, i);
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w_centroid), r5);
620 } else {
621 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
622 }
623 case INTERP_MODE_NOPERSPECTIVE:
624 BITSET_SET(c->noperspective_flags, i);
625 return vir_FADD(c, vir_MOV(c, vary), r5);
626 case INTERP_MODE_FLAT:
627 BITSET_SET(c->flat_shade_flags, i);
628 vir_MOV_dest(c, c->undef, vary);
629 return vir_MOV(c, r5);
630 default:
631 unreachable("Bad interp mode");
632 }
633 }
634
635 static void
636 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
637 int array_index)
638 {
639 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
640 int chan = var->data.location_frac + i;
641 c->inputs[attr * 4 + chan] =
642 emit_fragment_varying(c, var, chan, array_index);
643 }
644 }
645
646 static void
647 add_output(struct v3d_compile *c,
648 uint32_t decl_offset,
649 uint8_t slot,
650 uint8_t swizzle)
651 {
652 uint32_t old_array_size = c->outputs_array_size;
653 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
654 decl_offset + 1);
655
656 if (old_array_size != c->outputs_array_size) {
657 c->output_slots = reralloc(c,
658 c->output_slots,
659 struct v3d_varying_slot,
660 c->outputs_array_size);
661 }
662
663 c->output_slots[decl_offset] =
664 v3d_slot_from_slot_and_component(slot, swizzle);
665 }
666
667 static void
668 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
669 {
670 unsigned array_id = c->num_ubo_ranges++;
671 if (array_id >= c->ubo_ranges_array_size) {
672 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
673 array_id + 1);
674 c->ubo_ranges = reralloc(c, c->ubo_ranges,
675 struct v3d_ubo_range,
676 c->ubo_ranges_array_size);
677 c->ubo_range_used = reralloc(c, c->ubo_range_used,
678 bool,
679 c->ubo_ranges_array_size);
680 }
681
682 c->ubo_ranges[array_id].dst_offset = 0;
683 c->ubo_ranges[array_id].src_offset = start;
684 c->ubo_ranges[array_id].size = size;
685 c->ubo_range_used[array_id] = false;
686 }
687
688 /**
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
692 */
693 static bool
694 ntq_emit_comparison(struct v3d_compile *c,
695 nir_alu_instr *compare_instr,
696 enum v3d_qpu_cond *out_cond)
697 {
698 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
699 struct qreg src1;
700 if (nir_op_infos[compare_instr->op].num_inputs > 1)
701 src1 = ntq_get_alu_src(c, compare_instr, 1);
702 bool cond_invert = false;
703 struct qreg nop = vir_nop_reg();
704
705 switch (compare_instr->op) {
706 case nir_op_feq32:
707 case nir_op_seq:
708 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
709 break;
710 case nir_op_ieq32:
711 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
712 break;
713
714 case nir_op_fne32:
715 case nir_op_sne:
716 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719 case nir_op_ine32:
720 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
721 cond_invert = true;
722 break;
723
724 case nir_op_fge32:
725 case nir_op_sge:
726 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ige32:
729 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732 case nir_op_uge32:
733 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
734 cond_invert = true;
735 break;
736
737 case nir_op_slt:
738 case nir_op_flt32:
739 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
740 break;
741 case nir_op_ilt32:
742 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
743 break;
744 case nir_op_ult32:
745 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
746 break;
747
748 case nir_op_i2b32:
749 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
750 cond_invert = true;
751 break;
752
753 case nir_op_f2b32:
754 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
755 cond_invert = true;
756 break;
757
758 default:
759 return false;
760 }
761
762 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
763
764 return true;
765 }
766
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
769 */
770 static struct nir_alu_instr *
771 ntq_get_alu_parent(nir_src src)
772 {
773 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
774 return NULL;
775 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
776 if (!instr)
777 return NULL;
778
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
781 * src.
782 */
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 if (!instr->src[i].src.is_ssa)
785 return NULL;
786 }
787
788 return instr;
789 }
790
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
794 {
795 nir_alu_instr *compare = ntq_get_alu_parent(src);
796 if (!compare)
797 goto out;
798
799 enum v3d_qpu_cond cond;
800 if (ntq_emit_comparison(c, compare, &cond))
801 return cond;
802
803 out:
804 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
805 V3D_QPU_PF_PUSHZ);
806 return V3D_QPU_COND_IFNA;
807 }
808
809 static void
810 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
811 {
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr->dest.saturate);
814
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
818 */
819 if (instr->op == nir_op_vec2 ||
820 instr->op == nir_op_vec3 ||
821 instr->op == nir_op_vec4) {
822 struct qreg srcs[4];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
824 srcs[i] = ntq_get_src(c, instr->src[i].src,
825 instr->src[i].swizzle[0]);
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
827 ntq_store_dest(c, &instr->dest.dest, i,
828 vir_MOV(c, srcs[i]));
829 return;
830 }
831
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src[nir_op_infos[instr->op].num_inputs];
834 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
835 src[i] = ntq_get_alu_src(c, instr, i);
836 }
837
838 struct qreg result;
839
840 switch (instr->op) {
841 case nir_op_fmov:
842 case nir_op_imov:
843 result = vir_MOV(c, src[0]);
844 break;
845
846 case nir_op_fneg:
847 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
848 break;
849 case nir_op_ineg:
850 result = vir_NEG(c, src[0]);
851 break;
852
853 case nir_op_fmul:
854 result = vir_FMUL(c, src[0], src[1]);
855 break;
856 case nir_op_fadd:
857 result = vir_FADD(c, src[0], src[1]);
858 break;
859 case nir_op_fsub:
860 result = vir_FSUB(c, src[0], src[1]);
861 break;
862 case nir_op_fmin:
863 result = vir_FMIN(c, src[0], src[1]);
864 break;
865 case nir_op_fmax:
866 result = vir_FMAX(c, src[0], src[1]);
867 break;
868
869 case nir_op_f2i32: {
870 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
871 if (src0_alu && src0_alu->op == nir_op_fround_even) {
872 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
873 } else {
874 result = vir_FTOIZ(c, src[0]);
875 }
876 break;
877 }
878
879 case nir_op_f2u32:
880 result = vir_FTOUZ(c, src[0]);
881 break;
882 case nir_op_i2f32:
883 result = vir_ITOF(c, src[0]);
884 break;
885 case nir_op_u2f32:
886 result = vir_UTOF(c, src[0]);
887 break;
888 case nir_op_b2f32:
889 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
890 break;
891 case nir_op_b2i32:
892 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
893 break;
894
895 case nir_op_iadd:
896 result = vir_ADD(c, src[0], src[1]);
897 break;
898 case nir_op_ushr:
899 result = vir_SHR(c, src[0], src[1]);
900 break;
901 case nir_op_isub:
902 result = vir_SUB(c, src[0], src[1]);
903 break;
904 case nir_op_ishr:
905 result = vir_ASR(c, src[0], src[1]);
906 break;
907 case nir_op_ishl:
908 result = vir_SHL(c, src[0], src[1]);
909 break;
910 case nir_op_imin:
911 result = vir_MIN(c, src[0], src[1]);
912 break;
913 case nir_op_umin:
914 result = vir_UMIN(c, src[0], src[1]);
915 break;
916 case nir_op_imax:
917 result = vir_MAX(c, src[0], src[1]);
918 break;
919 case nir_op_umax:
920 result = vir_UMAX(c, src[0], src[1]);
921 break;
922 case nir_op_iand:
923 result = vir_AND(c, src[0], src[1]);
924 break;
925 case nir_op_ior:
926 result = vir_OR(c, src[0], src[1]);
927 break;
928 case nir_op_ixor:
929 result = vir_XOR(c, src[0], src[1]);
930 break;
931 case nir_op_inot:
932 result = vir_NOT(c, src[0]);
933 break;
934
935 case nir_op_ufind_msb:
936 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
937 break;
938
939 case nir_op_imul:
940 result = vir_UMUL(c, src[0], src[1]);
941 break;
942
943 case nir_op_seq:
944 case nir_op_sne:
945 case nir_op_sge:
946 case nir_op_slt: {
947 enum v3d_qpu_cond cond;
948 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
949 assert(ok);
950 result = vir_MOV(c, vir_SEL(c, cond,
951 vir_uniform_f(c, 1.0),
952 vir_uniform_f(c, 0.0)));
953 break;
954 }
955
956 case nir_op_i2b32:
957 case nir_op_f2b32:
958 case nir_op_feq32:
959 case nir_op_fne32:
960 case nir_op_fge32:
961 case nir_op_flt32:
962 case nir_op_ieq32:
963 case nir_op_ine32:
964 case nir_op_ige32:
965 case nir_op_uge32:
966 case nir_op_ilt32:
967 case nir_op_ult32: {
968 enum v3d_qpu_cond cond;
969 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
970 assert(ok);
971 result = vir_MOV(c, vir_SEL(c, cond,
972 vir_uniform_ui(c, ~0),
973 vir_uniform_ui(c, 0)));
974 break;
975 }
976
977 case nir_op_b32csel:
978 result = vir_MOV(c,
979 vir_SEL(c,
980 ntq_emit_bool_to_cond(c, instr->src[0].src),
981 src[1], src[2]));
982 break;
983
984 case nir_op_fcsel:
985 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
986 V3D_QPU_PF_PUSHZ);
987 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
988 src[1], src[2]));
989 break;
990
991 case nir_op_frcp:
992 result = vir_RECIP(c, src[0]);
993 break;
994 case nir_op_frsq:
995 result = vir_RSQRT(c, src[0]);
996 break;
997 case nir_op_fexp2:
998 result = vir_EXP(c, src[0]);
999 break;
1000 case nir_op_flog2:
1001 result = vir_LOG(c, src[0]);
1002 break;
1003
1004 case nir_op_fceil:
1005 result = vir_FCEIL(c, src[0]);
1006 break;
1007 case nir_op_ffloor:
1008 result = vir_FFLOOR(c, src[0]);
1009 break;
1010 case nir_op_fround_even:
1011 result = vir_FROUND(c, src[0]);
1012 break;
1013 case nir_op_ftrunc:
1014 result = vir_FTRUNC(c, src[0]);
1015 break;
1016
1017 case nir_op_fsin:
1018 result = ntq_fsincos(c, src[0], false);
1019 break;
1020 case nir_op_fcos:
1021 result = ntq_fsincos(c, src[0], true);
1022 break;
1023
1024 case nir_op_fsign:
1025 result = ntq_fsign(c, src[0]);
1026 break;
1027
1028 case nir_op_fabs: {
1029 result = vir_FMOV(c, src[0]);
1030 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1031 break;
1032 }
1033
1034 case nir_op_iabs:
1035 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1036 break;
1037
1038 case nir_op_fddx:
1039 case nir_op_fddx_coarse:
1040 case nir_op_fddx_fine:
1041 result = vir_FDX(c, src[0]);
1042 break;
1043
1044 case nir_op_fddy:
1045 case nir_op_fddy_coarse:
1046 case nir_op_fddy_fine:
1047 result = vir_FDY(c, src[0]);
1048 break;
1049
1050 case nir_op_uadd_carry:
1051 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1052 V3D_QPU_PF_PUSHC);
1053 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1054 vir_uniform_ui(c, ~0),
1055 vir_uniform_ui(c, 0)));
1056 break;
1057
1058 case nir_op_pack_half_2x16_split:
1059 result = vir_VFPACK(c, src[0], src[1]);
1060 break;
1061
1062 case nir_op_unpack_half_2x16_split_x:
1063 result = vir_FMOV(c, src[0]);
1064 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1065 break;
1066
1067 case nir_op_unpack_half_2x16_split_y:
1068 result = vir_FMOV(c, src[0]);
1069 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1070 break;
1071
1072 default:
1073 fprintf(stderr, "unknown NIR ALU inst: ");
1074 nir_print_instr(&instr->instr, stderr);
1075 fprintf(stderr, "\n");
1076 abort();
1077 }
1078
1079 /* We have a scalar result, so the instruction should only have a
1080 * single channel written to.
1081 */
1082 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1083 ntq_store_dest(c, &instr->dest.dest,
1084 ffs(instr->dest.write_mask) - 1, result);
1085 }
1086
1087 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1088 * specifier. They come from a register that's preloaded with 0xffffffff
1089 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1090 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1091 */
1092 #define TLB_TYPE_F16_COLOR (3 << 6)
1093 #define TLB_TYPE_I32_COLOR (1 << 6)
1094 #define TLB_TYPE_F32_COLOR (0 << 6)
1095 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1096 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1097 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1098 #define TLB_F16_SWAP_HI_LO (1 << 1)
1099 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1100 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1101 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1102
1103 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1104 * flag is set.
1105 */
1106 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1107 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1108 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1109 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1110 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1111
1112 /* Stencil is a single 32-bit write. */
1113 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1114
1115 static void
1116 emit_frag_end(struct v3d_compile *c)
1117 {
1118 /* XXX
1119 if (c->output_sample_mask_index != -1) {
1120 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1121 }
1122 */
1123
1124 bool has_any_tlb_color_write = false;
1125 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1126 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1127 has_any_tlb_color_write = true;
1128 }
1129
1130 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1131 struct nir_variable *var = c->output_color_var[0];
1132 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1133
1134 vir_SETMSF_dest(c, vir_nop_reg(),
1135 vir_AND(c,
1136 vir_MSF(c),
1137 vir_FTOC(c, color[3])));
1138 }
1139
1140 if (c->output_position_index != -1) {
1141 struct qinst *inst = vir_MOV_dest(c,
1142 vir_reg(QFILE_TLBU, 0),
1143 c->outputs[c->output_position_index]);
1144 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1145
1146 if (c->devinfo->ver >= 42) {
1147 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1148 TLB_SAMPLE_MODE_PER_PIXEL);
1149 } else
1150 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1151
1152 inst->src[vir_get_implicit_uniform_src(inst)] =
1153 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1154 c->writes_z = true;
1155 } else if (c->s->info.fs.uses_discard ||
1156 !c->s->info.fs.early_fragment_tests ||
1157 c->fs_key->sample_alpha_to_coverage ||
1158 !has_any_tlb_color_write) {
1159 /* Emit passthrough Z if it needed to be delayed until shader
1160 * end due to potential discards.
1161 *
1162 * Since (single-threaded) fragment shaders always need a TLB
1163 * write, emit passthrouh Z if we didn't have any color
1164 * buffers and flag us as potentially discarding, so that we
1165 * can use Z as the TLB write.
1166 */
1167 c->s->info.fs.uses_discard = true;
1168
1169 struct qinst *inst = vir_MOV_dest(c,
1170 vir_reg(QFILE_TLBU, 0),
1171 vir_nop_reg());
1172 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1173
1174 if (c->devinfo->ver >= 42) {
1175 /* The spec says the PER_PIXEL flag is ignored for
1176 * invariant writes, but the simulator demands it.
1177 */
1178 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1179 TLB_SAMPLE_MODE_PER_PIXEL);
1180 } else {
1181 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1182 }
1183
1184 inst->src[vir_get_implicit_uniform_src(inst)] =
1185 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1186 c->writes_z = true;
1187 }
1188
1189 /* XXX: Performance improvement: Merge Z write and color writes TLB
1190 * uniform setup
1191 */
1192
1193 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1194 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1195 continue;
1196
1197 nir_variable *var = c->output_color_var[rt];
1198 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1199 int num_components = glsl_get_vector_elements(var->type);
1200 uint32_t conf = 0xffffff00;
1201 struct qinst *inst;
1202
1203 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1204 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1205
1206 if (c->fs_key->swap_color_rb & (1 << rt))
1207 num_components = MAX2(num_components, 3);
1208
1209 assert(num_components != 0);
1210 switch (glsl_get_base_type(var->type)) {
1211 case GLSL_TYPE_UINT:
1212 case GLSL_TYPE_INT:
1213 /* The F32 vs I32 distinction was dropped in 4.2. */
1214 if (c->devinfo->ver < 42)
1215 conf |= TLB_TYPE_I32_COLOR;
1216 else
1217 conf |= TLB_TYPE_F32_COLOR;
1218 conf |= ((num_components - 1) <<
1219 TLB_VEC_SIZE_MINUS_1_SHIFT);
1220
1221 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1222 inst->src[vir_get_implicit_uniform_src(inst)] =
1223 vir_uniform_ui(c, conf);
1224
1225 for (int i = 1; i < num_components; i++) {
1226 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1227 color[i]);
1228 }
1229 break;
1230
1231 default: {
1232 struct qreg r = color[0];
1233 struct qreg g = color[1];
1234 struct qreg b = color[2];
1235 struct qreg a = color[3];
1236
1237 if (c->fs_key->f32_color_rb & (1 << rt)) {
1238 conf |= TLB_TYPE_F32_COLOR;
1239 conf |= ((num_components - 1) <<
1240 TLB_VEC_SIZE_MINUS_1_SHIFT);
1241 } else {
1242 conf |= TLB_TYPE_F16_COLOR;
1243 conf |= TLB_F16_SWAP_HI_LO;
1244 if (num_components >= 3)
1245 conf |= TLB_VEC_SIZE_4_F16;
1246 else
1247 conf |= TLB_VEC_SIZE_2_F16;
1248 }
1249
1250 if (c->fs_key->swap_color_rb & (1 << rt)) {
1251 r = color[2];
1252 b = color[0];
1253 }
1254
1255 if (c->fs_key->sample_alpha_to_one)
1256 a = vir_uniform_f(c, 1.0);
1257
1258 if (c->fs_key->f32_color_rb & (1 << rt)) {
1259 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1260 inst->src[vir_get_implicit_uniform_src(inst)] =
1261 vir_uniform_ui(c, conf);
1262
1263 if (num_components >= 2)
1264 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1265 if (num_components >= 3)
1266 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1267 if (num_components >= 4)
1268 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1269 } else {
1270 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1271 if (conf != ~0) {
1272 inst->dst.file = QFILE_TLBU;
1273 inst->src[vir_get_implicit_uniform_src(inst)] =
1274 vir_uniform_ui(c, conf);
1275 }
1276
1277 if (num_components >= 3)
1278 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1279 }
1280 break;
1281 }
1282 }
1283 }
1284 }
1285
1286 static void
1287 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1288 {
1289 if (c->devinfo->ver >= 40) {
1290 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1291 } else {
1292 /* XXX: v3d33_vir_vpm_write_setup(c); */
1293 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1294 }
1295 }
1296
1297 static void
1298 emit_vert_end(struct v3d_compile *c)
1299 {
1300 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1301 */
1302 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1303 vir_VPMWT(c);
1304 }
1305
1306 void
1307 v3d_optimize_nir(struct nir_shader *s)
1308 {
1309 bool progress;
1310
1311 do {
1312 progress = false;
1313
1314 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1315 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1316 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1317 NIR_PASS(progress, s, nir_copy_prop);
1318 NIR_PASS(progress, s, nir_opt_remove_phis);
1319 NIR_PASS(progress, s, nir_opt_dce);
1320 NIR_PASS(progress, s, nir_opt_dead_cf);
1321 NIR_PASS(progress, s, nir_opt_cse);
1322 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1323 NIR_PASS(progress, s, nir_opt_algebraic);
1324 NIR_PASS(progress, s, nir_opt_constant_folding);
1325 NIR_PASS(progress, s, nir_opt_undef);
1326 } while (progress);
1327
1328 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1329 }
1330
1331 static int
1332 driver_location_compare(const void *in_a, const void *in_b)
1333 {
1334 const nir_variable *const *a = in_a;
1335 const nir_variable *const *b = in_b;
1336
1337 return (*a)->data.driver_location - (*b)->data.driver_location;
1338 }
1339
1340 static struct qreg
1341 ntq_emit_vpm_read(struct v3d_compile *c,
1342 uint32_t *num_components_queued,
1343 uint32_t *remaining,
1344 uint32_t vpm_index)
1345 {
1346 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1347
1348 if (c->devinfo->ver >= 40 ) {
1349 return vir_LDVPMV_IN(c,
1350 vir_uniform_ui(c,
1351 (*num_components_queued)++));
1352 }
1353
1354 if (*num_components_queued != 0) {
1355 (*num_components_queued)--;
1356 return vir_MOV(c, vpm);
1357 }
1358
1359 uint32_t num_components = MIN2(*remaining, 32);
1360
1361 v3d33_vir_vpm_read_setup(c, num_components);
1362
1363 *num_components_queued = num_components - 1;
1364 *remaining -= num_components;
1365
1366 return vir_MOV(c, vpm);
1367 }
1368
1369 static void
1370 ntq_setup_vpm_inputs(struct v3d_compile *c)
1371 {
1372 /* Figure out how many components of each vertex attribute the shader
1373 * uses. Each variable should have been split to individual
1374 * components and unused ones DCEed. The vertex fetcher will load
1375 * from the start of the attribute to the number of components we
1376 * declare we need in c->vattr_sizes[].
1377 */
1378 nir_foreach_variable(var, &c->s->inputs) {
1379 /* No VS attribute array support. */
1380 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1381
1382 unsigned loc = var->data.driver_location;
1383 int start_component = var->data.location_frac;
1384 int num_components = glsl_get_components(var->type);
1385
1386 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1387 start_component + num_components);
1388 }
1389
1390 unsigned num_components = 0;
1391 uint32_t vpm_components_queued = 0;
1392 bool uses_iid = c->s->info.system_values_read &
1393 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1394 bool uses_vid = c->s->info.system_values_read &
1395 (1ull << SYSTEM_VALUE_VERTEX_ID);
1396 num_components += uses_iid;
1397 num_components += uses_vid;
1398
1399 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1400 num_components += c->vattr_sizes[i];
1401
1402 if (uses_iid) {
1403 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1404 &num_components, ~0);
1405 }
1406
1407 if (uses_vid) {
1408 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1409 &num_components, ~0);
1410 }
1411
1412 /* The actual loads will happen directly in nir_intrinsic_load_input
1413 * on newer versions.
1414 */
1415 if (c->devinfo->ver >= 40)
1416 return;
1417
1418 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1419 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1420 (loc + 1) * 4);
1421
1422 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1423 c->inputs[loc * 4 + i] =
1424 ntq_emit_vpm_read(c,
1425 &vpm_components_queued,
1426 &num_components,
1427 loc * 4 + i);
1428
1429 }
1430 }
1431
1432 if (c->devinfo->ver >= 40) {
1433 assert(vpm_components_queued == num_components);
1434 } else {
1435 assert(vpm_components_queued == 0);
1436 assert(num_components == 0);
1437 }
1438 }
1439
1440 static void
1441 ntq_setup_fs_inputs(struct v3d_compile *c)
1442 {
1443 unsigned num_entries = 0;
1444 unsigned num_components = 0;
1445 nir_foreach_variable(var, &c->s->inputs) {
1446 num_entries++;
1447 num_components += glsl_get_components(var->type);
1448 }
1449
1450 nir_variable *vars[num_entries];
1451
1452 unsigned i = 0;
1453 nir_foreach_variable(var, &c->s->inputs)
1454 vars[i++] = var;
1455
1456 /* Sort the variables so that we emit the input setup in
1457 * driver_location order. This is required for VPM reads, whose data
1458 * is fetched into the VPM in driver_location (TGSI register index)
1459 * order.
1460 */
1461 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1462
1463 for (unsigned i = 0; i < num_entries; i++) {
1464 nir_variable *var = vars[i];
1465 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1466 unsigned loc = var->data.driver_location;
1467
1468 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1469 (loc + array_len) * 4);
1470
1471 if (var->data.location == VARYING_SLOT_POS) {
1472 emit_fragcoord_input(c, loc);
1473 } else if (var->data.location == VARYING_SLOT_PNTC ||
1474 (var->data.location >= VARYING_SLOT_VAR0 &&
1475 (c->fs_key->point_sprite_mask &
1476 (1 << (var->data.location -
1477 VARYING_SLOT_VAR0))))) {
1478 c->inputs[loc * 4 + 0] = c->point_x;
1479 c->inputs[loc * 4 + 1] = c->point_y;
1480 } else {
1481 for (int j = 0; j < array_len; j++)
1482 emit_fragment_input(c, loc + j, var, j);
1483 }
1484 }
1485 }
1486
1487 static void
1488 ntq_setup_outputs(struct v3d_compile *c)
1489 {
1490 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1491 return;
1492
1493 nir_foreach_variable(var, &c->s->outputs) {
1494 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1495 unsigned loc = var->data.driver_location * 4;
1496
1497 assert(array_len == 1);
1498 (void)array_len;
1499
1500 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1501 add_output(c, loc + var->data.location_frac + i,
1502 var->data.location,
1503 var->data.location_frac + i);
1504 }
1505
1506 switch (var->data.location) {
1507 case FRAG_RESULT_COLOR:
1508 c->output_color_var[0] = var;
1509 c->output_color_var[1] = var;
1510 c->output_color_var[2] = var;
1511 c->output_color_var[3] = var;
1512 break;
1513 case FRAG_RESULT_DATA0:
1514 case FRAG_RESULT_DATA1:
1515 case FRAG_RESULT_DATA2:
1516 case FRAG_RESULT_DATA3:
1517 c->output_color_var[var->data.location -
1518 FRAG_RESULT_DATA0] = var;
1519 break;
1520 case FRAG_RESULT_DEPTH:
1521 c->output_position_index = loc;
1522 break;
1523 case FRAG_RESULT_SAMPLE_MASK:
1524 c->output_sample_mask_index = loc;
1525 break;
1526 }
1527 }
1528 }
1529
1530 static void
1531 ntq_setup_uniforms(struct v3d_compile *c)
1532 {
1533 nir_foreach_variable(var, &c->s->uniforms) {
1534 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1535 false);
1536 unsigned vec4_size = 4 * sizeof(float);
1537
1538 if (var->data.mode != nir_var_uniform)
1539 continue;
1540
1541 declare_uniform_range(c, var->data.driver_location * vec4_size,
1542 vec4_count * vec4_size);
1543
1544 }
1545 }
1546
1547 /**
1548 * Sets up the mapping from nir_register to struct qreg *.
1549 *
1550 * Each nir_register gets a struct qreg per 32-bit component being stored.
1551 */
1552 static void
1553 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1554 {
1555 foreach_list_typed(nir_register, nir_reg, node, list) {
1556 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1557 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1558 array_len *
1559 nir_reg->num_components);
1560
1561 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1562
1563 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1564 qregs[i] = vir_get_temp(c);
1565 }
1566 }
1567
1568 static void
1569 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1570 {
1571 /* XXX perf: Experiment with using immediate loads to avoid having
1572 * these end up in the uniform stream. Watch out for breaking the
1573 * small immediates optimization in the process!
1574 */
1575 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1576 for (int i = 0; i < instr->def.num_components; i++)
1577 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1578
1579 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1580 }
1581
1582 static void
1583 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1584 {
1585 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1586
1587 /* VIR needs there to be *some* value, so pick 0 (same as for
1588 * ntq_setup_registers().
1589 */
1590 for (int i = 0; i < instr->def.num_components; i++)
1591 qregs[i] = vir_uniform_ui(c, 0);
1592 }
1593
1594 static void
1595 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1596 {
1597 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1598 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1599 unsigned image_index = var->data.driver_location;
1600 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1601 bool is_array = glsl_sampler_type_is_array(sampler_type);
1602
1603 ntq_store_dest(c, &instr->dest, 0,
1604 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1605 if (instr->num_components > 1) {
1606 ntq_store_dest(c, &instr->dest, 1,
1607 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1608 image_index));
1609 }
1610 if (instr->num_components > 2) {
1611 ntq_store_dest(c, &instr->dest, 2,
1612 vir_uniform(c,
1613 is_array ?
1614 QUNIFORM_IMAGE_ARRAY_SIZE :
1615 QUNIFORM_IMAGE_DEPTH,
1616 image_index));
1617 }
1618 }
1619
1620 static void
1621 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1622 {
1623 unsigned offset;
1624
1625 switch (instr->intrinsic) {
1626 case nir_intrinsic_load_uniform:
1627 if (nir_src_is_const(instr->src[0])) {
1628 int offset = (nir_intrinsic_base(instr) +
1629 nir_src_as_uint(instr->src[0]));
1630 assert(offset % 4 == 0);
1631 /* We need dwords */
1632 offset = offset / 4;
1633 for (int i = 0; i < instr->num_components; i++) {
1634 ntq_store_dest(c, &instr->dest, i,
1635 vir_uniform(c, QUNIFORM_UNIFORM,
1636 offset + i));
1637 }
1638 } else {
1639 ntq_emit_tmu_general(c, instr, false);
1640 }
1641 break;
1642
1643 case nir_intrinsic_load_ubo:
1644 ntq_emit_tmu_general(c, instr, false);
1645 break;
1646
1647 case nir_intrinsic_ssbo_atomic_add:
1648 case nir_intrinsic_ssbo_atomic_imin:
1649 case nir_intrinsic_ssbo_atomic_umin:
1650 case nir_intrinsic_ssbo_atomic_imax:
1651 case nir_intrinsic_ssbo_atomic_umax:
1652 case nir_intrinsic_ssbo_atomic_and:
1653 case nir_intrinsic_ssbo_atomic_or:
1654 case nir_intrinsic_ssbo_atomic_xor:
1655 case nir_intrinsic_ssbo_atomic_exchange:
1656 case nir_intrinsic_ssbo_atomic_comp_swap:
1657 case nir_intrinsic_load_ssbo:
1658 case nir_intrinsic_store_ssbo:
1659 ntq_emit_tmu_general(c, instr, false);
1660 break;
1661
1662 case nir_intrinsic_shared_atomic_add:
1663 case nir_intrinsic_shared_atomic_imin:
1664 case nir_intrinsic_shared_atomic_umin:
1665 case nir_intrinsic_shared_atomic_imax:
1666 case nir_intrinsic_shared_atomic_umax:
1667 case nir_intrinsic_shared_atomic_and:
1668 case nir_intrinsic_shared_atomic_or:
1669 case nir_intrinsic_shared_atomic_xor:
1670 case nir_intrinsic_shared_atomic_exchange:
1671 case nir_intrinsic_shared_atomic_comp_swap:
1672 case nir_intrinsic_load_shared:
1673 case nir_intrinsic_store_shared:
1674 ntq_emit_tmu_general(c, instr, true);
1675 break;
1676
1677 case nir_intrinsic_image_deref_load:
1678 case nir_intrinsic_image_deref_store:
1679 case nir_intrinsic_image_deref_atomic_add:
1680 case nir_intrinsic_image_deref_atomic_min:
1681 case nir_intrinsic_image_deref_atomic_max:
1682 case nir_intrinsic_image_deref_atomic_and:
1683 case nir_intrinsic_image_deref_atomic_or:
1684 case nir_intrinsic_image_deref_atomic_xor:
1685 case nir_intrinsic_image_deref_atomic_exchange:
1686 case nir_intrinsic_image_deref_atomic_comp_swap:
1687 v3d40_vir_emit_image_load_store(c, instr);
1688 break;
1689
1690 case nir_intrinsic_get_buffer_size:
1691 ntq_store_dest(c, &instr->dest, 0,
1692 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1693 nir_src_as_uint(instr->src[0])));
1694 break;
1695
1696 case nir_intrinsic_load_user_clip_plane:
1697 for (int i = 0; i < instr->num_components; i++) {
1698 ntq_store_dest(c, &instr->dest, i,
1699 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1700 nir_intrinsic_ucp_id(instr) *
1701 4 + i));
1702 }
1703 break;
1704
1705 case nir_intrinsic_load_viewport_x_scale:
1706 ntq_store_dest(c, &instr->dest, 0,
1707 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1708 break;
1709
1710 case nir_intrinsic_load_viewport_y_scale:
1711 ntq_store_dest(c, &instr->dest, 0,
1712 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1713 break;
1714
1715 case nir_intrinsic_load_viewport_z_scale:
1716 ntq_store_dest(c, &instr->dest, 0,
1717 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1718 break;
1719
1720 case nir_intrinsic_load_viewport_z_offset:
1721 ntq_store_dest(c, &instr->dest, 0,
1722 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1723 break;
1724
1725 case nir_intrinsic_load_alpha_ref_float:
1726 ntq_store_dest(c, &instr->dest, 0,
1727 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1728 break;
1729
1730 case nir_intrinsic_load_sample_mask_in:
1731 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1732 break;
1733
1734 case nir_intrinsic_load_helper_invocation:
1735 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1736 ntq_store_dest(c, &instr->dest, 0,
1737 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1738 vir_uniform_ui(c, ~0),
1739 vir_uniform_ui(c, 0))));
1740 break;
1741
1742 case nir_intrinsic_load_front_face:
1743 /* The register contains 0 (front) or 1 (back), and we need to
1744 * turn it into a NIR bool where true means front.
1745 */
1746 ntq_store_dest(c, &instr->dest, 0,
1747 vir_ADD(c,
1748 vir_uniform_ui(c, -1),
1749 vir_REVF(c)));
1750 break;
1751
1752 case nir_intrinsic_load_instance_id:
1753 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1754 break;
1755
1756 case nir_intrinsic_load_vertex_id:
1757 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1758 break;
1759
1760 case nir_intrinsic_load_input:
1761 offset = (nir_intrinsic_base(instr) +
1762 nir_src_as_uint(instr->src[0]));
1763 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1764 c->devinfo->ver >= 40) {
1765 /* Emit the LDVPM directly now, rather than at the top
1766 * of the shader like we did for V3D 3.x (which needs
1767 * vpmsetup when not just taking the next offset).
1768 *
1769 * Note that delaying like this may introduce stalls,
1770 * as LDVPMV takes a minimum of 1 instruction but may
1771 * be slower if the VPM unit is busy with another QPU.
1772 */
1773 int index = 0;
1774 if (c->s->info.system_values_read &
1775 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1776 index++;
1777 }
1778 if (c->s->info.system_values_read &
1779 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1780 index++;
1781 }
1782 for (int i = 0; i < offset; i++)
1783 index += c->vattr_sizes[i];
1784 index += nir_intrinsic_component(instr);
1785 for (int i = 0; i < instr->num_components; i++) {
1786 struct qreg vpm_offset =
1787 vir_uniform_ui(c, index++);
1788 ntq_store_dest(c, &instr->dest, i,
1789 vir_LDVPMV_IN(c, vpm_offset));
1790 }
1791 } else {
1792 for (int i = 0; i < instr->num_components; i++) {
1793 int comp = nir_intrinsic_component(instr) + i;
1794 ntq_store_dest(c, &instr->dest, i,
1795 vir_MOV(c, c->inputs[offset * 4 +
1796 comp]));
1797 }
1798 }
1799 break;
1800
1801 case nir_intrinsic_store_output:
1802 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1803 offset = ((nir_intrinsic_base(instr) +
1804 nir_src_as_uint(instr->src[1])) * 4 +
1805 nir_intrinsic_component(instr));
1806 for (int i = 0; i < instr->num_components; i++) {
1807 c->outputs[offset + i] =
1808 vir_MOV(c,
1809 ntq_get_src(c,
1810 instr->src[0], i));
1811 }
1812 } else {
1813 assert(instr->num_components == 1);
1814
1815 vir_VPM_WRITE(c,
1816 ntq_get_src(c, instr->src[0], 0),
1817 nir_intrinsic_base(instr));
1818 }
1819 break;
1820
1821 case nir_intrinsic_image_deref_size:
1822 ntq_emit_image_size(c, instr);
1823 break;
1824
1825 case nir_intrinsic_discard:
1826 if (vir_in_nonuniform_control_flow(c)) {
1827 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1828 V3D_QPU_PF_PUSHZ);
1829 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1830 vir_uniform_ui(c, 0)),
1831 V3D_QPU_COND_IFA);
1832 } else {
1833 vir_SETMSF_dest(c, vir_nop_reg(),
1834 vir_uniform_ui(c, 0));
1835 }
1836 break;
1837
1838 case nir_intrinsic_discard_if: {
1839 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1840
1841 if (vir_in_nonuniform_control_flow(c)) {
1842 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1843 c->execute);
1844 if (cond == V3D_QPU_COND_IFA) {
1845 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1846 } else {
1847 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1848 cond = V3D_QPU_COND_IFA;
1849 }
1850 }
1851
1852 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1853 vir_uniform_ui(c, 0)), cond);
1854
1855 break;
1856 }
1857
1858 case nir_intrinsic_memory_barrier:
1859 case nir_intrinsic_memory_barrier_atomic_counter:
1860 case nir_intrinsic_memory_barrier_buffer:
1861 case nir_intrinsic_memory_barrier_image:
1862 case nir_intrinsic_memory_barrier_shared:
1863 /* We don't do any instruction scheduling of these NIR
1864 * instructions between each other, so we just need to make
1865 * sure that the TMU operations before the barrier are flushed
1866 * before the ones after the barrier. That is currently
1867 * handled by having a THRSW in each of them and a LDTMU
1868 * series or a TMUWT after.
1869 */
1870 break;
1871
1872 case nir_intrinsic_barrier:
1873 /* Emit a TSY op to get all invocations in the workgroup
1874 * (actually supergroup) to block until the last invocation
1875 * reaches the TSY op.
1876 */
1877 if (c->devinfo->ver >= 42) {
1878 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1879 V3D_QPU_WADDR_SYNCB));
1880 } else {
1881 struct qinst *sync =
1882 vir_BARRIERID_dest(c,
1883 vir_reg(QFILE_MAGIC,
1884 V3D_QPU_WADDR_SYNCU));
1885 sync->src[vir_get_implicit_uniform_src(sync)] =
1886 vir_uniform_ui(c,
1887 0xffffff00 |
1888 V3D_TSY_WAIT_INC_CHECK);
1889
1890 }
1891
1892 /* The blocking of a TSY op only happens at the next thread
1893 * switch. No texturing may be outstanding at the time of a
1894 * TSY blocking operation.
1895 */
1896 vir_emit_thrsw(c);
1897 break;
1898
1899 case nir_intrinsic_load_num_work_groups:
1900 for (int i = 0; i < 3; i++) {
1901 ntq_store_dest(c, &instr->dest, i,
1902 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1903 i));
1904 }
1905 break;
1906
1907 case nir_intrinsic_load_local_invocation_index:
1908 ntq_store_dest(c, &instr->dest, 0,
1909 vir_SHR(c, c->cs_payload[1],
1910 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1911 break;
1912
1913 case nir_intrinsic_load_work_group_id:
1914 ntq_store_dest(c, &instr->dest, 0,
1915 vir_AND(c, c->cs_payload[0],
1916 vir_uniform_ui(c, 0xffff)));
1917 ntq_store_dest(c, &instr->dest, 1,
1918 vir_SHR(c, c->cs_payload[0],
1919 vir_uniform_ui(c, 16)));
1920 ntq_store_dest(c, &instr->dest, 2,
1921 vir_AND(c, c->cs_payload[1],
1922 vir_uniform_ui(c, 0xffff)));
1923 break;
1924
1925 default:
1926 fprintf(stderr, "Unknown intrinsic: ");
1927 nir_print_instr(&instr->instr, stderr);
1928 fprintf(stderr, "\n");
1929 break;
1930 }
1931 }
1932
1933 /* Clears (activates) the execute flags for any channels whose jump target
1934 * matches this block.
1935 *
1936 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
1937 * enabling?
1938 *
1939 * XXX perf: For uniform control flow, we should be able to skip c->execute
1940 * handling entirely.
1941 */
1942 static void
1943 ntq_activate_execute_for_block(struct v3d_compile *c)
1944 {
1945 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
1946 c->execute, vir_uniform_ui(c, c->cur_block->index)),
1947 V3D_QPU_PF_PUSHZ);
1948
1949 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1950 }
1951
1952 static void
1953 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
1954 {
1955 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1956 bool empty_else_block =
1957 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1958 exec_list_is_empty(&nir_else_block->instr_list));
1959
1960 struct qblock *then_block = vir_new_block(c);
1961 struct qblock *after_block = vir_new_block(c);
1962 struct qblock *else_block;
1963 if (empty_else_block)
1964 else_block = after_block;
1965 else
1966 else_block = vir_new_block(c);
1967
1968 /* Set up the flags for the IF condition (taking the THEN branch). */
1969 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
1970
1971 /* Jump to ELSE. */
1972 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
1973 V3D_QPU_BRANCH_COND_ALLNA :
1974 V3D_QPU_BRANCH_COND_ALLA);
1975 vir_link_blocks(c->cur_block, else_block);
1976 vir_link_blocks(c->cur_block, then_block);
1977
1978 /* Process the THEN block. */
1979 vir_set_emit_block(c, then_block);
1980 ntq_emit_cf_list(c, &if_stmt->then_list);
1981
1982 if (!empty_else_block) {
1983 /* At the end of the THEN block, jump to ENDIF */
1984 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
1985 vir_link_blocks(c->cur_block, after_block);
1986
1987 /* Emit the else block. */
1988 vir_set_emit_block(c, else_block);
1989 ntq_activate_execute_for_block(c);
1990 ntq_emit_cf_list(c, &if_stmt->else_list);
1991 }
1992
1993 vir_link_blocks(c->cur_block, after_block);
1994
1995 vir_set_emit_block(c, after_block);
1996 }
1997
1998 static void
1999 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2000 {
2001 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2002 bool empty_else_block =
2003 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2004 exec_list_is_empty(&nir_else_block->instr_list));
2005
2006 struct qblock *then_block = vir_new_block(c);
2007 struct qblock *after_block = vir_new_block(c);
2008 struct qblock *else_block;
2009 if (empty_else_block)
2010 else_block = after_block;
2011 else
2012 else_block = vir_new_block(c);
2013
2014 bool was_uniform_control_flow = false;
2015 if (!vir_in_nonuniform_control_flow(c)) {
2016 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2017 was_uniform_control_flow = true;
2018 }
2019
2020 /* Set up the flags for the IF condition (taking the THEN branch). */
2021 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2022
2023 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2024 * was previously active (execute Z) for updating the exec flags.
2025 */
2026 if (was_uniform_control_flow) {
2027 cond = v3d_qpu_cond_invert(cond);
2028 } else {
2029 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2030 if (cond == V3D_QPU_COND_IFA) {
2031 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2032 } else {
2033 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2034 cond = V3D_QPU_COND_IFA;
2035 }
2036 }
2037
2038 vir_MOV_cond(c, cond,
2039 c->execute,
2040 vir_uniform_ui(c, else_block->index));
2041
2042 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2043 * through.
2044 */
2045 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2046 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2047 vir_link_blocks(c->cur_block, else_block);
2048 vir_link_blocks(c->cur_block, then_block);
2049
2050 /* Process the THEN block. */
2051 vir_set_emit_block(c, then_block);
2052 ntq_emit_cf_list(c, &if_stmt->then_list);
2053
2054 if (!empty_else_block) {
2055 /* Handle the end of the THEN block. First, all currently
2056 * active channels update their execute flags to point to
2057 * ENDIF
2058 */
2059 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2060 V3D_QPU_PF_PUSHZ);
2061 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2062 vir_uniform_ui(c, after_block->index));
2063
2064 /* If everything points at ENDIF, then jump there immediately. */
2065 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2066 c->execute,
2067 vir_uniform_ui(c, after_block->index)),
2068 V3D_QPU_PF_PUSHZ);
2069 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2070 vir_link_blocks(c->cur_block, after_block);
2071 vir_link_blocks(c->cur_block, else_block);
2072
2073 vir_set_emit_block(c, else_block);
2074 ntq_activate_execute_for_block(c);
2075 ntq_emit_cf_list(c, &if_stmt->else_list);
2076 }
2077
2078 vir_link_blocks(c->cur_block, after_block);
2079
2080 vir_set_emit_block(c, after_block);
2081 if (was_uniform_control_flow)
2082 c->execute = c->undef;
2083 else
2084 ntq_activate_execute_for_block(c);
2085 }
2086
2087 static void
2088 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2089 {
2090 bool was_in_control_flow = c->in_control_flow;
2091 c->in_control_flow = true;
2092 if (!vir_in_nonuniform_control_flow(c) &&
2093 nir_src_is_dynamically_uniform(nif->condition)) {
2094 ntq_emit_uniform_if(c, nif);
2095 } else {
2096 ntq_emit_nonuniform_if(c, nif);
2097 }
2098 c->in_control_flow = was_in_control_flow;
2099 }
2100
2101 static void
2102 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2103 {
2104 switch (jump->type) {
2105 case nir_jump_break:
2106 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2107 V3D_QPU_PF_PUSHZ);
2108 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2109 vir_uniform_ui(c, c->loop_break_block->index));
2110 break;
2111
2112 case nir_jump_continue:
2113 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2114 V3D_QPU_PF_PUSHZ);
2115 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2116 vir_uniform_ui(c, c->loop_cont_block->index));
2117 break;
2118
2119 case nir_jump_return:
2120 unreachable("All returns shouold be lowered\n");
2121 }
2122 }
2123
2124 static void
2125 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2126 {
2127 switch (instr->type) {
2128 case nir_instr_type_deref:
2129 /* ignored, will be walked by the intrinsic using it. */
2130 break;
2131
2132 case nir_instr_type_alu:
2133 ntq_emit_alu(c, nir_instr_as_alu(instr));
2134 break;
2135
2136 case nir_instr_type_intrinsic:
2137 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2138 break;
2139
2140 case nir_instr_type_load_const:
2141 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2142 break;
2143
2144 case nir_instr_type_ssa_undef:
2145 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2146 break;
2147
2148 case nir_instr_type_tex:
2149 ntq_emit_tex(c, nir_instr_as_tex(instr));
2150 break;
2151
2152 case nir_instr_type_jump:
2153 ntq_emit_jump(c, nir_instr_as_jump(instr));
2154 break;
2155
2156 default:
2157 fprintf(stderr, "Unknown NIR instr type: ");
2158 nir_print_instr(instr, stderr);
2159 fprintf(stderr, "\n");
2160 abort();
2161 }
2162 }
2163
2164 static void
2165 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2166 {
2167 nir_foreach_instr(instr, block) {
2168 ntq_emit_instr(c, instr);
2169 }
2170 }
2171
2172 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2173
2174 static void
2175 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2176 {
2177 bool was_in_control_flow = c->in_control_flow;
2178 c->in_control_flow = true;
2179
2180 bool was_uniform_control_flow = false;
2181 if (!vir_in_nonuniform_control_flow(c)) {
2182 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2183 was_uniform_control_flow = true;
2184 }
2185
2186 struct qblock *save_loop_cont_block = c->loop_cont_block;
2187 struct qblock *save_loop_break_block = c->loop_break_block;
2188
2189 c->loop_cont_block = vir_new_block(c);
2190 c->loop_break_block = vir_new_block(c);
2191
2192 vir_link_blocks(c->cur_block, c->loop_cont_block);
2193 vir_set_emit_block(c, c->loop_cont_block);
2194 ntq_activate_execute_for_block(c);
2195
2196 ntq_emit_cf_list(c, &loop->body);
2197
2198 /* Re-enable any previous continues now, so our ANYA check below
2199 * works.
2200 *
2201 * XXX: Use the .ORZ flags update, instead.
2202 */
2203 vir_set_pf(vir_XOR_dest(c,
2204 vir_nop_reg(),
2205 c->execute,
2206 vir_uniform_ui(c, c->loop_cont_block->index)),
2207 V3D_QPU_PF_PUSHZ);
2208 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2209
2210 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2211
2212 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2213 /* Pixels that were not dispatched or have been discarded should not
2214 * contribute to looping again.
2215 */
2216 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2217 vir_link_blocks(c->cur_block, c->loop_cont_block);
2218 vir_link_blocks(c->cur_block, c->loop_break_block);
2219
2220 vir_set_emit_block(c, c->loop_break_block);
2221 if (was_uniform_control_flow)
2222 c->execute = c->undef;
2223 else
2224 ntq_activate_execute_for_block(c);
2225
2226 c->loop_break_block = save_loop_break_block;
2227 c->loop_cont_block = save_loop_cont_block;
2228
2229 c->loops++;
2230
2231 c->in_control_flow = was_in_control_flow;
2232 }
2233
2234 static void
2235 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2236 {
2237 fprintf(stderr, "FUNCTIONS not handled.\n");
2238 abort();
2239 }
2240
2241 static void
2242 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2243 {
2244 foreach_list_typed(nir_cf_node, node, node, list) {
2245 switch (node->type) {
2246 case nir_cf_node_block:
2247 ntq_emit_block(c, nir_cf_node_as_block(node));
2248 break;
2249
2250 case nir_cf_node_if:
2251 ntq_emit_if(c, nir_cf_node_as_if(node));
2252 break;
2253
2254 case nir_cf_node_loop:
2255 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2256 break;
2257
2258 case nir_cf_node_function:
2259 ntq_emit_function(c, nir_cf_node_as_function(node));
2260 break;
2261
2262 default:
2263 fprintf(stderr, "Unknown NIR node type\n");
2264 abort();
2265 }
2266 }
2267 }
2268
2269 static void
2270 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2271 {
2272 ntq_setup_registers(c, &impl->registers);
2273 ntq_emit_cf_list(c, &impl->body);
2274 }
2275
2276 static void
2277 nir_to_vir(struct v3d_compile *c)
2278 {
2279 switch (c->s->info.stage) {
2280 case MESA_SHADER_FRAGMENT:
2281 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2282 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2283 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2284
2285 /* XXX perf: We could set the "disable implicit point/line
2286 * varyings" field in the shader record and not emit these, if
2287 * they're not going to be used.
2288 */
2289 if (c->fs_key->is_points) {
2290 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2291 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2292 } else if (c->fs_key->is_lines) {
2293 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2294 }
2295 break;
2296 case MESA_SHADER_COMPUTE:
2297 /* Set up the TSO for barriers, assuming we do some. */
2298 if (c->devinfo->ver < 42) {
2299 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2300 V3D_QPU_WADDR_SYNC));
2301 }
2302
2303 if (c->s->info.system_values_read &
2304 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2305 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2306 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2307 }
2308 if ((c->s->info.system_values_read &
2309 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2310 c->s->info.cs.shared_size) {
2311 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2312 }
2313
2314 /* Set up the division between gl_LocalInvocationIndex and
2315 * wg_in_mem in the payload reg.
2316 */
2317 int wg_size = (c->s->info.cs.local_size[0] *
2318 c->s->info.cs.local_size[1] *
2319 c->s->info.cs.local_size[2]);
2320 c->local_invocation_index_bits =
2321 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2322 assert(c->local_invocation_index_bits <= 8);
2323
2324 if (c->s->info.cs.shared_size) {
2325 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2326 vir_uniform_ui(c, 16));
2327 if (c->s->info.cs.local_size[0] != 1 ||
2328 c->s->info.cs.local_size[1] != 1 ||
2329 c->s->info.cs.local_size[2] != 1) {
2330 int wg_bits = (16 -
2331 c->local_invocation_index_bits);
2332 int wg_mask = (1 << wg_bits) - 1;
2333 wg_in_mem = vir_AND(c, wg_in_mem,
2334 vir_uniform_ui(c, wg_mask));
2335 }
2336 struct qreg shared_per_wg =
2337 vir_uniform_ui(c, c->s->info.cs.shared_size);
2338
2339 c->cs_shared_offset =
2340 vir_ADD(c,
2341 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2342 vir_UMUL(c, wg_in_mem, shared_per_wg));
2343 }
2344 break;
2345 default:
2346 break;
2347 }
2348
2349 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2350 ntq_setup_fs_inputs(c);
2351 else
2352 ntq_setup_vpm_inputs(c);
2353
2354 ntq_setup_outputs(c);
2355 ntq_setup_uniforms(c);
2356 ntq_setup_registers(c, &c->s->registers);
2357
2358 /* Find the main function and emit the body. */
2359 nir_foreach_function(function, c->s) {
2360 assert(strcmp(function->name, "main") == 0);
2361 assert(function->impl);
2362 ntq_emit_impl(c, function->impl);
2363 }
2364 }
2365
2366 const nir_shader_compiler_options v3d_nir_options = {
2367 .lower_all_io_to_temps = true,
2368 .lower_extract_byte = true,
2369 .lower_extract_word = true,
2370 .lower_bfm = true,
2371 .lower_bitfield_insert_to_shifts = true,
2372 .lower_bitfield_extract_to_shifts = true,
2373 .lower_bitfield_reverse = true,
2374 .lower_bit_count = true,
2375 .lower_cs_local_id_from_index = true,
2376 .lower_ffract = true,
2377 .lower_pack_unorm_2x16 = true,
2378 .lower_pack_snorm_2x16 = true,
2379 .lower_pack_unorm_4x8 = true,
2380 .lower_pack_snorm_4x8 = true,
2381 .lower_unpack_unorm_4x8 = true,
2382 .lower_unpack_snorm_4x8 = true,
2383 .lower_pack_half_2x16 = true,
2384 .lower_unpack_half_2x16 = true,
2385 .lower_fdiv = true,
2386 .lower_find_lsb = true,
2387 .lower_ffma = true,
2388 .lower_flrp32 = true,
2389 .lower_fpow = true,
2390 .lower_fsat = true,
2391 .lower_fsqrt = true,
2392 .lower_ifind_msb = true,
2393 .lower_isign = true,
2394 .lower_ldexp = true,
2395 .lower_mul_high = true,
2396 .lower_wpos_pntc = true,
2397 .native_integers = true,
2398 };
2399
2400 /**
2401 * When demoting a shader down to single-threaded, removes the THRSW
2402 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2403 * program end).
2404 */
2405 static void
2406 vir_remove_thrsw(struct v3d_compile *c)
2407 {
2408 vir_for_each_block(block, c) {
2409 vir_for_each_inst_safe(inst, block) {
2410 if (inst->qpu.sig.thrsw)
2411 vir_remove_instruction(c, inst);
2412 }
2413 }
2414
2415 c->last_thrsw = NULL;
2416 }
2417
2418 void
2419 vir_emit_last_thrsw(struct v3d_compile *c)
2420 {
2421 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2422 * switching, so disable threads if we didn't do any TMU ops (each of
2423 * which would have emitted a THRSW).
2424 */
2425 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2426 c->threads = 1;
2427 if (c->last_thrsw)
2428 vir_remove_thrsw(c);
2429 return;
2430 }
2431
2432 /* If we're threaded and the last THRSW was in conditional code, then
2433 * we need to emit another one so that we can flag it as the last
2434 * thrsw.
2435 */
2436 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2437 assert(c->devinfo->ver >= 41);
2438 vir_emit_thrsw(c);
2439 }
2440
2441 /* If we're threaded, then we need to mark the last THRSW instruction
2442 * so we can emit a pair of them at QPU emit time.
2443 *
2444 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2445 * post-last-THRSW state, so we can skip this.
2446 */
2447 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2448 assert(c->devinfo->ver >= 41);
2449 vir_emit_thrsw(c);
2450 }
2451
2452 if (c->last_thrsw)
2453 c->last_thrsw->is_last_thrsw = true;
2454 }
2455
2456 /* There's a flag in the shader for "center W is needed for reasons other than
2457 * non-centroid varyings", so we just walk the program after VIR optimization
2458 * to see if it's used. It should be harmless to set even if we only use
2459 * center W for varyings.
2460 */
2461 static void
2462 vir_check_payload_w(struct v3d_compile *c)
2463 {
2464 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2465 return;
2466
2467 vir_for_each_inst_inorder(inst, c) {
2468 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2469 if (inst->src[i].file == QFILE_REG &&
2470 inst->src[i].index == 0) {
2471 c->uses_center_w = true;
2472 return;
2473 }
2474 }
2475 }
2476
2477 }
2478
2479 void
2480 v3d_nir_to_vir(struct v3d_compile *c)
2481 {
2482 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2483 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2484 fprintf(stderr, "%s prog %d/%d NIR:\n",
2485 vir_get_stage_name(c),
2486 c->program_id, c->variant_id);
2487 nir_print_shader(c->s, stderr);
2488 }
2489
2490 nir_to_vir(c);
2491
2492 /* Emit the last THRSW before STVPM and TLB writes. */
2493 vir_emit_last_thrsw(c);
2494
2495 switch (c->s->info.stage) {
2496 case MESA_SHADER_FRAGMENT:
2497 emit_frag_end(c);
2498 break;
2499 case MESA_SHADER_VERTEX:
2500 emit_vert_end(c);
2501 break;
2502 default:
2503 unreachable("bad stage");
2504 }
2505
2506 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2507 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2508 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2509 vir_get_stage_name(c),
2510 c->program_id, c->variant_id);
2511 vir_dump(c);
2512 fprintf(stderr, "\n");
2513 }
2514
2515 vir_optimize(c);
2516 vir_lower_uniforms(c);
2517
2518 vir_check_payload_w(c);
2519
2520 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2521 * We used that on that platform to pipeline TMU writes and reduce the
2522 * number of thread switches, as well as try (mostly successfully) to
2523 * reduce maximum register pressure to allow more threads. We should
2524 * do something of that sort for V3D -- either instruction scheduling
2525 * here, or delay the the THRSW and LDTMUs from our texture
2526 * instructions until the results are needed.
2527 */
2528
2529 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2530 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2531 fprintf(stderr, "%s prog %d/%d VIR:\n",
2532 vir_get_stage_name(c),
2533 c->program_id, c->variant_id);
2534 vir_dump(c);
2535 fprintf(stderr, "\n");
2536 }
2537
2538 /* Attempt to allocate registers for the temporaries. If we fail,
2539 * reduce thread count and try again.
2540 */
2541 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2542 struct qpu_reg *temp_registers;
2543 while (true) {
2544 bool spilled;
2545 temp_registers = v3d_register_allocate(c, &spilled);
2546 if (spilled)
2547 continue;
2548
2549 if (temp_registers)
2550 break;
2551
2552 if (c->threads == min_threads) {
2553 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2554 c->threads);
2555 vir_dump(c);
2556 c->failed = true;
2557 return;
2558 }
2559
2560 c->threads /= 2;
2561
2562 if (c->threads == 1)
2563 vir_remove_thrsw(c);
2564 }
2565
2566 if (c->spill_size &&
2567 (V3D_DEBUG & (V3D_DEBUG_VIR |
2568 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2569 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2570 vir_get_stage_name(c),
2571 c->program_id, c->variant_id);
2572 vir_dump(c);
2573 fprintf(stderr, "\n");
2574 }
2575
2576 v3d_vir_to_qpu(c, temp_registers);
2577 }