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broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 /* XXX: Needs base level addition */
384 coords[next_coord++] =
385 ntq_get_src(c, instr->src[i].src, 0);
386
387 if (instr->op != nir_texop_txf &&
388 instr->op != nir_texop_tg4) {
389 p0_unpacked.disable_autolod_use_bias_only = true;
390 }
391 break;
392 case nir_tex_src_comparator:
393 coords[next_coord++] =
394 ntq_get_src(c, instr->src[i].src, 0);
395
396 p0_unpacked.shadow = true;
397 break;
398
399 case nir_tex_src_offset: {
400 nir_const_value *offset =
401 nir_src_as_const_value(instr->src[i].src);
402 p0_unpacked.texel_offset_for_s_coordinate =
403 offset->i32[0];
404
405 if (instr->coord_components >= 2)
406 p0_unpacked.texel_offset_for_t_coordinate =
407 offset->i32[1];
408
409 if (instr->coord_components >= 3)
410 p0_unpacked.texel_offset_for_r_coordinate =
411 offset->i32[2];
412 break;
413 }
414
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 uint32_t p0_packed;
421 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
422 (uint8_t *)&p0_packed,
423 &p0_unpacked);
424
425 /* There is no native support for GL texture rectangle coordinates, so
426 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
427 * 1]).
428 */
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
430 coords[0] = vir_FMUL(c, coords[0],
431 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
432 unit));
433 coords[1] = vir_FMUL(c, coords[1],
434 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
435 unit));
436 }
437
438 struct qreg texture_u[] = {
439 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
440 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
441 };
442 uint32_t next_texture_u = 0;
443
444 for (int i = 0; i < next_coord; i++) {
445 struct qreg dst;
446
447 if (i == next_coord - 1)
448 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
449 else
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
451
452 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
453
454 if (i < 2) {
455 tmu->has_implicit_uniform = true;
456 tmu->src[vir_get_implicit_uniform_src(tmu)] =
457 texture_u[next_texture_u++];
458 }
459 }
460
461 bool return_16 = (c->key->tex[unit].return_size == 16 ||
462 p0_unpacked.shadow);
463
464 struct qreg return_values[4];
465 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
466 return_values[i] = vir_LDTMU(c);
467 /* Swizzling .zw of an RG texture should give undefined results, not
468 * crash the compiler.
469 */
470 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
471 return_values[i] = c->undef;
472
473 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
474 struct qreg chan;
475
476 if (return_16) {
477 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
478 chan = return_values[i / 2];
479
480 enum v3d_qpu_input_unpack unpack;
481 if (i & 1)
482 unpack = V3D_QPU_UNPACK_H;
483 else
484 unpack = V3D_QPU_UNPACK_L;
485
486 chan = vir_FMOV(c, chan);
487 vir_set_unpack(c->defs[chan.index], 0, unpack);
488 } else {
489 chan = vir_MOV(c, return_values[i]);
490 }
491 ntq_store_dest(c, &instr->dest, i, chan);
492 }
493 }
494
495 static struct qreg
496 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
497 {
498 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
499 if (is_cos)
500 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
501
502 struct qreg periods = vir_FROUND(c, input);
503 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
504 vir_FSUB(c, input, periods));
505 return vir_XOR(c, sin_output, vir_SHL(c,
506 vir_FTOIN(c, periods),
507 vir_uniform_ui(c, -1)));
508 }
509
510 static struct qreg
511 ntq_fsign(struct v3d_compile *c, struct qreg src)
512 {
513 struct qreg t = vir_get_temp(c);
514
515 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
516 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
517 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
518 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
519 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
520 return vir_MOV(c, t);
521 }
522
523 static struct qreg
524 ntq_isign(struct v3d_compile *c, struct qreg src)
525 {
526 struct qreg t = vir_get_temp(c);
527
528 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
529 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
530 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
531 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
532 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
533 return vir_MOV(c, t);
534 }
535
536 static void
537 emit_fragcoord_input(struct v3d_compile *c, int attr)
538 {
539 c->inputs[attr * 4 + 0] = vir_FXCD(c);
540 c->inputs[attr * 4 + 1] = vir_FYCD(c);
541 c->inputs[attr * 4 + 2] = c->payload_z;
542 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
543 c->payload_w);
544 }
545
546 static struct qreg
547 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
548 uint8_t swizzle)
549 {
550 struct qreg vary = vir_reg(QFILE_VARY, ~0);
551 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
552
553 /* For gl_PointCoord input or distance along a line, we'll be called
554 * with no nir_variable, and we don't count toward VPM size so we
555 * don't track an input slot.
556 */
557 if (!var) {
558 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
559 }
560
561 int i = c->num_inputs++;
562 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
563 swizzle);
564
565 switch (var->data.interpolation) {
566 case INTERP_MODE_NONE:
567 /* If a gl_FrontColor or gl_BackColor input has no interp
568 * qualifier, then flag it for glShadeModel() handling by the
569 * driver.
570 */
571 switch (var->data.location) {
572 case VARYING_SLOT_COL0:
573 case VARYING_SLOT_COL1:
574 case VARYING_SLOT_BFC0:
575 case VARYING_SLOT_BFC1:
576 BITSET_SET(c->shade_model_flags, i);
577 break;
578 default:
579 break;
580 }
581 /* FALLTHROUGH */
582 case INTERP_MODE_SMOOTH:
583 if (var->data.centroid) {
584 return vir_FADD(c, vir_FMUL(c, vary,
585 c->payload_w_centroid), r5);
586 } else {
587 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
588 }
589 case INTERP_MODE_NOPERSPECTIVE:
590 /* C appears after the mov from the varying.
591 XXX: improve ldvary setup.
592 */
593 return vir_FADD(c, vir_MOV(c, vary), r5);
594 case INTERP_MODE_FLAT:
595 BITSET_SET(c->flat_shade_flags, i);
596 vir_MOV_dest(c, c->undef, vary);
597 return vir_MOV(c, r5);
598 default:
599 unreachable("Bad interp mode");
600 }
601 }
602
603 static void
604 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
605 {
606 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
607 c->inputs[attr * 4 + i] =
608 emit_fragment_varying(c, var, i);
609 }
610 }
611
612 static void
613 add_output(struct v3d_compile *c,
614 uint32_t decl_offset,
615 uint8_t slot,
616 uint8_t swizzle)
617 {
618 uint32_t old_array_size = c->outputs_array_size;
619 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
620 decl_offset + 1);
621
622 if (old_array_size != c->outputs_array_size) {
623 c->output_slots = reralloc(c,
624 c->output_slots,
625 struct v3d_varying_slot,
626 c->outputs_array_size);
627 }
628
629 c->output_slots[decl_offset] =
630 v3d_slot_from_slot_and_component(slot, swizzle);
631 }
632
633 static void
634 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
635 {
636 unsigned array_id = c->num_ubo_ranges++;
637 if (array_id >= c->ubo_ranges_array_size) {
638 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
639 array_id + 1);
640 c->ubo_ranges = reralloc(c, c->ubo_ranges,
641 struct v3d_ubo_range,
642 c->ubo_ranges_array_size);
643 c->ubo_range_used = reralloc(c, c->ubo_range_used,
644 bool,
645 c->ubo_ranges_array_size);
646 }
647
648 c->ubo_ranges[array_id].dst_offset = 0;
649 c->ubo_ranges[array_id].src_offset = start;
650 c->ubo_ranges[array_id].size = size;
651 c->ubo_range_used[array_id] = false;
652 }
653
654 /**
655 * If compare_instr is a valid comparison instruction, emits the
656 * compare_instr's comparison and returns the sel_instr's return value based
657 * on the compare_instr's result.
658 */
659 static bool
660 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
661 nir_alu_instr *compare_instr,
662 nir_alu_instr *sel_instr)
663 {
664 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
665 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
666 bool cond_invert = false;
667
668 switch (compare_instr->op) {
669 case nir_op_feq:
670 case nir_op_seq:
671 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
672 break;
673 case nir_op_ieq:
674 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
675 break;
676
677 case nir_op_fne:
678 case nir_op_sne:
679 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
680 cond_invert = true;
681 break;
682 case nir_op_ine:
683 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
684 cond_invert = true;
685 break;
686
687 case nir_op_fge:
688 case nir_op_sge:
689 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
690 break;
691 case nir_op_ige:
692 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
693 cond_invert = true;
694 break;
695 case nir_op_uge:
696 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
697 cond_invert = true;
698 break;
699
700 case nir_op_slt:
701 case nir_op_flt:
702 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
703 break;
704 case nir_op_ilt:
705 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
706 break;
707 case nir_op_ult:
708 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
709 break;
710
711 default:
712 return false;
713 }
714
715 enum v3d_qpu_cond cond = (cond_invert ?
716 V3D_QPU_COND_IFNA :
717 V3D_QPU_COND_IFA);
718
719 switch (sel_instr->op) {
720 case nir_op_seq:
721 case nir_op_sne:
722 case nir_op_sge:
723 case nir_op_slt:
724 *dest = vir_SEL(c, cond,
725 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
726 break;
727
728 case nir_op_bcsel:
729 *dest = vir_SEL(c, cond,
730 ntq_get_alu_src(c, sel_instr, 1),
731 ntq_get_alu_src(c, sel_instr, 2));
732 break;
733
734 default:
735 *dest = vir_SEL(c, cond,
736 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
737 break;
738 }
739
740 /* Make the temporary for nir_store_dest(). */
741 *dest = vir_MOV(c, *dest);
742
743 return true;
744 }
745
746 /**
747 * Attempts to fold a comparison generating a boolean result into the
748 * condition code for selecting between two values, instead of comparing the
749 * boolean result against 0 to generate the condition code.
750 */
751 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
752 struct qreg *src)
753 {
754 if (!instr->src[0].src.is_ssa)
755 goto out;
756 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
757 goto out;
758 nir_alu_instr *compare =
759 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
760 if (!compare)
761 goto out;
762
763 struct qreg dest;
764 if (ntq_emit_comparison(c, &dest, compare, instr))
765 return dest;
766
767 out:
768 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
769 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
770 }
771
772
773 static void
774 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
775 {
776 /* This should always be lowered to ALU operations for V3D. */
777 assert(!instr->dest.saturate);
778
779 /* Vectors are special in that they have non-scalarized writemasks,
780 * and just take the first swizzle channel for each argument in order
781 * into each writemask channel.
782 */
783 if (instr->op == nir_op_vec2 ||
784 instr->op == nir_op_vec3 ||
785 instr->op == nir_op_vec4) {
786 struct qreg srcs[4];
787 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
788 srcs[i] = ntq_get_src(c, instr->src[i].src,
789 instr->src[i].swizzle[0]);
790 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
791 ntq_store_dest(c, &instr->dest.dest, i,
792 vir_MOV(c, srcs[i]));
793 return;
794 }
795
796 /* General case: We can just grab the one used channel per src. */
797 struct qreg src[nir_op_infos[instr->op].num_inputs];
798 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
799 src[i] = ntq_get_alu_src(c, instr, i);
800 }
801
802 struct qreg result;
803
804 switch (instr->op) {
805 case nir_op_fmov:
806 case nir_op_imov:
807 result = vir_MOV(c, src[0]);
808 break;
809 case nir_op_fmul:
810 result = vir_FMUL(c, src[0], src[1]);
811 break;
812 case nir_op_fadd:
813 result = vir_FADD(c, src[0], src[1]);
814 break;
815 case nir_op_fsub:
816 result = vir_FSUB(c, src[0], src[1]);
817 break;
818 case nir_op_fmin:
819 result = vir_FMIN(c, src[0], src[1]);
820 break;
821 case nir_op_fmax:
822 result = vir_FMAX(c, src[0], src[1]);
823 break;
824
825 case nir_op_f2i32:
826 result = vir_FTOIZ(c, src[0]);
827 break;
828 case nir_op_f2u32:
829 result = vir_FTOUZ(c, src[0]);
830 break;
831 case nir_op_i2f32:
832 result = vir_ITOF(c, src[0]);
833 break;
834 case nir_op_u2f32:
835 result = vir_UTOF(c, src[0]);
836 break;
837 case nir_op_b2f:
838 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
839 break;
840 case nir_op_b2i:
841 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
842 break;
843 case nir_op_i2b:
844 case nir_op_f2b:
845 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
846 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
847 vir_uniform_ui(c, ~0),
848 vir_uniform_ui(c, 0)));
849 break;
850
851 case nir_op_iadd:
852 result = vir_ADD(c, src[0], src[1]);
853 break;
854 case nir_op_ushr:
855 result = vir_SHR(c, src[0], src[1]);
856 break;
857 case nir_op_isub:
858 result = vir_SUB(c, src[0], src[1]);
859 break;
860 case nir_op_ishr:
861 result = vir_ASR(c, src[0], src[1]);
862 break;
863 case nir_op_ishl:
864 result = vir_SHL(c, src[0], src[1]);
865 break;
866 case nir_op_imin:
867 result = vir_MIN(c, src[0], src[1]);
868 break;
869 case nir_op_umin:
870 result = vir_UMIN(c, src[0], src[1]);
871 break;
872 case nir_op_imax:
873 result = vir_MAX(c, src[0], src[1]);
874 break;
875 case nir_op_umax:
876 result = vir_UMAX(c, src[0], src[1]);
877 break;
878 case nir_op_iand:
879 result = vir_AND(c, src[0], src[1]);
880 break;
881 case nir_op_ior:
882 result = vir_OR(c, src[0], src[1]);
883 break;
884 case nir_op_ixor:
885 result = vir_XOR(c, src[0], src[1]);
886 break;
887 case nir_op_inot:
888 result = vir_NOT(c, src[0]);
889 break;
890
891 case nir_op_imul:
892 result = ntq_umul(c, src[0], src[1]);
893 break;
894
895 case nir_op_seq:
896 case nir_op_sne:
897 case nir_op_sge:
898 case nir_op_slt:
899 case nir_op_feq:
900 case nir_op_fne:
901 case nir_op_fge:
902 case nir_op_flt:
903 case nir_op_ieq:
904 case nir_op_ine:
905 case nir_op_ige:
906 case nir_op_uge:
907 case nir_op_ilt:
908 case nir_op_ult:
909 if (!ntq_emit_comparison(c, &result, instr, instr)) {
910 fprintf(stderr, "Bad comparison instruction\n");
911 }
912 break;
913
914 case nir_op_bcsel:
915 result = ntq_emit_bcsel(c, instr, src);
916 break;
917 case nir_op_fcsel:
918 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
919 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
920 src[1], src[2]));
921 break;
922
923 case nir_op_frcp:
924 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
925 break;
926 case nir_op_frsq:
927 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
928 break;
929 case nir_op_fexp2:
930 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
931 break;
932 case nir_op_flog2:
933 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
934 break;
935
936 case nir_op_fceil:
937 result = vir_FCEIL(c, src[0]);
938 break;
939 case nir_op_ffloor:
940 result = vir_FFLOOR(c, src[0]);
941 break;
942 case nir_op_fround_even:
943 result = vir_FROUND(c, src[0]);
944 break;
945 case nir_op_ftrunc:
946 result = vir_FTRUNC(c, src[0]);
947 break;
948 case nir_op_ffract:
949 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
950 break;
951
952 case nir_op_fsin:
953 result = ntq_fsincos(c, src[0], false);
954 break;
955 case nir_op_fcos:
956 result = ntq_fsincos(c, src[0], true);
957 break;
958
959 case nir_op_fsign:
960 result = ntq_fsign(c, src[0]);
961 break;
962 case nir_op_isign:
963 result = ntq_isign(c, src[0]);
964 break;
965
966 case nir_op_fabs: {
967 result = vir_FMOV(c, src[0]);
968 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
969 break;
970 }
971
972 case nir_op_iabs:
973 result = vir_MAX(c, src[0],
974 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
975 break;
976
977 case nir_op_fddx:
978 case nir_op_fddx_coarse:
979 case nir_op_fddx_fine:
980 result = vir_FDX(c, src[0]);
981 break;
982
983 case nir_op_fddy:
984 case nir_op_fddy_coarse:
985 case nir_op_fddy_fine:
986 result = vir_FDY(c, src[0]);
987 break;
988
989 default:
990 fprintf(stderr, "unknown NIR ALU inst: ");
991 nir_print_instr(&instr->instr, stderr);
992 fprintf(stderr, "\n");
993 abort();
994 }
995
996 /* We have a scalar result, so the instruction should only have a
997 * single channel written to.
998 */
999 assert(util_is_power_of_two(instr->dest.write_mask));
1000 ntq_store_dest(c, &instr->dest.dest,
1001 ffs(instr->dest.write_mask) - 1, result);
1002 }
1003
1004 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1005 * specifier. They come from a register that's preloaded with 0xffffffff
1006 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1007 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1008 */
1009 #define TLB_TYPE_F16_COLOR (3 << 6)
1010 #define TLB_TYPE_I32_COLOR (1 << 6)
1011 #define TLB_TYPE_F32_COLOR (0 << 6)
1012 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1013 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1014 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1015 #define TLB_F16_SWAP_HI_LO (1 << 1)
1016 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1017 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1018 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1019
1020 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1021 * flag is set.
1022 */
1023 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1024 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1025 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1026
1027 /* Stencil is a single 32-bit write. */
1028 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1029
1030 static void
1031 emit_frag_end(struct v3d_compile *c)
1032 {
1033 uint32_t discard_cond = V3D_QPU_COND_NONE;
1034 if (c->s->info.fs.uses_discard) {
1035 vir_PF(c, vir_MOV(c, c->discard), V3D_QPU_PF_PUSHZ);
1036 discard_cond = V3D_QPU_COND_IFA;
1037 }
1038
1039 /* XXX
1040 if (c->output_sample_mask_index != -1) {
1041 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1042 }
1043 */
1044
1045 if (c->output_position_index != -1) {
1046 struct qinst *inst = vir_MOV_dest(c,
1047 vir_reg(QFILE_TLBU, 0),
1048 c->outputs[c->output_position_index]);
1049 vir_set_cond(inst, discard_cond);
1050
1051 inst->src[vir_get_implicit_uniform_src(inst)] =
1052 vir_uniform_ui(c,
1053 TLB_TYPE_DEPTH |
1054 TLB_DEPTH_TYPE_PER_PIXEL |
1055 0xffffff00);
1056 } else if (c->s->info.fs.uses_discard) {
1057 struct qinst *inst = vir_MOV_dest(c,
1058 vir_reg(QFILE_TLBU, 0),
1059 vir_reg(QFILE_NULL, 0));
1060 vir_set_cond(inst, discard_cond);
1061
1062 inst->src[vir_get_implicit_uniform_src(inst)] =
1063 vir_uniform_ui(c,
1064 TLB_TYPE_DEPTH |
1065 TLB_DEPTH_TYPE_INVARIANT |
1066 0xffffff00);
1067 }
1068
1069 /* XXX: Performance improvement: Merge Z write and color writes TLB
1070 * uniform setup
1071 */
1072
1073 if (c->output_color_var) {
1074 nir_variable *var = c->output_color_var;
1075 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1076 int num_components = glsl_get_vector_elements(var->type);
1077 uint32_t conf = ~0;
1078 struct qinst *inst;
1079
1080 assert(num_components != 0);
1081 switch (glsl_get_base_type(var->type)) {
1082 case GLSL_TYPE_UINT:
1083 case GLSL_TYPE_INT:
1084 conf = (TLB_TYPE_I32_COLOR |
1085 TLB_SAMPLE_MODE_PER_PIXEL |
1086 ((7 - 0) << TLB_RENDER_TARGET_SHIFT) |
1087 ((num_components - 1) <<
1088 TLB_VEC_SIZE_MINUS_1_SHIFT) |
1089 0xffffff00);
1090
1091
1092 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1093 vir_set_cond(inst, discard_cond);
1094 inst->src[vir_get_implicit_uniform_src(inst)] =
1095 vir_uniform_ui(c, conf);
1096
1097 for (int i = 1; i < num_components; i++) {
1098 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1099 color[i]);
1100 vir_set_cond(inst, discard_cond);
1101 }
1102 break;
1103
1104 default: {
1105 struct qreg r = color[0];
1106 struct qreg g = color[1];
1107 struct qreg b = color[2];
1108 struct qreg a = color[3];
1109
1110 if (c->fs_key->swap_color_rb) {
1111 r = color[2];
1112 b = color[0];
1113 }
1114
1115 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1116 vir_set_cond(inst, discard_cond);
1117 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1118 vir_set_cond(inst, discard_cond);
1119 break;
1120 }
1121 }
1122 }
1123 }
1124
1125 static void
1126 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1127 {
1128 for (int i = 0; i < 2; i++) {
1129 struct qreg coord = c->outputs[c->output_position_index + i];
1130 coord = vir_FMUL(c, coord,
1131 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1132 0));
1133 coord = vir_FMUL(c, coord, rcp_w);
1134 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1135 coord);
1136 }
1137
1138 }
1139
1140 static void
1141 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1142 {
1143 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1144 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1145
1146 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1147 vir_FMUL(c, vir_FMUL(c,
1148 c->outputs[c->output_position_index + 2],
1149 zscale),
1150 rcp_w),
1151 zoffset);
1152 }
1153
1154 static void
1155 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1156 {
1157 vir_VPM_WRITE(c, rcp_w);
1158 }
1159
1160 static void
1161 emit_point_size_write(struct v3d_compile *c)
1162 {
1163 struct qreg point_size;
1164
1165 if (c->output_point_size_index != -1)
1166 point_size = c->outputs[c->output_point_size_index];
1167 else
1168 point_size = vir_uniform_f(c, 1.0);
1169
1170 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1171 * BCM21553).
1172 */
1173 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1174
1175 vir_VPM_WRITE(c, point_size);
1176 }
1177
1178 static void
1179 emit_vpm_write_setup(struct v3d_compile *c)
1180 {
1181 uint32_t packed;
1182 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1183 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1184
1185 .horiz = true,
1186 .laned = false,
1187 .segs = true,
1188 .stride = 1,
1189 .size = VPM_SETUP_SIZE_32_BIT,
1190 .addr = 0,
1191 };
1192
1193 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1194 (uint8_t *)&packed,
1195 &unpacked);
1196 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1197 }
1198
1199 static void
1200 emit_vert_end(struct v3d_compile *c)
1201 {
1202 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1203 c->outputs[c->output_position_index + 3]);
1204
1205 emit_vpm_write_setup(c);
1206
1207 if (c->vs_key->is_coord) {
1208 for (int i = 0; i < 4; i++)
1209 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1210 emit_scaled_viewport_write(c, rcp_w);
1211 if (c->vs_key->per_vertex_point_size) {
1212 emit_point_size_write(c);
1213 /* emit_rcp_wc_write(c, rcp_w); */
1214 }
1215 /* XXX: Z-only rendering */
1216 if (0)
1217 emit_zs_write(c, rcp_w);
1218 } else {
1219 emit_scaled_viewport_write(c, rcp_w);
1220 emit_zs_write(c, rcp_w);
1221 emit_rcp_wc_write(c, rcp_w);
1222 if (c->vs_key->per_vertex_point_size)
1223 emit_point_size_write(c);
1224 }
1225
1226 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1227 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1228 int j;
1229
1230 for (j = 0; j < c->num_outputs; j++) {
1231 struct v3d_varying_slot output = c->output_slots[j];
1232
1233 if (!memcmp(&input, &output, sizeof(input))) {
1234 vir_VPM_WRITE(c, c->outputs[j]);
1235 break;
1236 }
1237 }
1238 /* Emit padding if we didn't find a declared VS output for
1239 * this FS input.
1240 */
1241 if (j == c->num_outputs)
1242 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1243 }
1244 }
1245
1246 void
1247 v3d_optimize_nir(struct nir_shader *s)
1248 {
1249 bool progress;
1250
1251 do {
1252 progress = false;
1253
1254 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1255 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1256 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1257 NIR_PASS(progress, s, nir_copy_prop);
1258 NIR_PASS(progress, s, nir_opt_remove_phis);
1259 NIR_PASS(progress, s, nir_opt_dce);
1260 NIR_PASS(progress, s, nir_opt_dead_cf);
1261 NIR_PASS(progress, s, nir_opt_cse);
1262 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1263 NIR_PASS(progress, s, nir_opt_algebraic);
1264 NIR_PASS(progress, s, nir_opt_constant_folding);
1265 NIR_PASS(progress, s, nir_opt_undef);
1266 } while (progress);
1267 }
1268
1269 static int
1270 driver_location_compare(const void *in_a, const void *in_b)
1271 {
1272 const nir_variable *const *a = in_a;
1273 const nir_variable *const *b = in_b;
1274
1275 return (*a)->data.driver_location - (*b)->data.driver_location;
1276 }
1277
1278 static struct qreg
1279 ntq_emit_vpm_read(struct v3d_compile *c,
1280 uint32_t *num_components_queued,
1281 uint32_t *remaining,
1282 uint32_t vpm_index)
1283 {
1284 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1285
1286 if (*num_components_queued != 0) {
1287 (*num_components_queued)--;
1288 c->num_inputs++;
1289 return vir_MOV(c, vpm);
1290 }
1291
1292 uint32_t num_components = MIN2(*remaining, 32);
1293
1294 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1295 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1296
1297 .horiz = true,
1298 .laned = false,
1299 /* If the field is 0, that means a read count of 32. */
1300 .num = num_components & 31,
1301 .segs = true,
1302 .stride = 1,
1303 .size = VPM_SETUP_SIZE_32_BIT,
1304 .addr = c->num_inputs,
1305 };
1306
1307 uint32_t packed;
1308 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1309 (uint8_t *)&packed,
1310 &unpacked);
1311 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1312
1313 *num_components_queued = num_components - 1;
1314 *remaining -= num_components;
1315 c->num_inputs++;
1316
1317 return vir_MOV(c, vpm);
1318 }
1319
1320 static void
1321 ntq_setup_inputs(struct v3d_compile *c)
1322 {
1323 unsigned num_entries = 0;
1324 unsigned num_components = 0;
1325 nir_foreach_variable(var, &c->s->inputs) {
1326 num_entries++;
1327 num_components += glsl_get_components(var->type);
1328 }
1329
1330 nir_variable *vars[num_entries];
1331
1332 unsigned i = 0;
1333 nir_foreach_variable(var, &c->s->inputs)
1334 vars[i++] = var;
1335
1336 /* Sort the variables so that we emit the input setup in
1337 * driver_location order. This is required for VPM reads, whose data
1338 * is fetched into the VPM in driver_location (TGSI register index)
1339 * order.
1340 */
1341 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1342
1343 uint32_t vpm_components_queued = 0;
1344 if (c->s->stage == MESA_SHADER_VERTEX) {
1345 bool uses_iid = c->s->info.system_values_read &
1346 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1347 bool uses_vid = c->s->info.system_values_read &
1348 (1ull << SYSTEM_VALUE_VERTEX_ID);
1349
1350 num_components += uses_iid;
1351 num_components += uses_vid;
1352
1353 if (uses_iid) {
1354 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1355 &num_components, ~0);
1356 }
1357
1358 if (uses_vid) {
1359 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1360 &num_components, ~0);
1361 }
1362 }
1363
1364 for (unsigned i = 0; i < num_entries; i++) {
1365 nir_variable *var = vars[i];
1366 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1367 unsigned loc = var->data.driver_location;
1368
1369 assert(array_len == 1);
1370 (void)array_len;
1371 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1372 (loc + 1) * 4);
1373
1374 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1375 if (var->data.location == VARYING_SLOT_POS) {
1376 emit_fragcoord_input(c, loc);
1377 } else if (var->data.location == VARYING_SLOT_PNTC ||
1378 (var->data.location >= VARYING_SLOT_VAR0 &&
1379 (c->fs_key->point_sprite_mask &
1380 (1 << (var->data.location -
1381 VARYING_SLOT_VAR0))))) {
1382 c->inputs[loc * 4 + 0] = c->point_x;
1383 c->inputs[loc * 4 + 1] = c->point_y;
1384 } else {
1385 emit_fragment_input(c, loc, var);
1386 }
1387 } else {
1388 int var_components = glsl_get_components(var->type);
1389
1390 for (int i = 0; i < var_components; i++) {
1391 c->inputs[loc * 4 + i] =
1392 ntq_emit_vpm_read(c,
1393 &vpm_components_queued,
1394 &num_components,
1395 loc * 4 + i);
1396
1397 }
1398 c->vattr_sizes[loc] = var_components;
1399 }
1400 }
1401
1402 if (c->s->stage == MESA_SHADER_VERTEX) {
1403 assert(vpm_components_queued == 0);
1404 assert(num_components == 0);
1405 }
1406 }
1407
1408 static void
1409 ntq_setup_outputs(struct v3d_compile *c)
1410 {
1411 nir_foreach_variable(var, &c->s->outputs) {
1412 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1413 unsigned loc = var->data.driver_location * 4;
1414
1415 assert(array_len == 1);
1416 (void)array_len;
1417
1418 for (int i = 0; i < 4; i++)
1419 add_output(c, loc + i, var->data.location, i);
1420
1421 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1422 switch (var->data.location) {
1423 case FRAG_RESULT_COLOR:
1424 case FRAG_RESULT_DATA0:
1425 c->output_color_var = var;
1426 break;
1427 case FRAG_RESULT_DEPTH:
1428 c->output_position_index = loc;
1429 break;
1430 case FRAG_RESULT_SAMPLE_MASK:
1431 c->output_sample_mask_index = loc;
1432 break;
1433 }
1434 } else {
1435 switch (var->data.location) {
1436 case VARYING_SLOT_POS:
1437 c->output_position_index = loc;
1438 break;
1439 case VARYING_SLOT_PSIZ:
1440 c->output_point_size_index = loc;
1441 break;
1442 }
1443 }
1444 }
1445 }
1446
1447 static void
1448 ntq_setup_uniforms(struct v3d_compile *c)
1449 {
1450 nir_foreach_variable(var, &c->s->uniforms) {
1451 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1452 false);
1453 unsigned vec4_size = 4 * sizeof(float);
1454
1455 declare_uniform_range(c, var->data.driver_location * vec4_size,
1456 vec4_count * vec4_size);
1457
1458 }
1459 }
1460
1461 /**
1462 * Sets up the mapping from nir_register to struct qreg *.
1463 *
1464 * Each nir_register gets a struct qreg per 32-bit component being stored.
1465 */
1466 static void
1467 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1468 {
1469 foreach_list_typed(nir_register, nir_reg, node, list) {
1470 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1471 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1472 array_len *
1473 nir_reg->num_components);
1474
1475 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1476
1477 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1478 qregs[i] = vir_get_temp(c);
1479 }
1480 }
1481
1482 static void
1483 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1484 {
1485 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1486 for (int i = 0; i < instr->def.num_components; i++)
1487 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1488
1489 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1490 }
1491
1492 static void
1493 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1494 {
1495 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1496
1497 /* VIR needs there to be *some* value, so pick 0 (same as for
1498 * ntq_setup_registers().
1499 */
1500 for (int i = 0; i < instr->def.num_components; i++)
1501 qregs[i] = vir_uniform_ui(c, 0);
1502 }
1503
1504 static void
1505 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1506 {
1507 nir_const_value *const_offset;
1508 unsigned offset;
1509
1510 switch (instr->intrinsic) {
1511 case nir_intrinsic_load_uniform:
1512 assert(instr->num_components == 1);
1513 const_offset = nir_src_as_const_value(instr->src[0]);
1514 if (const_offset) {
1515 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1516 assert(offset % 4 == 0);
1517 /* We need dwords */
1518 offset = offset / 4;
1519 ntq_store_dest(c, &instr->dest, 0,
1520 vir_uniform(c, QUNIFORM_UNIFORM,
1521 offset));
1522 } else {
1523 ntq_store_dest(c, &instr->dest, 0,
1524 indirect_uniform_load(c, instr));
1525 }
1526 break;
1527
1528 case nir_intrinsic_load_ubo:
1529 for (int i = 0; i < instr->num_components; i++) {
1530 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1531
1532 /* Adjust for where we stored the TGSI register base. */
1533 vir_ADD_dest(c,
1534 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1535 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1536 vir_ADD(c,
1537 ntq_get_src(c, instr->src[1], 0),
1538 vir_uniform_ui(c, i * 4)));
1539
1540 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1541 }
1542 break;
1543
1544 const_offset = nir_src_as_const_value(instr->src[0]);
1545 if (const_offset) {
1546 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1547 assert(offset % 4 == 0);
1548 /* We need dwords */
1549 offset = offset / 4;
1550 ntq_store_dest(c, &instr->dest, 0,
1551 vir_uniform(c, QUNIFORM_UNIFORM,
1552 offset));
1553 } else {
1554 ntq_store_dest(c, &instr->dest, 0,
1555 indirect_uniform_load(c, instr));
1556 }
1557 break;
1558
1559 case nir_intrinsic_load_user_clip_plane:
1560 for (int i = 0; i < instr->num_components; i++) {
1561 ntq_store_dest(c, &instr->dest, i,
1562 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1563 nir_intrinsic_ucp_id(instr) *
1564 4 + i));
1565 }
1566 break;
1567
1568 case nir_intrinsic_load_alpha_ref_float:
1569 ntq_store_dest(c, &instr->dest, 0,
1570 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1571 break;
1572
1573 case nir_intrinsic_load_sample_mask_in:
1574 ntq_store_dest(c, &instr->dest, 0,
1575 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1576 break;
1577
1578 case nir_intrinsic_load_front_face:
1579 /* The register contains 0 (front) or 1 (back), and we need to
1580 * turn it into a NIR bool where true means front.
1581 */
1582 ntq_store_dest(c, &instr->dest, 0,
1583 vir_ADD(c,
1584 vir_uniform_ui(c, -1),
1585 vir_REVF(c)));
1586 break;
1587
1588 case nir_intrinsic_load_instance_id:
1589 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1590 break;
1591
1592 case nir_intrinsic_load_vertex_id:
1593 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1594 break;
1595
1596 case nir_intrinsic_load_input:
1597 const_offset = nir_src_as_const_value(instr->src[0]);
1598 assert(const_offset && "v3d doesn't support indirect inputs");
1599 for (int i = 0; i < instr->num_components; i++) {
1600 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1601 int comp = nir_intrinsic_component(instr) + i;
1602 ntq_store_dest(c, &instr->dest, i,
1603 vir_MOV(c, c->inputs[offset * 4 + comp]));
1604 }
1605 break;
1606
1607 case nir_intrinsic_store_output:
1608 const_offset = nir_src_as_const_value(instr->src[1]);
1609 assert(const_offset && "v3d doesn't support indirect outputs");
1610 offset = ((nir_intrinsic_base(instr) +
1611 const_offset->u32[0]) * 4 +
1612 nir_intrinsic_component(instr));
1613
1614 for (int i = 0; i < instr->num_components; i++) {
1615 c->outputs[offset + i] =
1616 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1617 }
1618 c->num_outputs = MAX2(c->num_outputs,
1619 offset + instr->num_components);
1620 break;
1621
1622 case nir_intrinsic_discard:
1623 if (c->execute.file != QFILE_NULL) {
1624 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1625 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard,
1626 vir_uniform_ui(c, ~0));
1627 } else {
1628 vir_MOV_dest(c, c->discard, vir_uniform_ui(c, ~0));
1629 }
1630 break;
1631
1632 case nir_intrinsic_discard_if: {
1633 /* true (~0) if we're discarding */
1634 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1635
1636 if (c->execute.file != QFILE_NULL) {
1637 /* execute == 0 means the channel is active. Invert
1638 * the condition so that we can use zero as "executing
1639 * and discarding."
1640 */
1641 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1642 V3D_QPU_PF_PUSHZ);
1643 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->discard, cond);
1644 } else {
1645 vir_OR_dest(c, c->discard, c->discard, cond);
1646 }
1647
1648 break;
1649 }
1650
1651 default:
1652 fprintf(stderr, "Unknown intrinsic: ");
1653 nir_print_instr(&instr->instr, stderr);
1654 fprintf(stderr, "\n");
1655 break;
1656 }
1657 }
1658
1659 /* Clears (activates) the execute flags for any channels whose jump target
1660 * matches this block.
1661 */
1662 static void
1663 ntq_activate_execute_for_block(struct v3d_compile *c)
1664 {
1665 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1666 V3D_QPU_PF_PUSHZ);
1667
1668 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1669 }
1670
1671 static void
1672 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1673 {
1674 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1675 bool empty_else_block =
1676 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1677 exec_list_is_empty(&nir_else_block->instr_list));
1678
1679 struct qblock *then_block = vir_new_block(c);
1680 struct qblock *after_block = vir_new_block(c);
1681 struct qblock *else_block;
1682 if (empty_else_block)
1683 else_block = after_block;
1684 else
1685 else_block = vir_new_block(c);
1686
1687 bool was_top_level = false;
1688 if (c->execute.file == QFILE_NULL) {
1689 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1690 was_top_level = true;
1691 }
1692
1693 /* Set A for executing (execute == 0) and jumping (if->condition ==
1694 * 0) channels, and then update execute flags for those to point to
1695 * the ELSE block.
1696 */
1697 vir_PF(c, vir_OR(c,
1698 c->execute,
1699 ntq_get_src(c, if_stmt->condition, 0)),
1700 V3D_QPU_PF_PUSHZ);
1701 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1702 c->execute,
1703 vir_uniform_ui(c, else_block->index));
1704
1705 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1706 * through.
1707 */
1708 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1709 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1710 vir_link_blocks(c->cur_block, else_block);
1711 vir_link_blocks(c->cur_block, then_block);
1712
1713 /* Process the THEN block. */
1714 vir_set_emit_block(c, then_block);
1715 ntq_emit_cf_list(c, &if_stmt->then_list);
1716
1717 if (!empty_else_block) {
1718 /* Handle the end of the THEN block. First, all currently
1719 * active channels update their execute flags to point to
1720 * ENDIF
1721 */
1722 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1723 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1724 vir_uniform_ui(c, after_block->index));
1725
1726 /* If everything points at ENDIF, then jump there immediately. */
1727 vir_PF(c, vir_SUB(c, c->execute,
1728 vir_uniform_ui(c, after_block->index)),
1729 V3D_QPU_PF_PUSHZ);
1730 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1731 vir_link_blocks(c->cur_block, after_block);
1732 vir_link_blocks(c->cur_block, else_block);
1733
1734 vir_set_emit_block(c, else_block);
1735 ntq_activate_execute_for_block(c);
1736 ntq_emit_cf_list(c, &if_stmt->else_list);
1737 }
1738
1739 vir_link_blocks(c->cur_block, after_block);
1740
1741 vir_set_emit_block(c, after_block);
1742 if (was_top_level)
1743 c->execute = c->undef;
1744 else
1745 ntq_activate_execute_for_block(c);
1746 }
1747
1748 static void
1749 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1750 {
1751 switch (jump->type) {
1752 case nir_jump_break:
1753 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1754 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1755 vir_uniform_ui(c, c->loop_break_block->index));
1756 break;
1757
1758 case nir_jump_continue:
1759 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1760 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1761 vir_uniform_ui(c, c->loop_cont_block->index));
1762 break;
1763
1764 case nir_jump_return:
1765 unreachable("All returns shouold be lowered\n");
1766 }
1767 }
1768
1769 static void
1770 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1771 {
1772 switch (instr->type) {
1773 case nir_instr_type_alu:
1774 ntq_emit_alu(c, nir_instr_as_alu(instr));
1775 break;
1776
1777 case nir_instr_type_intrinsic:
1778 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1779 break;
1780
1781 case nir_instr_type_load_const:
1782 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1783 break;
1784
1785 case nir_instr_type_ssa_undef:
1786 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1787 break;
1788
1789 case nir_instr_type_tex:
1790 ntq_emit_tex(c, nir_instr_as_tex(instr));
1791 break;
1792
1793 case nir_instr_type_jump:
1794 ntq_emit_jump(c, nir_instr_as_jump(instr));
1795 break;
1796
1797 default:
1798 fprintf(stderr, "Unknown NIR instr type: ");
1799 nir_print_instr(instr, stderr);
1800 fprintf(stderr, "\n");
1801 abort();
1802 }
1803 }
1804
1805 static void
1806 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1807 {
1808 nir_foreach_instr(instr, block) {
1809 ntq_emit_instr(c, instr);
1810 }
1811 }
1812
1813 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1814
1815 static void
1816 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1817 {
1818 bool was_top_level = false;
1819 if (c->execute.file == QFILE_NULL) {
1820 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1821 was_top_level = true;
1822 }
1823
1824 struct qblock *save_loop_cont_block = c->loop_cont_block;
1825 struct qblock *save_loop_break_block = c->loop_break_block;
1826
1827 c->loop_cont_block = vir_new_block(c);
1828 c->loop_break_block = vir_new_block(c);
1829
1830 vir_link_blocks(c->cur_block, c->loop_cont_block);
1831 vir_set_emit_block(c, c->loop_cont_block);
1832 ntq_activate_execute_for_block(c);
1833
1834 ntq_emit_cf_list(c, &loop->body);
1835
1836 /* Re-enable any previous continues now, so our ANYA check below
1837 * works.
1838 *
1839 * XXX: Use the .ORZ flags update, instead.
1840 */
1841 vir_PF(c, vir_SUB(c,
1842 c->execute,
1843 vir_uniform_ui(c, c->loop_cont_block->index)),
1844 V3D_QPU_PF_PUSHZ);
1845 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1846
1847 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1848
1849 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1850 vir_link_blocks(c->cur_block, c->loop_cont_block);
1851 vir_link_blocks(c->cur_block, c->loop_break_block);
1852
1853 vir_set_emit_block(c, c->loop_break_block);
1854 if (was_top_level)
1855 c->execute = c->undef;
1856 else
1857 ntq_activate_execute_for_block(c);
1858
1859 c->loop_break_block = save_loop_break_block;
1860 c->loop_cont_block = save_loop_cont_block;
1861 }
1862
1863 static void
1864 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1865 {
1866 fprintf(stderr, "FUNCTIONS not handled.\n");
1867 abort();
1868 }
1869
1870 static void
1871 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1872 {
1873 foreach_list_typed(nir_cf_node, node, node, list) {
1874 switch (node->type) {
1875 case nir_cf_node_block:
1876 ntq_emit_block(c, nir_cf_node_as_block(node));
1877 break;
1878
1879 case nir_cf_node_if:
1880 ntq_emit_if(c, nir_cf_node_as_if(node));
1881 break;
1882
1883 case nir_cf_node_loop:
1884 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1885 break;
1886
1887 case nir_cf_node_function:
1888 ntq_emit_function(c, nir_cf_node_as_function(node));
1889 break;
1890
1891 default:
1892 fprintf(stderr, "Unknown NIR node type\n");
1893 abort();
1894 }
1895 }
1896 }
1897
1898 static void
1899 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1900 {
1901 ntq_setup_registers(c, &impl->registers);
1902 ntq_emit_cf_list(c, &impl->body);
1903 }
1904
1905 static void
1906 nir_to_vir(struct v3d_compile *c)
1907 {
1908 if (c->s->stage == MESA_SHADER_FRAGMENT) {
1909 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1910 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1911 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1912
1913 if (c->s->info.fs.uses_discard)
1914 c->discard = vir_MOV(c, vir_uniform_ui(c, 0));
1915
1916 if (c->fs_key->is_points) {
1917 c->point_x = emit_fragment_varying(c, NULL, 0);
1918 c->point_y = emit_fragment_varying(c, NULL, 0);
1919 } else if (c->fs_key->is_lines) {
1920 c->line_x = emit_fragment_varying(c, NULL, 0);
1921 }
1922 }
1923
1924 ntq_setup_inputs(c);
1925 ntq_setup_outputs(c);
1926 ntq_setup_uniforms(c);
1927 ntq_setup_registers(c, &c->s->registers);
1928
1929 /* Find the main function and emit the body. */
1930 nir_foreach_function(function, c->s) {
1931 assert(strcmp(function->name, "main") == 0);
1932 assert(function->impl);
1933 ntq_emit_impl(c, function->impl);
1934 }
1935 }
1936
1937 const nir_shader_compiler_options v3d_nir_options = {
1938 .lower_extract_byte = true,
1939 .lower_extract_word = true,
1940 .lower_bitfield_insert = true,
1941 .lower_bitfield_extract = true,
1942 .lower_ffma = true,
1943 .lower_flrp32 = true,
1944 .lower_fpow = true,
1945 .lower_fsat = true,
1946 .lower_fsqrt = true,
1947 .lower_negate = true,
1948 .native_integers = true,
1949 };
1950
1951
1952 #if 0
1953 static int
1954 count_nir_instrs(nir_shader *nir)
1955 {
1956 int count = 0;
1957 nir_foreach_function(function, nir) {
1958 if (!function->impl)
1959 continue;
1960 nir_foreach_block(block, function->impl) {
1961 nir_foreach_instr(instr, block)
1962 count++;
1963 }
1964 }
1965 return count;
1966 }
1967 #endif
1968
1969 void
1970 v3d_nir_to_vir(struct v3d_compile *c)
1971 {
1972 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1973 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1974 fprintf(stderr, "%s prog %d/%d NIR:\n",
1975 vir_get_stage_name(c),
1976 c->program_id, c->variant_id);
1977 nir_print_shader(c->s, stderr);
1978 }
1979
1980 nir_to_vir(c);
1981
1982 switch (c->s->stage) {
1983 case MESA_SHADER_FRAGMENT:
1984 emit_frag_end(c);
1985 break;
1986 case MESA_SHADER_VERTEX:
1987 emit_vert_end(c);
1988 break;
1989 default:
1990 unreachable("bad stage");
1991 }
1992
1993 if (V3D_DEBUG & (V3D_DEBUG_VIR |
1994 v3d_debug_flag_for_shader_stage(c->s->stage))) {
1995 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
1996 vir_get_stage_name(c),
1997 c->program_id, c->variant_id);
1998 vir_dump(c);
1999 fprintf(stderr, "\n");
2000 }
2001
2002 vir_optimize(c);
2003 vir_lower_uniforms(c);
2004
2005 /* XXX: vir_schedule_instructions(c); */
2006
2007 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2008 v3d_debug_flag_for_shader_stage(c->s->stage))) {
2009 fprintf(stderr, "%s prog %d/%d VIR:\n",
2010 vir_get_stage_name(c),
2011 c->program_id, c->variant_id);
2012 vir_dump(c);
2013 fprintf(stderr, "\n");
2014 }
2015
2016 v3d_vir_to_qpu(c);
2017 }