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broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 /* XXX: Needs base level addition */
384 coords[next_coord++] =
385 ntq_get_src(c, instr->src[i].src, 0);
386
387 if (instr->op != nir_texop_txf &&
388 instr->op != nir_texop_tg4) {
389 p0_unpacked.disable_autolod_use_bias_only = true;
390 }
391 break;
392 case nir_tex_src_comparator:
393 coords[next_coord++] =
394 ntq_get_src(c, instr->src[i].src, 0);
395
396 p0_unpacked.shadow = true;
397 break;
398
399 case nir_tex_src_offset: {
400 nir_const_value *offset =
401 nir_src_as_const_value(instr->src[i].src);
402 p0_unpacked.texel_offset_for_s_coordinate =
403 offset->i32[0];
404
405 if (instr->coord_components >= 2)
406 p0_unpacked.texel_offset_for_t_coordinate =
407 offset->i32[1];
408
409 if (instr->coord_components >= 3)
410 p0_unpacked.texel_offset_for_r_coordinate =
411 offset->i32[2];
412 break;
413 }
414
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 uint32_t p0_packed;
421 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
422 (uint8_t *)&p0_packed,
423 &p0_unpacked);
424
425 /* There is no native support for GL texture rectangle coordinates, so
426 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
427 * 1]).
428 */
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
430 coords[0] = vir_FMUL(c, coords[0],
431 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
432 unit));
433 coords[1] = vir_FMUL(c, coords[1],
434 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
435 unit));
436 }
437
438 struct qreg texture_u[] = {
439 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
440 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
441 };
442 uint32_t next_texture_u = 0;
443
444 for (int i = 0; i < next_coord; i++) {
445 struct qreg dst;
446
447 if (i == next_coord - 1)
448 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
449 else
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
451
452 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
453
454 if (i < 2) {
455 tmu->has_implicit_uniform = true;
456 tmu->src[vir_get_implicit_uniform_src(tmu)] =
457 texture_u[next_texture_u++];
458 }
459 }
460
461 bool return_16 = (c->key->tex[unit].return_size == 16 ||
462 p0_unpacked.shadow);
463
464 struct qreg return_values[4];
465 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
466 return_values[i] = vir_LDTMU(c);
467 /* Swizzling .zw of an RG texture should give undefined results, not
468 * crash the compiler.
469 */
470 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
471 return_values[i] = c->undef;
472
473 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
474 struct qreg chan;
475
476 if (return_16) {
477 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
478 chan = return_values[i / 2];
479
480 if (nir_alu_type_get_base_type(instr->dest_type) ==
481 nir_type_float) {
482 enum v3d_qpu_input_unpack unpack;
483 if (i & 1)
484 unpack = V3D_QPU_UNPACK_H;
485 else
486 unpack = V3D_QPU_UNPACK_L;
487
488 chan = vir_FMOV(c, chan);
489 vir_set_unpack(c->defs[chan.index], 0, unpack);
490 } else {
491 /* If we're unpacking the low field, shift it
492 * up to the top first.
493 */
494 if ((i & 1) == 0) {
495 chan = vir_SHL(c, chan,
496 vir_uniform_ui(c, 16));
497 }
498
499 /* Do proper sign extension to a 32-bit int. */
500 if (nir_alu_type_get_base_type(instr->dest_type) ==
501 nir_type_int) {
502 chan = vir_ASR(c, chan,
503 vir_uniform_ui(c, 16));
504 } else {
505 chan = vir_SHR(c, chan,
506 vir_uniform_ui(c, 16));
507 }
508 }
509 } else {
510 chan = vir_MOV(c, return_values[i]);
511 }
512 ntq_store_dest(c, &instr->dest, i, chan);
513 }
514 }
515
516 static struct qreg
517 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
518 {
519 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
520 if (is_cos)
521 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
522
523 struct qreg periods = vir_FROUND(c, input);
524 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
525 vir_FSUB(c, input, periods));
526 return vir_XOR(c, sin_output, vir_SHL(c,
527 vir_FTOIN(c, periods),
528 vir_uniform_ui(c, -1)));
529 }
530
531 static struct qreg
532 ntq_fsign(struct v3d_compile *c, struct qreg src)
533 {
534 struct qreg t = vir_get_temp(c);
535
536 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
537 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
538 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
539 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
540 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
541 return vir_MOV(c, t);
542 }
543
544 static struct qreg
545 ntq_isign(struct v3d_compile *c, struct qreg src)
546 {
547 struct qreg t = vir_get_temp(c);
548
549 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
550 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
551 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
552 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
553 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
554 return vir_MOV(c, t);
555 }
556
557 static void
558 emit_fragcoord_input(struct v3d_compile *c, int attr)
559 {
560 c->inputs[attr * 4 + 0] = vir_FXCD(c);
561 c->inputs[attr * 4 + 1] = vir_FYCD(c);
562 c->inputs[attr * 4 + 2] = c->payload_z;
563 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
564 c->payload_w);
565 }
566
567 static struct qreg
568 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
569 uint8_t swizzle)
570 {
571 struct qreg vary = vir_reg(QFILE_VARY, ~0);
572 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
573
574 /* For gl_PointCoord input or distance along a line, we'll be called
575 * with no nir_variable, and we don't count toward VPM size so we
576 * don't track an input slot.
577 */
578 if (!var) {
579 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
580 }
581
582 int i = c->num_inputs++;
583 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
584 swizzle);
585
586 switch (var->data.interpolation) {
587 case INTERP_MODE_NONE:
588 /* If a gl_FrontColor or gl_BackColor input has no interp
589 * qualifier, then flag it for glShadeModel() handling by the
590 * driver.
591 */
592 switch (var->data.location) {
593 case VARYING_SLOT_COL0:
594 case VARYING_SLOT_COL1:
595 case VARYING_SLOT_BFC0:
596 case VARYING_SLOT_BFC1:
597 BITSET_SET(c->shade_model_flags, i);
598 break;
599 default:
600 break;
601 }
602 /* FALLTHROUGH */
603 case INTERP_MODE_SMOOTH:
604 if (var->data.centroid) {
605 return vir_FADD(c, vir_FMUL(c, vary,
606 c->payload_w_centroid), r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
609 }
610 case INTERP_MODE_NOPERSPECTIVE:
611 /* C appears after the mov from the varying.
612 XXX: improve ldvary setup.
613 */
614 return vir_FADD(c, vir_MOV(c, vary), r5);
615 case INTERP_MODE_FLAT:
616 BITSET_SET(c->flat_shade_flags, i);
617 vir_MOV_dest(c, c->undef, vary);
618 return vir_MOV(c, r5);
619 default:
620 unreachable("Bad interp mode");
621 }
622 }
623
624 static void
625 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
626 {
627 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
628 c->inputs[attr * 4 + i] =
629 emit_fragment_varying(c, var, i);
630 }
631 }
632
633 static void
634 add_output(struct v3d_compile *c,
635 uint32_t decl_offset,
636 uint8_t slot,
637 uint8_t swizzle)
638 {
639 uint32_t old_array_size = c->outputs_array_size;
640 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
641 decl_offset + 1);
642
643 if (old_array_size != c->outputs_array_size) {
644 c->output_slots = reralloc(c,
645 c->output_slots,
646 struct v3d_varying_slot,
647 c->outputs_array_size);
648 }
649
650 c->output_slots[decl_offset] =
651 v3d_slot_from_slot_and_component(slot, swizzle);
652 }
653
654 static void
655 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
656 {
657 unsigned array_id = c->num_ubo_ranges++;
658 if (array_id >= c->ubo_ranges_array_size) {
659 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
660 array_id + 1);
661 c->ubo_ranges = reralloc(c, c->ubo_ranges,
662 struct v3d_ubo_range,
663 c->ubo_ranges_array_size);
664 c->ubo_range_used = reralloc(c, c->ubo_range_used,
665 bool,
666 c->ubo_ranges_array_size);
667 }
668
669 c->ubo_ranges[array_id].dst_offset = 0;
670 c->ubo_ranges[array_id].src_offset = start;
671 c->ubo_ranges[array_id].size = size;
672 c->ubo_range_used[array_id] = false;
673 }
674
675 /**
676 * If compare_instr is a valid comparison instruction, emits the
677 * compare_instr's comparison and returns the sel_instr's return value based
678 * on the compare_instr's result.
679 */
680 static bool
681 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
682 nir_alu_instr *compare_instr,
683 nir_alu_instr *sel_instr)
684 {
685 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
686 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
687 bool cond_invert = false;
688
689 switch (compare_instr->op) {
690 case nir_op_feq:
691 case nir_op_seq:
692 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
693 break;
694 case nir_op_ieq:
695 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
696 break;
697
698 case nir_op_fne:
699 case nir_op_sne:
700 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
701 cond_invert = true;
702 break;
703 case nir_op_ine:
704 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
705 cond_invert = true;
706 break;
707
708 case nir_op_fge:
709 case nir_op_sge:
710 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
711 break;
712 case nir_op_ige:
713 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
714 cond_invert = true;
715 break;
716 case nir_op_uge:
717 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
718 cond_invert = true;
719 break;
720
721 case nir_op_slt:
722 case nir_op_flt:
723 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
724 break;
725 case nir_op_ilt:
726 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ult:
729 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
730 break;
731
732 default:
733 return false;
734 }
735
736 enum v3d_qpu_cond cond = (cond_invert ?
737 V3D_QPU_COND_IFNA :
738 V3D_QPU_COND_IFA);
739
740 switch (sel_instr->op) {
741 case nir_op_seq:
742 case nir_op_sne:
743 case nir_op_sge:
744 case nir_op_slt:
745 *dest = vir_SEL(c, cond,
746 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
747 break;
748
749 case nir_op_bcsel:
750 *dest = vir_SEL(c, cond,
751 ntq_get_alu_src(c, sel_instr, 1),
752 ntq_get_alu_src(c, sel_instr, 2));
753 break;
754
755 default:
756 *dest = vir_SEL(c, cond,
757 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
758 break;
759 }
760
761 /* Make the temporary for nir_store_dest(). */
762 *dest = vir_MOV(c, *dest);
763
764 return true;
765 }
766
767 /**
768 * Attempts to fold a comparison generating a boolean result into the
769 * condition code for selecting between two values, instead of comparing the
770 * boolean result against 0 to generate the condition code.
771 */
772 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
773 struct qreg *src)
774 {
775 if (!instr->src[0].src.is_ssa)
776 goto out;
777 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
778 goto out;
779 nir_alu_instr *compare =
780 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
781 if (!compare)
782 goto out;
783
784 struct qreg dest;
785 if (ntq_emit_comparison(c, &dest, compare, instr))
786 return dest;
787
788 out:
789 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
790 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
791 }
792
793
794 static void
795 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
796 {
797 /* This should always be lowered to ALU operations for V3D. */
798 assert(!instr->dest.saturate);
799
800 /* Vectors are special in that they have non-scalarized writemasks,
801 * and just take the first swizzle channel for each argument in order
802 * into each writemask channel.
803 */
804 if (instr->op == nir_op_vec2 ||
805 instr->op == nir_op_vec3 ||
806 instr->op == nir_op_vec4) {
807 struct qreg srcs[4];
808 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
809 srcs[i] = ntq_get_src(c, instr->src[i].src,
810 instr->src[i].swizzle[0]);
811 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
812 ntq_store_dest(c, &instr->dest.dest, i,
813 vir_MOV(c, srcs[i]));
814 return;
815 }
816
817 /* General case: We can just grab the one used channel per src. */
818 struct qreg src[nir_op_infos[instr->op].num_inputs];
819 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
820 src[i] = ntq_get_alu_src(c, instr, i);
821 }
822
823 struct qreg result;
824
825 switch (instr->op) {
826 case nir_op_fmov:
827 case nir_op_imov:
828 result = vir_MOV(c, src[0]);
829 break;
830
831 case nir_op_fneg:
832 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
833 break;
834 case nir_op_ineg:
835 result = vir_NEG(c, src[0]);
836 break;
837
838 case nir_op_fmul:
839 result = vir_FMUL(c, src[0], src[1]);
840 break;
841 case nir_op_fadd:
842 result = vir_FADD(c, src[0], src[1]);
843 break;
844 case nir_op_fsub:
845 result = vir_FSUB(c, src[0], src[1]);
846 break;
847 case nir_op_fmin:
848 result = vir_FMIN(c, src[0], src[1]);
849 break;
850 case nir_op_fmax:
851 result = vir_FMAX(c, src[0], src[1]);
852 break;
853
854 case nir_op_f2i32:
855 result = vir_FTOIZ(c, src[0]);
856 break;
857 case nir_op_f2u32:
858 result = vir_FTOUZ(c, src[0]);
859 break;
860 case nir_op_i2f32:
861 result = vir_ITOF(c, src[0]);
862 break;
863 case nir_op_u2f32:
864 result = vir_UTOF(c, src[0]);
865 break;
866 case nir_op_b2f:
867 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
868 break;
869 case nir_op_b2i:
870 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
871 break;
872 case nir_op_i2b:
873 case nir_op_f2b:
874 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
875 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
876 vir_uniform_ui(c, ~0),
877 vir_uniform_ui(c, 0)));
878 break;
879
880 case nir_op_iadd:
881 result = vir_ADD(c, src[0], src[1]);
882 break;
883 case nir_op_ushr:
884 result = vir_SHR(c, src[0], src[1]);
885 break;
886 case nir_op_isub:
887 result = vir_SUB(c, src[0], src[1]);
888 break;
889 case nir_op_ishr:
890 result = vir_ASR(c, src[0], src[1]);
891 break;
892 case nir_op_ishl:
893 result = vir_SHL(c, src[0], src[1]);
894 break;
895 case nir_op_imin:
896 result = vir_MIN(c, src[0], src[1]);
897 break;
898 case nir_op_umin:
899 result = vir_UMIN(c, src[0], src[1]);
900 break;
901 case nir_op_imax:
902 result = vir_MAX(c, src[0], src[1]);
903 break;
904 case nir_op_umax:
905 result = vir_UMAX(c, src[0], src[1]);
906 break;
907 case nir_op_iand:
908 result = vir_AND(c, src[0], src[1]);
909 break;
910 case nir_op_ior:
911 result = vir_OR(c, src[0], src[1]);
912 break;
913 case nir_op_ixor:
914 result = vir_XOR(c, src[0], src[1]);
915 break;
916 case nir_op_inot:
917 result = vir_NOT(c, src[0]);
918 break;
919
920 case nir_op_imul:
921 result = ntq_umul(c, src[0], src[1]);
922 break;
923
924 case nir_op_seq:
925 case nir_op_sne:
926 case nir_op_sge:
927 case nir_op_slt:
928 case nir_op_feq:
929 case nir_op_fne:
930 case nir_op_fge:
931 case nir_op_flt:
932 case nir_op_ieq:
933 case nir_op_ine:
934 case nir_op_ige:
935 case nir_op_uge:
936 case nir_op_ilt:
937 case nir_op_ult:
938 if (!ntq_emit_comparison(c, &result, instr, instr)) {
939 fprintf(stderr, "Bad comparison instruction\n");
940 }
941 break;
942
943 case nir_op_bcsel:
944 result = ntq_emit_bcsel(c, instr, src);
945 break;
946 case nir_op_fcsel:
947 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
948 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
949 src[1], src[2]));
950 break;
951
952 case nir_op_frcp:
953 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
954 break;
955 case nir_op_frsq:
956 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
957 break;
958 case nir_op_fexp2:
959 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
960 break;
961 case nir_op_flog2:
962 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
963 break;
964
965 case nir_op_fceil:
966 result = vir_FCEIL(c, src[0]);
967 break;
968 case nir_op_ffloor:
969 result = vir_FFLOOR(c, src[0]);
970 break;
971 case nir_op_fround_even:
972 result = vir_FROUND(c, src[0]);
973 break;
974 case nir_op_ftrunc:
975 result = vir_FTRUNC(c, src[0]);
976 break;
977 case nir_op_ffract:
978 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
979 break;
980
981 case nir_op_fsin:
982 result = ntq_fsincos(c, src[0], false);
983 break;
984 case nir_op_fcos:
985 result = ntq_fsincos(c, src[0], true);
986 break;
987
988 case nir_op_fsign:
989 result = ntq_fsign(c, src[0]);
990 break;
991 case nir_op_isign:
992 result = ntq_isign(c, src[0]);
993 break;
994
995 case nir_op_fabs: {
996 result = vir_FMOV(c, src[0]);
997 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
998 break;
999 }
1000
1001 case nir_op_iabs:
1002 result = vir_MAX(c, src[0],
1003 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1004 break;
1005
1006 case nir_op_fddx:
1007 case nir_op_fddx_coarse:
1008 case nir_op_fddx_fine:
1009 result = vir_FDX(c, src[0]);
1010 break;
1011
1012 case nir_op_fddy:
1013 case nir_op_fddy_coarse:
1014 case nir_op_fddy_fine:
1015 result = vir_FDY(c, src[0]);
1016 break;
1017
1018 default:
1019 fprintf(stderr, "unknown NIR ALU inst: ");
1020 nir_print_instr(&instr->instr, stderr);
1021 fprintf(stderr, "\n");
1022 abort();
1023 }
1024
1025 /* We have a scalar result, so the instruction should only have a
1026 * single channel written to.
1027 */
1028 assert(util_is_power_of_two(instr->dest.write_mask));
1029 ntq_store_dest(c, &instr->dest.dest,
1030 ffs(instr->dest.write_mask) - 1, result);
1031 }
1032
1033 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1034 * specifier. They come from a register that's preloaded with 0xffffffff
1035 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1036 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1037 */
1038 #define TLB_TYPE_F16_COLOR (3 << 6)
1039 #define TLB_TYPE_I32_COLOR (1 << 6)
1040 #define TLB_TYPE_F32_COLOR (0 << 6)
1041 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1042 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1043 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1044 #define TLB_F16_SWAP_HI_LO (1 << 1)
1045 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1046 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1047 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1048
1049 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1050 * flag is set.
1051 */
1052 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1053 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1054 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1055
1056 /* Stencil is a single 32-bit write. */
1057 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1058
1059 static void
1060 emit_frag_end(struct v3d_compile *c)
1061 {
1062 /* XXX
1063 if (c->output_sample_mask_index != -1) {
1064 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1065 }
1066 */
1067
1068 if (c->output_position_index != -1) {
1069 struct qinst *inst = vir_MOV_dest(c,
1070 vir_reg(QFILE_TLBU, 0),
1071 c->outputs[c->output_position_index]);
1072
1073 inst->src[vir_get_implicit_uniform_src(inst)] =
1074 vir_uniform_ui(c,
1075 TLB_TYPE_DEPTH |
1076 TLB_DEPTH_TYPE_PER_PIXEL |
1077 0xffffff00);
1078 } else if (c->s->info.fs.uses_discard) {
1079 struct qinst *inst = vir_MOV_dest(c,
1080 vir_reg(QFILE_TLBU, 0),
1081 vir_reg(QFILE_NULL, 0));
1082
1083 inst->src[vir_get_implicit_uniform_src(inst)] =
1084 vir_uniform_ui(c,
1085 TLB_TYPE_DEPTH |
1086 TLB_DEPTH_TYPE_INVARIANT |
1087 0xffffff00);
1088 }
1089
1090 /* XXX: Performance improvement: Merge Z write and color writes TLB
1091 * uniform setup
1092 */
1093
1094 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1095 if (!c->output_color_var[rt])
1096 continue;
1097
1098 nir_variable *var = c->output_color_var[rt];
1099 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1100 int num_components = glsl_get_vector_elements(var->type);
1101 uint32_t conf = 0xffffff00;
1102 struct qinst *inst;
1103
1104 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1105 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1106
1107 assert(num_components != 0);
1108 switch (glsl_get_base_type(var->type)) {
1109 case GLSL_TYPE_UINT:
1110 case GLSL_TYPE_INT:
1111 conf |= TLB_TYPE_I32_COLOR;
1112 conf |= ((num_components - 1) <<
1113 TLB_VEC_SIZE_MINUS_1_SHIFT);
1114
1115 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1116 inst->src[vir_get_implicit_uniform_src(inst)] =
1117 vir_uniform_ui(c, conf);
1118
1119 for (int i = 1; i < num_components; i++) {
1120 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1121 color[i]);
1122 }
1123 break;
1124
1125 default: {
1126 struct qreg r = color[0];
1127 struct qreg g = color[1];
1128 struct qreg b = color[2];
1129 struct qreg a = color[3];
1130
1131 if (c->fs_key->f32_color_rb) {
1132 conf |= TLB_TYPE_F32_COLOR;
1133 conf |= ((num_components - 1) <<
1134 TLB_VEC_SIZE_MINUS_1_SHIFT);
1135 } else {
1136 conf |= TLB_TYPE_F16_COLOR;
1137 conf |= TLB_F16_SWAP_HI_LO;
1138 if (num_components >= 3)
1139 conf |= TLB_VEC_SIZE_4_F16;
1140 else
1141 conf |= TLB_VEC_SIZE_2_F16;
1142 }
1143
1144 if (c->fs_key->swap_color_rb & (1 << rt)) {
1145 r = color[2];
1146 b = color[0];
1147 }
1148
1149 if (c->fs_key->f32_color_rb & (1 << rt)) {
1150 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1151 inst->src[vir_get_implicit_uniform_src(inst)] =
1152 vir_uniform_ui(c, conf);
1153
1154 for (int i = 1; i < num_components; i++) {
1155 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1156 color[i]);
1157 }
1158 } else {
1159 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1160 if (conf != ~0) {
1161 inst->dst.file = QFILE_TLBU;
1162 inst->src[vir_get_implicit_uniform_src(inst)] =
1163 vir_uniform_ui(c, conf);
1164 }
1165
1166 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1167 }
1168 break;
1169 }
1170 }
1171 }
1172 }
1173
1174 static void
1175 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1176 {
1177 for (int i = 0; i < 2; i++) {
1178 struct qreg coord = c->outputs[c->output_position_index + i];
1179 coord = vir_FMUL(c, coord,
1180 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1181 0));
1182 coord = vir_FMUL(c, coord, rcp_w);
1183 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1184 coord);
1185 }
1186
1187 }
1188
1189 static void
1190 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1191 {
1192 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1193 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1194
1195 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1196 vir_FMUL(c, vir_FMUL(c,
1197 c->outputs[c->output_position_index + 2],
1198 zscale),
1199 rcp_w),
1200 zoffset);
1201 }
1202
1203 static void
1204 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1205 {
1206 vir_VPM_WRITE(c, rcp_w);
1207 }
1208
1209 static void
1210 emit_point_size_write(struct v3d_compile *c)
1211 {
1212 struct qreg point_size;
1213
1214 if (c->output_point_size_index != -1)
1215 point_size = c->outputs[c->output_point_size_index];
1216 else
1217 point_size = vir_uniform_f(c, 1.0);
1218
1219 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1220 * BCM21553).
1221 */
1222 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1223
1224 vir_VPM_WRITE(c, point_size);
1225 }
1226
1227 static void
1228 emit_vpm_write_setup(struct v3d_compile *c)
1229 {
1230 uint32_t packed;
1231 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1232 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1233
1234 .horiz = true,
1235 .laned = false,
1236 .segs = true,
1237 .stride = 1,
1238 .size = VPM_SETUP_SIZE_32_BIT,
1239 .addr = 0,
1240 };
1241
1242 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1243 (uint8_t *)&packed,
1244 &unpacked);
1245 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1246 }
1247
1248 static void
1249 emit_vert_end(struct v3d_compile *c)
1250 {
1251 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1252 c->outputs[c->output_position_index + 3]);
1253
1254 emit_vpm_write_setup(c);
1255
1256 if (c->vs_key->is_coord) {
1257 for (int i = 0; i < 4; i++)
1258 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1259 emit_scaled_viewport_write(c, rcp_w);
1260 if (c->vs_key->per_vertex_point_size) {
1261 emit_point_size_write(c);
1262 /* emit_rcp_wc_write(c, rcp_w); */
1263 }
1264 /* XXX: Z-only rendering */
1265 if (0)
1266 emit_zs_write(c, rcp_w);
1267 } else {
1268 emit_scaled_viewport_write(c, rcp_w);
1269 emit_zs_write(c, rcp_w);
1270 emit_rcp_wc_write(c, rcp_w);
1271 if (c->vs_key->per_vertex_point_size)
1272 emit_point_size_write(c);
1273 }
1274
1275 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1276 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1277 int j;
1278
1279 for (j = 0; j < c->num_outputs; j++) {
1280 struct v3d_varying_slot output = c->output_slots[j];
1281
1282 if (!memcmp(&input, &output, sizeof(input))) {
1283 vir_VPM_WRITE(c, c->outputs[j]);
1284 break;
1285 }
1286 }
1287 /* Emit padding if we didn't find a declared VS output for
1288 * this FS input.
1289 */
1290 if (j == c->num_outputs)
1291 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1292 }
1293 }
1294
1295 void
1296 v3d_optimize_nir(struct nir_shader *s)
1297 {
1298 bool progress;
1299
1300 do {
1301 progress = false;
1302
1303 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1304 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1305 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1306 NIR_PASS(progress, s, nir_copy_prop);
1307 NIR_PASS(progress, s, nir_opt_remove_phis);
1308 NIR_PASS(progress, s, nir_opt_dce);
1309 NIR_PASS(progress, s, nir_opt_dead_cf);
1310 NIR_PASS(progress, s, nir_opt_cse);
1311 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1312 NIR_PASS(progress, s, nir_opt_algebraic);
1313 NIR_PASS(progress, s, nir_opt_constant_folding);
1314 NIR_PASS(progress, s, nir_opt_undef);
1315 } while (progress);
1316 }
1317
1318 static int
1319 driver_location_compare(const void *in_a, const void *in_b)
1320 {
1321 const nir_variable *const *a = in_a;
1322 const nir_variable *const *b = in_b;
1323
1324 return (*a)->data.driver_location - (*b)->data.driver_location;
1325 }
1326
1327 static struct qreg
1328 ntq_emit_vpm_read(struct v3d_compile *c,
1329 uint32_t *num_components_queued,
1330 uint32_t *remaining,
1331 uint32_t vpm_index)
1332 {
1333 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1334
1335 if (*num_components_queued != 0) {
1336 (*num_components_queued)--;
1337 c->num_inputs++;
1338 return vir_MOV(c, vpm);
1339 }
1340
1341 uint32_t num_components = MIN2(*remaining, 32);
1342
1343 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1344 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1345
1346 .horiz = true,
1347 .laned = false,
1348 /* If the field is 0, that means a read count of 32. */
1349 .num = num_components & 31,
1350 .segs = true,
1351 .stride = 1,
1352 .size = VPM_SETUP_SIZE_32_BIT,
1353 .addr = c->num_inputs,
1354 };
1355
1356 uint32_t packed;
1357 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1358 (uint8_t *)&packed,
1359 &unpacked);
1360 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1361
1362 *num_components_queued = num_components - 1;
1363 *remaining -= num_components;
1364 c->num_inputs++;
1365
1366 return vir_MOV(c, vpm);
1367 }
1368
1369 static void
1370 ntq_setup_inputs(struct v3d_compile *c)
1371 {
1372 unsigned num_entries = 0;
1373 unsigned num_components = 0;
1374 nir_foreach_variable(var, &c->s->inputs) {
1375 num_entries++;
1376 num_components += glsl_get_components(var->type);
1377 }
1378
1379 nir_variable *vars[num_entries];
1380
1381 unsigned i = 0;
1382 nir_foreach_variable(var, &c->s->inputs)
1383 vars[i++] = var;
1384
1385 /* Sort the variables so that we emit the input setup in
1386 * driver_location order. This is required for VPM reads, whose data
1387 * is fetched into the VPM in driver_location (TGSI register index)
1388 * order.
1389 */
1390 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1391
1392 uint32_t vpm_components_queued = 0;
1393 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1394 bool uses_iid = c->s->info.system_values_read &
1395 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1396 bool uses_vid = c->s->info.system_values_read &
1397 (1ull << SYSTEM_VALUE_VERTEX_ID);
1398
1399 num_components += uses_iid;
1400 num_components += uses_vid;
1401
1402 if (uses_iid) {
1403 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1404 &num_components, ~0);
1405 }
1406
1407 if (uses_vid) {
1408 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1409 &num_components, ~0);
1410 }
1411 }
1412
1413 for (unsigned i = 0; i < num_entries; i++) {
1414 nir_variable *var = vars[i];
1415 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1416 unsigned loc = var->data.driver_location;
1417
1418 assert(array_len == 1);
1419 (void)array_len;
1420 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1421 (loc + 1) * 4);
1422
1423 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1424 if (var->data.location == VARYING_SLOT_POS) {
1425 emit_fragcoord_input(c, loc);
1426 } else if (var->data.location == VARYING_SLOT_PNTC ||
1427 (var->data.location >= VARYING_SLOT_VAR0 &&
1428 (c->fs_key->point_sprite_mask &
1429 (1 << (var->data.location -
1430 VARYING_SLOT_VAR0))))) {
1431 c->inputs[loc * 4 + 0] = c->point_x;
1432 c->inputs[loc * 4 + 1] = c->point_y;
1433 } else {
1434 emit_fragment_input(c, loc, var);
1435 }
1436 } else {
1437 int var_components = glsl_get_components(var->type);
1438
1439 for (int i = 0; i < var_components; i++) {
1440 c->inputs[loc * 4 + i] =
1441 ntq_emit_vpm_read(c,
1442 &vpm_components_queued,
1443 &num_components,
1444 loc * 4 + i);
1445
1446 }
1447 c->vattr_sizes[loc] = var_components;
1448 }
1449 }
1450
1451 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1452 assert(vpm_components_queued == 0);
1453 assert(num_components == 0);
1454 }
1455 }
1456
1457 static void
1458 ntq_setup_outputs(struct v3d_compile *c)
1459 {
1460 nir_foreach_variable(var, &c->s->outputs) {
1461 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1462 unsigned loc = var->data.driver_location * 4;
1463
1464 assert(array_len == 1);
1465 (void)array_len;
1466
1467 for (int i = 0; i < 4; i++)
1468 add_output(c, loc + i, var->data.location, i);
1469
1470 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1471 switch (var->data.location) {
1472 case FRAG_RESULT_COLOR:
1473 c->output_color_var[0] = var;
1474 c->output_color_var[1] = var;
1475 c->output_color_var[2] = var;
1476 c->output_color_var[3] = var;
1477 break;
1478 case FRAG_RESULT_DATA0:
1479 case FRAG_RESULT_DATA1:
1480 case FRAG_RESULT_DATA2:
1481 case FRAG_RESULT_DATA3:
1482 c->output_color_var[var->data.location -
1483 FRAG_RESULT_DATA0] = var;
1484 break;
1485 case FRAG_RESULT_DEPTH:
1486 c->output_position_index = loc;
1487 break;
1488 case FRAG_RESULT_SAMPLE_MASK:
1489 c->output_sample_mask_index = loc;
1490 break;
1491 }
1492 } else {
1493 switch (var->data.location) {
1494 case VARYING_SLOT_POS:
1495 c->output_position_index = loc;
1496 break;
1497 case VARYING_SLOT_PSIZ:
1498 c->output_point_size_index = loc;
1499 break;
1500 }
1501 }
1502 }
1503 }
1504
1505 static void
1506 ntq_setup_uniforms(struct v3d_compile *c)
1507 {
1508 nir_foreach_variable(var, &c->s->uniforms) {
1509 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1510 false);
1511 unsigned vec4_size = 4 * sizeof(float);
1512
1513 declare_uniform_range(c, var->data.driver_location * vec4_size,
1514 vec4_count * vec4_size);
1515
1516 }
1517 }
1518
1519 /**
1520 * Sets up the mapping from nir_register to struct qreg *.
1521 *
1522 * Each nir_register gets a struct qreg per 32-bit component being stored.
1523 */
1524 static void
1525 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1526 {
1527 foreach_list_typed(nir_register, nir_reg, node, list) {
1528 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1529 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1530 array_len *
1531 nir_reg->num_components);
1532
1533 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1534
1535 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1536 qregs[i] = vir_get_temp(c);
1537 }
1538 }
1539
1540 static void
1541 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1542 {
1543 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1544 for (int i = 0; i < instr->def.num_components; i++)
1545 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1546
1547 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1548 }
1549
1550 static void
1551 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1552 {
1553 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1554
1555 /* VIR needs there to be *some* value, so pick 0 (same as for
1556 * ntq_setup_registers().
1557 */
1558 for (int i = 0; i < instr->def.num_components; i++)
1559 qregs[i] = vir_uniform_ui(c, 0);
1560 }
1561
1562 static void
1563 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1564 {
1565 nir_const_value *const_offset;
1566 unsigned offset;
1567
1568 switch (instr->intrinsic) {
1569 case nir_intrinsic_load_uniform:
1570 assert(instr->num_components == 1);
1571 const_offset = nir_src_as_const_value(instr->src[0]);
1572 if (const_offset) {
1573 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1574 assert(offset % 4 == 0);
1575 /* We need dwords */
1576 offset = offset / 4;
1577 ntq_store_dest(c, &instr->dest, 0,
1578 vir_uniform(c, QUNIFORM_UNIFORM,
1579 offset));
1580 } else {
1581 ntq_store_dest(c, &instr->dest, 0,
1582 indirect_uniform_load(c, instr));
1583 }
1584 break;
1585
1586 case nir_intrinsic_load_ubo:
1587 for (int i = 0; i < instr->num_components; i++) {
1588 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1589
1590 /* Adjust for where we stored the TGSI register base. */
1591 vir_ADD_dest(c,
1592 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1593 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1594 vir_ADD(c,
1595 ntq_get_src(c, instr->src[1], 0),
1596 vir_uniform_ui(c, i * 4)));
1597
1598 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1599 }
1600 break;
1601
1602 const_offset = nir_src_as_const_value(instr->src[0]);
1603 if (const_offset) {
1604 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1605 assert(offset % 4 == 0);
1606 /* We need dwords */
1607 offset = offset / 4;
1608 ntq_store_dest(c, &instr->dest, 0,
1609 vir_uniform(c, QUNIFORM_UNIFORM,
1610 offset));
1611 } else {
1612 ntq_store_dest(c, &instr->dest, 0,
1613 indirect_uniform_load(c, instr));
1614 }
1615 break;
1616
1617 case nir_intrinsic_load_user_clip_plane:
1618 for (int i = 0; i < instr->num_components; i++) {
1619 ntq_store_dest(c, &instr->dest, i,
1620 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1621 nir_intrinsic_ucp_id(instr) *
1622 4 + i));
1623 }
1624 break;
1625
1626 case nir_intrinsic_load_alpha_ref_float:
1627 ntq_store_dest(c, &instr->dest, 0,
1628 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1629 break;
1630
1631 case nir_intrinsic_load_sample_mask_in:
1632 ntq_store_dest(c, &instr->dest, 0,
1633 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1634 break;
1635
1636 case nir_intrinsic_load_front_face:
1637 /* The register contains 0 (front) or 1 (back), and we need to
1638 * turn it into a NIR bool where true means front.
1639 */
1640 ntq_store_dest(c, &instr->dest, 0,
1641 vir_ADD(c,
1642 vir_uniform_ui(c, -1),
1643 vir_REVF(c)));
1644 break;
1645
1646 case nir_intrinsic_load_instance_id:
1647 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1648 break;
1649
1650 case nir_intrinsic_load_vertex_id:
1651 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1652 break;
1653
1654 case nir_intrinsic_load_input:
1655 const_offset = nir_src_as_const_value(instr->src[0]);
1656 assert(const_offset && "v3d doesn't support indirect inputs");
1657 for (int i = 0; i < instr->num_components; i++) {
1658 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1659 int comp = nir_intrinsic_component(instr) + i;
1660 ntq_store_dest(c, &instr->dest, i,
1661 vir_MOV(c, c->inputs[offset * 4 + comp]));
1662 }
1663 break;
1664
1665 case nir_intrinsic_store_output:
1666 const_offset = nir_src_as_const_value(instr->src[1]);
1667 assert(const_offset && "v3d doesn't support indirect outputs");
1668 offset = ((nir_intrinsic_base(instr) +
1669 const_offset->u32[0]) * 4 +
1670 nir_intrinsic_component(instr));
1671
1672 for (int i = 0; i < instr->num_components; i++) {
1673 c->outputs[offset + i] =
1674 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1675 }
1676 c->num_outputs = MAX2(c->num_outputs,
1677 offset + instr->num_components);
1678 break;
1679
1680 case nir_intrinsic_discard:
1681 if (c->execute.file != QFILE_NULL) {
1682 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1683 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1684 vir_uniform_ui(c, 0)),
1685 V3D_QPU_COND_IFA);
1686 } else {
1687 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1688 vir_uniform_ui(c, 0));
1689 }
1690 break;
1691
1692 case nir_intrinsic_discard_if: {
1693 /* true (~0) if we're discarding */
1694 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1695
1696 if (c->execute.file != QFILE_NULL) {
1697 /* execute == 0 means the channel is active. Invert
1698 * the condition so that we can use zero as "executing
1699 * and discarding."
1700 */
1701 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1702 V3D_QPU_PF_PUSHZ);
1703 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1704 vir_uniform_ui(c, 0)),
1705 V3D_QPU_COND_IFA);
1706 } else {
1707 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1708 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1709 vir_uniform_ui(c, 0)),
1710 V3D_QPU_COND_IFNA);
1711 }
1712
1713 break;
1714 }
1715
1716 default:
1717 fprintf(stderr, "Unknown intrinsic: ");
1718 nir_print_instr(&instr->instr, stderr);
1719 fprintf(stderr, "\n");
1720 break;
1721 }
1722 }
1723
1724 /* Clears (activates) the execute flags for any channels whose jump target
1725 * matches this block.
1726 */
1727 static void
1728 ntq_activate_execute_for_block(struct v3d_compile *c)
1729 {
1730 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1731 V3D_QPU_PF_PUSHZ);
1732
1733 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1734 }
1735
1736 static void
1737 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1738 {
1739 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1740 bool empty_else_block =
1741 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1742 exec_list_is_empty(&nir_else_block->instr_list));
1743
1744 struct qblock *then_block = vir_new_block(c);
1745 struct qblock *after_block = vir_new_block(c);
1746 struct qblock *else_block;
1747 if (empty_else_block)
1748 else_block = after_block;
1749 else
1750 else_block = vir_new_block(c);
1751
1752 bool was_top_level = false;
1753 if (c->execute.file == QFILE_NULL) {
1754 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1755 was_top_level = true;
1756 }
1757
1758 /* Set A for executing (execute == 0) and jumping (if->condition ==
1759 * 0) channels, and then update execute flags for those to point to
1760 * the ELSE block.
1761 */
1762 vir_PF(c, vir_OR(c,
1763 c->execute,
1764 ntq_get_src(c, if_stmt->condition, 0)),
1765 V3D_QPU_PF_PUSHZ);
1766 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1767 c->execute,
1768 vir_uniform_ui(c, else_block->index));
1769
1770 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1771 * through.
1772 */
1773 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1774 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1775 vir_link_blocks(c->cur_block, else_block);
1776 vir_link_blocks(c->cur_block, then_block);
1777
1778 /* Process the THEN block. */
1779 vir_set_emit_block(c, then_block);
1780 ntq_emit_cf_list(c, &if_stmt->then_list);
1781
1782 if (!empty_else_block) {
1783 /* Handle the end of the THEN block. First, all currently
1784 * active channels update their execute flags to point to
1785 * ENDIF
1786 */
1787 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1788 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1789 vir_uniform_ui(c, after_block->index));
1790
1791 /* If everything points at ENDIF, then jump there immediately. */
1792 vir_PF(c, vir_SUB(c, c->execute,
1793 vir_uniform_ui(c, after_block->index)),
1794 V3D_QPU_PF_PUSHZ);
1795 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1796 vir_link_blocks(c->cur_block, after_block);
1797 vir_link_blocks(c->cur_block, else_block);
1798
1799 vir_set_emit_block(c, else_block);
1800 ntq_activate_execute_for_block(c);
1801 ntq_emit_cf_list(c, &if_stmt->else_list);
1802 }
1803
1804 vir_link_blocks(c->cur_block, after_block);
1805
1806 vir_set_emit_block(c, after_block);
1807 if (was_top_level)
1808 c->execute = c->undef;
1809 else
1810 ntq_activate_execute_for_block(c);
1811 }
1812
1813 static void
1814 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1815 {
1816 switch (jump->type) {
1817 case nir_jump_break:
1818 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1819 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1820 vir_uniform_ui(c, c->loop_break_block->index));
1821 break;
1822
1823 case nir_jump_continue:
1824 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1825 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1826 vir_uniform_ui(c, c->loop_cont_block->index));
1827 break;
1828
1829 case nir_jump_return:
1830 unreachable("All returns shouold be lowered\n");
1831 }
1832 }
1833
1834 static void
1835 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1836 {
1837 switch (instr->type) {
1838 case nir_instr_type_alu:
1839 ntq_emit_alu(c, nir_instr_as_alu(instr));
1840 break;
1841
1842 case nir_instr_type_intrinsic:
1843 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1844 break;
1845
1846 case nir_instr_type_load_const:
1847 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1848 break;
1849
1850 case nir_instr_type_ssa_undef:
1851 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1852 break;
1853
1854 case nir_instr_type_tex:
1855 ntq_emit_tex(c, nir_instr_as_tex(instr));
1856 break;
1857
1858 case nir_instr_type_jump:
1859 ntq_emit_jump(c, nir_instr_as_jump(instr));
1860 break;
1861
1862 default:
1863 fprintf(stderr, "Unknown NIR instr type: ");
1864 nir_print_instr(instr, stderr);
1865 fprintf(stderr, "\n");
1866 abort();
1867 }
1868 }
1869
1870 static void
1871 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1872 {
1873 nir_foreach_instr(instr, block) {
1874 ntq_emit_instr(c, instr);
1875 }
1876 }
1877
1878 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1879
1880 static void
1881 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1882 {
1883 bool was_top_level = false;
1884 if (c->execute.file == QFILE_NULL) {
1885 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1886 was_top_level = true;
1887 }
1888
1889 struct qblock *save_loop_cont_block = c->loop_cont_block;
1890 struct qblock *save_loop_break_block = c->loop_break_block;
1891
1892 c->loop_cont_block = vir_new_block(c);
1893 c->loop_break_block = vir_new_block(c);
1894
1895 vir_link_blocks(c->cur_block, c->loop_cont_block);
1896 vir_set_emit_block(c, c->loop_cont_block);
1897 ntq_activate_execute_for_block(c);
1898
1899 ntq_emit_cf_list(c, &loop->body);
1900
1901 /* Re-enable any previous continues now, so our ANYA check below
1902 * works.
1903 *
1904 * XXX: Use the .ORZ flags update, instead.
1905 */
1906 vir_PF(c, vir_SUB(c,
1907 c->execute,
1908 vir_uniform_ui(c, c->loop_cont_block->index)),
1909 V3D_QPU_PF_PUSHZ);
1910 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1911
1912 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1913
1914 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1915 vir_link_blocks(c->cur_block, c->loop_cont_block);
1916 vir_link_blocks(c->cur_block, c->loop_break_block);
1917
1918 vir_set_emit_block(c, c->loop_break_block);
1919 if (was_top_level)
1920 c->execute = c->undef;
1921 else
1922 ntq_activate_execute_for_block(c);
1923
1924 c->loop_break_block = save_loop_break_block;
1925 c->loop_cont_block = save_loop_cont_block;
1926 }
1927
1928 static void
1929 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1930 {
1931 fprintf(stderr, "FUNCTIONS not handled.\n");
1932 abort();
1933 }
1934
1935 static void
1936 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1937 {
1938 foreach_list_typed(nir_cf_node, node, node, list) {
1939 switch (node->type) {
1940 case nir_cf_node_block:
1941 ntq_emit_block(c, nir_cf_node_as_block(node));
1942 break;
1943
1944 case nir_cf_node_if:
1945 ntq_emit_if(c, nir_cf_node_as_if(node));
1946 break;
1947
1948 case nir_cf_node_loop:
1949 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1950 break;
1951
1952 case nir_cf_node_function:
1953 ntq_emit_function(c, nir_cf_node_as_function(node));
1954 break;
1955
1956 default:
1957 fprintf(stderr, "Unknown NIR node type\n");
1958 abort();
1959 }
1960 }
1961 }
1962
1963 static void
1964 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1965 {
1966 ntq_setup_registers(c, &impl->registers);
1967 ntq_emit_cf_list(c, &impl->body);
1968 }
1969
1970 static void
1971 nir_to_vir(struct v3d_compile *c)
1972 {
1973 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1974 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1975 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1976 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1977
1978 if (c->fs_key->is_points) {
1979 c->point_x = emit_fragment_varying(c, NULL, 0);
1980 c->point_y = emit_fragment_varying(c, NULL, 0);
1981 } else if (c->fs_key->is_lines) {
1982 c->line_x = emit_fragment_varying(c, NULL, 0);
1983 }
1984 }
1985
1986 ntq_setup_inputs(c);
1987 ntq_setup_outputs(c);
1988 ntq_setup_uniforms(c);
1989 ntq_setup_registers(c, &c->s->registers);
1990
1991 /* Find the main function and emit the body. */
1992 nir_foreach_function(function, c->s) {
1993 assert(strcmp(function->name, "main") == 0);
1994 assert(function->impl);
1995 ntq_emit_impl(c, function->impl);
1996 }
1997 }
1998
1999 const nir_shader_compiler_options v3d_nir_options = {
2000 .lower_extract_byte = true,
2001 .lower_extract_word = true,
2002 .lower_bitfield_insert = true,
2003 .lower_bitfield_extract = true,
2004 .lower_pack_unorm_2x16 = true,
2005 .lower_pack_snorm_2x16 = true,
2006 .lower_pack_unorm_4x8 = true,
2007 .lower_pack_snorm_4x8 = true,
2008 .lower_unpack_unorm_4x8 = true,
2009 .lower_unpack_snorm_4x8 = true,
2010 .lower_fdiv = true,
2011 .lower_ffma = true,
2012 .lower_flrp32 = true,
2013 .lower_fpow = true,
2014 .lower_fsat = true,
2015 .lower_fsqrt = true,
2016 .native_integers = true,
2017 };
2018
2019
2020 #if 0
2021 static int
2022 count_nir_instrs(nir_shader *nir)
2023 {
2024 int count = 0;
2025 nir_foreach_function(function, nir) {
2026 if (!function->impl)
2027 continue;
2028 nir_foreach_block(block, function->impl) {
2029 nir_foreach_instr(instr, block)
2030 count++;
2031 }
2032 }
2033 return count;
2034 }
2035 #endif
2036
2037 void
2038 v3d_nir_to_vir(struct v3d_compile *c)
2039 {
2040 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2041 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2042 fprintf(stderr, "%s prog %d/%d NIR:\n",
2043 vir_get_stage_name(c),
2044 c->program_id, c->variant_id);
2045 nir_print_shader(c->s, stderr);
2046 }
2047
2048 nir_to_vir(c);
2049
2050 switch (c->s->info.stage) {
2051 case MESA_SHADER_FRAGMENT:
2052 emit_frag_end(c);
2053 break;
2054 case MESA_SHADER_VERTEX:
2055 emit_vert_end(c);
2056 break;
2057 default:
2058 unreachable("bad stage");
2059 }
2060
2061 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2062 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2063 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2064 vir_get_stage_name(c),
2065 c->program_id, c->variant_id);
2066 vir_dump(c);
2067 fprintf(stderr, "\n");
2068 }
2069
2070 vir_optimize(c);
2071 vir_lower_uniforms(c);
2072
2073 /* XXX: vir_schedule_instructions(c); */
2074
2075 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2076 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2077 fprintf(stderr, "%s prog %d/%d VIR:\n",
2078 vir_get_stage_name(c),
2079 c->program_id, c->variant_id);
2080 vir_dump(c);
2081 fprintf(stderr, "\n");
2082 }
2083
2084 v3d_vir_to_qpu(c);
2085 }