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broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 coords[next_coord++] =
384 vir_FADD(c,
385 ntq_get_src(c, instr->src[i].src, 0),
386 vir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL,
387 unit));
388
389 if (instr->op != nir_texop_txf &&
390 instr->op != nir_texop_tg4) {
391 p0_unpacked.disable_autolod_use_bias_only = true;
392 }
393 break;
394 case nir_tex_src_comparator:
395 coords[next_coord++] =
396 ntq_get_src(c, instr->src[i].src, 0);
397
398 p0_unpacked.shadow = true;
399 break;
400
401 case nir_tex_src_offset: {
402 nir_const_value *offset =
403 nir_src_as_const_value(instr->src[i].src);
404 p0_unpacked.texel_offset_for_s_coordinate =
405 offset->i32[0];
406
407 if (instr->coord_components >= 2)
408 p0_unpacked.texel_offset_for_t_coordinate =
409 offset->i32[1];
410
411 if (instr->coord_components >= 3)
412 p0_unpacked.texel_offset_for_r_coordinate =
413 offset->i32[2];
414 break;
415 }
416
417 default:
418 unreachable("unknown texture source");
419 }
420 }
421
422 uint32_t p0_packed;
423 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
424 (uint8_t *)&p0_packed,
425 &p0_unpacked);
426
427 /* There is no native support for GL texture rectangle coordinates, so
428 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
429 * 1]).
430 */
431 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
432 coords[0] = vir_FMUL(c, coords[0],
433 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
434 unit));
435 coords[1] = vir_FMUL(c, coords[1],
436 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
437 unit));
438 }
439
440 struct qreg texture_u[] = {
441 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
442 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
443 };
444 uint32_t next_texture_u = 0;
445
446 for (int i = 0; i < next_coord; i++) {
447 struct qreg dst;
448
449 if (i == next_coord - 1)
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
451 else
452 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
453
454 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
455
456 if (i < 2) {
457 tmu->has_implicit_uniform = true;
458 tmu->src[vir_get_implicit_uniform_src(tmu)] =
459 texture_u[next_texture_u++];
460 }
461 }
462
463 bool return_16 = (c->key->tex[unit].return_size == 16 ||
464 p0_unpacked.shadow);
465
466 struct qreg return_values[4];
467 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
468 return_values[i] = vir_LDTMU(c);
469 /* Swizzling .zw of an RG texture should give undefined results, not
470 * crash the compiler.
471 */
472 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
473 return_values[i] = c->undef;
474
475 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
476 struct qreg chan;
477
478 if (return_16) {
479 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
480 chan = return_values[i / 2];
481
482 if (nir_alu_type_get_base_type(instr->dest_type) ==
483 nir_type_float) {
484 enum v3d_qpu_input_unpack unpack;
485 if (i & 1)
486 unpack = V3D_QPU_UNPACK_H;
487 else
488 unpack = V3D_QPU_UNPACK_L;
489
490 chan = vir_FMOV(c, chan);
491 vir_set_unpack(c->defs[chan.index], 0, unpack);
492 } else {
493 /* If we're unpacking the low field, shift it
494 * up to the top first.
495 */
496 if ((i & 1) == 0) {
497 chan = vir_SHL(c, chan,
498 vir_uniform_ui(c, 16));
499 }
500
501 /* Do proper sign extension to a 32-bit int. */
502 if (nir_alu_type_get_base_type(instr->dest_type) ==
503 nir_type_int) {
504 chan = vir_ASR(c, chan,
505 vir_uniform_ui(c, 16));
506 } else {
507 chan = vir_SHR(c, chan,
508 vir_uniform_ui(c, 16));
509 }
510 }
511 } else {
512 chan = vir_MOV(c, return_values[i]);
513 }
514 ntq_store_dest(c, &instr->dest, i, chan);
515 }
516 }
517
518 static struct qreg
519 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
520 {
521 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
522 if (is_cos)
523 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
524
525 struct qreg periods = vir_FROUND(c, input);
526 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
527 vir_FSUB(c, input, periods));
528 return vir_XOR(c, sin_output, vir_SHL(c,
529 vir_FTOIN(c, periods),
530 vir_uniform_ui(c, -1)));
531 }
532
533 static struct qreg
534 ntq_fsign(struct v3d_compile *c, struct qreg src)
535 {
536 struct qreg t = vir_get_temp(c);
537
538 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
539 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
540 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
541 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
542 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
543 return vir_MOV(c, t);
544 }
545
546 static struct qreg
547 ntq_isign(struct v3d_compile *c, struct qreg src)
548 {
549 struct qreg t = vir_get_temp(c);
550
551 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
552 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
553 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
554 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
555 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
556 return vir_MOV(c, t);
557 }
558
559 static void
560 emit_fragcoord_input(struct v3d_compile *c, int attr)
561 {
562 c->inputs[attr * 4 + 0] = vir_FXCD(c);
563 c->inputs[attr * 4 + 1] = vir_FYCD(c);
564 c->inputs[attr * 4 + 2] = c->payload_z;
565 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
566 c->payload_w);
567 }
568
569 static struct qreg
570 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
571 uint8_t swizzle)
572 {
573 struct qreg vary = vir_reg(QFILE_VARY, ~0);
574 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
575
576 /* For gl_PointCoord input or distance along a line, we'll be called
577 * with no nir_variable, and we don't count toward VPM size so we
578 * don't track an input slot.
579 */
580 if (!var) {
581 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
582 }
583
584 int i = c->num_inputs++;
585 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
586 swizzle);
587
588 switch (var->data.interpolation) {
589 case INTERP_MODE_NONE:
590 /* If a gl_FrontColor or gl_BackColor input has no interp
591 * qualifier, then flag it for glShadeModel() handling by the
592 * driver.
593 */
594 switch (var->data.location) {
595 case VARYING_SLOT_COL0:
596 case VARYING_SLOT_COL1:
597 case VARYING_SLOT_BFC0:
598 case VARYING_SLOT_BFC1:
599 BITSET_SET(c->shade_model_flags, i);
600 break;
601 default:
602 break;
603 }
604 /* FALLTHROUGH */
605 case INTERP_MODE_SMOOTH:
606 if (var->data.centroid) {
607 return vir_FADD(c, vir_FMUL(c, vary,
608 c->payload_w_centroid), r5);
609 } else {
610 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
611 }
612 case INTERP_MODE_NOPERSPECTIVE:
613 /* C appears after the mov from the varying.
614 XXX: improve ldvary setup.
615 */
616 return vir_FADD(c, vir_MOV(c, vary), r5);
617 case INTERP_MODE_FLAT:
618 BITSET_SET(c->flat_shade_flags, i);
619 vir_MOV_dest(c, c->undef, vary);
620 return vir_MOV(c, r5);
621 default:
622 unreachable("Bad interp mode");
623 }
624 }
625
626 static void
627 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
628 {
629 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
630 int chan = var->data.location_frac + i;
631 c->inputs[attr * 4 + chan] =
632 emit_fragment_varying(c, var, chan);
633 }
634 }
635
636 static void
637 add_output(struct v3d_compile *c,
638 uint32_t decl_offset,
639 uint8_t slot,
640 uint8_t swizzle)
641 {
642 uint32_t old_array_size = c->outputs_array_size;
643 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
644 decl_offset + 1);
645
646 if (old_array_size != c->outputs_array_size) {
647 c->output_slots = reralloc(c,
648 c->output_slots,
649 struct v3d_varying_slot,
650 c->outputs_array_size);
651 }
652
653 c->output_slots[decl_offset] =
654 v3d_slot_from_slot_and_component(slot, swizzle);
655 }
656
657 static void
658 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
659 {
660 unsigned array_id = c->num_ubo_ranges++;
661 if (array_id >= c->ubo_ranges_array_size) {
662 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
663 array_id + 1);
664 c->ubo_ranges = reralloc(c, c->ubo_ranges,
665 struct v3d_ubo_range,
666 c->ubo_ranges_array_size);
667 c->ubo_range_used = reralloc(c, c->ubo_range_used,
668 bool,
669 c->ubo_ranges_array_size);
670 }
671
672 c->ubo_ranges[array_id].dst_offset = 0;
673 c->ubo_ranges[array_id].src_offset = start;
674 c->ubo_ranges[array_id].size = size;
675 c->ubo_range_used[array_id] = false;
676 }
677
678 /**
679 * If compare_instr is a valid comparison instruction, emits the
680 * compare_instr's comparison and returns the sel_instr's return value based
681 * on the compare_instr's result.
682 */
683 static bool
684 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
685 nir_alu_instr *compare_instr,
686 nir_alu_instr *sel_instr)
687 {
688 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
689 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
690 bool cond_invert = false;
691
692 switch (compare_instr->op) {
693 case nir_op_feq:
694 case nir_op_seq:
695 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
696 break;
697 case nir_op_ieq:
698 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
699 break;
700
701 case nir_op_fne:
702 case nir_op_sne:
703 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
704 cond_invert = true;
705 break;
706 case nir_op_ine:
707 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
708 cond_invert = true;
709 break;
710
711 case nir_op_fge:
712 case nir_op_sge:
713 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
714 break;
715 case nir_op_ige:
716 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
717 cond_invert = true;
718 break;
719 case nir_op_uge:
720 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
721 cond_invert = true;
722 break;
723
724 case nir_op_slt:
725 case nir_op_flt:
726 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
727 break;
728 case nir_op_ilt:
729 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
730 break;
731 case nir_op_ult:
732 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
733 break;
734
735 default:
736 return false;
737 }
738
739 enum v3d_qpu_cond cond = (cond_invert ?
740 V3D_QPU_COND_IFNA :
741 V3D_QPU_COND_IFA);
742
743 switch (sel_instr->op) {
744 case nir_op_seq:
745 case nir_op_sne:
746 case nir_op_sge:
747 case nir_op_slt:
748 *dest = vir_SEL(c, cond,
749 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
750 break;
751
752 case nir_op_bcsel:
753 *dest = vir_SEL(c, cond,
754 ntq_get_alu_src(c, sel_instr, 1),
755 ntq_get_alu_src(c, sel_instr, 2));
756 break;
757
758 default:
759 *dest = vir_SEL(c, cond,
760 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
761 break;
762 }
763
764 /* Make the temporary for nir_store_dest(). */
765 *dest = vir_MOV(c, *dest);
766
767 return true;
768 }
769
770 /**
771 * Attempts to fold a comparison generating a boolean result into the
772 * condition code for selecting between two values, instead of comparing the
773 * boolean result against 0 to generate the condition code.
774 */
775 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
776 struct qreg *src)
777 {
778 if (!instr->src[0].src.is_ssa)
779 goto out;
780 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
781 goto out;
782 nir_alu_instr *compare =
783 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
784 if (!compare)
785 goto out;
786
787 struct qreg dest;
788 if (ntq_emit_comparison(c, &dest, compare, instr))
789 return dest;
790
791 out:
792 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
793 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
794 }
795
796
797 static void
798 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
799 {
800 /* This should always be lowered to ALU operations for V3D. */
801 assert(!instr->dest.saturate);
802
803 /* Vectors are special in that they have non-scalarized writemasks,
804 * and just take the first swizzle channel for each argument in order
805 * into each writemask channel.
806 */
807 if (instr->op == nir_op_vec2 ||
808 instr->op == nir_op_vec3 ||
809 instr->op == nir_op_vec4) {
810 struct qreg srcs[4];
811 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
812 srcs[i] = ntq_get_src(c, instr->src[i].src,
813 instr->src[i].swizzle[0]);
814 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
815 ntq_store_dest(c, &instr->dest.dest, i,
816 vir_MOV(c, srcs[i]));
817 return;
818 }
819
820 /* General case: We can just grab the one used channel per src. */
821 struct qreg src[nir_op_infos[instr->op].num_inputs];
822 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
823 src[i] = ntq_get_alu_src(c, instr, i);
824 }
825
826 struct qreg result;
827
828 switch (instr->op) {
829 case nir_op_fmov:
830 case nir_op_imov:
831 result = vir_MOV(c, src[0]);
832 break;
833
834 case nir_op_fneg:
835 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
836 break;
837 case nir_op_ineg:
838 result = vir_NEG(c, src[0]);
839 break;
840
841 case nir_op_fmul:
842 result = vir_FMUL(c, src[0], src[1]);
843 break;
844 case nir_op_fadd:
845 result = vir_FADD(c, src[0], src[1]);
846 break;
847 case nir_op_fsub:
848 result = vir_FSUB(c, src[0], src[1]);
849 break;
850 case nir_op_fmin:
851 result = vir_FMIN(c, src[0], src[1]);
852 break;
853 case nir_op_fmax:
854 result = vir_FMAX(c, src[0], src[1]);
855 break;
856
857 case nir_op_f2i32:
858 result = vir_FTOIZ(c, src[0]);
859 break;
860 case nir_op_f2u32:
861 result = vir_FTOUZ(c, src[0]);
862 break;
863 case nir_op_i2f32:
864 result = vir_ITOF(c, src[0]);
865 break;
866 case nir_op_u2f32:
867 result = vir_UTOF(c, src[0]);
868 break;
869 case nir_op_b2f:
870 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
871 break;
872 case nir_op_b2i:
873 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
874 break;
875 case nir_op_i2b:
876 case nir_op_f2b:
877 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
878 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
879 vir_uniform_ui(c, ~0),
880 vir_uniform_ui(c, 0)));
881 break;
882
883 case nir_op_iadd:
884 result = vir_ADD(c, src[0], src[1]);
885 break;
886 case nir_op_ushr:
887 result = vir_SHR(c, src[0], src[1]);
888 break;
889 case nir_op_isub:
890 result = vir_SUB(c, src[0], src[1]);
891 break;
892 case nir_op_ishr:
893 result = vir_ASR(c, src[0], src[1]);
894 break;
895 case nir_op_ishl:
896 result = vir_SHL(c, src[0], src[1]);
897 break;
898 case nir_op_imin:
899 result = vir_MIN(c, src[0], src[1]);
900 break;
901 case nir_op_umin:
902 result = vir_UMIN(c, src[0], src[1]);
903 break;
904 case nir_op_imax:
905 result = vir_MAX(c, src[0], src[1]);
906 break;
907 case nir_op_umax:
908 result = vir_UMAX(c, src[0], src[1]);
909 break;
910 case nir_op_iand:
911 result = vir_AND(c, src[0], src[1]);
912 break;
913 case nir_op_ior:
914 result = vir_OR(c, src[0], src[1]);
915 break;
916 case nir_op_ixor:
917 result = vir_XOR(c, src[0], src[1]);
918 break;
919 case nir_op_inot:
920 result = vir_NOT(c, src[0]);
921 break;
922
923 case nir_op_imul:
924 result = ntq_umul(c, src[0], src[1]);
925 break;
926
927 case nir_op_seq:
928 case nir_op_sne:
929 case nir_op_sge:
930 case nir_op_slt:
931 case nir_op_feq:
932 case nir_op_fne:
933 case nir_op_fge:
934 case nir_op_flt:
935 case nir_op_ieq:
936 case nir_op_ine:
937 case nir_op_ige:
938 case nir_op_uge:
939 case nir_op_ilt:
940 case nir_op_ult:
941 if (!ntq_emit_comparison(c, &result, instr, instr)) {
942 fprintf(stderr, "Bad comparison instruction\n");
943 }
944 break;
945
946 case nir_op_bcsel:
947 result = ntq_emit_bcsel(c, instr, src);
948 break;
949 case nir_op_fcsel:
950 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
951 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
952 src[1], src[2]));
953 break;
954
955 case nir_op_frcp:
956 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
957 break;
958 case nir_op_frsq:
959 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
960 break;
961 case nir_op_fexp2:
962 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
963 break;
964 case nir_op_flog2:
965 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
966 break;
967
968 case nir_op_fceil:
969 result = vir_FCEIL(c, src[0]);
970 break;
971 case nir_op_ffloor:
972 result = vir_FFLOOR(c, src[0]);
973 break;
974 case nir_op_fround_even:
975 result = vir_FROUND(c, src[0]);
976 break;
977 case nir_op_ftrunc:
978 result = vir_FTRUNC(c, src[0]);
979 break;
980 case nir_op_ffract:
981 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
982 break;
983
984 case nir_op_fsin:
985 result = ntq_fsincos(c, src[0], false);
986 break;
987 case nir_op_fcos:
988 result = ntq_fsincos(c, src[0], true);
989 break;
990
991 case nir_op_fsign:
992 result = ntq_fsign(c, src[0]);
993 break;
994 case nir_op_isign:
995 result = ntq_isign(c, src[0]);
996 break;
997
998 case nir_op_fabs: {
999 result = vir_FMOV(c, src[0]);
1000 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1001 break;
1002 }
1003
1004 case nir_op_iabs:
1005 result = vir_MAX(c, src[0],
1006 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1007 break;
1008
1009 case nir_op_fddx:
1010 case nir_op_fddx_coarse:
1011 case nir_op_fddx_fine:
1012 result = vir_FDX(c, src[0]);
1013 break;
1014
1015 case nir_op_fddy:
1016 case nir_op_fddy_coarse:
1017 case nir_op_fddy_fine:
1018 result = vir_FDY(c, src[0]);
1019 break;
1020
1021 default:
1022 fprintf(stderr, "unknown NIR ALU inst: ");
1023 nir_print_instr(&instr->instr, stderr);
1024 fprintf(stderr, "\n");
1025 abort();
1026 }
1027
1028 /* We have a scalar result, so the instruction should only have a
1029 * single channel written to.
1030 */
1031 assert(util_is_power_of_two(instr->dest.write_mask));
1032 ntq_store_dest(c, &instr->dest.dest,
1033 ffs(instr->dest.write_mask) - 1, result);
1034 }
1035
1036 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1037 * specifier. They come from a register that's preloaded with 0xffffffff
1038 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1039 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1040 */
1041 #define TLB_TYPE_F16_COLOR (3 << 6)
1042 #define TLB_TYPE_I32_COLOR (1 << 6)
1043 #define TLB_TYPE_F32_COLOR (0 << 6)
1044 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1045 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1046 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1047 #define TLB_F16_SWAP_HI_LO (1 << 1)
1048 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1049 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1050 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1051
1052 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1053 * flag is set.
1054 */
1055 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1056 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1057 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1058
1059 /* Stencil is a single 32-bit write. */
1060 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1061
1062 static void
1063 emit_frag_end(struct v3d_compile *c)
1064 {
1065 /* XXX
1066 if (c->output_sample_mask_index != -1) {
1067 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1068 }
1069 */
1070
1071 bool has_any_tlb_color_write = false;
1072 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1073 if (c->output_color_var[rt])
1074 has_any_tlb_color_write = true;
1075 }
1076
1077 if (c->output_position_index != -1) {
1078 struct qinst *inst = vir_MOV_dest(c,
1079 vir_reg(QFILE_TLBU, 0),
1080 c->outputs[c->output_position_index]);
1081
1082 inst->src[vir_get_implicit_uniform_src(inst)] =
1083 vir_uniform_ui(c,
1084 TLB_TYPE_DEPTH |
1085 TLB_DEPTH_TYPE_PER_PIXEL |
1086 0xffffff00);
1087 } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
1088 /* Emit passthrough Z if it needed to be delayed until shader
1089 * end due to potential discards.
1090 *
1091 * Since (single-threaded) fragment shaders always need a TLB
1092 * write, emit passthrouh Z if we didn't have any color
1093 * buffers and flag us as potentially discarding, so that we
1094 * can use Z as the TLB write.
1095 */
1096 c->s->info.fs.uses_discard = true;
1097
1098 struct qinst *inst = vir_MOV_dest(c,
1099 vir_reg(QFILE_TLBU, 0),
1100 vir_reg(QFILE_NULL, 0));
1101
1102 inst->src[vir_get_implicit_uniform_src(inst)] =
1103 vir_uniform_ui(c,
1104 TLB_TYPE_DEPTH |
1105 TLB_DEPTH_TYPE_INVARIANT |
1106 0xffffff00);
1107 }
1108
1109 /* XXX: Performance improvement: Merge Z write and color writes TLB
1110 * uniform setup
1111 */
1112
1113 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1114 if (!c->output_color_var[rt])
1115 continue;
1116
1117 nir_variable *var = c->output_color_var[rt];
1118 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1119 int num_components = glsl_get_vector_elements(var->type);
1120 uint32_t conf = 0xffffff00;
1121 struct qinst *inst;
1122
1123 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1124 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1125
1126 assert(num_components != 0);
1127 switch (glsl_get_base_type(var->type)) {
1128 case GLSL_TYPE_UINT:
1129 case GLSL_TYPE_INT:
1130 conf |= TLB_TYPE_I32_COLOR;
1131 conf |= ((num_components - 1) <<
1132 TLB_VEC_SIZE_MINUS_1_SHIFT);
1133
1134 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1135 inst->src[vir_get_implicit_uniform_src(inst)] =
1136 vir_uniform_ui(c, conf);
1137
1138 for (int i = 1; i < num_components; i++) {
1139 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1140 color[i]);
1141 }
1142 break;
1143
1144 default: {
1145 struct qreg r = color[0];
1146 struct qreg g = color[1];
1147 struct qreg b = color[2];
1148 struct qreg a = color[3];
1149
1150 if (c->fs_key->f32_color_rb) {
1151 conf |= TLB_TYPE_F32_COLOR;
1152 conf |= ((num_components - 1) <<
1153 TLB_VEC_SIZE_MINUS_1_SHIFT);
1154 } else {
1155 conf |= TLB_TYPE_F16_COLOR;
1156 conf |= TLB_F16_SWAP_HI_LO;
1157 if (num_components >= 3)
1158 conf |= TLB_VEC_SIZE_4_F16;
1159 else
1160 conf |= TLB_VEC_SIZE_2_F16;
1161 }
1162
1163 if (c->fs_key->swap_color_rb & (1 << rt)) {
1164 r = color[2];
1165 b = color[0];
1166 }
1167
1168 if (c->fs_key->f32_color_rb & (1 << rt)) {
1169 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1170 inst->src[vir_get_implicit_uniform_src(inst)] =
1171 vir_uniform_ui(c, conf);
1172
1173 for (int i = 1; i < num_components; i++) {
1174 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1175 color[i]);
1176 }
1177 } else {
1178 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1179 if (conf != ~0) {
1180 inst->dst.file = QFILE_TLBU;
1181 inst->src[vir_get_implicit_uniform_src(inst)] =
1182 vir_uniform_ui(c, conf);
1183 }
1184
1185 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1186 }
1187 break;
1188 }
1189 }
1190 }
1191 }
1192
1193 static void
1194 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1195 {
1196 for (int i = 0; i < 2; i++) {
1197 struct qreg coord = c->outputs[c->output_position_index + i];
1198 coord = vir_FMUL(c, coord,
1199 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1200 0));
1201 coord = vir_FMUL(c, coord, rcp_w);
1202 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1203 coord);
1204 }
1205
1206 }
1207
1208 static void
1209 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1210 {
1211 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1212 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1213
1214 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1215 vir_FMUL(c, vir_FMUL(c,
1216 c->outputs[c->output_position_index + 2],
1217 zscale),
1218 rcp_w),
1219 zoffset);
1220 }
1221
1222 static void
1223 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1224 {
1225 vir_VPM_WRITE(c, rcp_w);
1226 }
1227
1228 static void
1229 emit_point_size_write(struct v3d_compile *c)
1230 {
1231 struct qreg point_size;
1232
1233 if (c->output_point_size_index != -1)
1234 point_size = c->outputs[c->output_point_size_index];
1235 else
1236 point_size = vir_uniform_f(c, 1.0);
1237
1238 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1239 * BCM21553).
1240 */
1241 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1242
1243 vir_VPM_WRITE(c, point_size);
1244 }
1245
1246 static void
1247 emit_vpm_write_setup(struct v3d_compile *c)
1248 {
1249 uint32_t packed;
1250 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1251 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1252
1253 .horiz = true,
1254 .laned = false,
1255 .segs = true,
1256 .stride = 1,
1257 .size = VPM_SETUP_SIZE_32_BIT,
1258 .addr = 0,
1259 };
1260
1261 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1262 (uint8_t *)&packed,
1263 &unpacked);
1264 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1265 }
1266
1267 static void
1268 emit_vert_end(struct v3d_compile *c)
1269 {
1270 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1271 c->outputs[c->output_position_index + 3]);
1272
1273 emit_vpm_write_setup(c);
1274
1275 if (c->vs_key->is_coord) {
1276 for (int i = 0; i < 4; i++)
1277 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1278 emit_scaled_viewport_write(c, rcp_w);
1279 if (c->vs_key->per_vertex_point_size) {
1280 emit_point_size_write(c);
1281 /* emit_rcp_wc_write(c, rcp_w); */
1282 }
1283 /* XXX: Z-only rendering */
1284 if (0)
1285 emit_zs_write(c, rcp_w);
1286 } else {
1287 emit_scaled_viewport_write(c, rcp_w);
1288 emit_zs_write(c, rcp_w);
1289 emit_rcp_wc_write(c, rcp_w);
1290 if (c->vs_key->per_vertex_point_size)
1291 emit_point_size_write(c);
1292 }
1293
1294 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1295 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1296 int j;
1297
1298 for (j = 0; j < c->num_outputs; j++) {
1299 struct v3d_varying_slot output = c->output_slots[j];
1300
1301 if (!memcmp(&input, &output, sizeof(input))) {
1302 vir_VPM_WRITE(c, c->outputs[j]);
1303 break;
1304 }
1305 }
1306 /* Emit padding if we didn't find a declared VS output for
1307 * this FS input.
1308 */
1309 if (j == c->num_outputs)
1310 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1311 }
1312 }
1313
1314 void
1315 v3d_optimize_nir(struct nir_shader *s)
1316 {
1317 bool progress;
1318
1319 do {
1320 progress = false;
1321
1322 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1323 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1324 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1325 NIR_PASS(progress, s, nir_copy_prop);
1326 NIR_PASS(progress, s, nir_opt_remove_phis);
1327 NIR_PASS(progress, s, nir_opt_dce);
1328 NIR_PASS(progress, s, nir_opt_dead_cf);
1329 NIR_PASS(progress, s, nir_opt_cse);
1330 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1331 NIR_PASS(progress, s, nir_opt_algebraic);
1332 NIR_PASS(progress, s, nir_opt_constant_folding);
1333 NIR_PASS(progress, s, nir_opt_undef);
1334 } while (progress);
1335 }
1336
1337 static int
1338 driver_location_compare(const void *in_a, const void *in_b)
1339 {
1340 const nir_variable *const *a = in_a;
1341 const nir_variable *const *b = in_b;
1342
1343 return (*a)->data.driver_location - (*b)->data.driver_location;
1344 }
1345
1346 static struct qreg
1347 ntq_emit_vpm_read(struct v3d_compile *c,
1348 uint32_t *num_components_queued,
1349 uint32_t *remaining,
1350 uint32_t vpm_index)
1351 {
1352 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1353
1354 if (*num_components_queued != 0) {
1355 (*num_components_queued)--;
1356 c->num_inputs++;
1357 return vir_MOV(c, vpm);
1358 }
1359
1360 uint32_t num_components = MIN2(*remaining, 32);
1361
1362 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1363 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1364
1365 .horiz = true,
1366 .laned = false,
1367 /* If the field is 0, that means a read count of 32. */
1368 .num = num_components & 31,
1369 .segs = true,
1370 .stride = 1,
1371 .size = VPM_SETUP_SIZE_32_BIT,
1372 .addr = c->num_inputs,
1373 };
1374
1375 uint32_t packed;
1376 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1377 (uint8_t *)&packed,
1378 &unpacked);
1379 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1380
1381 *num_components_queued = num_components - 1;
1382 *remaining -= num_components;
1383 c->num_inputs++;
1384
1385 return vir_MOV(c, vpm);
1386 }
1387
1388 static void
1389 ntq_setup_inputs(struct v3d_compile *c)
1390 {
1391 unsigned num_entries = 0;
1392 unsigned num_components = 0;
1393 nir_foreach_variable(var, &c->s->inputs) {
1394 num_entries++;
1395 num_components += glsl_get_components(var->type);
1396 }
1397
1398 nir_variable *vars[num_entries];
1399
1400 unsigned i = 0;
1401 nir_foreach_variable(var, &c->s->inputs)
1402 vars[i++] = var;
1403
1404 /* Sort the variables so that we emit the input setup in
1405 * driver_location order. This is required for VPM reads, whose data
1406 * is fetched into the VPM in driver_location (TGSI register index)
1407 * order.
1408 */
1409 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1410
1411 uint32_t vpm_components_queued = 0;
1412 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1413 bool uses_iid = c->s->info.system_values_read &
1414 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1415 bool uses_vid = c->s->info.system_values_read &
1416 (1ull << SYSTEM_VALUE_VERTEX_ID);
1417
1418 num_components += uses_iid;
1419 num_components += uses_vid;
1420
1421 if (uses_iid) {
1422 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1423 &num_components, ~0);
1424 }
1425
1426 if (uses_vid) {
1427 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1428 &num_components, ~0);
1429 }
1430 }
1431
1432 for (unsigned i = 0; i < num_entries; i++) {
1433 nir_variable *var = vars[i];
1434 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1435 unsigned loc = var->data.driver_location;
1436
1437 assert(array_len == 1);
1438 (void)array_len;
1439 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1440 (loc + 1) * 4);
1441
1442 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1443 if (var->data.location == VARYING_SLOT_POS) {
1444 emit_fragcoord_input(c, loc);
1445 } else if (var->data.location == VARYING_SLOT_PNTC ||
1446 (var->data.location >= VARYING_SLOT_VAR0 &&
1447 (c->fs_key->point_sprite_mask &
1448 (1 << (var->data.location -
1449 VARYING_SLOT_VAR0))))) {
1450 c->inputs[loc * 4 + 0] = c->point_x;
1451 c->inputs[loc * 4 + 1] = c->point_y;
1452 } else {
1453 emit_fragment_input(c, loc, var);
1454 }
1455 } else {
1456 int var_components = glsl_get_components(var->type);
1457
1458 for (int i = 0; i < var_components; i++) {
1459 c->inputs[loc * 4 + i] =
1460 ntq_emit_vpm_read(c,
1461 &vpm_components_queued,
1462 &num_components,
1463 loc * 4 + i);
1464
1465 }
1466 c->vattr_sizes[loc] = var_components;
1467 }
1468 }
1469
1470 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1471 assert(vpm_components_queued == 0);
1472 assert(num_components == 0);
1473 }
1474 }
1475
1476 static void
1477 ntq_setup_outputs(struct v3d_compile *c)
1478 {
1479 nir_foreach_variable(var, &c->s->outputs) {
1480 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1481 unsigned loc = var->data.driver_location * 4;
1482
1483 assert(array_len == 1);
1484 (void)array_len;
1485
1486 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
1487 add_output(c, loc + var->data.location_frac + i,
1488 var->data.location,
1489 var->data.location_frac + i);
1490 }
1491
1492 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1493 switch (var->data.location) {
1494 case FRAG_RESULT_COLOR:
1495 c->output_color_var[0] = var;
1496 c->output_color_var[1] = var;
1497 c->output_color_var[2] = var;
1498 c->output_color_var[3] = var;
1499 break;
1500 case FRAG_RESULT_DATA0:
1501 case FRAG_RESULT_DATA1:
1502 case FRAG_RESULT_DATA2:
1503 case FRAG_RESULT_DATA3:
1504 c->output_color_var[var->data.location -
1505 FRAG_RESULT_DATA0] = var;
1506 break;
1507 case FRAG_RESULT_DEPTH:
1508 c->output_position_index = loc;
1509 break;
1510 case FRAG_RESULT_SAMPLE_MASK:
1511 c->output_sample_mask_index = loc;
1512 break;
1513 }
1514 } else {
1515 switch (var->data.location) {
1516 case VARYING_SLOT_POS:
1517 c->output_position_index = loc;
1518 break;
1519 case VARYING_SLOT_PSIZ:
1520 c->output_point_size_index = loc;
1521 break;
1522 }
1523 }
1524 }
1525 }
1526
1527 static void
1528 ntq_setup_uniforms(struct v3d_compile *c)
1529 {
1530 nir_foreach_variable(var, &c->s->uniforms) {
1531 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1532 false);
1533 unsigned vec4_size = 4 * sizeof(float);
1534
1535 declare_uniform_range(c, var->data.driver_location * vec4_size,
1536 vec4_count * vec4_size);
1537
1538 }
1539 }
1540
1541 /**
1542 * Sets up the mapping from nir_register to struct qreg *.
1543 *
1544 * Each nir_register gets a struct qreg per 32-bit component being stored.
1545 */
1546 static void
1547 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1548 {
1549 foreach_list_typed(nir_register, nir_reg, node, list) {
1550 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1551 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1552 array_len *
1553 nir_reg->num_components);
1554
1555 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1556
1557 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1558 qregs[i] = vir_get_temp(c);
1559 }
1560 }
1561
1562 static void
1563 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1564 {
1565 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1566 for (int i = 0; i < instr->def.num_components; i++)
1567 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1568
1569 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1570 }
1571
1572 static void
1573 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1574 {
1575 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1576
1577 /* VIR needs there to be *some* value, so pick 0 (same as for
1578 * ntq_setup_registers().
1579 */
1580 for (int i = 0; i < instr->def.num_components; i++)
1581 qregs[i] = vir_uniform_ui(c, 0);
1582 }
1583
1584 static void
1585 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1586 {
1587 nir_const_value *const_offset;
1588 unsigned offset;
1589
1590 switch (instr->intrinsic) {
1591 case nir_intrinsic_load_uniform:
1592 assert(instr->num_components == 1);
1593 const_offset = nir_src_as_const_value(instr->src[0]);
1594 if (const_offset) {
1595 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1596 assert(offset % 4 == 0);
1597 /* We need dwords */
1598 offset = offset / 4;
1599 ntq_store_dest(c, &instr->dest, 0,
1600 vir_uniform(c, QUNIFORM_UNIFORM,
1601 offset));
1602 } else {
1603 ntq_store_dest(c, &instr->dest, 0,
1604 indirect_uniform_load(c, instr));
1605 }
1606 break;
1607
1608 case nir_intrinsic_load_ubo:
1609 for (int i = 0; i < instr->num_components; i++) {
1610 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1611
1612 /* Adjust for where we stored the TGSI register base. */
1613 vir_ADD_dest(c,
1614 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1615 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1616 vir_ADD(c,
1617 ntq_get_src(c, instr->src[1], 0),
1618 vir_uniform_ui(c, i * 4)));
1619
1620 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1621 }
1622 break;
1623
1624 const_offset = nir_src_as_const_value(instr->src[0]);
1625 if (const_offset) {
1626 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1627 assert(offset % 4 == 0);
1628 /* We need dwords */
1629 offset = offset / 4;
1630 ntq_store_dest(c, &instr->dest, 0,
1631 vir_uniform(c, QUNIFORM_UNIFORM,
1632 offset));
1633 } else {
1634 ntq_store_dest(c, &instr->dest, 0,
1635 indirect_uniform_load(c, instr));
1636 }
1637 break;
1638
1639 case nir_intrinsic_load_user_clip_plane:
1640 for (int i = 0; i < instr->num_components; i++) {
1641 ntq_store_dest(c, &instr->dest, i,
1642 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1643 nir_intrinsic_ucp_id(instr) *
1644 4 + i));
1645 }
1646 break;
1647
1648 case nir_intrinsic_load_alpha_ref_float:
1649 ntq_store_dest(c, &instr->dest, 0,
1650 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1651 break;
1652
1653 case nir_intrinsic_load_sample_mask_in:
1654 ntq_store_dest(c, &instr->dest, 0,
1655 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1656 break;
1657
1658 case nir_intrinsic_load_front_face:
1659 /* The register contains 0 (front) or 1 (back), and we need to
1660 * turn it into a NIR bool where true means front.
1661 */
1662 ntq_store_dest(c, &instr->dest, 0,
1663 vir_ADD(c,
1664 vir_uniform_ui(c, -1),
1665 vir_REVF(c)));
1666 break;
1667
1668 case nir_intrinsic_load_instance_id:
1669 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1670 break;
1671
1672 case nir_intrinsic_load_vertex_id:
1673 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1674 break;
1675
1676 case nir_intrinsic_load_input:
1677 const_offset = nir_src_as_const_value(instr->src[0]);
1678 assert(const_offset && "v3d doesn't support indirect inputs");
1679 for (int i = 0; i < instr->num_components; i++) {
1680 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1681 int comp = nir_intrinsic_component(instr) + i;
1682 ntq_store_dest(c, &instr->dest, i,
1683 vir_MOV(c, c->inputs[offset * 4 + comp]));
1684 }
1685 break;
1686
1687 case nir_intrinsic_store_output:
1688 const_offset = nir_src_as_const_value(instr->src[1]);
1689 assert(const_offset && "v3d doesn't support indirect outputs");
1690 offset = ((nir_intrinsic_base(instr) +
1691 const_offset->u32[0]) * 4 +
1692 nir_intrinsic_component(instr));
1693
1694 for (int i = 0; i < instr->num_components; i++) {
1695 c->outputs[offset + i] =
1696 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1697 }
1698 c->num_outputs = MAX2(c->num_outputs,
1699 offset + instr->num_components);
1700 break;
1701
1702 case nir_intrinsic_discard:
1703 if (c->execute.file != QFILE_NULL) {
1704 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1705 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1706 vir_uniform_ui(c, 0)),
1707 V3D_QPU_COND_IFA);
1708 } else {
1709 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1710 vir_uniform_ui(c, 0));
1711 }
1712 break;
1713
1714 case nir_intrinsic_discard_if: {
1715 /* true (~0) if we're discarding */
1716 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1717
1718 if (c->execute.file != QFILE_NULL) {
1719 /* execute == 0 means the channel is active. Invert
1720 * the condition so that we can use zero as "executing
1721 * and discarding."
1722 */
1723 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1724 V3D_QPU_PF_PUSHZ);
1725 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1726 vir_uniform_ui(c, 0)),
1727 V3D_QPU_COND_IFA);
1728 } else {
1729 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1730 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1731 vir_uniform_ui(c, 0)),
1732 V3D_QPU_COND_IFNA);
1733 }
1734
1735 break;
1736 }
1737
1738 default:
1739 fprintf(stderr, "Unknown intrinsic: ");
1740 nir_print_instr(&instr->instr, stderr);
1741 fprintf(stderr, "\n");
1742 break;
1743 }
1744 }
1745
1746 /* Clears (activates) the execute flags for any channels whose jump target
1747 * matches this block.
1748 */
1749 static void
1750 ntq_activate_execute_for_block(struct v3d_compile *c)
1751 {
1752 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1753 V3D_QPU_PF_PUSHZ);
1754
1755 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1756 }
1757
1758 static void
1759 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1760 {
1761 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1762 bool empty_else_block =
1763 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1764 exec_list_is_empty(&nir_else_block->instr_list));
1765
1766 struct qblock *then_block = vir_new_block(c);
1767 struct qblock *after_block = vir_new_block(c);
1768 struct qblock *else_block;
1769 if (empty_else_block)
1770 else_block = after_block;
1771 else
1772 else_block = vir_new_block(c);
1773
1774 bool was_top_level = false;
1775 if (c->execute.file == QFILE_NULL) {
1776 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1777 was_top_level = true;
1778 }
1779
1780 /* Set A for executing (execute == 0) and jumping (if->condition ==
1781 * 0) channels, and then update execute flags for those to point to
1782 * the ELSE block.
1783 */
1784 vir_PF(c, vir_OR(c,
1785 c->execute,
1786 ntq_get_src(c, if_stmt->condition, 0)),
1787 V3D_QPU_PF_PUSHZ);
1788 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1789 c->execute,
1790 vir_uniform_ui(c, else_block->index));
1791
1792 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1793 * through.
1794 */
1795 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1796 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1797 vir_link_blocks(c->cur_block, else_block);
1798 vir_link_blocks(c->cur_block, then_block);
1799
1800 /* Process the THEN block. */
1801 vir_set_emit_block(c, then_block);
1802 ntq_emit_cf_list(c, &if_stmt->then_list);
1803
1804 if (!empty_else_block) {
1805 /* Handle the end of the THEN block. First, all currently
1806 * active channels update their execute flags to point to
1807 * ENDIF
1808 */
1809 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1810 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1811 vir_uniform_ui(c, after_block->index));
1812
1813 /* If everything points at ENDIF, then jump there immediately. */
1814 vir_PF(c, vir_SUB(c, c->execute,
1815 vir_uniform_ui(c, after_block->index)),
1816 V3D_QPU_PF_PUSHZ);
1817 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1818 vir_link_blocks(c->cur_block, after_block);
1819 vir_link_blocks(c->cur_block, else_block);
1820
1821 vir_set_emit_block(c, else_block);
1822 ntq_activate_execute_for_block(c);
1823 ntq_emit_cf_list(c, &if_stmt->else_list);
1824 }
1825
1826 vir_link_blocks(c->cur_block, after_block);
1827
1828 vir_set_emit_block(c, after_block);
1829 if (was_top_level)
1830 c->execute = c->undef;
1831 else
1832 ntq_activate_execute_for_block(c);
1833 }
1834
1835 static void
1836 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1837 {
1838 switch (jump->type) {
1839 case nir_jump_break:
1840 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1841 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1842 vir_uniform_ui(c, c->loop_break_block->index));
1843 break;
1844
1845 case nir_jump_continue:
1846 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1847 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1848 vir_uniform_ui(c, c->loop_cont_block->index));
1849 break;
1850
1851 case nir_jump_return:
1852 unreachable("All returns shouold be lowered\n");
1853 }
1854 }
1855
1856 static void
1857 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1858 {
1859 switch (instr->type) {
1860 case nir_instr_type_alu:
1861 ntq_emit_alu(c, nir_instr_as_alu(instr));
1862 break;
1863
1864 case nir_instr_type_intrinsic:
1865 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1866 break;
1867
1868 case nir_instr_type_load_const:
1869 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1870 break;
1871
1872 case nir_instr_type_ssa_undef:
1873 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1874 break;
1875
1876 case nir_instr_type_tex:
1877 ntq_emit_tex(c, nir_instr_as_tex(instr));
1878 break;
1879
1880 case nir_instr_type_jump:
1881 ntq_emit_jump(c, nir_instr_as_jump(instr));
1882 break;
1883
1884 default:
1885 fprintf(stderr, "Unknown NIR instr type: ");
1886 nir_print_instr(instr, stderr);
1887 fprintf(stderr, "\n");
1888 abort();
1889 }
1890 }
1891
1892 static void
1893 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1894 {
1895 nir_foreach_instr(instr, block) {
1896 ntq_emit_instr(c, instr);
1897 }
1898 }
1899
1900 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1901
1902 static void
1903 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1904 {
1905 bool was_top_level = false;
1906 if (c->execute.file == QFILE_NULL) {
1907 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1908 was_top_level = true;
1909 }
1910
1911 struct qblock *save_loop_cont_block = c->loop_cont_block;
1912 struct qblock *save_loop_break_block = c->loop_break_block;
1913
1914 c->loop_cont_block = vir_new_block(c);
1915 c->loop_break_block = vir_new_block(c);
1916
1917 vir_link_blocks(c->cur_block, c->loop_cont_block);
1918 vir_set_emit_block(c, c->loop_cont_block);
1919 ntq_activate_execute_for_block(c);
1920
1921 ntq_emit_cf_list(c, &loop->body);
1922
1923 /* Re-enable any previous continues now, so our ANYA check below
1924 * works.
1925 *
1926 * XXX: Use the .ORZ flags update, instead.
1927 */
1928 vir_PF(c, vir_SUB(c,
1929 c->execute,
1930 vir_uniform_ui(c, c->loop_cont_block->index)),
1931 V3D_QPU_PF_PUSHZ);
1932 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1933
1934 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1935
1936 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1937 vir_link_blocks(c->cur_block, c->loop_cont_block);
1938 vir_link_blocks(c->cur_block, c->loop_break_block);
1939
1940 vir_set_emit_block(c, c->loop_break_block);
1941 if (was_top_level)
1942 c->execute = c->undef;
1943 else
1944 ntq_activate_execute_for_block(c);
1945
1946 c->loop_break_block = save_loop_break_block;
1947 c->loop_cont_block = save_loop_cont_block;
1948 }
1949
1950 static void
1951 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1952 {
1953 fprintf(stderr, "FUNCTIONS not handled.\n");
1954 abort();
1955 }
1956
1957 static void
1958 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1959 {
1960 foreach_list_typed(nir_cf_node, node, node, list) {
1961 switch (node->type) {
1962 case nir_cf_node_block:
1963 ntq_emit_block(c, nir_cf_node_as_block(node));
1964 break;
1965
1966 case nir_cf_node_if:
1967 ntq_emit_if(c, nir_cf_node_as_if(node));
1968 break;
1969
1970 case nir_cf_node_loop:
1971 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1972 break;
1973
1974 case nir_cf_node_function:
1975 ntq_emit_function(c, nir_cf_node_as_function(node));
1976 break;
1977
1978 default:
1979 fprintf(stderr, "Unknown NIR node type\n");
1980 abort();
1981 }
1982 }
1983 }
1984
1985 static void
1986 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1987 {
1988 ntq_setup_registers(c, &impl->registers);
1989 ntq_emit_cf_list(c, &impl->body);
1990 }
1991
1992 static void
1993 nir_to_vir(struct v3d_compile *c)
1994 {
1995 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1996 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1997 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1998 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1999
2000 if (c->fs_key->is_points) {
2001 c->point_x = emit_fragment_varying(c, NULL, 0);
2002 c->point_y = emit_fragment_varying(c, NULL, 0);
2003 } else if (c->fs_key->is_lines) {
2004 c->line_x = emit_fragment_varying(c, NULL, 0);
2005 }
2006 }
2007
2008 ntq_setup_inputs(c);
2009 ntq_setup_outputs(c);
2010 ntq_setup_uniforms(c);
2011 ntq_setup_registers(c, &c->s->registers);
2012
2013 /* Find the main function and emit the body. */
2014 nir_foreach_function(function, c->s) {
2015 assert(strcmp(function->name, "main") == 0);
2016 assert(function->impl);
2017 ntq_emit_impl(c, function->impl);
2018 }
2019 }
2020
2021 const nir_shader_compiler_options v3d_nir_options = {
2022 .lower_extract_byte = true,
2023 .lower_extract_word = true,
2024 .lower_bitfield_insert = true,
2025 .lower_bitfield_extract = true,
2026 .lower_pack_unorm_2x16 = true,
2027 .lower_pack_snorm_2x16 = true,
2028 .lower_pack_unorm_4x8 = true,
2029 .lower_pack_snorm_4x8 = true,
2030 .lower_unpack_unorm_4x8 = true,
2031 .lower_unpack_snorm_4x8 = true,
2032 .lower_fdiv = true,
2033 .lower_ffma = true,
2034 .lower_flrp32 = true,
2035 .lower_fpow = true,
2036 .lower_fsat = true,
2037 .lower_fsqrt = true,
2038 .native_integers = true,
2039 };
2040
2041
2042 #if 0
2043 static int
2044 count_nir_instrs(nir_shader *nir)
2045 {
2046 int count = 0;
2047 nir_foreach_function(function, nir) {
2048 if (!function->impl)
2049 continue;
2050 nir_foreach_block(block, function->impl) {
2051 nir_foreach_instr(instr, block)
2052 count++;
2053 }
2054 }
2055 return count;
2056 }
2057 #endif
2058
2059 void
2060 v3d_nir_to_vir(struct v3d_compile *c)
2061 {
2062 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2063 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2064 fprintf(stderr, "%s prog %d/%d NIR:\n",
2065 vir_get_stage_name(c),
2066 c->program_id, c->variant_id);
2067 nir_print_shader(c->s, stderr);
2068 }
2069
2070 nir_to_vir(c);
2071
2072 switch (c->s->info.stage) {
2073 case MESA_SHADER_FRAGMENT:
2074 emit_frag_end(c);
2075 break;
2076 case MESA_SHADER_VERTEX:
2077 emit_vert_end(c);
2078 break;
2079 default:
2080 unreachable("bad stage");
2081 }
2082
2083 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2084 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2085 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2086 vir_get_stage_name(c),
2087 c->program_id, c->variant_id);
2088 vir_dump(c);
2089 fprintf(stderr, "\n");
2090 }
2091
2092 vir_optimize(c);
2093 vir_lower_uniforms(c);
2094
2095 /* XXX: vir_schedule_instructions(c); */
2096
2097 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2098 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2099 fprintf(stderr, "%s prog %d/%d VIR:\n",
2100 vir_get_stage_name(c),
2101 c->program_id, c->variant_id);
2102 vir_dump(c);
2103 fprintf(stderr, "\n");
2104 }
2105
2106 v3d_vir_to_qpu(c);
2107 }