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v3d: move implementation of some intrinsics to separate helpers
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125
126 /* We need to lock the scoreboard before any tlb acess happens. If this
127 * thread switch comes after we have emitted a tlb load, then it means
128 * that we can't lock on the last thread switch any more.
129 */
130 if (c->emitted_tlb_load)
131 c->lock_scoreboard_on_first_thrsw = true;
132 }
133
134 static uint32_t
135 v3d_general_tmu_op(nir_intrinsic_instr *instr)
136 {
137 switch (instr->intrinsic) {
138 case nir_intrinsic_load_ssbo:
139 case nir_intrinsic_load_ubo:
140 case nir_intrinsic_load_uniform:
141 case nir_intrinsic_load_shared:
142 case nir_intrinsic_load_scratch:
143 return GENERAL_TMU_READ_OP_READ;
144 case nir_intrinsic_store_ssbo:
145 case nir_intrinsic_store_shared:
146 case nir_intrinsic_store_scratch:
147 return GENERAL_TMU_WRITE_OP_WRITE;
148 case nir_intrinsic_ssbo_atomic_add:
149 case nir_intrinsic_shared_atomic_add:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
151 case nir_intrinsic_ssbo_atomic_imin:
152 case nir_intrinsic_shared_atomic_imin:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
154 case nir_intrinsic_ssbo_atomic_umin:
155 case nir_intrinsic_shared_atomic_umin:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
157 case nir_intrinsic_ssbo_atomic_imax:
158 case nir_intrinsic_shared_atomic_imax:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
160 case nir_intrinsic_ssbo_atomic_umax:
161 case nir_intrinsic_shared_atomic_umax:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
163 case nir_intrinsic_ssbo_atomic_and:
164 case nir_intrinsic_shared_atomic_and:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
166 case nir_intrinsic_ssbo_atomic_or:
167 case nir_intrinsic_shared_atomic_or:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
169 case nir_intrinsic_ssbo_atomic_xor:
170 case nir_intrinsic_shared_atomic_xor:
171 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
172 case nir_intrinsic_ssbo_atomic_exchange:
173 case nir_intrinsic_shared_atomic_exchange:
174 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
175 case nir_intrinsic_ssbo_atomic_comp_swap:
176 case nir_intrinsic_shared_atomic_comp_swap:
177 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
178 default:
179 unreachable("unknown intrinsic op");
180 }
181 }
182
183 /**
184 * Implements indirect uniform loads and SSBO accesses through the TMU general
185 * memory access interface.
186 */
187 static void
188 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
189 bool is_shared_or_scratch)
190 {
191 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
192 * wants to have support for inc/dec?
193 */
194
195 uint32_t tmu_op = v3d_general_tmu_op(instr);
196 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
197 instr->intrinsic == nir_intrinsic_store_scratch ||
198 instr->intrinsic == nir_intrinsic_store_shared);
199 bool has_index = !is_shared_or_scratch;
200
201 int offset_src;
202 int tmu_writes = 1; /* address */
203 if (instr->intrinsic == nir_intrinsic_load_uniform) {
204 offset_src = 0;
205 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
206 instr->intrinsic == nir_intrinsic_load_ubo ||
207 instr->intrinsic == nir_intrinsic_load_scratch ||
208 instr->intrinsic == nir_intrinsic_load_shared) {
209 offset_src = 0 + has_index;
210 } else if (is_store) {
211 offset_src = 1 + has_index;
212 for (int i = 0; i < instr->num_components; i++) {
213 vir_MOV_dest(c,
214 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
215 ntq_get_src(c, instr->src[0], i));
216 tmu_writes++;
217 }
218 } else {
219 offset_src = 0 + has_index;
220 vir_MOV_dest(c,
221 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
222 ntq_get_src(c, instr->src[1 + has_index], 0));
223 tmu_writes++;
224 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
225 vir_MOV_dest(c,
226 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
227 ntq_get_src(c, instr->src[2 + has_index],
228 0));
229 tmu_writes++;
230 }
231 }
232
233 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
234 uint32_t const_offset = 0;
235 if (!dynamic_src)
236 const_offset = nir_src_as_uint(instr->src[offset_src]);
237
238 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
239 * storing at the same time.
240 */
241 while (tmu_writes > 16 / c->threads)
242 c->threads /= 2;
243
244 struct qreg offset;
245 if (instr->intrinsic == nir_intrinsic_load_uniform) {
246 const_offset += nir_intrinsic_base(instr);
247 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
248 v3d_unit_data_create(0, const_offset));
249 const_offset = 0;
250 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
251 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
252 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
253 * 1 (0 is gallium's constant buffer 0).
254 */
255 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
256 v3d_unit_data_create(index, const_offset));
257 const_offset = 0;
258 } else if (is_shared_or_scratch) {
259 /* Shared and scratch variables have no buffer index, and all
260 * start from a common base that we set up at the start of
261 * dispatch.
262 */
263 if (instr->intrinsic == nir_intrinsic_load_scratch ||
264 instr->intrinsic == nir_intrinsic_store_scratch) {
265 offset = c->spill_base;
266 } else {
267 offset = c->cs_shared_offset;
268 const_offset += nir_intrinsic_base(instr);
269 }
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 /* The spec says that for atomics, the TYPE field is ignored, but that
277 * doesn't seem to be the case for CMPXCHG. Just use the number of
278 * tmud writes we did to decide the type (or choose "32bit" for atomic
279 * reads, which has been fine).
280 */
281 int num_components;
282 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG)
283 num_components = 2;
284 else
285 num_components = instr->num_components;
286
287 uint32_t config = (0xffffff00 |
288 tmu_op |
289 GENERAL_TMU_LOOKUP_PER_PIXEL);
290 if (num_components == 1) {
291 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
292 } else {
293 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + num_components - 2;
294 }
295
296 if (vir_in_nonuniform_control_flow(c)) {
297 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
298 V3D_QPU_PF_PUSHZ);
299 }
300
301 struct qreg tmua;
302 if (config == ~0)
303 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
304 else
305 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
306
307 struct qinst *tmu;
308 if (dynamic_src) {
309 if (const_offset != 0) {
310 offset = vir_ADD(c, offset,
311 vir_uniform_ui(c, const_offset));
312 }
313 tmu = vir_ADD_dest(c, tmua, offset,
314 ntq_get_src(c, instr->src[offset_src], 0));
315 } else {
316 if (const_offset != 0) {
317 tmu = vir_ADD_dest(c, tmua, offset,
318 vir_uniform_ui(c, const_offset));
319 } else {
320 tmu = vir_MOV_dest(c, tmua, offset);
321 }
322 }
323
324 if (config != ~0) {
325 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
326 config);
327 }
328
329 if (vir_in_nonuniform_control_flow(c))
330 vir_set_cond(tmu, V3D_QPU_COND_IFA);
331
332 vir_emit_thrsw(c);
333
334 /* Read the result, or wait for the TMU op to complete. */
335 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
336 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
337
338 if (nir_intrinsic_dest_components(instr) == 0)
339 vir_TMUWT(c);
340 }
341
342 static struct qreg *
343 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
344 {
345 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
346 def->num_components);
347 _mesa_hash_table_insert(c->def_ht, def, qregs);
348 return qregs;
349 }
350
351 /**
352 * This function is responsible for getting VIR results into the associated
353 * storage for a NIR instruction.
354 *
355 * If it's a NIR SSA def, then we just set the associated hash table entry to
356 * the new result.
357 *
358 * If it's a NIR reg, then we need to update the existing qreg assigned to the
359 * NIR destination with the incoming value. To do that without introducing
360 * new MOVs, we require that the incoming qreg either be a uniform, or be
361 * SSA-defined by the previous VIR instruction in the block and rewritable by
362 * this function. That lets us sneak ahead and insert the SF flag beforehand
363 * (knowing that the previous instruction doesn't depend on flags) and rewrite
364 * its destination to be the NIR reg's destination
365 */
366 void
367 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
368 struct qreg result)
369 {
370 struct qinst *last_inst = NULL;
371 if (!list_empty(&c->cur_block->instructions))
372 last_inst = (struct qinst *)c->cur_block->instructions.prev;
373
374 assert((result.file == QFILE_TEMP &&
375 last_inst && last_inst == c->defs[result.index]));
376
377 if (dest->is_ssa) {
378 assert(chan < dest->ssa.num_components);
379
380 struct qreg *qregs;
381 struct hash_entry *entry =
382 _mesa_hash_table_search(c->def_ht, &dest->ssa);
383
384 if (entry)
385 qregs = entry->data;
386 else
387 qregs = ntq_init_ssa_def(c, &dest->ssa);
388
389 qregs[chan] = result;
390 } else {
391 nir_register *reg = dest->reg.reg;
392 assert(dest->reg.base_offset == 0);
393 assert(reg->num_array_elems == 0);
394 struct hash_entry *entry =
395 _mesa_hash_table_search(c->def_ht, reg);
396 struct qreg *qregs = entry->data;
397
398 /* Insert a MOV if the source wasn't an SSA def in the
399 * previous instruction.
400 */
401 if ((vir_in_nonuniform_control_flow(c) &&
402 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
403 result = vir_MOV(c, result);
404 last_inst = c->defs[result.index];
405 }
406
407 /* We know they're both temps, so just rewrite index. */
408 c->defs[last_inst->dst.index] = NULL;
409 last_inst->dst.index = qregs[chan].index;
410
411 /* If we're in control flow, then make this update of the reg
412 * conditional on the execution mask.
413 */
414 if (vir_in_nonuniform_control_flow(c)) {
415 last_inst->dst.index = qregs[chan].index;
416
417 /* Set the flags to the current exec mask.
418 */
419 c->cursor = vir_before_inst(last_inst);
420 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
421 V3D_QPU_PF_PUSHZ);
422 c->cursor = vir_after_inst(last_inst);
423
424 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
425 }
426 }
427 }
428
429 struct qreg
430 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
431 {
432 struct hash_entry *entry;
433 if (src.is_ssa) {
434 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
435 assert(i < src.ssa->num_components);
436 } else {
437 nir_register *reg = src.reg.reg;
438 entry = _mesa_hash_table_search(c->def_ht, reg);
439 assert(reg->num_array_elems == 0);
440 assert(src.reg.base_offset == 0);
441 assert(i < reg->num_components);
442 }
443
444 struct qreg *qregs = entry->data;
445 return qregs[i];
446 }
447
448 static struct qreg
449 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
450 unsigned src)
451 {
452 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
453 unsigned chan = ffs(instr->dest.write_mask) - 1;
454 struct qreg r = ntq_get_src(c, instr->src[src].src,
455 instr->src[src].swizzle[chan]);
456
457 assert(!instr->src[src].abs);
458 assert(!instr->src[src].negate);
459
460 return r;
461 };
462
463 static struct qreg
464 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
465 {
466 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
467 }
468
469 static void
470 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
471 {
472 unsigned unit = instr->texture_index;
473 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
474 int dest_size = nir_tex_instr_dest_size(instr);
475
476 struct qreg lod = c->undef;
477 if (lod_index != -1)
478 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
479
480 for (int i = 0; i < dest_size; i++) {
481 assert(i < 3);
482 enum quniform_contents contents;
483
484 if (instr->is_array && i == dest_size - 1)
485 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
486 else
487 contents = QUNIFORM_TEXTURE_WIDTH + i;
488
489 struct qreg size = vir_uniform(c, contents, unit);
490
491 switch (instr->sampler_dim) {
492 case GLSL_SAMPLER_DIM_1D:
493 case GLSL_SAMPLER_DIM_2D:
494 case GLSL_SAMPLER_DIM_MS:
495 case GLSL_SAMPLER_DIM_3D:
496 case GLSL_SAMPLER_DIM_CUBE:
497 /* Don't minify the array size. */
498 if (!(instr->is_array && i == dest_size - 1)) {
499 size = ntq_minify(c, size, lod);
500 }
501 break;
502
503 case GLSL_SAMPLER_DIM_RECT:
504 /* There's no LOD field for rects */
505 break;
506
507 default:
508 unreachable("Bad sampler type");
509 }
510
511 ntq_store_dest(c, &instr->dest, i, size);
512 }
513 }
514
515 static void
516 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
517 {
518 unsigned unit = instr->texture_index;
519
520 /* Since each texture sampling op requires uploading uniforms to
521 * reference the texture, there's no HW support for texture size and
522 * you just upload uniforms containing the size.
523 */
524 switch (instr->op) {
525 case nir_texop_query_levels:
526 ntq_store_dest(c, &instr->dest, 0,
527 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
528 return;
529 case nir_texop_txs:
530 ntq_emit_txs(c, instr);
531 return;
532 default:
533 break;
534 }
535
536 if (c->devinfo->ver >= 40)
537 v3d40_vir_emit_tex(c, instr);
538 else
539 v3d33_vir_emit_tex(c, instr);
540 }
541
542 static struct qreg
543 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
544 {
545 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
546 if (is_cos)
547 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
548
549 struct qreg periods = vir_FROUND(c, input);
550 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
551 return vir_XOR(c, sin_output, vir_SHL(c,
552 vir_FTOIN(c, periods),
553 vir_uniform_ui(c, -1)));
554 }
555
556 static struct qreg
557 ntq_fsign(struct v3d_compile *c, struct qreg src)
558 {
559 struct qreg t = vir_get_temp(c);
560
561 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
562 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
563 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
564 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
565 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
566 return vir_MOV(c, t);
567 }
568
569 static void
570 emit_fragcoord_input(struct v3d_compile *c, int attr)
571 {
572 c->inputs[attr * 4 + 0] = vir_FXCD(c);
573 c->inputs[attr * 4 + 1] = vir_FYCD(c);
574 c->inputs[attr * 4 + 2] = c->payload_z;
575 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
576 }
577
578 static struct qreg
579 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
580 uint8_t swizzle, int array_index)
581 {
582 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
583 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
584
585 struct qreg vary;
586 if (c->devinfo->ver >= 41) {
587 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
588 c->undef, c->undef);
589 ldvary->qpu.sig.ldvary = true;
590 vary = vir_emit_def(c, ldvary);
591 } else {
592 vir_NOP(c)->qpu.sig.ldvary = true;
593 vary = r3;
594 }
595
596 /* For gl_PointCoord input or distance along a line, we'll be called
597 * with no nir_variable, and we don't count toward VPM size so we
598 * don't track an input slot.
599 */
600 if (!var) {
601 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
602 }
603
604 int i = c->num_inputs++;
605 c->input_slots[i] =
606 v3d_slot_from_slot_and_component(var->data.location +
607 array_index, swizzle);
608
609 switch (var->data.interpolation) {
610 case INTERP_MODE_NONE:
611 /* If a gl_FrontColor or gl_BackColor input has no interp
612 * qualifier, then if we're using glShadeModel(GL_FLAT) it
613 * needs to be flat shaded.
614 */
615 switch (var->data.location + array_index) {
616 case VARYING_SLOT_COL0:
617 case VARYING_SLOT_COL1:
618 case VARYING_SLOT_BFC0:
619 case VARYING_SLOT_BFC1:
620 if (c->fs_key->shade_model_flat) {
621 BITSET_SET(c->flat_shade_flags, i);
622 vir_MOV_dest(c, c->undef, vary);
623 return vir_MOV(c, r5);
624 } else {
625 return vir_FADD(c, vir_FMUL(c, vary,
626 c->payload_w), r5);
627 }
628 default:
629 break;
630 }
631 /* FALLTHROUGH */
632 case INTERP_MODE_SMOOTH:
633 if (var->data.centroid) {
634 BITSET_SET(c->centroid_flags, i);
635 return vir_FADD(c, vir_FMUL(c, vary,
636 c->payload_w_centroid), r5);
637 } else {
638 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
639 }
640 case INTERP_MODE_NOPERSPECTIVE:
641 BITSET_SET(c->noperspective_flags, i);
642 return vir_FADD(c, vir_MOV(c, vary), r5);
643 case INTERP_MODE_FLAT:
644 BITSET_SET(c->flat_shade_flags, i);
645 vir_MOV_dest(c, c->undef, vary);
646 return vir_MOV(c, r5);
647 default:
648 unreachable("Bad interp mode");
649 }
650 }
651
652 static void
653 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
654 int array_index)
655 {
656 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
657 int chan = var->data.location_frac + i;
658 c->inputs[attr * 4 + chan] =
659 emit_fragment_varying(c, var, chan, array_index);
660 }
661 }
662
663 static void
664 add_output(struct v3d_compile *c,
665 uint32_t decl_offset,
666 uint8_t slot,
667 uint8_t swizzle)
668 {
669 uint32_t old_array_size = c->outputs_array_size;
670 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
671 decl_offset + 1);
672
673 if (old_array_size != c->outputs_array_size) {
674 c->output_slots = reralloc(c,
675 c->output_slots,
676 struct v3d_varying_slot,
677 c->outputs_array_size);
678 }
679
680 c->output_slots[decl_offset] =
681 v3d_slot_from_slot_and_component(slot, swizzle);
682 }
683
684 /**
685 * If compare_instr is a valid comparison instruction, emits the
686 * compare_instr's comparison and returns the sel_instr's return value based
687 * on the compare_instr's result.
688 */
689 static bool
690 ntq_emit_comparison(struct v3d_compile *c,
691 nir_alu_instr *compare_instr,
692 enum v3d_qpu_cond *out_cond)
693 {
694 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
695 struct qreg src1;
696 if (nir_op_infos[compare_instr->op].num_inputs > 1)
697 src1 = ntq_get_alu_src(c, compare_instr, 1);
698 bool cond_invert = false;
699 struct qreg nop = vir_nop_reg();
700
701 switch (compare_instr->op) {
702 case nir_op_feq32:
703 case nir_op_seq:
704 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
705 break;
706 case nir_op_ieq32:
707 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
708 break;
709
710 case nir_op_fne32:
711 case nir_op_sne:
712 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
713 cond_invert = true;
714 break;
715 case nir_op_ine32:
716 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719
720 case nir_op_fge32:
721 case nir_op_sge:
722 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
723 break;
724 case nir_op_ige32:
725 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
726 cond_invert = true;
727 break;
728 case nir_op_uge32:
729 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732
733 case nir_op_slt:
734 case nir_op_flt32:
735 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
736 break;
737 case nir_op_ilt32:
738 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
739 break;
740 case nir_op_ult32:
741 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
742 break;
743
744 case nir_op_i2b32:
745 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
746 cond_invert = true;
747 break;
748
749 case nir_op_f2b32:
750 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
751 cond_invert = true;
752 break;
753
754 default:
755 return false;
756 }
757
758 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
759
760 return true;
761 }
762
763 /* Finds an ALU instruction that generates our src value that could
764 * (potentially) be greedily emitted in the consuming instruction.
765 */
766 static struct nir_alu_instr *
767 ntq_get_alu_parent(nir_src src)
768 {
769 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
770 return NULL;
771 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
772 if (!instr)
773 return NULL;
774
775 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
776 * moving emission of the ALU instr down past another write of the
777 * src.
778 */
779 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
780 if (!instr->src[i].src.is_ssa)
781 return NULL;
782 }
783
784 return instr;
785 }
786
787 /* Turns a NIR bool into a condition code to predicate on. */
788 static enum v3d_qpu_cond
789 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
790 {
791 nir_alu_instr *compare = ntq_get_alu_parent(src);
792 if (!compare)
793 goto out;
794
795 enum v3d_qpu_cond cond;
796 if (ntq_emit_comparison(c, compare, &cond))
797 return cond;
798
799 out:
800 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
801 V3D_QPU_PF_PUSHZ);
802 return V3D_QPU_COND_IFNA;
803 }
804
805 static void
806 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
807 {
808 /* This should always be lowered to ALU operations for V3D. */
809 assert(!instr->dest.saturate);
810
811 /* Vectors are special in that they have non-scalarized writemasks,
812 * and just take the first swizzle channel for each argument in order
813 * into each writemask channel.
814 */
815 if (instr->op == nir_op_vec2 ||
816 instr->op == nir_op_vec3 ||
817 instr->op == nir_op_vec4) {
818 struct qreg srcs[4];
819 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
820 srcs[i] = ntq_get_src(c, instr->src[i].src,
821 instr->src[i].swizzle[0]);
822 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
823 ntq_store_dest(c, &instr->dest.dest, i,
824 vir_MOV(c, srcs[i]));
825 return;
826 }
827
828 /* General case: We can just grab the one used channel per src. */
829 struct qreg src[nir_op_infos[instr->op].num_inputs];
830 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
831 src[i] = ntq_get_alu_src(c, instr, i);
832 }
833
834 struct qreg result;
835
836 switch (instr->op) {
837 case nir_op_mov:
838 result = vir_MOV(c, src[0]);
839 break;
840
841 case nir_op_fneg:
842 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
843 break;
844 case nir_op_ineg:
845 result = vir_NEG(c, src[0]);
846 break;
847
848 case nir_op_fmul:
849 result = vir_FMUL(c, src[0], src[1]);
850 break;
851 case nir_op_fadd:
852 result = vir_FADD(c, src[0], src[1]);
853 break;
854 case nir_op_fsub:
855 result = vir_FSUB(c, src[0], src[1]);
856 break;
857 case nir_op_fmin:
858 result = vir_FMIN(c, src[0], src[1]);
859 break;
860 case nir_op_fmax:
861 result = vir_FMAX(c, src[0], src[1]);
862 break;
863
864 case nir_op_f2i32: {
865 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
866 if (src0_alu && src0_alu->op == nir_op_fround_even) {
867 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
868 } else {
869 result = vir_FTOIZ(c, src[0]);
870 }
871 break;
872 }
873
874 case nir_op_f2u32:
875 result = vir_FTOUZ(c, src[0]);
876 break;
877 case nir_op_i2f32:
878 result = vir_ITOF(c, src[0]);
879 break;
880 case nir_op_u2f32:
881 result = vir_UTOF(c, src[0]);
882 break;
883 case nir_op_b2f32:
884 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
885 break;
886 case nir_op_b2i32:
887 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
888 break;
889
890 case nir_op_iadd:
891 result = vir_ADD(c, src[0], src[1]);
892 break;
893 case nir_op_ushr:
894 result = vir_SHR(c, src[0], src[1]);
895 break;
896 case nir_op_isub:
897 result = vir_SUB(c, src[0], src[1]);
898 break;
899 case nir_op_ishr:
900 result = vir_ASR(c, src[0], src[1]);
901 break;
902 case nir_op_ishl:
903 result = vir_SHL(c, src[0], src[1]);
904 break;
905 case nir_op_imin:
906 result = vir_MIN(c, src[0], src[1]);
907 break;
908 case nir_op_umin:
909 result = vir_UMIN(c, src[0], src[1]);
910 break;
911 case nir_op_imax:
912 result = vir_MAX(c, src[0], src[1]);
913 break;
914 case nir_op_umax:
915 result = vir_UMAX(c, src[0], src[1]);
916 break;
917 case nir_op_iand:
918 result = vir_AND(c, src[0], src[1]);
919 break;
920 case nir_op_ior:
921 result = vir_OR(c, src[0], src[1]);
922 break;
923 case nir_op_ixor:
924 result = vir_XOR(c, src[0], src[1]);
925 break;
926 case nir_op_inot:
927 result = vir_NOT(c, src[0]);
928 break;
929
930 case nir_op_ufind_msb:
931 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
932 break;
933
934 case nir_op_imul:
935 result = vir_UMUL(c, src[0], src[1]);
936 break;
937
938 case nir_op_seq:
939 case nir_op_sne:
940 case nir_op_sge:
941 case nir_op_slt: {
942 enum v3d_qpu_cond cond;
943 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
944 assert(ok);
945 result = vir_MOV(c, vir_SEL(c, cond,
946 vir_uniform_f(c, 1.0),
947 vir_uniform_f(c, 0.0)));
948 break;
949 }
950
951 case nir_op_i2b32:
952 case nir_op_f2b32:
953 case nir_op_feq32:
954 case nir_op_fne32:
955 case nir_op_fge32:
956 case nir_op_flt32:
957 case nir_op_ieq32:
958 case nir_op_ine32:
959 case nir_op_ige32:
960 case nir_op_uge32:
961 case nir_op_ilt32:
962 case nir_op_ult32: {
963 enum v3d_qpu_cond cond;
964 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
965 assert(ok);
966 result = vir_MOV(c, vir_SEL(c, cond,
967 vir_uniform_ui(c, ~0),
968 vir_uniform_ui(c, 0)));
969 break;
970 }
971
972 case nir_op_b32csel:
973 result = vir_MOV(c,
974 vir_SEL(c,
975 ntq_emit_bool_to_cond(c, instr->src[0].src),
976 src[1], src[2]));
977 break;
978
979 case nir_op_fcsel:
980 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
981 V3D_QPU_PF_PUSHZ);
982 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
983 src[1], src[2]));
984 break;
985
986 case nir_op_frcp:
987 result = vir_RECIP(c, src[0]);
988 break;
989 case nir_op_frsq:
990 result = vir_RSQRT(c, src[0]);
991 break;
992 case nir_op_fexp2:
993 result = vir_EXP(c, src[0]);
994 break;
995 case nir_op_flog2:
996 result = vir_LOG(c, src[0]);
997 break;
998
999 case nir_op_fceil:
1000 result = vir_FCEIL(c, src[0]);
1001 break;
1002 case nir_op_ffloor:
1003 result = vir_FFLOOR(c, src[0]);
1004 break;
1005 case nir_op_fround_even:
1006 result = vir_FROUND(c, src[0]);
1007 break;
1008 case nir_op_ftrunc:
1009 result = vir_FTRUNC(c, src[0]);
1010 break;
1011
1012 case nir_op_fsin:
1013 result = ntq_fsincos(c, src[0], false);
1014 break;
1015 case nir_op_fcos:
1016 result = ntq_fsincos(c, src[0], true);
1017 break;
1018
1019 case nir_op_fsign:
1020 result = ntq_fsign(c, src[0]);
1021 break;
1022
1023 case nir_op_fabs: {
1024 result = vir_FMOV(c, src[0]);
1025 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1026 break;
1027 }
1028
1029 case nir_op_iabs:
1030 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1031 break;
1032
1033 case nir_op_fddx:
1034 case nir_op_fddx_coarse:
1035 case nir_op_fddx_fine:
1036 result = vir_FDX(c, src[0]);
1037 break;
1038
1039 case nir_op_fddy:
1040 case nir_op_fddy_coarse:
1041 case nir_op_fddy_fine:
1042 result = vir_FDY(c, src[0]);
1043 break;
1044
1045 case nir_op_uadd_carry:
1046 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1047 V3D_QPU_PF_PUSHC);
1048 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1049 vir_uniform_ui(c, ~0),
1050 vir_uniform_ui(c, 0)));
1051 break;
1052
1053 case nir_op_pack_half_2x16_split:
1054 result = vir_VFPACK(c, src[0], src[1]);
1055 break;
1056
1057 case nir_op_unpack_half_2x16_split_x:
1058 result = vir_FMOV(c, src[0]);
1059 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1060 break;
1061
1062 case nir_op_unpack_half_2x16_split_y:
1063 result = vir_FMOV(c, src[0]);
1064 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1065 break;
1066
1067 default:
1068 fprintf(stderr, "unknown NIR ALU inst: ");
1069 nir_print_instr(&instr->instr, stderr);
1070 fprintf(stderr, "\n");
1071 abort();
1072 }
1073
1074 /* We have a scalar result, so the instruction should only have a
1075 * single channel written to.
1076 */
1077 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1078 ntq_store_dest(c, &instr->dest.dest,
1079 ffs(instr->dest.write_mask) - 1, result);
1080 }
1081
1082 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1083 * specifier. They come from a register that's preloaded with 0xffffffff
1084 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1085 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1086 */
1087 #define TLB_TYPE_F16_COLOR (3 << 6)
1088 #define TLB_TYPE_I32_COLOR (1 << 6)
1089 #define TLB_TYPE_F32_COLOR (0 << 6)
1090 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1091 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1092 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1093 #define TLB_F16_SWAP_HI_LO (1 << 1)
1094 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1095 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1096 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1097
1098 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1099 * flag is set.
1100 */
1101 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1102 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1103 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1104 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1105 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1106
1107 /* Stencil is a single 32-bit write. */
1108 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1109
1110 static void
1111 emit_frag_end(struct v3d_compile *c)
1112 {
1113 /* XXX
1114 if (c->output_sample_mask_index != -1) {
1115 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1116 }
1117 */
1118
1119 bool has_any_tlb_color_write = false;
1120 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1121 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1122 has_any_tlb_color_write = true;
1123 }
1124
1125 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1126 struct nir_variable *var = c->output_color_var[0];
1127 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1128
1129 vir_SETMSF_dest(c, vir_nop_reg(),
1130 vir_AND(c,
1131 vir_MSF(c),
1132 vir_FTOC(c, color[3])));
1133 }
1134
1135 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1136 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1137 if (c->output_position_index != -1) {
1138 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1139 c->outputs[c->output_position_index]);
1140 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1141
1142 if (c->devinfo->ver >= 42) {
1143 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1144 TLB_SAMPLE_MODE_PER_PIXEL);
1145 } else
1146 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1147
1148 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1149 tlb_specifier |
1150 0xffffff00);
1151 c->writes_z = true;
1152 } else if (c->s->info.fs.uses_discard ||
1153 !c->s->info.fs.early_fragment_tests ||
1154 c->fs_key->sample_alpha_to_coverage ||
1155 !has_any_tlb_color_write) {
1156 /* Emit passthrough Z if it needed to be delayed until shader
1157 * end due to potential discards.
1158 *
1159 * Since (single-threaded) fragment shaders always need a TLB
1160 * write, emit passthrouh Z if we didn't have any color
1161 * buffers and flag us as potentially discarding, so that we
1162 * can use Z as the TLB write.
1163 */
1164 c->s->info.fs.uses_discard = true;
1165
1166 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1167 vir_nop_reg());
1168 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1169
1170 if (c->devinfo->ver >= 42) {
1171 /* The spec says the PER_PIXEL flag is ignored for
1172 * invariant writes, but the simulator demands it.
1173 */
1174 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1175 TLB_SAMPLE_MODE_PER_PIXEL);
1176 } else {
1177 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1178 }
1179
1180 inst->uniform = vir_get_uniform_index(c,
1181 QUNIFORM_CONSTANT,
1182 tlb_specifier |
1183 0xffffff00);
1184 c->writes_z = true;
1185 }
1186
1187 /* XXX: Performance improvement: Merge Z write and color writes TLB
1188 * uniform setup
1189 */
1190
1191 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1192 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1193 continue;
1194
1195 nir_variable *var = c->output_color_var[rt];
1196 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1197 int num_components = glsl_get_vector_elements(var->type);
1198 uint32_t conf = 0xffffff00;
1199 struct qinst *inst;
1200
1201 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1202 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1203
1204 if (c->fs_key->swap_color_rb & (1 << rt))
1205 num_components = MAX2(num_components, 3);
1206
1207 assert(num_components != 0);
1208 switch (glsl_get_base_type(var->type)) {
1209 case GLSL_TYPE_UINT:
1210 case GLSL_TYPE_INT:
1211 /* The F32 vs I32 distinction was dropped in 4.2. */
1212 if (c->devinfo->ver < 42)
1213 conf |= TLB_TYPE_I32_COLOR;
1214 else
1215 conf |= TLB_TYPE_F32_COLOR;
1216 conf |= ((num_components - 1) <<
1217 TLB_VEC_SIZE_MINUS_1_SHIFT);
1218
1219 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1220 inst->uniform = vir_get_uniform_index(c,
1221 QUNIFORM_CONSTANT,
1222 conf);
1223
1224 for (int i = 1; i < num_components; i++) {
1225 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1226 }
1227 break;
1228
1229 default: {
1230 struct qreg r = color[0];
1231 struct qreg g = color[1];
1232 struct qreg b = color[2];
1233 struct qreg a = color[3];
1234
1235 if (c->fs_key->f32_color_rb & (1 << rt)) {
1236 conf |= TLB_TYPE_F32_COLOR;
1237 conf |= ((num_components - 1) <<
1238 TLB_VEC_SIZE_MINUS_1_SHIFT);
1239 } else {
1240 conf |= TLB_TYPE_F16_COLOR;
1241 conf |= TLB_F16_SWAP_HI_LO;
1242 if (num_components >= 3)
1243 conf |= TLB_VEC_SIZE_4_F16;
1244 else
1245 conf |= TLB_VEC_SIZE_2_F16;
1246 }
1247
1248 if (c->fs_key->swap_color_rb & (1 << rt)) {
1249 r = color[2];
1250 b = color[0];
1251 }
1252
1253 if (c->fs_key->sample_alpha_to_one)
1254 a = vir_uniform_f(c, 1.0);
1255
1256 if (c->fs_key->f32_color_rb & (1 << rt)) {
1257 inst = vir_MOV_dest(c, tlbu_reg, r);
1258 inst->uniform = vir_get_uniform_index(c,
1259 QUNIFORM_CONSTANT,
1260 conf);
1261
1262 if (num_components >= 2)
1263 vir_MOV_dest(c, tlb_reg, g);
1264 if (num_components >= 3)
1265 vir_MOV_dest(c, tlb_reg, b);
1266 if (num_components >= 4)
1267 vir_MOV_dest(c, tlb_reg, a);
1268 } else {
1269 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1270 if (conf != ~0) {
1271 inst->dst = tlbu_reg;
1272 inst->uniform = vir_get_uniform_index(c,
1273 QUNIFORM_CONSTANT,
1274 conf);
1275 }
1276
1277 if (num_components >= 3)
1278 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1279 }
1280 break;
1281 }
1282 }
1283 }
1284 }
1285
1286 static void
1287 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1288 {
1289 if (c->devinfo->ver >= 40) {
1290 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1291 } else {
1292 /* XXX: v3d33_vir_vpm_write_setup(c); */
1293 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1294 }
1295 }
1296
1297 static void
1298 emit_vert_end(struct v3d_compile *c)
1299 {
1300 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1301 */
1302 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1303 vir_VPMWT(c);
1304 }
1305
1306 void
1307 v3d_optimize_nir(struct nir_shader *s)
1308 {
1309 bool progress;
1310 unsigned lower_flrp =
1311 (s->options->lower_flrp16 ? 16 : 0) |
1312 (s->options->lower_flrp32 ? 32 : 0) |
1313 (s->options->lower_flrp64 ? 64 : 0);
1314
1315 do {
1316 progress = false;
1317
1318 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1319 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1320 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1321 NIR_PASS(progress, s, nir_copy_prop);
1322 NIR_PASS(progress, s, nir_opt_remove_phis);
1323 NIR_PASS(progress, s, nir_opt_dce);
1324 NIR_PASS(progress, s, nir_opt_dead_cf);
1325 NIR_PASS(progress, s, nir_opt_cse);
1326 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1327 NIR_PASS(progress, s, nir_opt_algebraic);
1328 NIR_PASS(progress, s, nir_opt_constant_folding);
1329
1330 if (lower_flrp != 0) {
1331 bool lower_flrp_progress = false;
1332
1333 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1334 lower_flrp,
1335 false /* always_precise */,
1336 s->options->lower_ffma);
1337 if (lower_flrp_progress) {
1338 NIR_PASS(progress, s, nir_opt_constant_folding);
1339 progress = true;
1340 }
1341
1342 /* Nothing should rematerialize any flrps, so we only
1343 * need to do this lowering once.
1344 */
1345 lower_flrp = 0;
1346 }
1347
1348 NIR_PASS(progress, s, nir_opt_undef);
1349 } while (progress);
1350
1351 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1352 }
1353
1354 static int
1355 driver_location_compare(const void *in_a, const void *in_b)
1356 {
1357 const nir_variable *const *a = in_a;
1358 const nir_variable *const *b = in_b;
1359
1360 return (*a)->data.driver_location - (*b)->data.driver_location;
1361 }
1362
1363 static struct qreg
1364 ntq_emit_vpm_read(struct v3d_compile *c,
1365 uint32_t *num_components_queued,
1366 uint32_t *remaining,
1367 uint32_t vpm_index)
1368 {
1369 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1370
1371 if (c->devinfo->ver >= 40 ) {
1372 return vir_LDVPMV_IN(c,
1373 vir_uniform_ui(c,
1374 (*num_components_queued)++));
1375 }
1376
1377 if (*num_components_queued != 0) {
1378 (*num_components_queued)--;
1379 return vir_MOV(c, vpm);
1380 }
1381
1382 uint32_t num_components = MIN2(*remaining, 32);
1383
1384 v3d33_vir_vpm_read_setup(c, num_components);
1385
1386 *num_components_queued = num_components - 1;
1387 *remaining -= num_components;
1388
1389 return vir_MOV(c, vpm);
1390 }
1391
1392 static void
1393 ntq_setup_vpm_inputs(struct v3d_compile *c)
1394 {
1395 /* Figure out how many components of each vertex attribute the shader
1396 * uses. Each variable should have been split to individual
1397 * components and unused ones DCEed. The vertex fetcher will load
1398 * from the start of the attribute to the number of components we
1399 * declare we need in c->vattr_sizes[].
1400 */
1401 nir_foreach_variable(var, &c->s->inputs) {
1402 /* No VS attribute array support. */
1403 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1404
1405 unsigned loc = var->data.driver_location;
1406 int start_component = var->data.location_frac;
1407 int num_components = glsl_get_components(var->type);
1408
1409 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1410 start_component + num_components);
1411 }
1412
1413 unsigned num_components = 0;
1414 uint32_t vpm_components_queued = 0;
1415 bool uses_iid = c->s->info.system_values_read &
1416 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1417 bool uses_vid = c->s->info.system_values_read &
1418 (1ull << SYSTEM_VALUE_VERTEX_ID);
1419 num_components += uses_iid;
1420 num_components += uses_vid;
1421
1422 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1423 num_components += c->vattr_sizes[i];
1424
1425 if (uses_iid) {
1426 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1427 &num_components, ~0);
1428 }
1429
1430 if (uses_vid) {
1431 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1432 &num_components, ~0);
1433 }
1434
1435 /* The actual loads will happen directly in nir_intrinsic_load_input
1436 * on newer versions.
1437 */
1438 if (c->devinfo->ver >= 40)
1439 return;
1440
1441 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1442 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1443 (loc + 1) * 4);
1444
1445 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1446 c->inputs[loc * 4 + i] =
1447 ntq_emit_vpm_read(c,
1448 &vpm_components_queued,
1449 &num_components,
1450 loc * 4 + i);
1451
1452 }
1453 }
1454
1455 if (c->devinfo->ver >= 40) {
1456 assert(vpm_components_queued == num_components);
1457 } else {
1458 assert(vpm_components_queued == 0);
1459 assert(num_components == 0);
1460 }
1461 }
1462
1463 static bool
1464 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1465 {
1466 return (var->data.location == VARYING_SLOT_PNTC ||
1467 (var->data.location >= VARYING_SLOT_VAR0 &&
1468 (c->fs_key->point_sprite_mask &
1469 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1470 }
1471
1472 static bool
1473 program_reads_point_coord(struct v3d_compile *c)
1474 {
1475 nir_foreach_variable(var, &c->s->inputs) {
1476 if (var_needs_point_coord(c, var))
1477 return true;
1478 }
1479
1480 return false;
1481 }
1482
1483 static void
1484 ntq_setup_fs_inputs(struct v3d_compile *c)
1485 {
1486 unsigned num_entries = 0;
1487 unsigned num_components = 0;
1488 nir_foreach_variable(var, &c->s->inputs) {
1489 num_entries++;
1490 num_components += glsl_get_components(var->type);
1491 }
1492
1493 nir_variable *vars[num_entries];
1494
1495 unsigned i = 0;
1496 nir_foreach_variable(var, &c->s->inputs)
1497 vars[i++] = var;
1498
1499 /* Sort the variables so that we emit the input setup in
1500 * driver_location order. This is required for VPM reads, whose data
1501 * is fetched into the VPM in driver_location (TGSI register index)
1502 * order.
1503 */
1504 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1505
1506 for (unsigned i = 0; i < num_entries; i++) {
1507 nir_variable *var = vars[i];
1508 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1509 unsigned loc = var->data.driver_location;
1510
1511 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1512 (loc + array_len) * 4);
1513
1514 if (var->data.location == VARYING_SLOT_POS) {
1515 emit_fragcoord_input(c, loc);
1516 } else if (var_needs_point_coord(c, var)) {
1517 c->inputs[loc * 4 + 0] = c->point_x;
1518 c->inputs[loc * 4 + 1] = c->point_y;
1519 } else {
1520 for (int j = 0; j < array_len; j++)
1521 emit_fragment_input(c, loc + j, var, j);
1522 }
1523 }
1524 }
1525
1526 static void
1527 ntq_setup_outputs(struct v3d_compile *c)
1528 {
1529 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1530 return;
1531
1532 nir_foreach_variable(var, &c->s->outputs) {
1533 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1534 unsigned loc = var->data.driver_location * 4;
1535
1536 assert(array_len == 1);
1537 (void)array_len;
1538
1539 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1540 add_output(c, loc + var->data.location_frac + i,
1541 var->data.location,
1542 var->data.location_frac + i);
1543 }
1544
1545 switch (var->data.location) {
1546 case FRAG_RESULT_COLOR:
1547 c->output_color_var[0] = var;
1548 c->output_color_var[1] = var;
1549 c->output_color_var[2] = var;
1550 c->output_color_var[3] = var;
1551 break;
1552 case FRAG_RESULT_DATA0:
1553 case FRAG_RESULT_DATA1:
1554 case FRAG_RESULT_DATA2:
1555 case FRAG_RESULT_DATA3:
1556 c->output_color_var[var->data.location -
1557 FRAG_RESULT_DATA0] = var;
1558 break;
1559 case FRAG_RESULT_DEPTH:
1560 c->output_position_index = loc;
1561 break;
1562 case FRAG_RESULT_SAMPLE_MASK:
1563 c->output_sample_mask_index = loc;
1564 break;
1565 }
1566 }
1567 }
1568
1569 /**
1570 * Sets up the mapping from nir_register to struct qreg *.
1571 *
1572 * Each nir_register gets a struct qreg per 32-bit component being stored.
1573 */
1574 static void
1575 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1576 {
1577 foreach_list_typed(nir_register, nir_reg, node, list) {
1578 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1579 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1580 array_len *
1581 nir_reg->num_components);
1582
1583 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1584
1585 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1586 qregs[i] = vir_get_temp(c);
1587 }
1588 }
1589
1590 static void
1591 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1592 {
1593 /* XXX perf: Experiment with using immediate loads to avoid having
1594 * these end up in the uniform stream. Watch out for breaking the
1595 * small immediates optimization in the process!
1596 */
1597 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1598 for (int i = 0; i < instr->def.num_components; i++)
1599 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1600
1601 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1602 }
1603
1604 static void
1605 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1606 {
1607 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1608
1609 /* VIR needs there to be *some* value, so pick 0 (same as for
1610 * ntq_setup_registers().
1611 */
1612 for (int i = 0; i < instr->def.num_components; i++)
1613 qregs[i] = vir_uniform_ui(c, 0);
1614 }
1615
1616 static void
1617 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1618 {
1619 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1620 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1621 unsigned image_index = var->data.driver_location;
1622 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1623 bool is_array = glsl_sampler_type_is_array(sampler_type);
1624
1625 ntq_store_dest(c, &instr->dest, 0,
1626 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1627 if (instr->num_components > 1) {
1628 ntq_store_dest(c, &instr->dest, 1,
1629 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1630 image_index));
1631 }
1632 if (instr->num_components > 2) {
1633 ntq_store_dest(c, &instr->dest, 2,
1634 vir_uniform(c,
1635 is_array ?
1636 QUNIFORM_IMAGE_ARRAY_SIZE :
1637 QUNIFORM_IMAGE_DEPTH,
1638 image_index));
1639 }
1640 }
1641
1642 static void
1643 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1644 {
1645 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1646
1647 int rt = nir_src_as_uint(instr->src[0]);
1648 assert(rt < V3D_MAX_DRAW_BUFFERS);
1649
1650 int sample_index = nir_intrinsic_base(instr) ;
1651 assert(sample_index == 0); /* XXX: multisample */
1652
1653 int component = nir_intrinsic_component(instr);
1654 assert(component < 4);
1655
1656 /* We need to emit our TLB reads after we have acquired the scoreboard
1657 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1658 * the last thread switch to improve parallelism, however, that is only
1659 * guaranteed to happen before the tlb color writes.
1660 *
1661 * To fix that, we make sure we always emit a thread switch before the
1662 * first tlb color read. If that happens to be the last thread switch
1663 * we emit, then everything is fine, but otherwsie, if any code after
1664 * this point needs to emit additional thread switches, then we will
1665 * switch the strategy to locking the scoreboard on the first thread
1666 * switch instead -- see vir_emit_thrsw().
1667 */
1668 if (!c->emitted_tlb_load) {
1669 if (!c->last_thrsw_at_top_level) {
1670 assert(c->devinfo->ver >= 41);
1671 vir_emit_thrsw(c);
1672 }
1673
1674 c->emitted_tlb_load = true;
1675 }
1676
1677 struct qreg *color_reads =
1678 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1679
1680 if (color_reads[component].file == QFILE_NULL) {
1681 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1682 int num_components =
1683 util_format_get_nr_components(rt_format);
1684
1685 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1686 if (swap_rb)
1687 num_components = MAX2(num_components, 3);
1688
1689 nir_variable *var = c->output_color_var[rt];
1690 enum glsl_base_type type = glsl_get_base_type(var->type);
1691
1692 bool is_int_format = type == GLSL_TYPE_INT ||
1693 type == GLSL_TYPE_UINT;
1694
1695 bool is_32b_tlb_format = is_int_format ||
1696 (c->fs_key->f32_color_rb & (1 << rt));
1697
1698 uint32_t conf = 0xffffff00;
1699 conf |= TLB_SAMPLE_MODE_PER_PIXEL; /* XXX: multisample */
1700 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1701
1702 if (is_32b_tlb_format) {
1703 /* The F32 vs I32 distinction was dropped in 4.2. */
1704 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1705 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1706
1707 conf |= ((num_components - 1) <<
1708 TLB_VEC_SIZE_MINUS_1_SHIFT);
1709 } else {
1710 conf |= TLB_TYPE_F16_COLOR;
1711 conf |= TLB_F16_SWAP_HI_LO;
1712
1713 if (num_components >= 3)
1714 conf |= TLB_VEC_SIZE_4_F16;
1715 else
1716 conf |= TLB_VEC_SIZE_2_F16;
1717 }
1718
1719 struct qreg r, g, b, a;
1720 if (is_32b_tlb_format) {
1721 r = conf != 0xffffffff ? vir_TLBU_COLOR_READ(c, conf) :
1722 vir_TLB_COLOR_READ(c);
1723 if (num_components >= 2)
1724 g = vir_TLB_COLOR_READ(c);
1725 if (num_components >= 3)
1726 b = vir_TLB_COLOR_READ(c);
1727 if (num_components >= 4)
1728 a = vir_TLB_COLOR_READ(c);
1729 } else {
1730 struct qreg rg = conf != 0xffffffff ?
1731 vir_TLBU_COLOR_READ(c, conf) :
1732 vir_TLB_COLOR_READ(c);
1733 r = vir_FMOV(c, rg);
1734 vir_set_unpack(c->defs[r.index], 0, V3D_QPU_UNPACK_L);
1735 g = vir_FMOV(c, rg);
1736 vir_set_unpack(c->defs[g.index], 0, V3D_QPU_UNPACK_H);
1737
1738 if (num_components > 2) {
1739 struct qreg ba = vir_TLB_COLOR_READ(c);
1740 b = vir_FMOV(c, ba);
1741 vir_set_unpack(c->defs[b.index], 0,
1742 V3D_QPU_UNPACK_L);
1743 a = vir_FMOV(c, ba);
1744 vir_set_unpack(c->defs[a.index], 0,
1745 V3D_QPU_UNPACK_H);
1746 }
1747 }
1748
1749 color_reads[0] = swap_rb ? b : r;
1750 if (num_components >= 2)
1751 color_reads[1] = g;
1752 if (num_components >= 3)
1753 color_reads[2] = swap_rb ? r : b;
1754 if (num_components >= 4)
1755 color_reads[3] = a;
1756 }
1757
1758 assert(color_reads[component].file != QFILE_NULL);
1759 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, color_reads[component]));
1760 }
1761
1762 static void
1763 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1764 {
1765 if (nir_src_is_const(instr->src[0])) {
1766 int offset = (nir_intrinsic_base(instr) +
1767 nir_src_as_uint(instr->src[0]));
1768 assert(offset % 4 == 0);
1769 /* We need dwords */
1770 offset = offset / 4;
1771 for (int i = 0; i < instr->num_components; i++) {
1772 ntq_store_dest(c, &instr->dest, i,
1773 vir_uniform(c, QUNIFORM_UNIFORM,
1774 offset + i));
1775 }
1776 } else {
1777 ntq_emit_tmu_general(c, instr, false);
1778 }
1779 }
1780
1781 static void
1782 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1783 {
1784 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1785 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1786 */
1787 unsigned offset =
1788 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1789
1790 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1791 /* Emit the LDVPM directly now, rather than at the top
1792 * of the shader like we did for V3D 3.x (which needs
1793 * vpmsetup when not just taking the next offset).
1794 *
1795 * Note that delaying like this may introduce stalls,
1796 * as LDVPMV takes a minimum of 1 instruction but may
1797 * be slower if the VPM unit is busy with another QPU.
1798 */
1799 int index = 0;
1800 if (c->s->info.system_values_read &
1801 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1802 index++;
1803 }
1804 if (c->s->info.system_values_read &
1805 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1806 index++;
1807 }
1808 for (int i = 0; i < offset; i++)
1809 index += c->vattr_sizes[i];
1810 index += nir_intrinsic_component(instr);
1811 for (int i = 0; i < instr->num_components; i++) {
1812 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1813 ntq_store_dest(c, &instr->dest, i,
1814 vir_LDVPMV_IN(c, vpm_offset));
1815 }
1816 } else {
1817 for (int i = 0; i < instr->num_components; i++) {
1818 int comp = nir_intrinsic_component(instr) + i;
1819 ntq_store_dest(c, &instr->dest, i,
1820 vir_MOV(c, c->inputs[offset * 4 + comp]));
1821 }
1822 }
1823 }
1824
1825 static void
1826 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
1827 {
1828 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1829 * stvpmd with non-uniform offsets and enable
1830 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1831 */
1832 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1833 unsigned offset = ((nir_intrinsic_base(instr) +
1834 nir_src_as_uint(instr->src[1])) * 4 +
1835 nir_intrinsic_component(instr));
1836 for (int i = 0; i < instr->num_components; i++) {
1837 c->outputs[offset + i] =
1838 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1839 }
1840 } else {
1841 assert(instr->num_components == 1);
1842
1843 vir_VPM_WRITE(c,
1844 ntq_get_src(c, instr->src[0], 0),
1845 nir_intrinsic_base(instr));
1846 }
1847 }
1848
1849 static void
1850 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1851 {
1852 switch (instr->intrinsic) {
1853 case nir_intrinsic_load_uniform:
1854 ntq_emit_load_uniform(c, instr);
1855 break;
1856
1857 case nir_intrinsic_load_ubo:
1858 ntq_emit_tmu_general(c, instr, false);
1859 break;
1860
1861 case nir_intrinsic_ssbo_atomic_add:
1862 case nir_intrinsic_ssbo_atomic_imin:
1863 case nir_intrinsic_ssbo_atomic_umin:
1864 case nir_intrinsic_ssbo_atomic_imax:
1865 case nir_intrinsic_ssbo_atomic_umax:
1866 case nir_intrinsic_ssbo_atomic_and:
1867 case nir_intrinsic_ssbo_atomic_or:
1868 case nir_intrinsic_ssbo_atomic_xor:
1869 case nir_intrinsic_ssbo_atomic_exchange:
1870 case nir_intrinsic_ssbo_atomic_comp_swap:
1871 case nir_intrinsic_load_ssbo:
1872 case nir_intrinsic_store_ssbo:
1873 ntq_emit_tmu_general(c, instr, false);
1874 break;
1875
1876 case nir_intrinsic_shared_atomic_add:
1877 case nir_intrinsic_shared_atomic_imin:
1878 case nir_intrinsic_shared_atomic_umin:
1879 case nir_intrinsic_shared_atomic_imax:
1880 case nir_intrinsic_shared_atomic_umax:
1881 case nir_intrinsic_shared_atomic_and:
1882 case nir_intrinsic_shared_atomic_or:
1883 case nir_intrinsic_shared_atomic_xor:
1884 case nir_intrinsic_shared_atomic_exchange:
1885 case nir_intrinsic_shared_atomic_comp_swap:
1886 case nir_intrinsic_load_shared:
1887 case nir_intrinsic_store_shared:
1888 case nir_intrinsic_load_scratch:
1889 case nir_intrinsic_store_scratch:
1890 ntq_emit_tmu_general(c, instr, true);
1891 break;
1892
1893 case nir_intrinsic_image_deref_load:
1894 case nir_intrinsic_image_deref_store:
1895 case nir_intrinsic_image_deref_atomic_add:
1896 case nir_intrinsic_image_deref_atomic_min:
1897 case nir_intrinsic_image_deref_atomic_max:
1898 case nir_intrinsic_image_deref_atomic_and:
1899 case nir_intrinsic_image_deref_atomic_or:
1900 case nir_intrinsic_image_deref_atomic_xor:
1901 case nir_intrinsic_image_deref_atomic_exchange:
1902 case nir_intrinsic_image_deref_atomic_comp_swap:
1903 v3d40_vir_emit_image_load_store(c, instr);
1904 break;
1905
1906 case nir_intrinsic_get_buffer_size:
1907 ntq_store_dest(c, &instr->dest, 0,
1908 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1909 nir_src_as_uint(instr->src[0])));
1910 break;
1911
1912 case nir_intrinsic_load_user_clip_plane:
1913 for (int i = 0; i < instr->num_components; i++) {
1914 ntq_store_dest(c, &instr->dest, i,
1915 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1916 nir_intrinsic_ucp_id(instr) *
1917 4 + i));
1918 }
1919 break;
1920
1921 case nir_intrinsic_load_viewport_x_scale:
1922 ntq_store_dest(c, &instr->dest, 0,
1923 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1924 break;
1925
1926 case nir_intrinsic_load_viewport_y_scale:
1927 ntq_store_dest(c, &instr->dest, 0,
1928 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1929 break;
1930
1931 case nir_intrinsic_load_viewport_z_scale:
1932 ntq_store_dest(c, &instr->dest, 0,
1933 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1934 break;
1935
1936 case nir_intrinsic_load_viewport_z_offset:
1937 ntq_store_dest(c, &instr->dest, 0,
1938 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1939 break;
1940
1941 case nir_intrinsic_load_alpha_ref_float:
1942 ntq_store_dest(c, &instr->dest, 0,
1943 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1944 break;
1945
1946 case nir_intrinsic_load_sample_mask_in:
1947 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1948 break;
1949
1950 case nir_intrinsic_load_helper_invocation:
1951 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1952 ntq_store_dest(c, &instr->dest, 0,
1953 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1954 vir_uniform_ui(c, ~0),
1955 vir_uniform_ui(c, 0))));
1956 break;
1957
1958 case nir_intrinsic_load_front_face:
1959 /* The register contains 0 (front) or 1 (back), and we need to
1960 * turn it into a NIR bool where true means front.
1961 */
1962 ntq_store_dest(c, &instr->dest, 0,
1963 vir_ADD(c,
1964 vir_uniform_ui(c, -1),
1965 vir_REVF(c)));
1966 break;
1967
1968 case nir_intrinsic_load_instance_id:
1969 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1970 break;
1971
1972 case nir_intrinsic_load_vertex_id:
1973 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1974 break;
1975
1976 case nir_intrinsic_load_tlb_color_v3d:
1977 vir_emit_tlb_color_read(c, instr);
1978 break;
1979
1980 case nir_intrinsic_load_input:
1981 ntq_emit_load_input(c, instr);
1982 break;
1983
1984 case nir_intrinsic_store_output:
1985 ntq_emit_store_output(c, instr);
1986 break;
1987
1988 case nir_intrinsic_image_deref_size:
1989 ntq_emit_image_size(c, instr);
1990 break;
1991
1992 case nir_intrinsic_discard:
1993 if (vir_in_nonuniform_control_flow(c)) {
1994 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1995 V3D_QPU_PF_PUSHZ);
1996 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1997 vir_uniform_ui(c, 0)),
1998 V3D_QPU_COND_IFA);
1999 } else {
2000 vir_SETMSF_dest(c, vir_nop_reg(),
2001 vir_uniform_ui(c, 0));
2002 }
2003 break;
2004
2005 case nir_intrinsic_discard_if: {
2006 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2007
2008 if (vir_in_nonuniform_control_flow(c)) {
2009 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2010 c->execute);
2011 if (cond == V3D_QPU_COND_IFA) {
2012 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2013 } else {
2014 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2015 cond = V3D_QPU_COND_IFA;
2016 }
2017 }
2018
2019 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2020 vir_uniform_ui(c, 0)), cond);
2021
2022 break;
2023 }
2024
2025 case nir_intrinsic_memory_barrier:
2026 case nir_intrinsic_memory_barrier_atomic_counter:
2027 case nir_intrinsic_memory_barrier_buffer:
2028 case nir_intrinsic_memory_barrier_image:
2029 case nir_intrinsic_memory_barrier_shared:
2030 case nir_intrinsic_group_memory_barrier:
2031 /* We don't do any instruction scheduling of these NIR
2032 * instructions between each other, so we just need to make
2033 * sure that the TMU operations before the barrier are flushed
2034 * before the ones after the barrier. That is currently
2035 * handled by having a THRSW in each of them and a LDTMU
2036 * series or a TMUWT after.
2037 */
2038 break;
2039
2040 case nir_intrinsic_barrier:
2041 /* Emit a TSY op to get all invocations in the workgroup
2042 * (actually supergroup) to block until the last invocation
2043 * reaches the TSY op.
2044 */
2045 if (c->devinfo->ver >= 42) {
2046 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2047 V3D_QPU_WADDR_SYNCB));
2048 } else {
2049 struct qinst *sync =
2050 vir_BARRIERID_dest(c,
2051 vir_reg(QFILE_MAGIC,
2052 V3D_QPU_WADDR_SYNCU));
2053 sync->uniform =
2054 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2055 0xffffff00 |
2056 V3D_TSY_WAIT_INC_CHECK);
2057
2058 }
2059
2060 /* The blocking of a TSY op only happens at the next thread
2061 * switch. No texturing may be outstanding at the time of a
2062 * TSY blocking operation.
2063 */
2064 vir_emit_thrsw(c);
2065 break;
2066
2067 case nir_intrinsic_load_num_work_groups:
2068 for (int i = 0; i < 3; i++) {
2069 ntq_store_dest(c, &instr->dest, i,
2070 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2071 i));
2072 }
2073 break;
2074
2075 case nir_intrinsic_load_local_invocation_index:
2076 ntq_store_dest(c, &instr->dest, 0,
2077 vir_SHR(c, c->cs_payload[1],
2078 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2079 break;
2080
2081 case nir_intrinsic_load_work_group_id:
2082 ntq_store_dest(c, &instr->dest, 0,
2083 vir_AND(c, c->cs_payload[0],
2084 vir_uniform_ui(c, 0xffff)));
2085 ntq_store_dest(c, &instr->dest, 1,
2086 vir_SHR(c, c->cs_payload[0],
2087 vir_uniform_ui(c, 16)));
2088 ntq_store_dest(c, &instr->dest, 2,
2089 vir_AND(c, c->cs_payload[1],
2090 vir_uniform_ui(c, 0xffff)));
2091 break;
2092
2093 case nir_intrinsic_load_subgroup_id:
2094 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2095 break;
2096
2097 default:
2098 fprintf(stderr, "Unknown intrinsic: ");
2099 nir_print_instr(&instr->instr, stderr);
2100 fprintf(stderr, "\n");
2101 break;
2102 }
2103 }
2104
2105 /* Clears (activates) the execute flags for any channels whose jump target
2106 * matches this block.
2107 *
2108 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2109 * enabling?
2110 *
2111 * XXX perf: For uniform control flow, we should be able to skip c->execute
2112 * handling entirely.
2113 */
2114 static void
2115 ntq_activate_execute_for_block(struct v3d_compile *c)
2116 {
2117 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2118 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2119 V3D_QPU_PF_PUSHZ);
2120
2121 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2122 }
2123
2124 static void
2125 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2126 {
2127 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2128 bool empty_else_block =
2129 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2130 exec_list_is_empty(&nir_else_block->instr_list));
2131
2132 struct qblock *then_block = vir_new_block(c);
2133 struct qblock *after_block = vir_new_block(c);
2134 struct qblock *else_block;
2135 if (empty_else_block)
2136 else_block = after_block;
2137 else
2138 else_block = vir_new_block(c);
2139
2140 /* Set up the flags for the IF condition (taking the THEN branch). */
2141 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2142
2143 /* Jump to ELSE. */
2144 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2145 V3D_QPU_BRANCH_COND_ALLNA :
2146 V3D_QPU_BRANCH_COND_ALLA);
2147 vir_link_blocks(c->cur_block, else_block);
2148 vir_link_blocks(c->cur_block, then_block);
2149
2150 /* Process the THEN block. */
2151 vir_set_emit_block(c, then_block);
2152 ntq_emit_cf_list(c, &if_stmt->then_list);
2153
2154 if (!empty_else_block) {
2155 /* At the end of the THEN block, jump to ENDIF */
2156 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2157 vir_link_blocks(c->cur_block, after_block);
2158
2159 /* Emit the else block. */
2160 vir_set_emit_block(c, else_block);
2161 ntq_emit_cf_list(c, &if_stmt->else_list);
2162 }
2163
2164 vir_link_blocks(c->cur_block, after_block);
2165
2166 vir_set_emit_block(c, after_block);
2167 }
2168
2169 static void
2170 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2171 {
2172 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2173 bool empty_else_block =
2174 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2175 exec_list_is_empty(&nir_else_block->instr_list));
2176
2177 struct qblock *then_block = vir_new_block(c);
2178 struct qblock *after_block = vir_new_block(c);
2179 struct qblock *else_block;
2180 if (empty_else_block)
2181 else_block = after_block;
2182 else
2183 else_block = vir_new_block(c);
2184
2185 bool was_uniform_control_flow = false;
2186 if (!vir_in_nonuniform_control_flow(c)) {
2187 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2188 was_uniform_control_flow = true;
2189 }
2190
2191 /* Set up the flags for the IF condition (taking the THEN branch). */
2192 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2193
2194 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2195 * was previously active (execute Z) for updating the exec flags.
2196 */
2197 if (was_uniform_control_flow) {
2198 cond = v3d_qpu_cond_invert(cond);
2199 } else {
2200 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2201 if (cond == V3D_QPU_COND_IFA) {
2202 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2203 } else {
2204 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2205 cond = V3D_QPU_COND_IFA;
2206 }
2207 }
2208
2209 vir_MOV_cond(c, cond,
2210 c->execute,
2211 vir_uniform_ui(c, else_block->index));
2212
2213 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2214 * through.
2215 */
2216 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2217 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2218 vir_link_blocks(c->cur_block, else_block);
2219 vir_link_blocks(c->cur_block, then_block);
2220
2221 /* Process the THEN block. */
2222 vir_set_emit_block(c, then_block);
2223 ntq_emit_cf_list(c, &if_stmt->then_list);
2224
2225 if (!empty_else_block) {
2226 /* Handle the end of the THEN block. First, all currently
2227 * active channels update their execute flags to point to
2228 * ENDIF
2229 */
2230 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2231 V3D_QPU_PF_PUSHZ);
2232 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2233 vir_uniform_ui(c, after_block->index));
2234
2235 /* If everything points at ENDIF, then jump there immediately. */
2236 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2237 c->execute,
2238 vir_uniform_ui(c, after_block->index)),
2239 V3D_QPU_PF_PUSHZ);
2240 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2241 vir_link_blocks(c->cur_block, after_block);
2242 vir_link_blocks(c->cur_block, else_block);
2243
2244 vir_set_emit_block(c, else_block);
2245 ntq_activate_execute_for_block(c);
2246 ntq_emit_cf_list(c, &if_stmt->else_list);
2247 }
2248
2249 vir_link_blocks(c->cur_block, after_block);
2250
2251 vir_set_emit_block(c, after_block);
2252 if (was_uniform_control_flow)
2253 c->execute = c->undef;
2254 else
2255 ntq_activate_execute_for_block(c);
2256 }
2257
2258 static void
2259 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2260 {
2261 bool was_in_control_flow = c->in_control_flow;
2262 c->in_control_flow = true;
2263 if (!vir_in_nonuniform_control_flow(c) &&
2264 nir_src_is_dynamically_uniform(nif->condition)) {
2265 ntq_emit_uniform_if(c, nif);
2266 } else {
2267 ntq_emit_nonuniform_if(c, nif);
2268 }
2269 c->in_control_flow = was_in_control_flow;
2270 }
2271
2272 static void
2273 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2274 {
2275 switch (jump->type) {
2276 case nir_jump_break:
2277 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2278 V3D_QPU_PF_PUSHZ);
2279 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2280 vir_uniform_ui(c, c->loop_break_block->index));
2281 break;
2282
2283 case nir_jump_continue:
2284 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2285 V3D_QPU_PF_PUSHZ);
2286 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2287 vir_uniform_ui(c, c->loop_cont_block->index));
2288 break;
2289
2290 case nir_jump_return:
2291 unreachable("All returns shouold be lowered\n");
2292 }
2293 }
2294
2295 static void
2296 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2297 {
2298 switch (instr->type) {
2299 case nir_instr_type_deref:
2300 /* ignored, will be walked by the intrinsic using it. */
2301 break;
2302
2303 case nir_instr_type_alu:
2304 ntq_emit_alu(c, nir_instr_as_alu(instr));
2305 break;
2306
2307 case nir_instr_type_intrinsic:
2308 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2309 break;
2310
2311 case nir_instr_type_load_const:
2312 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2313 break;
2314
2315 case nir_instr_type_ssa_undef:
2316 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2317 break;
2318
2319 case nir_instr_type_tex:
2320 ntq_emit_tex(c, nir_instr_as_tex(instr));
2321 break;
2322
2323 case nir_instr_type_jump:
2324 ntq_emit_jump(c, nir_instr_as_jump(instr));
2325 break;
2326
2327 default:
2328 fprintf(stderr, "Unknown NIR instr type: ");
2329 nir_print_instr(instr, stderr);
2330 fprintf(stderr, "\n");
2331 abort();
2332 }
2333 }
2334
2335 static void
2336 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2337 {
2338 nir_foreach_instr(instr, block) {
2339 ntq_emit_instr(c, instr);
2340 }
2341 }
2342
2343 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2344
2345 static void
2346 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2347 {
2348 bool was_in_control_flow = c->in_control_flow;
2349 c->in_control_flow = true;
2350
2351 bool was_uniform_control_flow = false;
2352 if (!vir_in_nonuniform_control_flow(c)) {
2353 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2354 was_uniform_control_flow = true;
2355 }
2356
2357 struct qblock *save_loop_cont_block = c->loop_cont_block;
2358 struct qblock *save_loop_break_block = c->loop_break_block;
2359
2360 c->loop_cont_block = vir_new_block(c);
2361 c->loop_break_block = vir_new_block(c);
2362
2363 vir_link_blocks(c->cur_block, c->loop_cont_block);
2364 vir_set_emit_block(c, c->loop_cont_block);
2365 ntq_activate_execute_for_block(c);
2366
2367 ntq_emit_cf_list(c, &loop->body);
2368
2369 /* Re-enable any previous continues now, so our ANYA check below
2370 * works.
2371 *
2372 * XXX: Use the .ORZ flags update, instead.
2373 */
2374 vir_set_pf(vir_XOR_dest(c,
2375 vir_nop_reg(),
2376 c->execute,
2377 vir_uniform_ui(c, c->loop_cont_block->index)),
2378 V3D_QPU_PF_PUSHZ);
2379 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2380
2381 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2382
2383 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2384 /* Pixels that were not dispatched or have been discarded should not
2385 * contribute to looping again.
2386 */
2387 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2388 vir_link_blocks(c->cur_block, c->loop_cont_block);
2389 vir_link_blocks(c->cur_block, c->loop_break_block);
2390
2391 vir_set_emit_block(c, c->loop_break_block);
2392 if (was_uniform_control_flow)
2393 c->execute = c->undef;
2394 else
2395 ntq_activate_execute_for_block(c);
2396
2397 c->loop_break_block = save_loop_break_block;
2398 c->loop_cont_block = save_loop_cont_block;
2399
2400 c->loops++;
2401
2402 c->in_control_flow = was_in_control_flow;
2403 }
2404
2405 static void
2406 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2407 {
2408 fprintf(stderr, "FUNCTIONS not handled.\n");
2409 abort();
2410 }
2411
2412 static void
2413 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2414 {
2415 foreach_list_typed(nir_cf_node, node, node, list) {
2416 switch (node->type) {
2417 case nir_cf_node_block:
2418 ntq_emit_block(c, nir_cf_node_as_block(node));
2419 break;
2420
2421 case nir_cf_node_if:
2422 ntq_emit_if(c, nir_cf_node_as_if(node));
2423 break;
2424
2425 case nir_cf_node_loop:
2426 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2427 break;
2428
2429 case nir_cf_node_function:
2430 ntq_emit_function(c, nir_cf_node_as_function(node));
2431 break;
2432
2433 default:
2434 fprintf(stderr, "Unknown NIR node type\n");
2435 abort();
2436 }
2437 }
2438 }
2439
2440 static void
2441 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2442 {
2443 ntq_setup_registers(c, &impl->registers);
2444 ntq_emit_cf_list(c, &impl->body);
2445 }
2446
2447 static void
2448 nir_to_vir(struct v3d_compile *c)
2449 {
2450 switch (c->s->info.stage) {
2451 case MESA_SHADER_FRAGMENT:
2452 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2453 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2454 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2455
2456 /* V3D 4.x can disable implicit point coordinate varyings if
2457 * they are not used.
2458 */
2459 if (c->fs_key->is_points &&
2460 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2461 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2462 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2463 c->uses_implicit_point_line_varyings = true;
2464 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2465 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2466 c->uses_implicit_point_line_varyings = true;
2467 }
2468 break;
2469 case MESA_SHADER_COMPUTE:
2470 /* Set up the TSO for barriers, assuming we do some. */
2471 if (c->devinfo->ver < 42) {
2472 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2473 V3D_QPU_WADDR_SYNC));
2474 }
2475
2476 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2477 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2478
2479 /* Set up the division between gl_LocalInvocationIndex and
2480 * wg_in_mem in the payload reg.
2481 */
2482 int wg_size = (c->s->info.cs.local_size[0] *
2483 c->s->info.cs.local_size[1] *
2484 c->s->info.cs.local_size[2]);
2485 c->local_invocation_index_bits =
2486 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2487 assert(c->local_invocation_index_bits <= 8);
2488
2489 if (c->s->info.cs.shared_size) {
2490 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2491 vir_uniform_ui(c, 16));
2492 if (c->s->info.cs.local_size[0] != 1 ||
2493 c->s->info.cs.local_size[1] != 1 ||
2494 c->s->info.cs.local_size[2] != 1) {
2495 int wg_bits = (16 -
2496 c->local_invocation_index_bits);
2497 int wg_mask = (1 << wg_bits) - 1;
2498 wg_in_mem = vir_AND(c, wg_in_mem,
2499 vir_uniform_ui(c, wg_mask));
2500 }
2501 struct qreg shared_per_wg =
2502 vir_uniform_ui(c, c->s->info.cs.shared_size);
2503
2504 c->cs_shared_offset =
2505 vir_ADD(c,
2506 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2507 vir_UMUL(c, wg_in_mem, shared_per_wg));
2508 }
2509 break;
2510 default:
2511 break;
2512 }
2513
2514 if (c->s->scratch_size) {
2515 v3d_setup_spill_base(c);
2516 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2517 }
2518
2519 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2520 ntq_setup_fs_inputs(c);
2521 else
2522 ntq_setup_vpm_inputs(c);
2523
2524 ntq_setup_outputs(c);
2525
2526 /* Find the main function and emit the body. */
2527 nir_foreach_function(function, c->s) {
2528 assert(strcmp(function->name, "main") == 0);
2529 assert(function->impl);
2530 ntq_emit_impl(c, function->impl);
2531 }
2532 }
2533
2534 const nir_shader_compiler_options v3d_nir_options = {
2535 .lower_all_io_to_temps = true,
2536 .lower_extract_byte = true,
2537 .lower_extract_word = true,
2538 .lower_bitfield_insert_to_shifts = true,
2539 .lower_bitfield_extract_to_shifts = true,
2540 .lower_bitfield_reverse = true,
2541 .lower_bit_count = true,
2542 .lower_cs_local_id_from_index = true,
2543 .lower_ffract = true,
2544 .lower_fmod = true,
2545 .lower_pack_unorm_2x16 = true,
2546 .lower_pack_snorm_2x16 = true,
2547 .lower_pack_unorm_4x8 = true,
2548 .lower_pack_snorm_4x8 = true,
2549 .lower_unpack_unorm_4x8 = true,
2550 .lower_unpack_snorm_4x8 = true,
2551 .lower_pack_half_2x16 = true,
2552 .lower_unpack_half_2x16 = true,
2553 .lower_fdiv = true,
2554 .lower_find_lsb = true,
2555 .lower_ffma = true,
2556 .lower_flrp32 = true,
2557 .lower_fpow = true,
2558 .lower_fsat = true,
2559 .lower_fsqrt = true,
2560 .lower_ifind_msb = true,
2561 .lower_isign = true,
2562 .lower_ldexp = true,
2563 .lower_mul_high = true,
2564 .lower_wpos_pntc = true,
2565 .lower_rotate = true,
2566 };
2567
2568 /**
2569 * When demoting a shader down to single-threaded, removes the THRSW
2570 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2571 * program end).
2572 */
2573 static void
2574 vir_remove_thrsw(struct v3d_compile *c)
2575 {
2576 vir_for_each_block(block, c) {
2577 vir_for_each_inst_safe(inst, block) {
2578 if (inst->qpu.sig.thrsw)
2579 vir_remove_instruction(c, inst);
2580 }
2581 }
2582
2583 c->last_thrsw = NULL;
2584 }
2585
2586 void
2587 vir_emit_last_thrsw(struct v3d_compile *c)
2588 {
2589 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2590 * switching, so disable threads if we didn't do any TMU ops (each of
2591 * which would have emitted a THRSW).
2592 */
2593 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2594 c->threads = 1;
2595 if (c->last_thrsw)
2596 vir_remove_thrsw(c);
2597 return;
2598 }
2599
2600 /* If we're threaded and the last THRSW was in conditional code, then
2601 * we need to emit another one so that we can flag it as the last
2602 * thrsw.
2603 */
2604 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2605 assert(c->devinfo->ver >= 41);
2606 vir_emit_thrsw(c);
2607 }
2608
2609 /* If we're threaded, then we need to mark the last THRSW instruction
2610 * so we can emit a pair of them at QPU emit time.
2611 *
2612 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2613 * post-last-THRSW state, so we can skip this.
2614 */
2615 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2616 assert(c->devinfo->ver >= 41);
2617 vir_emit_thrsw(c);
2618 }
2619
2620 if (c->last_thrsw)
2621 c->last_thrsw->is_last_thrsw = true;
2622 }
2623
2624 /* There's a flag in the shader for "center W is needed for reasons other than
2625 * non-centroid varyings", so we just walk the program after VIR optimization
2626 * to see if it's used. It should be harmless to set even if we only use
2627 * center W for varyings.
2628 */
2629 static void
2630 vir_check_payload_w(struct v3d_compile *c)
2631 {
2632 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2633 return;
2634
2635 vir_for_each_inst_inorder(inst, c) {
2636 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2637 if (inst->src[i].file == QFILE_REG &&
2638 inst->src[i].index == 0) {
2639 c->uses_center_w = true;
2640 return;
2641 }
2642 }
2643 }
2644
2645 }
2646
2647 void
2648 v3d_nir_to_vir(struct v3d_compile *c)
2649 {
2650 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2651 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2652 fprintf(stderr, "%s prog %d/%d NIR:\n",
2653 vir_get_stage_name(c),
2654 c->program_id, c->variant_id);
2655 nir_print_shader(c->s, stderr);
2656 }
2657
2658 nir_to_vir(c);
2659
2660 /* Emit the last THRSW before STVPM and TLB writes. */
2661 vir_emit_last_thrsw(c);
2662
2663 switch (c->s->info.stage) {
2664 case MESA_SHADER_FRAGMENT:
2665 emit_frag_end(c);
2666 break;
2667 case MESA_SHADER_VERTEX:
2668 emit_vert_end(c);
2669 break;
2670 case MESA_SHADER_COMPUTE:
2671 break;
2672 default:
2673 unreachable("bad stage");
2674 }
2675
2676 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2677 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2678 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2679 vir_get_stage_name(c),
2680 c->program_id, c->variant_id);
2681 vir_dump(c);
2682 fprintf(stderr, "\n");
2683 }
2684
2685 vir_optimize(c);
2686
2687 vir_check_payload_w(c);
2688
2689 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2690 * We used that on that platform to pipeline TMU writes and reduce the
2691 * number of thread switches, as well as try (mostly successfully) to
2692 * reduce maximum register pressure to allow more threads. We should
2693 * do something of that sort for V3D -- either instruction scheduling
2694 * here, or delay the the THRSW and LDTMUs from our texture
2695 * instructions until the results are needed.
2696 */
2697
2698 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2699 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2700 fprintf(stderr, "%s prog %d/%d VIR:\n",
2701 vir_get_stage_name(c),
2702 c->program_id, c->variant_id);
2703 vir_dump(c);
2704 fprintf(stderr, "\n");
2705 }
2706
2707 /* Attempt to allocate registers for the temporaries. If we fail,
2708 * reduce thread count and try again.
2709 */
2710 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2711 struct qpu_reg *temp_registers;
2712 while (true) {
2713 bool spilled;
2714 temp_registers = v3d_register_allocate(c, &spilled);
2715 if (spilled)
2716 continue;
2717
2718 if (temp_registers)
2719 break;
2720
2721 if (c->threads == min_threads) {
2722 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2723 c->threads);
2724 vir_dump(c);
2725 c->failed = true;
2726 return;
2727 }
2728
2729 c->threads /= 2;
2730
2731 if (c->threads == 1)
2732 vir_remove_thrsw(c);
2733 }
2734
2735 if (c->spills &&
2736 (V3D_DEBUG & (V3D_DEBUG_VIR |
2737 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2738 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2739 vir_get_stage_name(c),
2740 c->program_id, c->variant_id);
2741 vir_dump(c);
2742 fprintf(stderr, "\n");
2743 }
2744
2745 v3d_vir_to_qpu(c, temp_registers);
2746 }