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nir: add lower_all_io_to_temps flag
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
78 {
79 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
80 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
81 }
82
83 static struct qreg
84 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
85 {
86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
87 uint32_t offset = nir_intrinsic_base(intr);
88 struct v3d_ubo_range *range = NULL;
89 unsigned i;
90
91 for (i = 0; i < c->num_ubo_ranges; i++) {
92 range = &c->ubo_ranges[i];
93 if (offset >= range->src_offset &&
94 offset < range->src_offset + range->size) {
95 break;
96 }
97 }
98 /* The driver-location-based offset always has to be within a declared
99 * uniform range.
100 */
101 assert(i != c->num_ubo_ranges);
102 if (!c->ubo_range_used[i]) {
103 c->ubo_range_used[i] = true;
104 range->dst_offset = c->next_ubo_dst_offset;
105 c->next_ubo_dst_offset += range->size;
106 }
107
108 offset -= range->src_offset;
109
110 if (range->dst_offset + offset != 0) {
111 indirect_offset = vir_ADD(c, indirect_offset,
112 vir_uniform_ui(c, range->dst_offset +
113 offset));
114 }
115
116 /* Adjust for where we stored the TGSI register base. */
117 vir_ADD_dest(c,
118 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
119 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
120 indirect_offset);
121
122 vir_emit_thrsw(c);
123 return vir_LDTMU(c);
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 /**
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
138 *
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
140 * the new result.
141 *
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
149 */
150 void
151 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
152 struct qreg result)
153 {
154 struct qinst *last_inst = NULL;
155 if (!list_empty(&c->cur_block->instructions))
156 last_inst = (struct qinst *)c->cur_block->instructions.prev;
157
158 assert(result.file == QFILE_UNIF ||
159 (result.file == QFILE_TEMP &&
160 last_inst && last_inst == c->defs[result.index]));
161
162 if (dest->is_ssa) {
163 assert(chan < dest->ssa.num_components);
164
165 struct qreg *qregs;
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, &dest->ssa);
168
169 if (entry)
170 qregs = entry->data;
171 else
172 qregs = ntq_init_ssa_def(c, &dest->ssa);
173
174 qregs[chan] = result;
175 } else {
176 nir_register *reg = dest->reg.reg;
177 assert(dest->reg.base_offset == 0);
178 assert(reg->num_array_elems == 0);
179 struct hash_entry *entry =
180 _mesa_hash_table_search(c->def_ht, reg);
181 struct qreg *qregs = entry->data;
182
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
185 */
186 if (result.file == QFILE_UNIF) {
187 result = vir_MOV(c, result);
188 last_inst = c->defs[result.index];
189 }
190
191 /* We know they're both temps, so just rewrite index. */
192 c->defs[last_inst->dst.index] = NULL;
193 last_inst->dst.index = qregs[chan].index;
194
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
197 */
198 if (c->execute.file != QFILE_NULL) {
199 last_inst->dst.index = qregs[chan].index;
200
201 /* Set the flags to the current exec mask. To insert
202 * the flags push, we temporarily remove our SSA
203 * instruction.
204 */
205 list_del(&last_inst->link);
206 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
207 list_addtail(&last_inst->link,
208 &c->cur_block->instructions);
209
210 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
211 last_inst->cond_is_exec_mask = true;
212 }
213 }
214 }
215
216 struct qreg
217 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
218 {
219 struct hash_entry *entry;
220 if (src.is_ssa) {
221 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
222 assert(i < src.ssa->num_components);
223 } else {
224 nir_register *reg = src.reg.reg;
225 entry = _mesa_hash_table_search(c->def_ht, reg);
226 assert(reg->num_array_elems == 0);
227 assert(src.reg.base_offset == 0);
228 assert(i < reg->num_components);
229 }
230
231 struct qreg *qregs = entry->data;
232 return qregs[i];
233 }
234
235 static struct qreg
236 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
237 unsigned src)
238 {
239 assert(util_is_power_of_two(instr->dest.write_mask));
240 unsigned chan = ffs(instr->dest.write_mask) - 1;
241 struct qreg r = ntq_get_src(c, instr->src[src].src,
242 instr->src[src].swizzle[chan]);
243
244 assert(!instr->src[src].abs);
245 assert(!instr->src[src].negate);
246
247 return r;
248 };
249
250 static inline struct qreg
251 vir_SAT(struct v3d_compile *c, struct qreg val)
252 {
253 return vir_FMAX(c,
254 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
255 vir_uniform_f(c, 0.0));
256 }
257
258 static struct qreg
259 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
260 {
261 vir_MULTOP(c, src0, src1);
262 return vir_UMUL24(c, src0, src1);
263 }
264
265 static struct qreg
266 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
267 {
268 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
269 }
270
271 static void
272 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
273 {
274 unsigned unit = instr->texture_index;
275 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
276 int dest_size = nir_tex_instr_dest_size(instr);
277
278 struct qreg lod = c->undef;
279 if (lod_index != -1)
280 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
281
282 for (int i = 0; i < dest_size; i++) {
283 assert(i < 3);
284 enum quniform_contents contents;
285
286 if (instr->is_array && i == dest_size - 1)
287 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
288 else
289 contents = QUNIFORM_TEXTURE_WIDTH + i;
290
291 struct qreg size = vir_uniform(c, contents, unit);
292
293 switch (instr->sampler_dim) {
294 case GLSL_SAMPLER_DIM_1D:
295 case GLSL_SAMPLER_DIM_2D:
296 case GLSL_SAMPLER_DIM_3D:
297 case GLSL_SAMPLER_DIM_CUBE:
298 /* Don't minify the array size. */
299 if (!(instr->is_array && i == dest_size - 1)) {
300 size = ntq_minify(c, size, lod);
301 }
302 break;
303
304 case GLSL_SAMPLER_DIM_RECT:
305 /* There's no LOD field for rects */
306 break;
307
308 default:
309 unreachable("Bad sampler type");
310 }
311
312 ntq_store_dest(c, &instr->dest, i, size);
313 }
314 }
315
316 static void
317 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
318 {
319 unsigned unit = instr->texture_index;
320
321 /* Since each texture sampling op requires uploading uniforms to
322 * reference the texture, there's no HW support for texture size and
323 * you just upload uniforms containing the size.
324 */
325 switch (instr->op) {
326 case nir_texop_query_levels:
327 ntq_store_dest(c, &instr->dest, 0,
328 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
329 return;
330 case nir_texop_txs:
331 ntq_emit_txs(c, instr);
332 return;
333 default:
334 break;
335 }
336
337 if (c->devinfo->ver >= 40)
338 v3d40_vir_emit_tex(c, instr);
339 else
340 v3d33_vir_emit_tex(c, instr);
341 }
342
343 static struct qreg
344 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
345 {
346 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
347 if (is_cos)
348 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
349
350 struct qreg periods = vir_FROUND(c, input);
351 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
352 vir_FSUB(c, input, periods));
353 return vir_XOR(c, sin_output, vir_SHL(c,
354 vir_FTOIN(c, periods),
355 vir_uniform_ui(c, -1)));
356 }
357
358 static struct qreg
359 ntq_fsign(struct v3d_compile *c, struct qreg src)
360 {
361 struct qreg t = vir_get_temp(c);
362
363 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
364 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
365 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
366 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
367 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
368 return vir_MOV(c, t);
369 }
370
371 static struct qreg
372 ntq_isign(struct v3d_compile *c, struct qreg src)
373 {
374 struct qreg t = vir_get_temp(c);
375
376 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
377 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
378 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
379 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
380 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
381 return vir_MOV(c, t);
382 }
383
384 static void
385 emit_fragcoord_input(struct v3d_compile *c, int attr)
386 {
387 c->inputs[attr * 4 + 0] = vir_FXCD(c);
388 c->inputs[attr * 4 + 1] = vir_FYCD(c);
389 c->inputs[attr * 4 + 2] = c->payload_z;
390 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
391 c->payload_w);
392 }
393
394 static struct qreg
395 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
396 uint8_t swizzle)
397 {
398 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
399 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
400
401 struct qreg vary;
402 if (c->devinfo->ver >= 41) {
403 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
404 c->undef, c->undef);
405 ldvary->qpu.sig.ldvary = true;
406 vary = vir_emit_def(c, ldvary);
407 } else {
408 vir_NOP(c)->qpu.sig.ldvary = true;
409 vary = r3;
410 }
411
412 /* For gl_PointCoord input or distance along a line, we'll be called
413 * with no nir_variable, and we don't count toward VPM size so we
414 * don't track an input slot.
415 */
416 if (!var) {
417 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
418 }
419
420 int i = c->num_inputs++;
421 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
422 swizzle);
423
424 switch (var->data.interpolation) {
425 case INTERP_MODE_NONE:
426 /* If a gl_FrontColor or gl_BackColor input has no interp
427 * qualifier, then if we're using glShadeModel(GL_FLAT) it
428 * needs to be flat shaded.
429 */
430 switch (var->data.location) {
431 case VARYING_SLOT_COL0:
432 case VARYING_SLOT_COL1:
433 case VARYING_SLOT_BFC0:
434 case VARYING_SLOT_BFC1:
435 if (c->fs_key->shade_model_flat) {
436 BITSET_SET(c->flat_shade_flags, i);
437 vir_MOV_dest(c, c->undef, vary);
438 return vir_MOV(c, r5);
439 } else {
440 return vir_FADD(c, vir_FMUL(c, vary,
441 c->payload_w), r5);
442 }
443 default:
444 break;
445 }
446 /* FALLTHROUGH */
447 case INTERP_MODE_SMOOTH:
448 if (var->data.centroid) {
449 return vir_FADD(c, vir_FMUL(c, vary,
450 c->payload_w_centroid), r5);
451 } else {
452 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
453 }
454 case INTERP_MODE_NOPERSPECTIVE:
455 /* C appears after the mov from the varying.
456 XXX: improve ldvary setup.
457 */
458 return vir_FADD(c, vir_MOV(c, vary), r5);
459 case INTERP_MODE_FLAT:
460 BITSET_SET(c->flat_shade_flags, i);
461 vir_MOV_dest(c, c->undef, vary);
462 return vir_MOV(c, r5);
463 default:
464 unreachable("Bad interp mode");
465 }
466 }
467
468 static void
469 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
470 {
471 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
472 int chan = var->data.location_frac + i;
473 c->inputs[attr * 4 + chan] =
474 emit_fragment_varying(c, var, chan);
475 }
476 }
477
478 static void
479 add_output(struct v3d_compile *c,
480 uint32_t decl_offset,
481 uint8_t slot,
482 uint8_t swizzle)
483 {
484 uint32_t old_array_size = c->outputs_array_size;
485 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
486 decl_offset + 1);
487
488 if (old_array_size != c->outputs_array_size) {
489 c->output_slots = reralloc(c,
490 c->output_slots,
491 struct v3d_varying_slot,
492 c->outputs_array_size);
493 }
494
495 c->output_slots[decl_offset] =
496 v3d_slot_from_slot_and_component(slot, swizzle);
497 }
498
499 static void
500 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
501 {
502 unsigned array_id = c->num_ubo_ranges++;
503 if (array_id >= c->ubo_ranges_array_size) {
504 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
505 array_id + 1);
506 c->ubo_ranges = reralloc(c, c->ubo_ranges,
507 struct v3d_ubo_range,
508 c->ubo_ranges_array_size);
509 c->ubo_range_used = reralloc(c, c->ubo_range_used,
510 bool,
511 c->ubo_ranges_array_size);
512 }
513
514 c->ubo_ranges[array_id].dst_offset = 0;
515 c->ubo_ranges[array_id].src_offset = start;
516 c->ubo_ranges[array_id].size = size;
517 c->ubo_range_used[array_id] = false;
518 }
519
520 /**
521 * If compare_instr is a valid comparison instruction, emits the
522 * compare_instr's comparison and returns the sel_instr's return value based
523 * on the compare_instr's result.
524 */
525 static bool
526 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
527 nir_alu_instr *compare_instr,
528 nir_alu_instr *sel_instr)
529 {
530 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
531 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
532 bool cond_invert = false;
533
534 switch (compare_instr->op) {
535 case nir_op_feq:
536 case nir_op_seq:
537 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
538 break;
539 case nir_op_ieq:
540 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
541 break;
542
543 case nir_op_fne:
544 case nir_op_sne:
545 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
546 cond_invert = true;
547 break;
548 case nir_op_ine:
549 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
550 cond_invert = true;
551 break;
552
553 case nir_op_fge:
554 case nir_op_sge:
555 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
556 break;
557 case nir_op_ige:
558 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
559 cond_invert = true;
560 break;
561 case nir_op_uge:
562 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
563 cond_invert = true;
564 break;
565
566 case nir_op_slt:
567 case nir_op_flt:
568 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
569 break;
570 case nir_op_ilt:
571 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
572 break;
573 case nir_op_ult:
574 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
575 break;
576
577 default:
578 return false;
579 }
580
581 enum v3d_qpu_cond cond = (cond_invert ?
582 V3D_QPU_COND_IFNA :
583 V3D_QPU_COND_IFA);
584
585 switch (sel_instr->op) {
586 case nir_op_seq:
587 case nir_op_sne:
588 case nir_op_sge:
589 case nir_op_slt:
590 *dest = vir_SEL(c, cond,
591 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
592 break;
593
594 case nir_op_bcsel:
595 *dest = vir_SEL(c, cond,
596 ntq_get_alu_src(c, sel_instr, 1),
597 ntq_get_alu_src(c, sel_instr, 2));
598 break;
599
600 default:
601 *dest = vir_SEL(c, cond,
602 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
603 break;
604 }
605
606 /* Make the temporary for nir_store_dest(). */
607 *dest = vir_MOV(c, *dest);
608
609 return true;
610 }
611
612 /**
613 * Attempts to fold a comparison generating a boolean result into the
614 * condition code for selecting between two values, instead of comparing the
615 * boolean result against 0 to generate the condition code.
616 */
617 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
618 struct qreg *src)
619 {
620 if (!instr->src[0].src.is_ssa)
621 goto out;
622 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
623 goto out;
624 nir_alu_instr *compare =
625 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
626 if (!compare)
627 goto out;
628
629 struct qreg dest;
630 if (ntq_emit_comparison(c, &dest, compare, instr))
631 return dest;
632
633 out:
634 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
635 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
636 }
637
638
639 static void
640 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
641 {
642 /* This should always be lowered to ALU operations for V3D. */
643 assert(!instr->dest.saturate);
644
645 /* Vectors are special in that they have non-scalarized writemasks,
646 * and just take the first swizzle channel for each argument in order
647 * into each writemask channel.
648 */
649 if (instr->op == nir_op_vec2 ||
650 instr->op == nir_op_vec3 ||
651 instr->op == nir_op_vec4) {
652 struct qreg srcs[4];
653 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
654 srcs[i] = ntq_get_src(c, instr->src[i].src,
655 instr->src[i].swizzle[0]);
656 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
657 ntq_store_dest(c, &instr->dest.dest, i,
658 vir_MOV(c, srcs[i]));
659 return;
660 }
661
662 /* General case: We can just grab the one used channel per src. */
663 struct qreg src[nir_op_infos[instr->op].num_inputs];
664 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
665 src[i] = ntq_get_alu_src(c, instr, i);
666 }
667
668 struct qreg result;
669
670 switch (instr->op) {
671 case nir_op_fmov:
672 case nir_op_imov:
673 result = vir_MOV(c, src[0]);
674 break;
675
676 case nir_op_fneg:
677 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
678 break;
679 case nir_op_ineg:
680 result = vir_NEG(c, src[0]);
681 break;
682
683 case nir_op_fmul:
684 result = vir_FMUL(c, src[0], src[1]);
685 break;
686 case nir_op_fadd:
687 result = vir_FADD(c, src[0], src[1]);
688 break;
689 case nir_op_fsub:
690 result = vir_FSUB(c, src[0], src[1]);
691 break;
692 case nir_op_fmin:
693 result = vir_FMIN(c, src[0], src[1]);
694 break;
695 case nir_op_fmax:
696 result = vir_FMAX(c, src[0], src[1]);
697 break;
698
699 case nir_op_f2i32:
700 result = vir_FTOIZ(c, src[0]);
701 break;
702 case nir_op_f2u32:
703 result = vir_FTOUZ(c, src[0]);
704 break;
705 case nir_op_i2f32:
706 result = vir_ITOF(c, src[0]);
707 break;
708 case nir_op_u2f32:
709 result = vir_UTOF(c, src[0]);
710 break;
711 case nir_op_b2f:
712 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
713 break;
714 case nir_op_b2i:
715 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
716 break;
717 case nir_op_i2b:
718 case nir_op_f2b:
719 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
720 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
721 vir_uniform_ui(c, ~0),
722 vir_uniform_ui(c, 0)));
723 break;
724
725 case nir_op_iadd:
726 result = vir_ADD(c, src[0], src[1]);
727 break;
728 case nir_op_ushr:
729 result = vir_SHR(c, src[0], src[1]);
730 break;
731 case nir_op_isub:
732 result = vir_SUB(c, src[0], src[1]);
733 break;
734 case nir_op_ishr:
735 result = vir_ASR(c, src[0], src[1]);
736 break;
737 case nir_op_ishl:
738 result = vir_SHL(c, src[0], src[1]);
739 break;
740 case nir_op_imin:
741 result = vir_MIN(c, src[0], src[1]);
742 break;
743 case nir_op_umin:
744 result = vir_UMIN(c, src[0], src[1]);
745 break;
746 case nir_op_imax:
747 result = vir_MAX(c, src[0], src[1]);
748 break;
749 case nir_op_umax:
750 result = vir_UMAX(c, src[0], src[1]);
751 break;
752 case nir_op_iand:
753 result = vir_AND(c, src[0], src[1]);
754 break;
755 case nir_op_ior:
756 result = vir_OR(c, src[0], src[1]);
757 break;
758 case nir_op_ixor:
759 result = vir_XOR(c, src[0], src[1]);
760 break;
761 case nir_op_inot:
762 result = vir_NOT(c, src[0]);
763 break;
764
765 case nir_op_imul:
766 result = ntq_umul(c, src[0], src[1]);
767 break;
768
769 case nir_op_seq:
770 case nir_op_sne:
771 case nir_op_sge:
772 case nir_op_slt:
773 case nir_op_feq:
774 case nir_op_fne:
775 case nir_op_fge:
776 case nir_op_flt:
777 case nir_op_ieq:
778 case nir_op_ine:
779 case nir_op_ige:
780 case nir_op_uge:
781 case nir_op_ilt:
782 case nir_op_ult:
783 if (!ntq_emit_comparison(c, &result, instr, instr)) {
784 fprintf(stderr, "Bad comparison instruction\n");
785 }
786 break;
787
788 case nir_op_bcsel:
789 result = ntq_emit_bcsel(c, instr, src);
790 break;
791 case nir_op_fcsel:
792 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
793 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
794 src[1], src[2]));
795 break;
796
797 case nir_op_frcp:
798 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
799 break;
800 case nir_op_frsq:
801 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
802 break;
803 case nir_op_fexp2:
804 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
805 break;
806 case nir_op_flog2:
807 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
808 break;
809
810 case nir_op_fceil:
811 result = vir_FCEIL(c, src[0]);
812 break;
813 case nir_op_ffloor:
814 result = vir_FFLOOR(c, src[0]);
815 break;
816 case nir_op_fround_even:
817 result = vir_FROUND(c, src[0]);
818 break;
819 case nir_op_ftrunc:
820 result = vir_FTRUNC(c, src[0]);
821 break;
822 case nir_op_ffract:
823 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
824 break;
825
826 case nir_op_fsin:
827 result = ntq_fsincos(c, src[0], false);
828 break;
829 case nir_op_fcos:
830 result = ntq_fsincos(c, src[0], true);
831 break;
832
833 case nir_op_fsign:
834 result = ntq_fsign(c, src[0]);
835 break;
836 case nir_op_isign:
837 result = ntq_isign(c, src[0]);
838 break;
839
840 case nir_op_fabs: {
841 result = vir_FMOV(c, src[0]);
842 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
843 break;
844 }
845
846 case nir_op_iabs:
847 result = vir_MAX(c, src[0],
848 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
849 break;
850
851 case nir_op_fddx:
852 case nir_op_fddx_coarse:
853 case nir_op_fddx_fine:
854 result = vir_FDX(c, src[0]);
855 break;
856
857 case nir_op_fddy:
858 case nir_op_fddy_coarse:
859 case nir_op_fddy_fine:
860 result = vir_FDY(c, src[0]);
861 break;
862
863 default:
864 fprintf(stderr, "unknown NIR ALU inst: ");
865 nir_print_instr(&instr->instr, stderr);
866 fprintf(stderr, "\n");
867 abort();
868 }
869
870 /* We have a scalar result, so the instruction should only have a
871 * single channel written to.
872 */
873 assert(util_is_power_of_two(instr->dest.write_mask));
874 ntq_store_dest(c, &instr->dest.dest,
875 ffs(instr->dest.write_mask) - 1, result);
876 }
877
878 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
879 * specifier. They come from a register that's preloaded with 0xffffffff
880 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
881 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
882 */
883 #define TLB_TYPE_F16_COLOR (3 << 6)
884 #define TLB_TYPE_I32_COLOR (1 << 6)
885 #define TLB_TYPE_F32_COLOR (0 << 6)
886 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
887 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
888 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
889 #define TLB_F16_SWAP_HI_LO (1 << 1)
890 #define TLB_VEC_SIZE_4_F16 (1 << 0)
891 #define TLB_VEC_SIZE_2_F16 (0 << 0)
892 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
893
894 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
895 * flag is set.
896 */
897 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
898 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
899 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
900
901 /* Stencil is a single 32-bit write. */
902 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
903
904 static void
905 emit_frag_end(struct v3d_compile *c)
906 {
907 /* XXX
908 if (c->output_sample_mask_index != -1) {
909 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
910 }
911 */
912
913 bool has_any_tlb_color_write = false;
914 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
915 if (c->output_color_var[rt])
916 has_any_tlb_color_write = true;
917 }
918
919 if (c->output_position_index != -1) {
920 struct qinst *inst = vir_MOV_dest(c,
921 vir_reg(QFILE_TLBU, 0),
922 c->outputs[c->output_position_index]);
923
924 inst->src[vir_get_implicit_uniform_src(inst)] =
925 vir_uniform_ui(c,
926 TLB_TYPE_DEPTH |
927 TLB_DEPTH_TYPE_PER_PIXEL |
928 0xffffff00);
929 } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
930 /* Emit passthrough Z if it needed to be delayed until shader
931 * end due to potential discards.
932 *
933 * Since (single-threaded) fragment shaders always need a TLB
934 * write, emit passthrouh Z if we didn't have any color
935 * buffers and flag us as potentially discarding, so that we
936 * can use Z as the TLB write.
937 */
938 c->s->info.fs.uses_discard = true;
939
940 struct qinst *inst = vir_MOV_dest(c,
941 vir_reg(QFILE_TLBU, 0),
942 vir_reg(QFILE_NULL, 0));
943
944 inst->src[vir_get_implicit_uniform_src(inst)] =
945 vir_uniform_ui(c,
946 TLB_TYPE_DEPTH |
947 TLB_DEPTH_TYPE_INVARIANT |
948 0xffffff00);
949 }
950
951 /* XXX: Performance improvement: Merge Z write and color writes TLB
952 * uniform setup
953 */
954
955 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
956 if (!c->output_color_var[rt])
957 continue;
958
959 nir_variable *var = c->output_color_var[rt];
960 struct qreg *color = &c->outputs[var->data.driver_location * 4];
961 int num_components = glsl_get_vector_elements(var->type);
962 uint32_t conf = 0xffffff00;
963 struct qinst *inst;
964
965 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
966 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
967
968 assert(num_components != 0);
969 switch (glsl_get_base_type(var->type)) {
970 case GLSL_TYPE_UINT:
971 case GLSL_TYPE_INT:
972 /* The F32 vs I32 distinction was dropped in 4.2. */
973 if (c->devinfo->ver < 42)
974 conf |= TLB_TYPE_I32_COLOR;
975 else
976 conf |= TLB_TYPE_F32_COLOR;
977 conf |= ((num_components - 1) <<
978 TLB_VEC_SIZE_MINUS_1_SHIFT);
979
980 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
981 inst->src[vir_get_implicit_uniform_src(inst)] =
982 vir_uniform_ui(c, conf);
983
984 for (int i = 1; i < num_components; i++) {
985 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
986 color[i]);
987 }
988 break;
989
990 default: {
991 struct qreg r = color[0];
992 struct qreg g = color[1];
993 struct qreg b = color[2];
994 struct qreg a = color[3];
995
996 if (c->fs_key->f32_color_rb) {
997 conf |= TLB_TYPE_F32_COLOR;
998 conf |= ((num_components - 1) <<
999 TLB_VEC_SIZE_MINUS_1_SHIFT);
1000 } else {
1001 conf |= TLB_TYPE_F16_COLOR;
1002 conf |= TLB_F16_SWAP_HI_LO;
1003 if (num_components >= 3)
1004 conf |= TLB_VEC_SIZE_4_F16;
1005 else
1006 conf |= TLB_VEC_SIZE_2_F16;
1007 }
1008
1009 if (c->fs_key->swap_color_rb & (1 << rt)) {
1010 r = color[2];
1011 b = color[0];
1012 }
1013
1014 if (c->fs_key->f32_color_rb & (1 << rt)) {
1015 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1016 inst->src[vir_get_implicit_uniform_src(inst)] =
1017 vir_uniform_ui(c, conf);
1018
1019 for (int i = 1; i < num_components; i++) {
1020 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1021 color[i]);
1022 }
1023 } else {
1024 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1025 if (conf != ~0) {
1026 inst->dst.file = QFILE_TLBU;
1027 inst->src[vir_get_implicit_uniform_src(inst)] =
1028 vir_uniform_ui(c, conf);
1029 }
1030
1031 if (num_components >= 3)
1032 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1033 }
1034 break;
1035 }
1036 }
1037 }
1038 }
1039
1040 static void
1041 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1042 {
1043 if (c->devinfo->ver >= 40) {
1044 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1045 *vpm_index = *vpm_index + 1;
1046 } else {
1047 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1048 }
1049
1050 c->num_vpm_writes++;
1051 }
1052
1053 static void
1054 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1055 uint32_t *vpm_index)
1056 {
1057 for (int i = 0; i < 2; i++) {
1058 struct qreg coord = c->outputs[c->output_position_index + i];
1059 coord = vir_FMUL(c, coord,
1060 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1061 0));
1062 coord = vir_FMUL(c, coord, rcp_w);
1063 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1064 }
1065
1066 }
1067
1068 static void
1069 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1070 {
1071 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1072 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1073
1074 struct qreg z = c->outputs[c->output_position_index + 2];
1075 z = vir_FMUL(c, z, zscale);
1076 z = vir_FMUL(c, z, rcp_w);
1077 z = vir_FADD(c, z, zoffset);
1078 vir_VPM_WRITE(c, z, vpm_index);
1079 }
1080
1081 static void
1082 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1083 {
1084 vir_VPM_WRITE(c, rcp_w, vpm_index);
1085 }
1086
1087 static void
1088 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1089 {
1090 struct qreg point_size;
1091
1092 if (c->output_point_size_index != -1)
1093 point_size = c->outputs[c->output_point_size_index];
1094 else
1095 point_size = vir_uniform_f(c, 1.0);
1096
1097 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1098 * BCM21553).
1099 */
1100 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1101
1102 vir_VPM_WRITE(c, point_size, vpm_index);
1103 }
1104
1105 static void
1106 emit_vpm_write_setup(struct v3d_compile *c)
1107 {
1108 if (c->devinfo->ver >= 40)
1109 return;
1110
1111 v3d33_vir_vpm_write_setup(c);
1112 }
1113
1114 static void
1115 emit_vert_end(struct v3d_compile *c)
1116 {
1117 uint32_t vpm_index = 0;
1118 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1119 c->outputs[c->output_position_index + 3]);
1120
1121 emit_vpm_write_setup(c);
1122
1123 if (c->vs_key->is_coord) {
1124 for (int i = 0; i < 4; i++)
1125 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1126 &vpm_index);
1127 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1128 if (c->vs_key->per_vertex_point_size) {
1129 emit_point_size_write(c, &vpm_index);
1130 /* emit_rcp_wc_write(c, rcp_w); */
1131 }
1132 /* XXX: Z-only rendering */
1133 if (0)
1134 emit_zs_write(c, rcp_w, &vpm_index);
1135 } else {
1136 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1137 emit_zs_write(c, rcp_w, &vpm_index);
1138 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1139 if (c->vs_key->per_vertex_point_size)
1140 emit_point_size_write(c, &vpm_index);
1141 }
1142
1143 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1144 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1145 int j;
1146
1147 for (j = 0; j < c->num_outputs; j++) {
1148 struct v3d_varying_slot output = c->output_slots[j];
1149
1150 if (!memcmp(&input, &output, sizeof(input))) {
1151 vir_VPM_WRITE(c, c->outputs[j],
1152 &vpm_index);
1153 break;
1154 }
1155 }
1156 /* Emit padding if we didn't find a declared VS output for
1157 * this FS input.
1158 */
1159 if (j == c->num_outputs)
1160 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1161 &vpm_index);
1162 }
1163
1164 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1165 */
1166 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1167 vir_VPMWT(c);
1168 }
1169
1170 void
1171 v3d_optimize_nir(struct nir_shader *s)
1172 {
1173 bool progress;
1174
1175 do {
1176 progress = false;
1177
1178 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1179 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1180 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1181 NIR_PASS(progress, s, nir_copy_prop);
1182 NIR_PASS(progress, s, nir_opt_remove_phis);
1183 NIR_PASS(progress, s, nir_opt_dce);
1184 NIR_PASS(progress, s, nir_opt_dead_cf);
1185 NIR_PASS(progress, s, nir_opt_cse);
1186 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1187 NIR_PASS(progress, s, nir_opt_algebraic);
1188 NIR_PASS(progress, s, nir_opt_constant_folding);
1189 NIR_PASS(progress, s, nir_opt_undef);
1190 } while (progress);
1191 }
1192
1193 static int
1194 driver_location_compare(const void *in_a, const void *in_b)
1195 {
1196 const nir_variable *const *a = in_a;
1197 const nir_variable *const *b = in_b;
1198
1199 return (*a)->data.driver_location - (*b)->data.driver_location;
1200 }
1201
1202 static struct qreg
1203 ntq_emit_vpm_read(struct v3d_compile *c,
1204 uint32_t *num_components_queued,
1205 uint32_t *remaining,
1206 uint32_t vpm_index)
1207 {
1208 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1209
1210 if (c->devinfo->ver >= 40 ) {
1211 return vir_LDVPMV_IN(c,
1212 vir_uniform_ui(c,
1213 (*num_components_queued)++));
1214 }
1215
1216 if (*num_components_queued != 0) {
1217 (*num_components_queued)--;
1218 c->num_inputs++;
1219 return vir_MOV(c, vpm);
1220 }
1221
1222 uint32_t num_components = MIN2(*remaining, 32);
1223
1224 v3d33_vir_vpm_read_setup(c, num_components);
1225
1226 *num_components_queued = num_components - 1;
1227 *remaining -= num_components;
1228 c->num_inputs++;
1229
1230 return vir_MOV(c, vpm);
1231 }
1232
1233 static void
1234 ntq_setup_inputs(struct v3d_compile *c)
1235 {
1236 unsigned num_entries = 0;
1237 unsigned num_components = 0;
1238 nir_foreach_variable(var, &c->s->inputs) {
1239 num_entries++;
1240 num_components += glsl_get_components(var->type);
1241 }
1242
1243 nir_variable *vars[num_entries];
1244
1245 unsigned i = 0;
1246 nir_foreach_variable(var, &c->s->inputs)
1247 vars[i++] = var;
1248
1249 /* Sort the variables so that we emit the input setup in
1250 * driver_location order. This is required for VPM reads, whose data
1251 * is fetched into the VPM in driver_location (TGSI register index)
1252 * order.
1253 */
1254 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1255
1256 uint32_t vpm_components_queued = 0;
1257 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1258 bool uses_iid = c->s->info.system_values_read &
1259 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1260 bool uses_vid = c->s->info.system_values_read &
1261 (1ull << SYSTEM_VALUE_VERTEX_ID);
1262
1263 num_components += uses_iid;
1264 num_components += uses_vid;
1265
1266 if (uses_iid) {
1267 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1268 &num_components, ~0);
1269 }
1270
1271 if (uses_vid) {
1272 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1273 &num_components, ~0);
1274 }
1275 }
1276
1277 for (unsigned i = 0; i < num_entries; i++) {
1278 nir_variable *var = vars[i];
1279 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1280 unsigned loc = var->data.driver_location;
1281
1282 assert(array_len == 1);
1283 (void)array_len;
1284 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1285 (loc + 1) * 4);
1286
1287 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1288 if (var->data.location == VARYING_SLOT_POS) {
1289 emit_fragcoord_input(c, loc);
1290 } else if (var->data.location == VARYING_SLOT_PNTC ||
1291 (var->data.location >= VARYING_SLOT_VAR0 &&
1292 (c->fs_key->point_sprite_mask &
1293 (1 << (var->data.location -
1294 VARYING_SLOT_VAR0))))) {
1295 c->inputs[loc * 4 + 0] = c->point_x;
1296 c->inputs[loc * 4 + 1] = c->point_y;
1297 } else {
1298 emit_fragment_input(c, loc, var);
1299 }
1300 } else {
1301 int var_components = glsl_get_components(var->type);
1302
1303 for (int i = 0; i < var_components; i++) {
1304 c->inputs[loc * 4 + i] =
1305 ntq_emit_vpm_read(c,
1306 &vpm_components_queued,
1307 &num_components,
1308 loc * 4 + i);
1309
1310 }
1311 c->vattr_sizes[loc] = var_components;
1312 }
1313 }
1314
1315 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1316 if (c->devinfo->ver >= 40) {
1317 assert(vpm_components_queued == num_components);
1318 } else {
1319 assert(vpm_components_queued == 0);
1320 assert(num_components == 0);
1321 }
1322 }
1323 }
1324
1325 static void
1326 ntq_setup_outputs(struct v3d_compile *c)
1327 {
1328 nir_foreach_variable(var, &c->s->outputs) {
1329 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1330 unsigned loc = var->data.driver_location * 4;
1331
1332 assert(array_len == 1);
1333 (void)array_len;
1334
1335 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
1336 add_output(c, loc + var->data.location_frac + i,
1337 var->data.location,
1338 var->data.location_frac + i);
1339 }
1340
1341 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1342 switch (var->data.location) {
1343 case FRAG_RESULT_COLOR:
1344 c->output_color_var[0] = var;
1345 c->output_color_var[1] = var;
1346 c->output_color_var[2] = var;
1347 c->output_color_var[3] = var;
1348 break;
1349 case FRAG_RESULT_DATA0:
1350 case FRAG_RESULT_DATA1:
1351 case FRAG_RESULT_DATA2:
1352 case FRAG_RESULT_DATA3:
1353 c->output_color_var[var->data.location -
1354 FRAG_RESULT_DATA0] = var;
1355 break;
1356 case FRAG_RESULT_DEPTH:
1357 c->output_position_index = loc;
1358 break;
1359 case FRAG_RESULT_SAMPLE_MASK:
1360 c->output_sample_mask_index = loc;
1361 break;
1362 }
1363 } else {
1364 switch (var->data.location) {
1365 case VARYING_SLOT_POS:
1366 c->output_position_index = loc;
1367 break;
1368 case VARYING_SLOT_PSIZ:
1369 c->output_point_size_index = loc;
1370 break;
1371 }
1372 }
1373 }
1374 }
1375
1376 static void
1377 ntq_setup_uniforms(struct v3d_compile *c)
1378 {
1379 nir_foreach_variable(var, &c->s->uniforms) {
1380 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1381 false);
1382 unsigned vec4_size = 4 * sizeof(float);
1383
1384 declare_uniform_range(c, var->data.driver_location * vec4_size,
1385 vec4_count * vec4_size);
1386
1387 }
1388 }
1389
1390 /**
1391 * Sets up the mapping from nir_register to struct qreg *.
1392 *
1393 * Each nir_register gets a struct qreg per 32-bit component being stored.
1394 */
1395 static void
1396 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1397 {
1398 foreach_list_typed(nir_register, nir_reg, node, list) {
1399 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1400 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1401 array_len *
1402 nir_reg->num_components);
1403
1404 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1405
1406 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1407 qregs[i] = vir_get_temp(c);
1408 }
1409 }
1410
1411 static void
1412 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1413 {
1414 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1415 for (int i = 0; i < instr->def.num_components; i++)
1416 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1417
1418 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1419 }
1420
1421 static void
1422 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1423 {
1424 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1425
1426 /* VIR needs there to be *some* value, so pick 0 (same as for
1427 * ntq_setup_registers().
1428 */
1429 for (int i = 0; i < instr->def.num_components; i++)
1430 qregs[i] = vir_uniform_ui(c, 0);
1431 }
1432
1433 static void
1434 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1435 {
1436 nir_const_value *const_offset;
1437 unsigned offset;
1438
1439 switch (instr->intrinsic) {
1440 case nir_intrinsic_load_uniform:
1441 assert(instr->num_components == 1);
1442 const_offset = nir_src_as_const_value(instr->src[0]);
1443 if (const_offset) {
1444 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1445 assert(offset % 4 == 0);
1446 /* We need dwords */
1447 offset = offset / 4;
1448 ntq_store_dest(c, &instr->dest, 0,
1449 vir_uniform(c, QUNIFORM_UNIFORM,
1450 offset));
1451 } else {
1452 ntq_store_dest(c, &instr->dest, 0,
1453 indirect_uniform_load(c, instr));
1454 }
1455 break;
1456
1457 case nir_intrinsic_load_ubo:
1458 for (int i = 0; i < instr->num_components; i++) {
1459 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1460
1461 /* Adjust for where we stored the TGSI register base. */
1462 vir_ADD_dest(c,
1463 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1464 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1465 vir_ADD(c,
1466 ntq_get_src(c, instr->src[1], 0),
1467 vir_uniform_ui(c, i * 4)));
1468
1469 vir_emit_thrsw(c);
1470
1471 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1472 }
1473 break;
1474
1475 const_offset = nir_src_as_const_value(instr->src[0]);
1476 if (const_offset) {
1477 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1478 assert(offset % 4 == 0);
1479 /* We need dwords */
1480 offset = offset / 4;
1481 ntq_store_dest(c, &instr->dest, 0,
1482 vir_uniform(c, QUNIFORM_UNIFORM,
1483 offset));
1484 } else {
1485 ntq_store_dest(c, &instr->dest, 0,
1486 indirect_uniform_load(c, instr));
1487 }
1488 break;
1489
1490 case nir_intrinsic_load_user_clip_plane:
1491 for (int i = 0; i < instr->num_components; i++) {
1492 ntq_store_dest(c, &instr->dest, i,
1493 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1494 nir_intrinsic_ucp_id(instr) *
1495 4 + i));
1496 }
1497 break;
1498
1499 case nir_intrinsic_load_alpha_ref_float:
1500 ntq_store_dest(c, &instr->dest, 0,
1501 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1502 break;
1503
1504 case nir_intrinsic_load_sample_mask_in:
1505 ntq_store_dest(c, &instr->dest, 0,
1506 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1507 break;
1508
1509 case nir_intrinsic_load_front_face:
1510 /* The register contains 0 (front) or 1 (back), and we need to
1511 * turn it into a NIR bool where true means front.
1512 */
1513 ntq_store_dest(c, &instr->dest, 0,
1514 vir_ADD(c,
1515 vir_uniform_ui(c, -1),
1516 vir_REVF(c)));
1517 break;
1518
1519 case nir_intrinsic_load_instance_id:
1520 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1521 break;
1522
1523 case nir_intrinsic_load_vertex_id:
1524 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1525 break;
1526
1527 case nir_intrinsic_load_input:
1528 const_offset = nir_src_as_const_value(instr->src[0]);
1529 assert(const_offset && "v3d doesn't support indirect inputs");
1530 for (int i = 0; i < instr->num_components; i++) {
1531 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1532 int comp = nir_intrinsic_component(instr) + i;
1533 ntq_store_dest(c, &instr->dest, i,
1534 vir_MOV(c, c->inputs[offset * 4 + comp]));
1535 }
1536 break;
1537
1538 case nir_intrinsic_store_output:
1539 const_offset = nir_src_as_const_value(instr->src[1]);
1540 assert(const_offset && "v3d doesn't support indirect outputs");
1541 offset = ((nir_intrinsic_base(instr) +
1542 const_offset->u32[0]) * 4 +
1543 nir_intrinsic_component(instr));
1544
1545 for (int i = 0; i < instr->num_components; i++) {
1546 c->outputs[offset + i] =
1547 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1548 }
1549 c->num_outputs = MAX2(c->num_outputs,
1550 offset + instr->num_components);
1551 break;
1552
1553 case nir_intrinsic_discard:
1554 if (c->execute.file != QFILE_NULL) {
1555 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1556 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1557 vir_uniform_ui(c, 0)),
1558 V3D_QPU_COND_IFA);
1559 } else {
1560 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1561 vir_uniform_ui(c, 0));
1562 }
1563 break;
1564
1565 case nir_intrinsic_discard_if: {
1566 /* true (~0) if we're discarding */
1567 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1568
1569 if (c->execute.file != QFILE_NULL) {
1570 /* execute == 0 means the channel is active. Invert
1571 * the condition so that we can use zero as "executing
1572 * and discarding."
1573 */
1574 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1575 V3D_QPU_PF_PUSHZ);
1576 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1577 vir_uniform_ui(c, 0)),
1578 V3D_QPU_COND_IFA);
1579 } else {
1580 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1581 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1582 vir_uniform_ui(c, 0)),
1583 V3D_QPU_COND_IFNA);
1584 }
1585
1586 break;
1587 }
1588
1589 default:
1590 fprintf(stderr, "Unknown intrinsic: ");
1591 nir_print_instr(&instr->instr, stderr);
1592 fprintf(stderr, "\n");
1593 break;
1594 }
1595 }
1596
1597 /* Clears (activates) the execute flags for any channels whose jump target
1598 * matches this block.
1599 */
1600 static void
1601 ntq_activate_execute_for_block(struct v3d_compile *c)
1602 {
1603 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1604 V3D_QPU_PF_PUSHZ);
1605
1606 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1607 }
1608
1609 static void
1610 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1611 {
1612 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1613 bool empty_else_block =
1614 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1615 exec_list_is_empty(&nir_else_block->instr_list));
1616
1617 struct qblock *then_block = vir_new_block(c);
1618 struct qblock *after_block = vir_new_block(c);
1619 struct qblock *else_block;
1620 if (empty_else_block)
1621 else_block = after_block;
1622 else
1623 else_block = vir_new_block(c);
1624
1625 bool was_top_level = false;
1626 if (c->execute.file == QFILE_NULL) {
1627 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1628 was_top_level = true;
1629 }
1630
1631 /* Set A for executing (execute == 0) and jumping (if->condition ==
1632 * 0) channels, and then update execute flags for those to point to
1633 * the ELSE block.
1634 */
1635 vir_PF(c, vir_OR(c,
1636 c->execute,
1637 ntq_get_src(c, if_stmt->condition, 0)),
1638 V3D_QPU_PF_PUSHZ);
1639 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1640 c->execute,
1641 vir_uniform_ui(c, else_block->index));
1642
1643 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1644 * through.
1645 */
1646 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1647 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1648 vir_link_blocks(c->cur_block, else_block);
1649 vir_link_blocks(c->cur_block, then_block);
1650
1651 /* Process the THEN block. */
1652 vir_set_emit_block(c, then_block);
1653 ntq_emit_cf_list(c, &if_stmt->then_list);
1654
1655 if (!empty_else_block) {
1656 /* Handle the end of the THEN block. First, all currently
1657 * active channels update their execute flags to point to
1658 * ENDIF
1659 */
1660 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1661 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1662 vir_uniform_ui(c, after_block->index));
1663
1664 /* If everything points at ENDIF, then jump there immediately. */
1665 vir_PF(c, vir_XOR(c, c->execute,
1666 vir_uniform_ui(c, after_block->index)),
1667 V3D_QPU_PF_PUSHZ);
1668 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1669 vir_link_blocks(c->cur_block, after_block);
1670 vir_link_blocks(c->cur_block, else_block);
1671
1672 vir_set_emit_block(c, else_block);
1673 ntq_activate_execute_for_block(c);
1674 ntq_emit_cf_list(c, &if_stmt->else_list);
1675 }
1676
1677 vir_link_blocks(c->cur_block, after_block);
1678
1679 vir_set_emit_block(c, after_block);
1680 if (was_top_level)
1681 c->execute = c->undef;
1682 else
1683 ntq_activate_execute_for_block(c);
1684 }
1685
1686 static void
1687 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1688 {
1689 switch (jump->type) {
1690 case nir_jump_break:
1691 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1692 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1693 vir_uniform_ui(c, c->loop_break_block->index));
1694 break;
1695
1696 case nir_jump_continue:
1697 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1698 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1699 vir_uniform_ui(c, c->loop_cont_block->index));
1700 break;
1701
1702 case nir_jump_return:
1703 unreachable("All returns shouold be lowered\n");
1704 }
1705 }
1706
1707 static void
1708 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1709 {
1710 switch (instr->type) {
1711 case nir_instr_type_alu:
1712 ntq_emit_alu(c, nir_instr_as_alu(instr));
1713 break;
1714
1715 case nir_instr_type_intrinsic:
1716 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1717 break;
1718
1719 case nir_instr_type_load_const:
1720 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1721 break;
1722
1723 case nir_instr_type_ssa_undef:
1724 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1725 break;
1726
1727 case nir_instr_type_tex:
1728 ntq_emit_tex(c, nir_instr_as_tex(instr));
1729 break;
1730
1731 case nir_instr_type_jump:
1732 ntq_emit_jump(c, nir_instr_as_jump(instr));
1733 break;
1734
1735 default:
1736 fprintf(stderr, "Unknown NIR instr type: ");
1737 nir_print_instr(instr, stderr);
1738 fprintf(stderr, "\n");
1739 abort();
1740 }
1741 }
1742
1743 static void
1744 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1745 {
1746 nir_foreach_instr(instr, block) {
1747 ntq_emit_instr(c, instr);
1748 }
1749 }
1750
1751 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1752
1753 static void
1754 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1755 {
1756 bool was_top_level = false;
1757 if (c->execute.file == QFILE_NULL) {
1758 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1759 was_top_level = true;
1760 }
1761
1762 struct qblock *save_loop_cont_block = c->loop_cont_block;
1763 struct qblock *save_loop_break_block = c->loop_break_block;
1764
1765 c->loop_cont_block = vir_new_block(c);
1766 c->loop_break_block = vir_new_block(c);
1767
1768 vir_link_blocks(c->cur_block, c->loop_cont_block);
1769 vir_set_emit_block(c, c->loop_cont_block);
1770 ntq_activate_execute_for_block(c);
1771
1772 ntq_emit_cf_list(c, &loop->body);
1773
1774 /* Re-enable any previous continues now, so our ANYA check below
1775 * works.
1776 *
1777 * XXX: Use the .ORZ flags update, instead.
1778 */
1779 vir_PF(c, vir_XOR(c,
1780 c->execute,
1781 vir_uniform_ui(c, c->loop_cont_block->index)),
1782 V3D_QPU_PF_PUSHZ);
1783 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1784
1785 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1786
1787 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1788 /* Pixels that were not dispatched or have been discarded should not
1789 * contribute to looping again.
1790 */
1791 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1792 vir_link_blocks(c->cur_block, c->loop_cont_block);
1793 vir_link_blocks(c->cur_block, c->loop_break_block);
1794
1795 vir_set_emit_block(c, c->loop_break_block);
1796 if (was_top_level)
1797 c->execute = c->undef;
1798 else
1799 ntq_activate_execute_for_block(c);
1800
1801 c->loop_break_block = save_loop_break_block;
1802 c->loop_cont_block = save_loop_cont_block;
1803 }
1804
1805 static void
1806 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1807 {
1808 fprintf(stderr, "FUNCTIONS not handled.\n");
1809 abort();
1810 }
1811
1812 static void
1813 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1814 {
1815 foreach_list_typed(nir_cf_node, node, node, list) {
1816 switch (node->type) {
1817 case nir_cf_node_block:
1818 ntq_emit_block(c, nir_cf_node_as_block(node));
1819 break;
1820
1821 case nir_cf_node_if:
1822 ntq_emit_if(c, nir_cf_node_as_if(node));
1823 break;
1824
1825 case nir_cf_node_loop:
1826 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1827 break;
1828
1829 case nir_cf_node_function:
1830 ntq_emit_function(c, nir_cf_node_as_function(node));
1831 break;
1832
1833 default:
1834 fprintf(stderr, "Unknown NIR node type\n");
1835 abort();
1836 }
1837 }
1838 }
1839
1840 static void
1841 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1842 {
1843 ntq_setup_registers(c, &impl->registers);
1844 ntq_emit_cf_list(c, &impl->body);
1845 }
1846
1847 static void
1848 nir_to_vir(struct v3d_compile *c)
1849 {
1850 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1851 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1852 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1853 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1854
1855 if (c->fs_key->is_points) {
1856 c->point_x = emit_fragment_varying(c, NULL, 0);
1857 c->point_y = emit_fragment_varying(c, NULL, 0);
1858 } else if (c->fs_key->is_lines) {
1859 c->line_x = emit_fragment_varying(c, NULL, 0);
1860 }
1861 }
1862
1863 ntq_setup_inputs(c);
1864 ntq_setup_outputs(c);
1865 ntq_setup_uniforms(c);
1866 ntq_setup_registers(c, &c->s->registers);
1867
1868 /* Find the main function and emit the body. */
1869 nir_foreach_function(function, c->s) {
1870 assert(strcmp(function->name, "main") == 0);
1871 assert(function->impl);
1872 ntq_emit_impl(c, function->impl);
1873 }
1874 }
1875
1876 const nir_shader_compiler_options v3d_nir_options = {
1877 .lower_all_io_to_temps = true,
1878 .lower_extract_byte = true,
1879 .lower_extract_word = true,
1880 .lower_bitfield_insert = true,
1881 .lower_bitfield_extract = true,
1882 .lower_pack_unorm_2x16 = true,
1883 .lower_pack_snorm_2x16 = true,
1884 .lower_pack_unorm_4x8 = true,
1885 .lower_pack_snorm_4x8 = true,
1886 .lower_unpack_unorm_4x8 = true,
1887 .lower_unpack_snorm_4x8 = true,
1888 .lower_fdiv = true,
1889 .lower_ffma = true,
1890 .lower_flrp32 = true,
1891 .lower_fpow = true,
1892 .lower_fsat = true,
1893 .lower_fsqrt = true,
1894 .native_integers = true,
1895 };
1896
1897
1898 #if 0
1899 static int
1900 count_nir_instrs(nir_shader *nir)
1901 {
1902 int count = 0;
1903 nir_foreach_function(function, nir) {
1904 if (!function->impl)
1905 continue;
1906 nir_foreach_block(block, function->impl) {
1907 nir_foreach_instr(instr, block)
1908 count++;
1909 }
1910 }
1911 return count;
1912 }
1913 #endif
1914
1915 /**
1916 * When demoting a shader down to single-threaded, removes the THRSW
1917 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1918 * program end).
1919 */
1920 static void
1921 vir_remove_thrsw(struct v3d_compile *c)
1922 {
1923 vir_for_each_block(block, c) {
1924 vir_for_each_inst_safe(inst, block) {
1925 if (inst->qpu.sig.thrsw)
1926 vir_remove_instruction(c, inst);
1927 }
1928 }
1929
1930 c->last_thrsw = NULL;
1931 }
1932
1933 static void
1934 vir_emit_last_thrsw(struct v3d_compile *c)
1935 {
1936 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1937 * switching, so disable threads if we didn't do any TMU ops (each of
1938 * which would have emitted a THRSW).
1939 */
1940 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
1941 c->threads = 1;
1942 if (c->last_thrsw)
1943 vir_remove_thrsw(c);
1944 return;
1945 }
1946
1947 /* If we're threaded and the last THRSW was in conditional code, then
1948 * we need to emit another one so that we can flag it as the last
1949 * thrsw.
1950 */
1951 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
1952 assert(c->devinfo->ver >= 41);
1953 vir_emit_thrsw(c);
1954 }
1955
1956 /* If we're threaded, then we need to mark the last THRSW instruction
1957 * so we can emit a pair of them at QPU emit time.
1958 *
1959 * For V3D 4.x, we can spawn the non-fragment shaders already in the
1960 * post-last-THRSW state, so we can skip this.
1961 */
1962 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
1963 assert(c->devinfo->ver >= 41);
1964 vir_emit_thrsw(c);
1965 }
1966
1967 if (c->last_thrsw)
1968 c->last_thrsw->is_last_thrsw = true;
1969 }
1970
1971 void
1972 v3d_nir_to_vir(struct v3d_compile *c)
1973 {
1974 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1975 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
1976 fprintf(stderr, "%s prog %d/%d NIR:\n",
1977 vir_get_stage_name(c),
1978 c->program_id, c->variant_id);
1979 nir_print_shader(c->s, stderr);
1980 }
1981
1982 nir_to_vir(c);
1983
1984 /* Emit the last THRSW before STVPM and TLB writes. */
1985 vir_emit_last_thrsw(c);
1986
1987 switch (c->s->info.stage) {
1988 case MESA_SHADER_FRAGMENT:
1989 emit_frag_end(c);
1990 break;
1991 case MESA_SHADER_VERTEX:
1992 emit_vert_end(c);
1993 break;
1994 default:
1995 unreachable("bad stage");
1996 }
1997
1998 if (V3D_DEBUG & (V3D_DEBUG_VIR |
1999 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2000 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2001 vir_get_stage_name(c),
2002 c->program_id, c->variant_id);
2003 vir_dump(c);
2004 fprintf(stderr, "\n");
2005 }
2006
2007 vir_optimize(c);
2008 vir_lower_uniforms(c);
2009
2010 /* XXX: vir_schedule_instructions(c); */
2011
2012 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2013 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2014 fprintf(stderr, "%s prog %d/%d VIR:\n",
2015 vir_get_stage_name(c),
2016 c->program_id, c->variant_id);
2017 vir_dump(c);
2018 fprintf(stderr, "\n");
2019 }
2020
2021 /* Compute the live ranges so we can figure out interference. */
2022 vir_calculate_live_intervals(c);
2023
2024 /* Attempt to allocate registers for the temporaries. If we fail,
2025 * reduce thread count and try again.
2026 */
2027 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2028 struct qpu_reg *temp_registers;
2029 while (true) {
2030 temp_registers = v3d_register_allocate(c);
2031
2032 if (temp_registers)
2033 break;
2034
2035 if (c->threads == min_threads) {
2036 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2037 c->threads);
2038 vir_dump(c);
2039 c->failed = true;
2040 return;
2041 }
2042
2043 c->threads /= 2;
2044
2045 if (c->threads == 1)
2046 vir_remove_thrsw(c);
2047 }
2048
2049 v3d_vir_to_qpu(c, temp_registers);
2050 }