2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
36 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
39 resize_qreg_array(struct v3d_compile
*c
,
44 if (*size
>= decl_size
)
47 uint32_t old_size
= *size
;
48 *size
= MAX2(*size
* 2, decl_size
);
49 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
51 fprintf(stderr
, "Malloc failure\n");
55 for (uint32_t i
= old_size
; i
< *size
; i
++)
56 (*regs
)[i
] = c
->undef
;
60 vir_emit_thrsw(struct v3d_compile
*c
)
65 /* Always thread switch after each texture operation for now.
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
71 c
->last_thrsw
= vir_NOP(c
);
72 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
73 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
77 indirect_uniform_load(struct v3d_compile
*c
, nir_intrinsic_instr
*intr
)
79 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
80 uint32_t offset
= nir_intrinsic_base(intr
);
81 struct v3d_ubo_range
*range
= NULL
;
84 for (i
= 0; i
< c
->num_ubo_ranges
; i
++) {
85 range
= &c
->ubo_ranges
[i
];
86 if (offset
>= range
->src_offset
&&
87 offset
< range
->src_offset
+ range
->size
) {
91 /* The driver-location-based offset always has to be within a declared
94 assert(i
!= c
->num_ubo_ranges
);
95 if (!c
->ubo_range_used
[i
]) {
96 c
->ubo_range_used
[i
] = true;
97 range
->dst_offset
= c
->next_ubo_dst_offset
;
98 c
->next_ubo_dst_offset
+= range
->size
;
101 offset
-= range
->src_offset
;
103 if (range
->dst_offset
+ offset
!= 0) {
104 indirect_offset
= vir_ADD(c
, indirect_offset
,
105 vir_uniform_ui(c
, range
->dst_offset
+
109 /* Adjust for where we stored the TGSI register base. */
111 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
112 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 0),
120 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
122 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
123 def
->num_components
);
124 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
129 * This function is responsible for getting VIR results into the associated
130 * storage for a NIR instruction.
132 * If it's a NIR SSA def, then we just set the associated hash table entry to
135 * If it's a NIR reg, then we need to update the existing qreg assigned to the
136 * NIR destination with the incoming value. To do that without introducing
137 * new MOVs, we require that the incoming qreg either be a uniform, or be
138 * SSA-defined by the previous VIR instruction in the block and rewritable by
139 * this function. That lets us sneak ahead and insert the SF flag beforehand
140 * (knowing that the previous instruction doesn't depend on flags) and rewrite
141 * its destination to be the NIR reg's destination
144 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
147 struct qinst
*last_inst
= NULL
;
148 if (!list_empty(&c
->cur_block
->instructions
))
149 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
151 assert(result
.file
== QFILE_UNIF
||
152 (result
.file
== QFILE_TEMP
&&
153 last_inst
&& last_inst
== c
->defs
[result
.index
]));
156 assert(chan
< dest
->ssa
.num_components
);
159 struct hash_entry
*entry
=
160 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
165 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
167 qregs
[chan
] = result
;
169 nir_register
*reg
= dest
->reg
.reg
;
170 assert(dest
->reg
.base_offset
== 0);
171 assert(reg
->num_array_elems
== 0);
172 struct hash_entry
*entry
=
173 _mesa_hash_table_search(c
->def_ht
, reg
);
174 struct qreg
*qregs
= entry
->data
;
176 /* Insert a MOV if the source wasn't an SSA def in the
177 * previous instruction.
179 if (result
.file
== QFILE_UNIF
) {
180 result
= vir_MOV(c
, result
);
181 last_inst
= c
->defs
[result
.index
];
184 /* We know they're both temps, so just rewrite index. */
185 c
->defs
[last_inst
->dst
.index
] = NULL
;
186 last_inst
->dst
.index
= qregs
[chan
].index
;
188 /* If we're in control flow, then make this update of the reg
189 * conditional on the execution mask.
191 if (c
->execute
.file
!= QFILE_NULL
) {
192 last_inst
->dst
.index
= qregs
[chan
].index
;
194 /* Set the flags to the current exec mask.
196 c
->cursor
= vir_before_inst(last_inst
);
197 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
198 c
->cursor
= vir_after_inst(last_inst
);
200 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
201 last_inst
->cond_is_exec_mask
= true;
207 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
209 struct hash_entry
*entry
;
211 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
212 assert(i
< src
.ssa
->num_components
);
214 nir_register
*reg
= src
.reg
.reg
;
215 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
216 assert(reg
->num_array_elems
== 0);
217 assert(src
.reg
.base_offset
== 0);
218 assert(i
< reg
->num_components
);
221 struct qreg
*qregs
= entry
->data
;
226 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
229 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
230 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
231 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
232 instr
->src
[src
].swizzle
[chan
]);
234 assert(!instr
->src
[src
].abs
);
235 assert(!instr
->src
[src
].negate
);
241 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
243 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
247 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
249 unsigned unit
= instr
->texture_index
;
250 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
251 int dest_size
= nir_tex_instr_dest_size(instr
);
253 struct qreg lod
= c
->undef
;
255 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
257 for (int i
= 0; i
< dest_size
; i
++) {
259 enum quniform_contents contents
;
261 if (instr
->is_array
&& i
== dest_size
- 1)
262 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
264 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
266 struct qreg size
= vir_uniform(c
, contents
, unit
);
268 switch (instr
->sampler_dim
) {
269 case GLSL_SAMPLER_DIM_1D
:
270 case GLSL_SAMPLER_DIM_2D
:
271 case GLSL_SAMPLER_DIM_3D
:
272 case GLSL_SAMPLER_DIM_CUBE
:
273 /* Don't minify the array size. */
274 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
275 size
= ntq_minify(c
, size
, lod
);
279 case GLSL_SAMPLER_DIM_RECT
:
280 /* There's no LOD field for rects */
284 unreachable("Bad sampler type");
287 ntq_store_dest(c
, &instr
->dest
, i
, size
);
292 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
294 unsigned unit
= instr
->texture_index
;
296 /* Since each texture sampling op requires uploading uniforms to
297 * reference the texture, there's no HW support for texture size and
298 * you just upload uniforms containing the size.
301 case nir_texop_query_levels
:
302 ntq_store_dest(c
, &instr
->dest
, 0,
303 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
306 ntq_emit_txs(c
, instr
);
312 if (c
->devinfo
->ver
>= 40)
313 v3d40_vir_emit_tex(c
, instr
);
315 v3d33_vir_emit_tex(c
, instr
);
319 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
321 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
323 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
325 struct qreg periods
= vir_FROUND(c
, input
);
326 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
327 return vir_XOR(c
, sin_output
, vir_SHL(c
,
328 vir_FTOIN(c
, periods
),
329 vir_uniform_ui(c
, -1)));
333 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
335 struct qreg t
= vir_get_temp(c
);
337 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
338 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHZ
);
339 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
340 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHN
);
341 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
342 return vir_MOV(c
, t
);
346 ntq_isign(struct v3d_compile
*c
, struct qreg src
)
348 struct qreg t
= vir_get_temp(c
);
350 vir_MOV_dest(c
, t
, vir_uniform_ui(c
, 0));
351 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHZ
);
352 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_ui(c
, 1));
353 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHN
);
354 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_ui(c
, -1));
355 return vir_MOV(c
, t
);
359 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
361 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
362 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
363 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
364 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
368 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
371 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
372 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
375 if (c
->devinfo
->ver
>= 41) {
376 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
378 ldvary
->qpu
.sig
.ldvary
= true;
379 vary
= vir_emit_def(c
, ldvary
);
381 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
385 /* For gl_PointCoord input or distance along a line, we'll be called
386 * with no nir_variable, and we don't count toward VPM size so we
387 * don't track an input slot.
390 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
393 int i
= c
->num_inputs
++;
394 c
->input_slots
[i
] = v3d_slot_from_slot_and_component(var
->data
.location
,
397 switch (var
->data
.interpolation
) {
398 case INTERP_MODE_NONE
:
399 /* If a gl_FrontColor or gl_BackColor input has no interp
400 * qualifier, then if we're using glShadeModel(GL_FLAT) it
401 * needs to be flat shaded.
403 switch (var
->data
.location
) {
404 case VARYING_SLOT_COL0
:
405 case VARYING_SLOT_COL1
:
406 case VARYING_SLOT_BFC0
:
407 case VARYING_SLOT_BFC1
:
408 if (c
->fs_key
->shade_model_flat
) {
409 BITSET_SET(c
->flat_shade_flags
, i
);
410 vir_MOV_dest(c
, c
->undef
, vary
);
411 return vir_MOV(c
, r5
);
413 return vir_FADD(c
, vir_FMUL(c
, vary
,
420 case INTERP_MODE_SMOOTH
:
421 if (var
->data
.centroid
) {
422 BITSET_SET(c
->centroid_flags
, i
);
423 return vir_FADD(c
, vir_FMUL(c
, vary
,
424 c
->payload_w_centroid
), r5
);
426 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
428 case INTERP_MODE_NOPERSPECTIVE
:
429 BITSET_SET(c
->noperspective_flags
, i
);
430 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
431 case INTERP_MODE_FLAT
:
432 BITSET_SET(c
->flat_shade_flags
, i
);
433 vir_MOV_dest(c
, c
->undef
, vary
);
434 return vir_MOV(c
, r5
);
436 unreachable("Bad interp mode");
441 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
)
443 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
444 int chan
= var
->data
.location_frac
+ i
;
445 c
->inputs
[attr
* 4 + chan
] =
446 emit_fragment_varying(c
, var
, chan
);
451 add_output(struct v3d_compile
*c
,
452 uint32_t decl_offset
,
456 uint32_t old_array_size
= c
->outputs_array_size
;
457 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
460 if (old_array_size
!= c
->outputs_array_size
) {
461 c
->output_slots
= reralloc(c
,
463 struct v3d_varying_slot
,
464 c
->outputs_array_size
);
467 c
->output_slots
[decl_offset
] =
468 v3d_slot_from_slot_and_component(slot
, swizzle
);
472 declare_uniform_range(struct v3d_compile
*c
, uint32_t start
, uint32_t size
)
474 unsigned array_id
= c
->num_ubo_ranges
++;
475 if (array_id
>= c
->ubo_ranges_array_size
) {
476 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
478 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
479 struct v3d_ubo_range
,
480 c
->ubo_ranges_array_size
);
481 c
->ubo_range_used
= reralloc(c
, c
->ubo_range_used
,
483 c
->ubo_ranges_array_size
);
486 c
->ubo_ranges
[array_id
].dst_offset
= 0;
487 c
->ubo_ranges
[array_id
].src_offset
= start
;
488 c
->ubo_ranges
[array_id
].size
= size
;
489 c
->ubo_range_used
[array_id
] = false;
493 * If compare_instr is a valid comparison instruction, emits the
494 * compare_instr's comparison and returns the sel_instr's return value based
495 * on the compare_instr's result.
498 ntq_emit_comparison(struct v3d_compile
*c
, struct qreg
*dest
,
499 nir_alu_instr
*compare_instr
,
500 nir_alu_instr
*sel_instr
)
502 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
504 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
505 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
506 bool cond_invert
= false;
508 switch (compare_instr
->op
) {
511 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
514 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
519 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
523 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
529 vir_PF(c
, vir_FCMP(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
532 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
536 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
542 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHN
);
545 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
548 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
555 enum v3d_qpu_cond cond
= (cond_invert
?
559 switch (sel_instr
->op
) {
564 *dest
= vir_SEL(c
, cond
,
565 vir_uniform_f(c
, 1.0), vir_uniform_f(c
, 0.0));
569 *dest
= vir_SEL(c
, cond
,
570 ntq_get_alu_src(c
, sel_instr
, 1),
571 ntq_get_alu_src(c
, sel_instr
, 2));
575 *dest
= vir_SEL(c
, cond
,
576 vir_uniform_ui(c
, ~0), vir_uniform_ui(c
, 0));
580 /* Make the temporary for nir_store_dest(). */
581 *dest
= vir_MOV(c
, *dest
);
587 * Attempts to fold a comparison generating a boolean result into the
588 * condition code for selecting between two values, instead of comparing the
589 * boolean result against 0 to generate the condition code.
591 static struct qreg
ntq_emit_bcsel(struct v3d_compile
*c
, nir_alu_instr
*instr
,
594 if (!instr
->src
[0].src
.is_ssa
)
596 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
598 nir_alu_instr
*compare
=
599 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
604 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
608 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
609 return vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
, src
[1], src
[2]));
614 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
616 /* This should always be lowered to ALU operations for V3D. */
617 assert(!instr
->dest
.saturate
);
619 /* Vectors are special in that they have non-scalarized writemasks,
620 * and just take the first swizzle channel for each argument in order
621 * into each writemask channel.
623 if (instr
->op
== nir_op_vec2
||
624 instr
->op
== nir_op_vec3
||
625 instr
->op
== nir_op_vec4
) {
627 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
628 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
629 instr
->src
[i
].swizzle
[0]);
630 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
631 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
632 vir_MOV(c
, srcs
[i
]));
636 /* General case: We can just grab the one used channel per src. */
637 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
638 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
647 result
= vir_MOV(c
, src
[0]);
651 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
654 result
= vir_NEG(c
, src
[0]);
658 result
= vir_FMUL(c
, src
[0], src
[1]);
661 result
= vir_FADD(c
, src
[0], src
[1]);
664 result
= vir_FSUB(c
, src
[0], src
[1]);
667 result
= vir_FMIN(c
, src
[0], src
[1]);
670 result
= vir_FMAX(c
, src
[0], src
[1]);
674 result
= vir_FTOIZ(c
, src
[0]);
677 result
= vir_FTOUZ(c
, src
[0]);
680 result
= vir_ITOF(c
, src
[0]);
683 result
= vir_UTOF(c
, src
[0]);
686 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
689 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
693 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
694 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
695 vir_uniform_ui(c
, ~0),
696 vir_uniform_ui(c
, 0)));
700 result
= vir_ADD(c
, src
[0], src
[1]);
703 result
= vir_SHR(c
, src
[0], src
[1]);
706 result
= vir_SUB(c
, src
[0], src
[1]);
709 result
= vir_ASR(c
, src
[0], src
[1]);
712 result
= vir_SHL(c
, src
[0], src
[1]);
715 result
= vir_MIN(c
, src
[0], src
[1]);
718 result
= vir_UMIN(c
, src
[0], src
[1]);
721 result
= vir_MAX(c
, src
[0], src
[1]);
724 result
= vir_UMAX(c
, src
[0], src
[1]);
727 result
= vir_AND(c
, src
[0], src
[1]);
730 result
= vir_OR(c
, src
[0], src
[1]);
733 result
= vir_XOR(c
, src
[0], src
[1]);
736 result
= vir_NOT(c
, src
[0]);
739 case nir_op_ufind_msb
:
740 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
744 result
= vir_UMUL(c
, src
[0], src
[1]);
761 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
762 fprintf(stderr
, "Bad comparison instruction\n");
767 result
= ntq_emit_bcsel(c
, instr
, src
);
770 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
771 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
776 result
= vir_RECIP(c
, src
[0]);
779 result
= vir_RSQRT(c
, src
[0]);
782 result
= vir_EXP(c
, src
[0]);
785 result
= vir_LOG(c
, src
[0]);
789 result
= vir_FCEIL(c
, src
[0]);
792 result
= vir_FFLOOR(c
, src
[0]);
794 case nir_op_fround_even
:
795 result
= vir_FROUND(c
, src
[0]);
798 result
= vir_FTRUNC(c
, src
[0]);
801 result
= vir_FSUB(c
, src
[0], vir_FFLOOR(c
, src
[0]));
805 result
= ntq_fsincos(c
, src
[0], false);
808 result
= ntq_fsincos(c
, src
[0], true);
812 result
= ntq_fsign(c
, src
[0]);
815 result
= ntq_isign(c
, src
[0]);
819 result
= vir_FMOV(c
, src
[0]);
820 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
825 result
= vir_MAX(c
, src
[0],
826 vir_SUB(c
, vir_uniform_ui(c
, 0), src
[0]));
830 case nir_op_fddx_coarse
:
831 case nir_op_fddx_fine
:
832 result
= vir_FDX(c
, src
[0]);
836 case nir_op_fddy_coarse
:
837 case nir_op_fddy_fine
:
838 result
= vir_FDY(c
, src
[0]);
841 case nir_op_uadd_carry
:
842 vir_PF(c
, vir_ADD(c
, src
[0], src
[1]), V3D_QPU_PF_PUSHC
);
843 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
844 vir_uniform_ui(c
, ~0),
845 vir_uniform_ui(c
, 0)));
848 case nir_op_pack_half_2x16_split
:
849 result
= vir_VFPACK(c
, src
[0], src
[1]);
852 case nir_op_unpack_half_2x16_split_x
:
853 result
= vir_FMOV(c
, src
[0]);
854 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
857 case nir_op_unpack_half_2x16_split_y
:
858 result
= vir_FMOV(c
, src
[0]);
859 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
863 fprintf(stderr
, "unknown NIR ALU inst: ");
864 nir_print_instr(&instr
->instr
, stderr
);
865 fprintf(stderr
, "\n");
869 /* We have a scalar result, so the instruction should only have a
870 * single channel written to.
872 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
873 ntq_store_dest(c
, &instr
->dest
.dest
,
874 ffs(instr
->dest
.write_mask
) - 1, result
);
877 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
878 * specifier. They come from a register that's preloaded with 0xffffffff
879 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
880 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
882 #define TLB_TYPE_F16_COLOR (3 << 6)
883 #define TLB_TYPE_I32_COLOR (1 << 6)
884 #define TLB_TYPE_F32_COLOR (0 << 6)
885 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
886 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
887 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
888 #define TLB_F16_SWAP_HI_LO (1 << 1)
889 #define TLB_VEC_SIZE_4_F16 (1 << 0)
890 #define TLB_VEC_SIZE_2_F16 (0 << 0)
891 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
893 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
896 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
897 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
898 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
900 /* Stencil is a single 32-bit write. */
901 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
904 emit_frag_end(struct v3d_compile
*c
)
907 if (c->output_sample_mask_index != -1) {
908 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
912 bool has_any_tlb_color_write
= false;
913 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
914 if (c
->output_color_var
[rt
])
915 has_any_tlb_color_write
= true;
918 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
919 struct nir_variable
*var
= c
->output_color_var
[0];
920 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
922 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
925 vir_FTOC(c
, color
[3])));
928 if (c
->output_position_index
!= -1) {
929 struct qinst
*inst
= vir_MOV_dest(c
,
930 vir_reg(QFILE_TLBU
, 0),
931 c
->outputs
[c
->output_position_index
]);
933 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
936 TLB_DEPTH_TYPE_PER_PIXEL
|
938 } else if (c
->s
->info
.fs
.uses_discard
||
939 c
->fs_key
->sample_alpha_to_coverage
||
940 !has_any_tlb_color_write
) {
941 /* Emit passthrough Z if it needed to be delayed until shader
942 * end due to potential discards.
944 * Since (single-threaded) fragment shaders always need a TLB
945 * write, emit passthrouh Z if we didn't have any color
946 * buffers and flag us as potentially discarding, so that we
947 * can use Z as the TLB write.
949 c
->s
->info
.fs
.uses_discard
= true;
951 struct qinst
*inst
= vir_MOV_dest(c
,
952 vir_reg(QFILE_TLBU
, 0),
953 vir_reg(QFILE_NULL
, 0));
955 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
958 TLB_DEPTH_TYPE_INVARIANT
|
962 /* XXX: Performance improvement: Merge Z write and color writes TLB
966 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
967 if (!c
->output_color_var
[rt
])
970 nir_variable
*var
= c
->output_color_var
[rt
];
971 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
972 int num_components
= glsl_get_vector_elements(var
->type
);
973 uint32_t conf
= 0xffffff00;
976 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
977 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
979 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
980 num_components
= MAX2(num_components
, 3);
982 assert(num_components
!= 0);
983 switch (glsl_get_base_type(var
->type
)) {
986 /* The F32 vs I32 distinction was dropped in 4.2. */
987 if (c
->devinfo
->ver
< 42)
988 conf
|= TLB_TYPE_I32_COLOR
;
990 conf
|= TLB_TYPE_F32_COLOR
;
991 conf
|= ((num_components
- 1) <<
992 TLB_VEC_SIZE_MINUS_1_SHIFT
);
994 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
995 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
996 vir_uniform_ui(c
, conf
);
998 for (int i
= 1; i
< num_components
; i
++) {
999 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
1005 struct qreg r
= color
[0];
1006 struct qreg g
= color
[1];
1007 struct qreg b
= color
[2];
1008 struct qreg a
= color
[3];
1010 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1011 conf
|= TLB_TYPE_F32_COLOR
;
1012 conf
|= ((num_components
- 1) <<
1013 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1015 conf
|= TLB_TYPE_F16_COLOR
;
1016 conf
|= TLB_F16_SWAP_HI_LO
;
1017 if (num_components
>= 3)
1018 conf
|= TLB_VEC_SIZE_4_F16
;
1020 conf
|= TLB_VEC_SIZE_2_F16
;
1023 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1028 if (c
->fs_key
->sample_alpha_to_one
)
1029 a
= vir_uniform_f(c
, 1.0);
1031 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1032 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), r
);
1033 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1034 vir_uniform_ui(c
, conf
);
1036 if (num_components
>= 2)
1037 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), g
);
1038 if (num_components
>= 3)
1039 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), b
);
1040 if (num_components
>= 4)
1041 vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0), a
);
1043 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), r
, g
);
1045 inst
->dst
.file
= QFILE_TLBU
;
1046 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1047 vir_uniform_ui(c
, conf
);
1050 if (num_components
>= 3)
1051 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), b
, a
);
1060 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t *vpm_index
)
1062 if (c
->devinfo
->ver
>= 40) {
1063 vir_STVPMV(c
, vir_uniform_ui(c
, *vpm_index
), val
);
1064 *vpm_index
= *vpm_index
+ 1;
1066 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1069 c
->num_vpm_writes
++;
1073 emit_scaled_viewport_write(struct v3d_compile
*c
, struct qreg rcp_w
,
1074 uint32_t *vpm_index
)
1076 for (int i
= 0; i
< 2; i
++) {
1077 struct qreg coord
= c
->outputs
[c
->output_position_index
+ i
];
1078 coord
= vir_FMUL(c
, coord
,
1079 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
,
1081 coord
= vir_FMUL(c
, coord
, rcp_w
);
1082 vir_VPM_WRITE(c
, vir_FTOIN(c
, coord
), vpm_index
);
1088 emit_zs_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1090 struct qreg zscale
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1091 struct qreg zoffset
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1093 struct qreg z
= c
->outputs
[c
->output_position_index
+ 2];
1094 z
= vir_FMUL(c
, z
, zscale
);
1095 z
= vir_FMUL(c
, z
, rcp_w
);
1096 z
= vir_FADD(c
, z
, zoffset
);
1097 vir_VPM_WRITE(c
, z
, vpm_index
);
1101 emit_rcp_wc_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1103 vir_VPM_WRITE(c
, rcp_w
, vpm_index
);
1107 emit_point_size_write(struct v3d_compile
*c
, uint32_t *vpm_index
)
1109 struct qreg point_size
;
1111 if (c
->output_point_size_index
!= -1)
1112 point_size
= c
->outputs
[c
->output_point_size_index
];
1114 point_size
= vir_uniform_f(c
, 1.0);
1116 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1119 point_size
= vir_FMAX(c
, point_size
, vir_uniform_f(c
, .125));
1121 vir_VPM_WRITE(c
, point_size
, vpm_index
);
1125 emit_vpm_write_setup(struct v3d_compile
*c
)
1127 if (c
->devinfo
->ver
>= 40)
1130 v3d33_vir_vpm_write_setup(c
);
1134 * Sets up c->outputs[c->output_position_index] for the vertex shader
1135 * epilogue, if an output vertex position wasn't specified in the user's
1136 * shader. This may be the case for transform feedback with rasterizer
1140 setup_default_position(struct v3d_compile
*c
)
1142 if (c
->output_position_index
!= -1)
1145 c
->output_position_index
= c
->outputs_array_size
;
1146 for (int i
= 0; i
< 4; i
++) {
1148 c
->output_position_index
+ i
,
1149 VARYING_SLOT_POS
, i
);
1154 emit_vert_end(struct v3d_compile
*c
)
1156 setup_default_position(c
);
1158 uint32_t vpm_index
= 0;
1159 struct qreg rcp_w
= vir_RECIP(c
,
1160 c
->outputs
[c
->output_position_index
+ 3]);
1162 emit_vpm_write_setup(c
);
1164 if (c
->vs_key
->is_coord
) {
1165 for (int i
= 0; i
< 4; i
++)
1166 vir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
],
1168 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1169 if (c
->vs_key
->per_vertex_point_size
) {
1170 emit_point_size_write(c
, &vpm_index
);
1171 /* emit_rcp_wc_write(c, rcp_w); */
1173 /* XXX: Z-only rendering */
1175 emit_zs_write(c
, rcp_w
, &vpm_index
);
1177 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1178 emit_zs_write(c
, rcp_w
, &vpm_index
);
1179 emit_rcp_wc_write(c
, rcp_w
, &vpm_index
);
1180 if (c
->vs_key
->per_vertex_point_size
)
1181 emit_point_size_write(c
, &vpm_index
);
1184 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
1185 struct v3d_varying_slot input
= c
->vs_key
->fs_inputs
[i
];
1188 for (j
= 0; j
< c
->num_outputs
; j
++) {
1189 struct v3d_varying_slot output
= c
->output_slots
[j
];
1191 if (!memcmp(&input
, &output
, sizeof(input
))) {
1192 vir_VPM_WRITE(c
, c
->outputs
[j
],
1197 /* Emit padding if we didn't find a declared VS output for
1200 if (j
== c
->num_outputs
)
1201 vir_VPM_WRITE(c
, vir_uniform_f(c
, 0.0),
1205 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1207 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1212 v3d_optimize_nir(struct nir_shader
*s
)
1219 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1220 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1221 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1222 NIR_PASS(progress
, s
, nir_copy_prop
);
1223 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1224 NIR_PASS(progress
, s
, nir_opt_dce
);
1225 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1226 NIR_PASS(progress
, s
, nir_opt_cse
);
1227 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1228 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1229 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1230 NIR_PASS(progress
, s
, nir_opt_undef
);
1233 NIR_PASS(progress
, s
, nir_opt_move_load_ubo
);
1237 driver_location_compare(const void *in_a
, const void *in_b
)
1239 const nir_variable
*const *a
= in_a
;
1240 const nir_variable
*const *b
= in_b
;
1242 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1246 ntq_emit_vpm_read(struct v3d_compile
*c
,
1247 uint32_t *num_components_queued
,
1248 uint32_t *remaining
,
1251 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1253 if (c
->devinfo
->ver
>= 40 ) {
1254 return vir_LDVPMV_IN(c
,
1256 (*num_components_queued
)++));
1259 if (*num_components_queued
!= 0) {
1260 (*num_components_queued
)--;
1262 return vir_MOV(c
, vpm
);
1265 uint32_t num_components
= MIN2(*remaining
, 32);
1267 v3d33_vir_vpm_read_setup(c
, num_components
);
1269 *num_components_queued
= num_components
- 1;
1270 *remaining
-= num_components
;
1273 return vir_MOV(c
, vpm
);
1277 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1279 unsigned num_entries
= 0;
1280 unsigned num_components
= 0;
1281 nir_foreach_variable(var
, &c
->s
->inputs
) {
1283 num_components
+= glsl_get_components(var
->type
);
1286 nir_variable
*vars
[num_entries
];
1289 nir_foreach_variable(var
, &c
->s
->inputs
)
1292 /* Sort the variables so that we emit the input setup in
1293 * driver_location order. This is required for VPM reads, whose data
1294 * is fetched into the VPM in driver_location (TGSI register index)
1297 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1299 uint32_t vpm_components_queued
= 0;
1300 bool uses_iid
= c
->s
->info
.system_values_read
&
1301 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1302 bool uses_vid
= c
->s
->info
.system_values_read
&
1303 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1305 num_components
+= uses_iid
;
1306 num_components
+= uses_vid
;
1309 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1310 &num_components
, ~0);
1314 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1315 &num_components
, ~0);
1318 for (unsigned i
= 0; i
< num_entries
; i
++) {
1319 nir_variable
*var
= vars
[i
];
1320 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1321 unsigned loc
= var
->data
.driver_location
;
1323 assert(array_len
== 1);
1325 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1328 int var_components
= glsl_get_components(var
->type
);
1330 for (int i
= 0; i
< var_components
; i
++) {
1331 c
->inputs
[loc
* 4 + i
] =
1332 ntq_emit_vpm_read(c
,
1333 &vpm_components_queued
,
1338 c
->vattr_sizes
[loc
] = var_components
;
1341 if (c
->devinfo
->ver
>= 40) {
1342 assert(vpm_components_queued
== num_components
);
1344 assert(vpm_components_queued
== 0);
1345 assert(num_components
== 0);
1350 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1352 unsigned num_entries
= 0;
1353 unsigned num_components
= 0;
1354 nir_foreach_variable(var
, &c
->s
->inputs
) {
1356 num_components
+= glsl_get_components(var
->type
);
1359 nir_variable
*vars
[num_entries
];
1362 nir_foreach_variable(var
, &c
->s
->inputs
)
1365 /* Sort the variables so that we emit the input setup in
1366 * driver_location order. This is required for VPM reads, whose data
1367 * is fetched into the VPM in driver_location (TGSI register index)
1370 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1372 for (unsigned i
= 0; i
< num_entries
; i
++) {
1373 nir_variable
*var
= vars
[i
];
1374 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1375 unsigned loc
= var
->data
.driver_location
;
1377 assert(array_len
== 1);
1379 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1382 if (var
->data
.location
== VARYING_SLOT_POS
) {
1383 emit_fragcoord_input(c
, loc
);
1384 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1385 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1386 (c
->fs_key
->point_sprite_mask
&
1387 (1 << (var
->data
.location
-
1388 VARYING_SLOT_VAR0
))))) {
1389 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1390 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1392 emit_fragment_input(c
, loc
, var
);
1398 ntq_setup_outputs(struct v3d_compile
*c
)
1400 nir_foreach_variable(var
, &c
->s
->outputs
) {
1401 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1402 unsigned loc
= var
->data
.driver_location
* 4;
1404 assert(array_len
== 1);
1407 for (int i
= 0; i
< 4; i
++) {
1408 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1410 var
->data
.location_frac
+ i
);
1413 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1414 switch (var
->data
.location
) {
1415 case FRAG_RESULT_COLOR
:
1416 c
->output_color_var
[0] = var
;
1417 c
->output_color_var
[1] = var
;
1418 c
->output_color_var
[2] = var
;
1419 c
->output_color_var
[3] = var
;
1421 case FRAG_RESULT_DATA0
:
1422 case FRAG_RESULT_DATA1
:
1423 case FRAG_RESULT_DATA2
:
1424 case FRAG_RESULT_DATA3
:
1425 c
->output_color_var
[var
->data
.location
-
1426 FRAG_RESULT_DATA0
] = var
;
1428 case FRAG_RESULT_DEPTH
:
1429 c
->output_position_index
= loc
;
1431 case FRAG_RESULT_SAMPLE_MASK
:
1432 c
->output_sample_mask_index
= loc
;
1436 switch (var
->data
.location
) {
1437 case VARYING_SLOT_POS
:
1438 c
->output_position_index
= loc
;
1440 case VARYING_SLOT_PSIZ
:
1441 c
->output_point_size_index
= loc
;
1449 ntq_setup_uniforms(struct v3d_compile
*c
)
1451 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1452 uint32_t vec4_count
= glsl_count_attribute_slots(var
->type
,
1454 unsigned vec4_size
= 4 * sizeof(float);
1456 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1457 vec4_count
* vec4_size
);
1463 * Sets up the mapping from nir_register to struct qreg *.
1465 * Each nir_register gets a struct qreg per 32-bit component being stored.
1468 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1470 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1471 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1472 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1474 nir_reg
->num_components
);
1476 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1478 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1479 qregs
[i
] = vir_get_temp(c
);
1484 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1486 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1487 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1488 qregs
[i
] = vir_uniform_ui(c
, instr
->value
.u32
[i
]);
1490 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1494 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1496 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1498 /* VIR needs there to be *some* value, so pick 0 (same as for
1499 * ntq_setup_registers().
1501 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1502 qregs
[i
] = vir_uniform_ui(c
, 0);
1506 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1508 nir_const_value
*const_offset
;
1511 switch (instr
->intrinsic
) {
1512 case nir_intrinsic_load_uniform
:
1513 assert(instr
->num_components
== 1);
1514 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1516 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1517 assert(offset
% 4 == 0);
1518 /* We need dwords */
1519 offset
= offset
/ 4;
1520 ntq_store_dest(c
, &instr
->dest
, 0,
1521 vir_uniform(c
, QUNIFORM_UNIFORM
,
1524 ntq_store_dest(c
, &instr
->dest
, 0,
1525 indirect_uniform_load(c
, instr
));
1529 case nir_intrinsic_load_ubo
:
1530 for (int i
= 0; i
< instr
->num_components
; i
++) {
1531 int ubo
= nir_src_as_const_value(instr
->src
[0])->u32
[0];
1533 /* Adjust for where we stored the TGSI register base. */
1535 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
1536 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 1 + ubo
),
1538 ntq_get_src(c
, instr
->src
[1], 0),
1539 vir_uniform_ui(c
, i
* 4)));
1543 ntq_store_dest(c
, &instr
->dest
, i
, vir_LDTMU(c
));
1547 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1549 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1550 assert(offset
% 4 == 0);
1551 /* We need dwords */
1552 offset
= offset
/ 4;
1553 ntq_store_dest(c
, &instr
->dest
, 0,
1554 vir_uniform(c
, QUNIFORM_UNIFORM
,
1557 ntq_store_dest(c
, &instr
->dest
, 0,
1558 indirect_uniform_load(c
, instr
));
1562 case nir_intrinsic_load_user_clip_plane
:
1563 for (int i
= 0; i
< instr
->num_components
; i
++) {
1564 ntq_store_dest(c
, &instr
->dest
, i
,
1565 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1566 nir_intrinsic_ucp_id(instr
) *
1571 case nir_intrinsic_load_alpha_ref_float
:
1572 ntq_store_dest(c
, &instr
->dest
, 0,
1573 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1576 case nir_intrinsic_load_sample_mask_in
:
1577 ntq_store_dest(c
, &instr
->dest
, 0,
1578 vir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1581 case nir_intrinsic_load_front_face
:
1582 /* The register contains 0 (front) or 1 (back), and we need to
1583 * turn it into a NIR bool where true means front.
1585 ntq_store_dest(c
, &instr
->dest
, 0,
1587 vir_uniform_ui(c
, -1),
1591 case nir_intrinsic_load_instance_id
:
1592 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1595 case nir_intrinsic_load_vertex_id
:
1596 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1599 case nir_intrinsic_load_input
:
1600 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1601 assert(const_offset
&& "v3d doesn't support indirect inputs");
1602 for (int i
= 0; i
< instr
->num_components
; i
++) {
1603 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1604 int comp
= nir_intrinsic_component(instr
) + i
;
1605 ntq_store_dest(c
, &instr
->dest
, i
,
1606 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1610 case nir_intrinsic_store_output
:
1611 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1612 assert(const_offset
&& "v3d doesn't support indirect outputs");
1613 offset
= ((nir_intrinsic_base(instr
) +
1614 const_offset
->u32
[0]) * 4 +
1615 nir_intrinsic_component(instr
));
1617 for (int i
= 0; i
< instr
->num_components
; i
++) {
1618 c
->outputs
[offset
+ i
] =
1619 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1621 c
->num_outputs
= MAX2(c
->num_outputs
,
1622 offset
+ instr
->num_components
);
1625 case nir_intrinsic_discard
:
1626 if (c
->execute
.file
!= QFILE_NULL
) {
1627 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1628 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1629 vir_uniform_ui(c
, 0)),
1632 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1633 vir_uniform_ui(c
, 0));
1637 case nir_intrinsic_discard_if
: {
1638 /* true (~0) if we're discarding */
1639 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1641 if (c
->execute
.file
!= QFILE_NULL
) {
1642 /* execute == 0 means the channel is active. Invert
1643 * the condition so that we can use zero as "executing
1646 vir_PF(c
, vir_OR(c
, c
->execute
, vir_NOT(c
, cond
)),
1648 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1649 vir_uniform_ui(c
, 0)),
1652 vir_PF(c
, cond
, V3D_QPU_PF_PUSHZ
);
1653 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1654 vir_uniform_ui(c
, 0)),
1662 fprintf(stderr
, "Unknown intrinsic: ");
1663 nir_print_instr(&instr
->instr
, stderr
);
1664 fprintf(stderr
, "\n");
1669 /* Clears (activates) the execute flags for any channels whose jump target
1670 * matches this block.
1673 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1675 vir_PF(c
, vir_XOR(c
, c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1678 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1682 ntq_emit_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1684 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1685 bool empty_else_block
=
1686 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1687 exec_list_is_empty(&nir_else_block
->instr_list
));
1689 struct qblock
*then_block
= vir_new_block(c
);
1690 struct qblock
*after_block
= vir_new_block(c
);
1691 struct qblock
*else_block
;
1692 if (empty_else_block
)
1693 else_block
= after_block
;
1695 else_block
= vir_new_block(c
);
1697 bool was_top_level
= false;
1698 if (c
->execute
.file
== QFILE_NULL
) {
1699 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1700 was_top_level
= true;
1703 /* Set A for executing (execute == 0) and jumping (if->condition ==
1704 * 0) channels, and then update execute flags for those to point to
1709 ntq_get_src(c
, if_stmt
->condition
, 0)),
1711 vir_MOV_cond(c
, V3D_QPU_COND_IFA
,
1713 vir_uniform_ui(c
, else_block
->index
));
1715 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1718 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1719 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
1720 vir_link_blocks(c
->cur_block
, else_block
);
1721 vir_link_blocks(c
->cur_block
, then_block
);
1723 /* Process the THEN block. */
1724 vir_set_emit_block(c
, then_block
);
1725 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1727 if (!empty_else_block
) {
1728 /* Handle the end of the THEN block. First, all currently
1729 * active channels update their execute flags to point to
1732 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1733 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1734 vir_uniform_ui(c
, after_block
->index
));
1736 /* If everything points at ENDIF, then jump there immediately. */
1737 vir_PF(c
, vir_XOR(c
, c
->execute
,
1738 vir_uniform_ui(c
, after_block
->index
)),
1740 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
1741 vir_link_blocks(c
->cur_block
, after_block
);
1742 vir_link_blocks(c
->cur_block
, else_block
);
1744 vir_set_emit_block(c
, else_block
);
1745 ntq_activate_execute_for_block(c
);
1746 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1749 vir_link_blocks(c
->cur_block
, after_block
);
1751 vir_set_emit_block(c
, after_block
);
1753 c
->execute
= c
->undef
;
1755 ntq_activate_execute_for_block(c
);
1759 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
1761 switch (jump
->type
) {
1762 case nir_jump_break
:
1763 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1764 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1765 vir_uniform_ui(c
, c
->loop_break_block
->index
));
1768 case nir_jump_continue
:
1769 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1770 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1771 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
1774 case nir_jump_return
:
1775 unreachable("All returns shouold be lowered\n");
1780 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
1782 switch (instr
->type
) {
1783 case nir_instr_type_alu
:
1784 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1787 case nir_instr_type_intrinsic
:
1788 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1791 case nir_instr_type_load_const
:
1792 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1795 case nir_instr_type_ssa_undef
:
1796 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1799 case nir_instr_type_tex
:
1800 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1803 case nir_instr_type_jump
:
1804 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1808 fprintf(stderr
, "Unknown NIR instr type: ");
1809 nir_print_instr(instr
, stderr
);
1810 fprintf(stderr
, "\n");
1816 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
1818 nir_foreach_instr(instr
, block
) {
1819 ntq_emit_instr(c
, instr
);
1823 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
1826 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
1828 bool was_top_level
= false;
1829 if (c
->execute
.file
== QFILE_NULL
) {
1830 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1831 was_top_level
= true;
1834 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1835 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1837 c
->loop_cont_block
= vir_new_block(c
);
1838 c
->loop_break_block
= vir_new_block(c
);
1840 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1841 vir_set_emit_block(c
, c
->loop_cont_block
);
1842 ntq_activate_execute_for_block(c
);
1844 ntq_emit_cf_list(c
, &loop
->body
);
1846 /* Re-enable any previous continues now, so our ANYA check below
1849 * XXX: Use the .ORZ flags update, instead.
1851 vir_PF(c
, vir_XOR(c
,
1853 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
1855 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1857 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1859 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
1860 /* Pixels that were not dispatched or have been discarded should not
1861 * contribute to looping again.
1863 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
1864 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1865 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1867 vir_set_emit_block(c
, c
->loop_break_block
);
1869 c
->execute
= c
->undef
;
1871 ntq_activate_execute_for_block(c
);
1873 c
->loop_break_block
= save_loop_break_block
;
1874 c
->loop_cont_block
= save_loop_cont_block
;
1878 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
1880 fprintf(stderr
, "FUNCTIONS not handled.\n");
1885 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
1887 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1888 switch (node
->type
) {
1889 case nir_cf_node_block
:
1890 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1893 case nir_cf_node_if
:
1894 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1897 case nir_cf_node_loop
:
1898 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1901 case nir_cf_node_function
:
1902 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1906 fprintf(stderr
, "Unknown NIR node type\n");
1913 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
1915 ntq_setup_registers(c
, &impl
->registers
);
1916 ntq_emit_cf_list(c
, &impl
->body
);
1920 nir_to_vir(struct v3d_compile
*c
)
1922 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1923 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
1924 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
1925 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
1927 if (c
->fs_key
->is_points
) {
1928 c
->point_x
= emit_fragment_varying(c
, NULL
, 0);
1929 c
->point_y
= emit_fragment_varying(c
, NULL
, 0);
1930 } else if (c
->fs_key
->is_lines
) {
1931 c
->line_x
= emit_fragment_varying(c
, NULL
, 0);
1935 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
1936 ntq_setup_fs_inputs(c
);
1938 ntq_setup_vpm_inputs(c
);
1940 ntq_setup_outputs(c
);
1941 ntq_setup_uniforms(c
);
1942 ntq_setup_registers(c
, &c
->s
->registers
);
1944 /* Find the main function and emit the body. */
1945 nir_foreach_function(function
, c
->s
) {
1946 assert(strcmp(function
->name
, "main") == 0);
1947 assert(function
->impl
);
1948 ntq_emit_impl(c
, function
->impl
);
1952 const nir_shader_compiler_options v3d_nir_options
= {
1953 .lower_all_io_to_temps
= true,
1954 .lower_extract_byte
= true,
1955 .lower_extract_word
= true,
1957 .lower_bitfield_insert_to_shifts
= true,
1958 .lower_bitfield_extract_to_shifts
= true,
1959 .lower_bitfield_reverse
= true,
1960 .lower_bit_count
= true,
1961 .lower_pack_unorm_2x16
= true,
1962 .lower_pack_snorm_2x16
= true,
1963 .lower_pack_unorm_4x8
= true,
1964 .lower_pack_snorm_4x8
= true,
1965 .lower_unpack_unorm_4x8
= true,
1966 .lower_unpack_snorm_4x8
= true,
1967 .lower_pack_half_2x16
= true,
1968 .lower_unpack_half_2x16
= true,
1970 .lower_find_lsb
= true,
1972 .lower_flrp32
= true,
1975 .lower_fsqrt
= true,
1976 .lower_ifind_msb
= true,
1977 .lower_ldexp
= true,
1978 .lower_mul_high
= true,
1979 .lower_wpos_pntc
= true,
1980 .native_integers
= true,
1986 count_nir_instrs(nir_shader
*nir
)
1989 nir_foreach_function(function
, nir
) {
1990 if (!function
->impl
)
1992 nir_foreach_block(block
, function
->impl
) {
1993 nir_foreach_instr(instr
, block
)
2002 * When demoting a shader down to single-threaded, removes the THRSW
2003 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2007 vir_remove_thrsw(struct v3d_compile
*c
)
2009 vir_for_each_block(block
, c
) {
2010 vir_for_each_inst_safe(inst
, block
) {
2011 if (inst
->qpu
.sig
.thrsw
)
2012 vir_remove_instruction(c
, inst
);
2016 c
->last_thrsw
= NULL
;
2020 vir_emit_last_thrsw(struct v3d_compile
*c
)
2022 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2023 * switching, so disable threads if we didn't do any TMU ops (each of
2024 * which would have emitted a THRSW).
2026 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2029 vir_remove_thrsw(c
);
2033 /* If we're threaded and the last THRSW was in conditional code, then
2034 * we need to emit another one so that we can flag it as the last
2037 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2038 assert(c
->devinfo
->ver
>= 41);
2042 /* If we're threaded, then we need to mark the last THRSW instruction
2043 * so we can emit a pair of them at QPU emit time.
2045 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2046 * post-last-THRSW state, so we can skip this.
2048 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2049 assert(c
->devinfo
->ver
>= 41);
2054 c
->last_thrsw
->is_last_thrsw
= true;
2057 /* There's a flag in the shader for "center W is needed for reasons other than
2058 * non-centroid varyings", so we just walk the program after VIR optimization
2059 * to see if it's used. It should be harmless to set even if we only use
2060 * center W for varyings.
2063 vir_check_payload_w(struct v3d_compile
*c
)
2065 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2068 vir_for_each_inst_inorder(inst
, c
) {
2069 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2070 if (inst
->src
[i
].file
== QFILE_REG
&&
2071 inst
->src
[i
].index
== 0) {
2072 c
->uses_center_w
= true;
2081 v3d_nir_to_vir(struct v3d_compile
*c
)
2083 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2084 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2085 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2086 vir_get_stage_name(c
),
2087 c
->program_id
, c
->variant_id
);
2088 nir_print_shader(c
->s
, stderr
);
2093 /* Emit the last THRSW before STVPM and TLB writes. */
2094 vir_emit_last_thrsw(c
);
2096 switch (c
->s
->info
.stage
) {
2097 case MESA_SHADER_FRAGMENT
:
2100 case MESA_SHADER_VERTEX
:
2104 unreachable("bad stage");
2107 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2108 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2109 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2110 vir_get_stage_name(c
),
2111 c
->program_id
, c
->variant_id
);
2113 fprintf(stderr
, "\n");
2117 vir_lower_uniforms(c
);
2119 vir_check_payload_w(c
);
2121 /* XXX: vir_schedule_instructions(c); */
2123 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2124 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2125 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2126 vir_get_stage_name(c
),
2127 c
->program_id
, c
->variant_id
);
2129 fprintf(stderr
, "\n");
2132 /* Attempt to allocate registers for the temporaries. If we fail,
2133 * reduce thread count and try again.
2135 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2136 struct qpu_reg
*temp_registers
;
2139 temp_registers
= v3d_register_allocate(c
, &spilled
);
2146 if (c
->threads
== min_threads
) {
2147 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2156 if (c
->threads
== 1)
2157 vir_remove_thrsw(c
);
2160 v3d_vir_to_qpu(c
, temp_registers
);