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v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL)
287 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
288
289 struct qreg dest;
290 if (config == ~0)
291 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
292 else
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
294
295 struct qinst *tmu;
296 if (nir_src_is_const(instr->src[offset_src]) &&
297 nir_src_as_uint(instr->src[offset_src]) == 0) {
298 tmu = vir_MOV_dest(c, dest, offset);
299 } else {
300 tmu = vir_ADD_dest(c, dest,
301 offset,
302 ntq_get_src(c, instr->src[offset_src], 0));
303 }
304
305 if (config != ~0) {
306 tmu->src[vir_get_implicit_uniform_src(tmu)] =
307 vir_uniform_ui(c, config);
308 }
309
310 if (c->execute.file != QFILE_NULL)
311 vir_set_cond(tmu, V3D_QPU_COND_IFA);
312
313 vir_emit_thrsw(c);
314
315 /* Read the result, or wait for the TMU op to complete. */
316 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
317 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
318
319 if (nir_intrinsic_dest_components(instr) == 0)
320 vir_TMUWT(c);
321 }
322
323 static struct qreg *
324 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
325 {
326 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
327 def->num_components);
328 _mesa_hash_table_insert(c->def_ht, def, qregs);
329 return qregs;
330 }
331
332 /**
333 * This function is responsible for getting VIR results into the associated
334 * storage for a NIR instruction.
335 *
336 * If it's a NIR SSA def, then we just set the associated hash table entry to
337 * the new result.
338 *
339 * If it's a NIR reg, then we need to update the existing qreg assigned to the
340 * NIR destination with the incoming value. To do that without introducing
341 * new MOVs, we require that the incoming qreg either be a uniform, or be
342 * SSA-defined by the previous VIR instruction in the block and rewritable by
343 * this function. That lets us sneak ahead and insert the SF flag beforehand
344 * (knowing that the previous instruction doesn't depend on flags) and rewrite
345 * its destination to be the NIR reg's destination
346 */
347 void
348 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
349 struct qreg result)
350 {
351 struct qinst *last_inst = NULL;
352 if (!list_empty(&c->cur_block->instructions))
353 last_inst = (struct qinst *)c->cur_block->instructions.prev;
354
355 assert(result.file == QFILE_UNIF ||
356 (result.file == QFILE_TEMP &&
357 last_inst && last_inst == c->defs[result.index]));
358
359 if (dest->is_ssa) {
360 assert(chan < dest->ssa.num_components);
361
362 struct qreg *qregs;
363 struct hash_entry *entry =
364 _mesa_hash_table_search(c->def_ht, &dest->ssa);
365
366 if (entry)
367 qregs = entry->data;
368 else
369 qregs = ntq_init_ssa_def(c, &dest->ssa);
370
371 qregs[chan] = result;
372 } else {
373 nir_register *reg = dest->reg.reg;
374 assert(dest->reg.base_offset == 0);
375 assert(reg->num_array_elems == 0);
376 struct hash_entry *entry =
377 _mesa_hash_table_search(c->def_ht, reg);
378 struct qreg *qregs = entry->data;
379
380 /* Insert a MOV if the source wasn't an SSA def in the
381 * previous instruction.
382 */
383 if (result.file == QFILE_UNIF) {
384 result = vir_MOV(c, result);
385 last_inst = c->defs[result.index];
386 }
387
388 /* We know they're both temps, so just rewrite index. */
389 c->defs[last_inst->dst.index] = NULL;
390 last_inst->dst.index = qregs[chan].index;
391
392 /* If we're in control flow, then make this update of the reg
393 * conditional on the execution mask.
394 */
395 if (c->execute.file != QFILE_NULL) {
396 last_inst->dst.index = qregs[chan].index;
397
398 /* Set the flags to the current exec mask.
399 */
400 c->cursor = vir_before_inst(last_inst);
401 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
402 c->cursor = vir_after_inst(last_inst);
403
404 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
405 last_inst->cond_is_exec_mask = true;
406 }
407 }
408 }
409
410 struct qreg
411 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
412 {
413 struct hash_entry *entry;
414 if (src.is_ssa) {
415 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
416 assert(i < src.ssa->num_components);
417 } else {
418 nir_register *reg = src.reg.reg;
419 entry = _mesa_hash_table_search(c->def_ht, reg);
420 assert(reg->num_array_elems == 0);
421 assert(src.reg.base_offset == 0);
422 assert(i < reg->num_components);
423 }
424
425 struct qreg *qregs = entry->data;
426 return qregs[i];
427 }
428
429 static struct qreg
430 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
431 unsigned src)
432 {
433 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
434 unsigned chan = ffs(instr->dest.write_mask) - 1;
435 struct qreg r = ntq_get_src(c, instr->src[src].src,
436 instr->src[src].swizzle[chan]);
437
438 assert(!instr->src[src].abs);
439 assert(!instr->src[src].negate);
440
441 return r;
442 };
443
444 static struct qreg
445 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
446 {
447 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
448 }
449
450 static void
451 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
452 {
453 unsigned unit = instr->texture_index;
454 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
455 int dest_size = nir_tex_instr_dest_size(instr);
456
457 struct qreg lod = c->undef;
458 if (lod_index != -1)
459 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
460
461 for (int i = 0; i < dest_size; i++) {
462 assert(i < 3);
463 enum quniform_contents contents;
464
465 if (instr->is_array && i == dest_size - 1)
466 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
467 else
468 contents = QUNIFORM_TEXTURE_WIDTH + i;
469
470 struct qreg size = vir_uniform(c, contents, unit);
471
472 switch (instr->sampler_dim) {
473 case GLSL_SAMPLER_DIM_1D:
474 case GLSL_SAMPLER_DIM_2D:
475 case GLSL_SAMPLER_DIM_MS:
476 case GLSL_SAMPLER_DIM_3D:
477 case GLSL_SAMPLER_DIM_CUBE:
478 /* Don't minify the array size. */
479 if (!(instr->is_array && i == dest_size - 1)) {
480 size = ntq_minify(c, size, lod);
481 }
482 break;
483
484 case GLSL_SAMPLER_DIM_RECT:
485 /* There's no LOD field for rects */
486 break;
487
488 default:
489 unreachable("Bad sampler type");
490 }
491
492 ntq_store_dest(c, &instr->dest, i, size);
493 }
494 }
495
496 static void
497 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
498 {
499 unsigned unit = instr->texture_index;
500
501 /* Since each texture sampling op requires uploading uniforms to
502 * reference the texture, there's no HW support for texture size and
503 * you just upload uniforms containing the size.
504 */
505 switch (instr->op) {
506 case nir_texop_query_levels:
507 ntq_store_dest(c, &instr->dest, 0,
508 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
509 return;
510 case nir_texop_txs:
511 ntq_emit_txs(c, instr);
512 return;
513 default:
514 break;
515 }
516
517 if (c->devinfo->ver >= 40)
518 v3d40_vir_emit_tex(c, instr);
519 else
520 v3d33_vir_emit_tex(c, instr);
521 }
522
523 static struct qreg
524 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
525 {
526 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
527 if (is_cos)
528 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
529
530 struct qreg periods = vir_FROUND(c, input);
531 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
532 return vir_XOR(c, sin_output, vir_SHL(c,
533 vir_FTOIN(c, periods),
534 vir_uniform_ui(c, -1)));
535 }
536
537 static struct qreg
538 ntq_fsign(struct v3d_compile *c, struct qreg src)
539 {
540 struct qreg t = vir_get_temp(c);
541
542 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
543 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
544 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
545 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
546 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
547 return vir_MOV(c, t);
548 }
549
550 static void
551 emit_fragcoord_input(struct v3d_compile *c, int attr)
552 {
553 c->inputs[attr * 4 + 0] = vir_FXCD(c);
554 c->inputs[attr * 4 + 1] = vir_FYCD(c);
555 c->inputs[attr * 4 + 2] = c->payload_z;
556 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
557 }
558
559 static struct qreg
560 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
561 uint8_t swizzle, int array_index)
562 {
563 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
564 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
565
566 struct qreg vary;
567 if (c->devinfo->ver >= 41) {
568 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
569 c->undef, c->undef);
570 ldvary->qpu.sig.ldvary = true;
571 vary = vir_emit_def(c, ldvary);
572 } else {
573 vir_NOP(c)->qpu.sig.ldvary = true;
574 vary = r3;
575 }
576
577 /* For gl_PointCoord input or distance along a line, we'll be called
578 * with no nir_variable, and we don't count toward VPM size so we
579 * don't track an input slot.
580 */
581 if (!var) {
582 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
583 }
584
585 int i = c->num_inputs++;
586 c->input_slots[i] =
587 v3d_slot_from_slot_and_component(var->data.location +
588 array_index, swizzle);
589
590 switch (var->data.interpolation) {
591 case INTERP_MODE_NONE:
592 /* If a gl_FrontColor or gl_BackColor input has no interp
593 * qualifier, then if we're using glShadeModel(GL_FLAT) it
594 * needs to be flat shaded.
595 */
596 switch (var->data.location + array_index) {
597 case VARYING_SLOT_COL0:
598 case VARYING_SLOT_COL1:
599 case VARYING_SLOT_BFC0:
600 case VARYING_SLOT_BFC1:
601 if (c->fs_key->shade_model_flat) {
602 BITSET_SET(c->flat_shade_flags, i);
603 vir_MOV_dest(c, c->undef, vary);
604 return vir_MOV(c, r5);
605 } else {
606 return vir_FADD(c, vir_FMUL(c, vary,
607 c->payload_w), r5);
608 }
609 default:
610 break;
611 }
612 /* FALLTHROUGH */
613 case INTERP_MODE_SMOOTH:
614 if (var->data.centroid) {
615 BITSET_SET(c->centroid_flags, i);
616 return vir_FADD(c, vir_FMUL(c, vary,
617 c->payload_w_centroid), r5);
618 } else {
619 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
620 }
621 case INTERP_MODE_NOPERSPECTIVE:
622 BITSET_SET(c->noperspective_flags, i);
623 return vir_FADD(c, vir_MOV(c, vary), r5);
624 case INTERP_MODE_FLAT:
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 default:
629 unreachable("Bad interp mode");
630 }
631 }
632
633 static void
634 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
635 int array_index)
636 {
637 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
638 int chan = var->data.location_frac + i;
639 c->inputs[attr * 4 + chan] =
640 emit_fragment_varying(c, var, chan, array_index);
641 }
642 }
643
644 static void
645 add_output(struct v3d_compile *c,
646 uint32_t decl_offset,
647 uint8_t slot,
648 uint8_t swizzle)
649 {
650 uint32_t old_array_size = c->outputs_array_size;
651 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
652 decl_offset + 1);
653
654 if (old_array_size != c->outputs_array_size) {
655 c->output_slots = reralloc(c,
656 c->output_slots,
657 struct v3d_varying_slot,
658 c->outputs_array_size);
659 }
660
661 c->output_slots[decl_offset] =
662 v3d_slot_from_slot_and_component(slot, swizzle);
663 }
664
665 static void
666 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
667 {
668 unsigned array_id = c->num_ubo_ranges++;
669 if (array_id >= c->ubo_ranges_array_size) {
670 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
671 array_id + 1);
672 c->ubo_ranges = reralloc(c, c->ubo_ranges,
673 struct v3d_ubo_range,
674 c->ubo_ranges_array_size);
675 c->ubo_range_used = reralloc(c, c->ubo_range_used,
676 bool,
677 c->ubo_ranges_array_size);
678 }
679
680 c->ubo_ranges[array_id].dst_offset = 0;
681 c->ubo_ranges[array_id].src_offset = start;
682 c->ubo_ranges[array_id].size = size;
683 c->ubo_range_used[array_id] = false;
684 }
685
686 /**
687 * If compare_instr is a valid comparison instruction, emits the
688 * compare_instr's comparison and returns the sel_instr's return value based
689 * on the compare_instr's result.
690 */
691 static bool
692 ntq_emit_comparison(struct v3d_compile *c,
693 nir_alu_instr *compare_instr,
694 enum v3d_qpu_cond *out_cond)
695 {
696 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
697 struct qreg src1;
698 if (nir_op_infos[compare_instr->op].num_inputs > 1)
699 src1 = ntq_get_alu_src(c, compare_instr, 1);
700 bool cond_invert = false;
701 struct qreg nop = vir_reg(QFILE_NULL, 0);
702
703 switch (compare_instr->op) {
704 case nir_op_feq32:
705 case nir_op_seq:
706 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
707 break;
708 case nir_op_ieq32:
709 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711
712 case nir_op_fne32:
713 case nir_op_sne:
714 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
715 cond_invert = true;
716 break;
717 case nir_op_ine32:
718 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
719 cond_invert = true;
720 break;
721
722 case nir_op_fge32:
723 case nir_op_sge:
724 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
725 break;
726 case nir_op_ige32:
727 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 cond_invert = true;
729 break;
730 case nir_op_uge32:
731 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
732 cond_invert = true;
733 break;
734
735 case nir_op_slt:
736 case nir_op_flt32:
737 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
738 break;
739 case nir_op_ilt32:
740 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
741 break;
742 case nir_op_ult32:
743 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
744 break;
745
746 default:
747 return false;
748 }
749
750 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
751
752 return true;
753 }
754
755 /* Finds an ALU instruction that generates our src value that could
756 * (potentially) be greedily emitted in the consuming instruction.
757 */
758 static struct nir_alu_instr *
759 ntq_get_alu_parent(nir_src src)
760 {
761 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
762 return NULL;
763 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
764 if (!instr)
765 return NULL;
766
767 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
768 * moving emission of the ALU instr down past another write of the
769 * src.
770 */
771 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
772 if (!instr->src[i].src.is_ssa)
773 return NULL;
774 }
775
776 return instr;
777 }
778
779 /**
780 * Attempts to fold a comparison generating a boolean result into the
781 * condition code for selecting between two values, instead of comparing the
782 * boolean result against 0 to generate the condition code.
783 */
784 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
785 struct qreg *src)
786 {
787 nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src);
788 if (!compare)
789 goto out;
790
791 enum v3d_qpu_cond cond;
792 if (ntq_emit_comparison(c, compare, &cond))
793 return vir_MOV(c, vir_SEL(c, cond, src[1], src[2]));
794
795 out:
796 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
797 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
798 }
799
800
801 static void
802 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
803 {
804 /* This should always be lowered to ALU operations for V3D. */
805 assert(!instr->dest.saturate);
806
807 /* Vectors are special in that they have non-scalarized writemasks,
808 * and just take the first swizzle channel for each argument in order
809 * into each writemask channel.
810 */
811 if (instr->op == nir_op_vec2 ||
812 instr->op == nir_op_vec3 ||
813 instr->op == nir_op_vec4) {
814 struct qreg srcs[4];
815 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
816 srcs[i] = ntq_get_src(c, instr->src[i].src,
817 instr->src[i].swizzle[0]);
818 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
819 ntq_store_dest(c, &instr->dest.dest, i,
820 vir_MOV(c, srcs[i]));
821 return;
822 }
823
824 /* General case: We can just grab the one used channel per src. */
825 struct qreg src[nir_op_infos[instr->op].num_inputs];
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
827 src[i] = ntq_get_alu_src(c, instr, i);
828 }
829
830 struct qreg result;
831
832 switch (instr->op) {
833 case nir_op_fmov:
834 case nir_op_imov:
835 result = vir_MOV(c, src[0]);
836 break;
837
838 case nir_op_fneg:
839 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
840 break;
841 case nir_op_ineg:
842 result = vir_NEG(c, src[0]);
843 break;
844
845 case nir_op_fmul:
846 result = vir_FMUL(c, src[0], src[1]);
847 break;
848 case nir_op_fadd:
849 result = vir_FADD(c, src[0], src[1]);
850 break;
851 case nir_op_fsub:
852 result = vir_FSUB(c, src[0], src[1]);
853 break;
854 case nir_op_fmin:
855 result = vir_FMIN(c, src[0], src[1]);
856 break;
857 case nir_op_fmax:
858 result = vir_FMAX(c, src[0], src[1]);
859 break;
860
861 case nir_op_f2i32:
862 result = vir_FTOIZ(c, src[0]);
863 break;
864 case nir_op_f2u32:
865 result = vir_FTOUZ(c, src[0]);
866 break;
867 case nir_op_i2f32:
868 result = vir_ITOF(c, src[0]);
869 break;
870 case nir_op_u2f32:
871 result = vir_UTOF(c, src[0]);
872 break;
873 case nir_op_b2f32:
874 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
875 break;
876 case nir_op_b2i32:
877 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
878 break;
879 case nir_op_i2b32:
880 case nir_op_f2b32:
881 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
882 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
883 vir_uniform_ui(c, ~0),
884 vir_uniform_ui(c, 0)));
885 break;
886
887 case nir_op_iadd:
888 result = vir_ADD(c, src[0], src[1]);
889 break;
890 case nir_op_ushr:
891 result = vir_SHR(c, src[0], src[1]);
892 break;
893 case nir_op_isub:
894 result = vir_SUB(c, src[0], src[1]);
895 break;
896 case nir_op_ishr:
897 result = vir_ASR(c, src[0], src[1]);
898 break;
899 case nir_op_ishl:
900 result = vir_SHL(c, src[0], src[1]);
901 break;
902 case nir_op_imin:
903 result = vir_MIN(c, src[0], src[1]);
904 break;
905 case nir_op_umin:
906 result = vir_UMIN(c, src[0], src[1]);
907 break;
908 case nir_op_imax:
909 result = vir_MAX(c, src[0], src[1]);
910 break;
911 case nir_op_umax:
912 result = vir_UMAX(c, src[0], src[1]);
913 break;
914 case nir_op_iand:
915 result = vir_AND(c, src[0], src[1]);
916 break;
917 case nir_op_ior:
918 result = vir_OR(c, src[0], src[1]);
919 break;
920 case nir_op_ixor:
921 result = vir_XOR(c, src[0], src[1]);
922 break;
923 case nir_op_inot:
924 result = vir_NOT(c, src[0]);
925 break;
926
927 case nir_op_ufind_msb:
928 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
929 break;
930
931 case nir_op_imul:
932 result = vir_UMUL(c, src[0], src[1]);
933 break;
934
935 case nir_op_seq:
936 case nir_op_sne:
937 case nir_op_sge:
938 case nir_op_slt: {
939 enum v3d_qpu_cond cond;
940 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
941 assert(ok);
942 result = vir_MOV(c, vir_SEL(c, cond,
943 vir_uniform_f(c, 1.0),
944 vir_uniform_f(c, 0.0)));
945 break;
946 }
947
948 case nir_op_feq32:
949 case nir_op_fne32:
950 case nir_op_fge32:
951 case nir_op_flt32:
952 case nir_op_ieq32:
953 case nir_op_ine32:
954 case nir_op_ige32:
955 case nir_op_uge32:
956 case nir_op_ilt32:
957 case nir_op_ult32: {
958 enum v3d_qpu_cond cond;
959 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
960 assert(ok);
961 result = vir_MOV(c, vir_SEL(c, cond,
962 vir_uniform_ui(c, ~0),
963 vir_uniform_ui(c, 0)));
964 break;
965 }
966
967 case nir_op_b32csel:
968 result = ntq_emit_bcsel(c, instr, src);
969 break;
970 case nir_op_fcsel:
971 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
972 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
973 src[1], src[2]));
974 break;
975
976 case nir_op_frcp:
977 result = vir_RECIP(c, src[0]);
978 break;
979 case nir_op_frsq:
980 result = vir_RSQRT(c, src[0]);
981 break;
982 case nir_op_fexp2:
983 result = vir_EXP(c, src[0]);
984 break;
985 case nir_op_flog2:
986 result = vir_LOG(c, src[0]);
987 break;
988
989 case nir_op_fceil:
990 result = vir_FCEIL(c, src[0]);
991 break;
992 case nir_op_ffloor:
993 result = vir_FFLOOR(c, src[0]);
994 break;
995 case nir_op_fround_even:
996 result = vir_FROUND(c, src[0]);
997 break;
998 case nir_op_ftrunc:
999 result = vir_FTRUNC(c, src[0]);
1000 break;
1001 case nir_op_ffract:
1002 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
1003 break;
1004
1005 case nir_op_fsin:
1006 result = ntq_fsincos(c, src[0], false);
1007 break;
1008 case nir_op_fcos:
1009 result = ntq_fsincos(c, src[0], true);
1010 break;
1011
1012 case nir_op_fsign:
1013 result = ntq_fsign(c, src[0]);
1014 break;
1015
1016 case nir_op_fabs: {
1017 result = vir_FMOV(c, src[0]);
1018 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1019 break;
1020 }
1021
1022 case nir_op_iabs:
1023 result = vir_MAX(c, src[0],
1024 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1025 break;
1026
1027 case nir_op_fddx:
1028 case nir_op_fddx_coarse:
1029 case nir_op_fddx_fine:
1030 result = vir_FDX(c, src[0]);
1031 break;
1032
1033 case nir_op_fddy:
1034 case nir_op_fddy_coarse:
1035 case nir_op_fddy_fine:
1036 result = vir_FDY(c, src[0]);
1037 break;
1038
1039 case nir_op_uadd_carry:
1040 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
1041 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1042 vir_uniform_ui(c, ~0),
1043 vir_uniform_ui(c, 0)));
1044 break;
1045
1046 case nir_op_pack_half_2x16_split:
1047 result = vir_VFPACK(c, src[0], src[1]);
1048 break;
1049
1050 case nir_op_unpack_half_2x16_split_x:
1051 /* XXX perf: It would be good to be able to merge this unpack
1052 * with whatever uses our result.
1053 */
1054 result = vir_FMOV(c, src[0]);
1055 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1056 break;
1057
1058 case nir_op_unpack_half_2x16_split_y:
1059 result = vir_FMOV(c, src[0]);
1060 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1061 break;
1062
1063 default:
1064 fprintf(stderr, "unknown NIR ALU inst: ");
1065 nir_print_instr(&instr->instr, stderr);
1066 fprintf(stderr, "\n");
1067 abort();
1068 }
1069
1070 /* We have a scalar result, so the instruction should only have a
1071 * single channel written to.
1072 */
1073 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1074 ntq_store_dest(c, &instr->dest.dest,
1075 ffs(instr->dest.write_mask) - 1, result);
1076 }
1077
1078 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1079 * specifier. They come from a register that's preloaded with 0xffffffff
1080 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1081 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1082 */
1083 #define TLB_TYPE_F16_COLOR (3 << 6)
1084 #define TLB_TYPE_I32_COLOR (1 << 6)
1085 #define TLB_TYPE_F32_COLOR (0 << 6)
1086 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1087 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1088 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1089 #define TLB_F16_SWAP_HI_LO (1 << 1)
1090 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1091 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1092 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1093
1094 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1095 * flag is set.
1096 */
1097 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1098 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1099 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1100 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1101 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1102
1103 /* Stencil is a single 32-bit write. */
1104 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1105
1106 static void
1107 emit_frag_end(struct v3d_compile *c)
1108 {
1109 /* XXX
1110 if (c->output_sample_mask_index != -1) {
1111 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1112 }
1113 */
1114
1115 bool has_any_tlb_color_write = false;
1116 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1117 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1118 has_any_tlb_color_write = true;
1119 }
1120
1121 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1122 struct nir_variable *var = c->output_color_var[0];
1123 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1124
1125 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1126 vir_AND(c,
1127 vir_MSF(c),
1128 vir_FTOC(c, color[3])));
1129 }
1130
1131 if (c->output_position_index != -1) {
1132 struct qinst *inst = vir_MOV_dest(c,
1133 vir_reg(QFILE_TLBU, 0),
1134 c->outputs[c->output_position_index]);
1135 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1136
1137 if (c->devinfo->ver >= 42) {
1138 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1139 TLB_SAMPLE_MODE_PER_PIXEL);
1140 } else
1141 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1142
1143 inst->src[vir_get_implicit_uniform_src(inst)] =
1144 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1145 c->writes_z = true;
1146 } else if (c->s->info.fs.uses_discard ||
1147 !c->s->info.fs.early_fragment_tests ||
1148 c->fs_key->sample_alpha_to_coverage ||
1149 !has_any_tlb_color_write) {
1150 /* Emit passthrough Z if it needed to be delayed until shader
1151 * end due to potential discards.
1152 *
1153 * Since (single-threaded) fragment shaders always need a TLB
1154 * write, emit passthrouh Z if we didn't have any color
1155 * buffers and flag us as potentially discarding, so that we
1156 * can use Z as the TLB write.
1157 */
1158 c->s->info.fs.uses_discard = true;
1159
1160 struct qinst *inst = vir_MOV_dest(c,
1161 vir_reg(QFILE_TLBU, 0),
1162 vir_reg(QFILE_NULL, 0));
1163 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1164
1165 if (c->devinfo->ver >= 42) {
1166 /* The spec says the PER_PIXEL flag is ignored for
1167 * invariant writes, but the simulator demands it.
1168 */
1169 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1170 TLB_SAMPLE_MODE_PER_PIXEL);
1171 } else {
1172 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1173 }
1174
1175 inst->src[vir_get_implicit_uniform_src(inst)] =
1176 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1177 c->writes_z = true;
1178 }
1179
1180 /* XXX: Performance improvement: Merge Z write and color writes TLB
1181 * uniform setup
1182 */
1183
1184 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1185 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1186 continue;
1187
1188 nir_variable *var = c->output_color_var[rt];
1189 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1190 int num_components = glsl_get_vector_elements(var->type);
1191 uint32_t conf = 0xffffff00;
1192 struct qinst *inst;
1193
1194 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1195 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1196
1197 if (c->fs_key->swap_color_rb & (1 << rt))
1198 num_components = MAX2(num_components, 3);
1199
1200 assert(num_components != 0);
1201 switch (glsl_get_base_type(var->type)) {
1202 case GLSL_TYPE_UINT:
1203 case GLSL_TYPE_INT:
1204 /* The F32 vs I32 distinction was dropped in 4.2. */
1205 if (c->devinfo->ver < 42)
1206 conf |= TLB_TYPE_I32_COLOR;
1207 else
1208 conf |= TLB_TYPE_F32_COLOR;
1209 conf |= ((num_components - 1) <<
1210 TLB_VEC_SIZE_MINUS_1_SHIFT);
1211
1212 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1213 inst->src[vir_get_implicit_uniform_src(inst)] =
1214 vir_uniform_ui(c, conf);
1215
1216 for (int i = 1; i < num_components; i++) {
1217 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1218 color[i]);
1219 }
1220 break;
1221
1222 default: {
1223 struct qreg r = color[0];
1224 struct qreg g = color[1];
1225 struct qreg b = color[2];
1226 struct qreg a = color[3];
1227
1228 if (c->fs_key->f32_color_rb & (1 << rt)) {
1229 conf |= TLB_TYPE_F32_COLOR;
1230 conf |= ((num_components - 1) <<
1231 TLB_VEC_SIZE_MINUS_1_SHIFT);
1232 } else {
1233 conf |= TLB_TYPE_F16_COLOR;
1234 conf |= TLB_F16_SWAP_HI_LO;
1235 if (num_components >= 3)
1236 conf |= TLB_VEC_SIZE_4_F16;
1237 else
1238 conf |= TLB_VEC_SIZE_2_F16;
1239 }
1240
1241 if (c->fs_key->swap_color_rb & (1 << rt)) {
1242 r = color[2];
1243 b = color[0];
1244 }
1245
1246 if (c->fs_key->sample_alpha_to_one)
1247 a = vir_uniform_f(c, 1.0);
1248
1249 if (c->fs_key->f32_color_rb & (1 << rt)) {
1250 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1251 inst->src[vir_get_implicit_uniform_src(inst)] =
1252 vir_uniform_ui(c, conf);
1253
1254 if (num_components >= 2)
1255 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1256 if (num_components >= 3)
1257 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1258 if (num_components >= 4)
1259 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1260 } else {
1261 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1262 if (conf != ~0) {
1263 inst->dst.file = QFILE_TLBU;
1264 inst->src[vir_get_implicit_uniform_src(inst)] =
1265 vir_uniform_ui(c, conf);
1266 }
1267
1268 if (num_components >= 3)
1269 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1270 }
1271 break;
1272 }
1273 }
1274 }
1275 }
1276
1277 static void
1278 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1279 {
1280 if (c->devinfo->ver >= 40) {
1281 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1282 *vpm_index = *vpm_index + 1;
1283 } else {
1284 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1285 }
1286
1287 c->num_vpm_writes++;
1288 }
1289
1290 static void
1291 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1292 uint32_t *vpm_index)
1293 {
1294 for (int i = 0; i < 2; i++) {
1295 struct qreg coord = c->outputs[c->output_position_index + i];
1296 coord = vir_FMUL(c, coord,
1297 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1298 0));
1299 coord = vir_FMUL(c, coord, rcp_w);
1300 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1301 }
1302
1303 }
1304
1305 static void
1306 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1307 {
1308 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1309 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1310
1311 struct qreg z = c->outputs[c->output_position_index + 2];
1312 z = vir_FMUL(c, z, zscale);
1313 z = vir_FMUL(c, z, rcp_w);
1314 z = vir_FADD(c, z, zoffset);
1315 vir_VPM_WRITE(c, z, vpm_index);
1316 }
1317
1318 static void
1319 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1320 {
1321 vir_VPM_WRITE(c, rcp_w, vpm_index);
1322 }
1323
1324 static void
1325 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1326 {
1327 struct qreg point_size;
1328
1329 if (c->output_point_size_index != -1)
1330 point_size = c->outputs[c->output_point_size_index];
1331 else
1332 point_size = vir_uniform_f(c, 1.0);
1333
1334 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1335 * BCM21553).
1336 */
1337 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1338
1339 vir_VPM_WRITE(c, point_size, vpm_index);
1340 }
1341
1342 static void
1343 emit_vpm_write_setup(struct v3d_compile *c)
1344 {
1345 if (c->devinfo->ver >= 40)
1346 return;
1347
1348 v3d33_vir_vpm_write_setup(c);
1349 }
1350
1351 /**
1352 * Sets up c->outputs[c->output_position_index] for the vertex shader
1353 * epilogue, if an output vertex position wasn't specified in the user's
1354 * shader. This may be the case for transform feedback with rasterizer
1355 * discard enabled.
1356 */
1357 static void
1358 setup_default_position(struct v3d_compile *c)
1359 {
1360 if (c->output_position_index != -1)
1361 return;
1362
1363 c->output_position_index = c->outputs_array_size;
1364 for (int i = 0; i < 4; i++) {
1365 add_output(c,
1366 c->output_position_index + i,
1367 VARYING_SLOT_POS, i);
1368 }
1369 }
1370
1371 static void
1372 emit_vert_end(struct v3d_compile *c)
1373 {
1374 setup_default_position(c);
1375
1376 uint32_t vpm_index = 0;
1377 struct qreg rcp_w = vir_RECIP(c,
1378 c->outputs[c->output_position_index + 3]);
1379
1380 emit_vpm_write_setup(c);
1381
1382 if (c->vs_key->is_coord) {
1383 for (int i = 0; i < 4; i++)
1384 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1385 &vpm_index);
1386 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1387 if (c->vs_key->per_vertex_point_size) {
1388 emit_point_size_write(c, &vpm_index);
1389 /* emit_rcp_wc_write(c, rcp_w); */
1390 }
1391 /* XXX: Z-only rendering */
1392 if (0)
1393 emit_zs_write(c, rcp_w, &vpm_index);
1394 } else {
1395 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1396 emit_zs_write(c, rcp_w, &vpm_index);
1397 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1398 if (c->vs_key->per_vertex_point_size)
1399 emit_point_size_write(c, &vpm_index);
1400 }
1401
1402 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1403 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1404 int j;
1405
1406 for (j = 0; j < c->num_outputs; j++) {
1407 struct v3d_varying_slot output = c->output_slots[j];
1408
1409 if (!memcmp(&input, &output, sizeof(input))) {
1410 vir_VPM_WRITE(c, c->outputs[j],
1411 &vpm_index);
1412 break;
1413 }
1414 }
1415 /* Emit padding if we didn't find a declared VS output for
1416 * this FS input.
1417 */
1418 if (j == c->num_outputs)
1419 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1420 &vpm_index);
1421 }
1422
1423 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1424 */
1425 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1426 vir_VPMWT(c);
1427 }
1428
1429 void
1430 v3d_optimize_nir(struct nir_shader *s)
1431 {
1432 bool progress;
1433
1434 do {
1435 progress = false;
1436
1437 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1438 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1439 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1440 NIR_PASS(progress, s, nir_copy_prop);
1441 NIR_PASS(progress, s, nir_opt_remove_phis);
1442 NIR_PASS(progress, s, nir_opt_dce);
1443 NIR_PASS(progress, s, nir_opt_dead_cf);
1444 NIR_PASS(progress, s, nir_opt_cse);
1445 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1446 NIR_PASS(progress, s, nir_opt_algebraic);
1447 NIR_PASS(progress, s, nir_opt_constant_folding);
1448 NIR_PASS(progress, s, nir_opt_undef);
1449 } while (progress);
1450
1451 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1452 }
1453
1454 static int
1455 driver_location_compare(const void *in_a, const void *in_b)
1456 {
1457 const nir_variable *const *a = in_a;
1458 const nir_variable *const *b = in_b;
1459
1460 return (*a)->data.driver_location - (*b)->data.driver_location;
1461 }
1462
1463 static struct qreg
1464 ntq_emit_vpm_read(struct v3d_compile *c,
1465 uint32_t *num_components_queued,
1466 uint32_t *remaining,
1467 uint32_t vpm_index)
1468 {
1469 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1470
1471 if (c->devinfo->ver >= 40 ) {
1472 return vir_LDVPMV_IN(c,
1473 vir_uniform_ui(c,
1474 (*num_components_queued)++));
1475 }
1476
1477 if (*num_components_queued != 0) {
1478 (*num_components_queued)--;
1479 c->num_inputs++;
1480 return vir_MOV(c, vpm);
1481 }
1482
1483 uint32_t num_components = MIN2(*remaining, 32);
1484
1485 v3d33_vir_vpm_read_setup(c, num_components);
1486
1487 *num_components_queued = num_components - 1;
1488 *remaining -= num_components;
1489 c->num_inputs++;
1490
1491 return vir_MOV(c, vpm);
1492 }
1493
1494 static void
1495 ntq_setup_vpm_inputs(struct v3d_compile *c)
1496 {
1497 /* Figure out how many components of each vertex attribute the shader
1498 * uses. Each variable should have been split to individual
1499 * components and unused ones DCEed. The vertex fetcher will load
1500 * from the start of the attribute to the number of components we
1501 * declare we need in c->vattr_sizes[].
1502 */
1503 nir_foreach_variable(var, &c->s->inputs) {
1504 /* No VS attribute array support. */
1505 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1506
1507 unsigned loc = var->data.driver_location;
1508 int start_component = var->data.location_frac;
1509 int num_components = glsl_get_components(var->type);
1510
1511 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1512 start_component + num_components);
1513 }
1514
1515 unsigned num_components = 0;
1516 uint32_t vpm_components_queued = 0;
1517 bool uses_iid = c->s->info.system_values_read &
1518 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1519 bool uses_vid = c->s->info.system_values_read &
1520 (1ull << SYSTEM_VALUE_VERTEX_ID);
1521 num_components += uses_iid;
1522 num_components += uses_vid;
1523
1524 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1525 num_components += c->vattr_sizes[i];
1526
1527 if (uses_iid) {
1528 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1529 &num_components, ~0);
1530 }
1531
1532 if (uses_vid) {
1533 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1534 &num_components, ~0);
1535 }
1536
1537 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1538 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1539 (loc + 1) * 4);
1540
1541 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1542 c->inputs[loc * 4 + i] =
1543 ntq_emit_vpm_read(c,
1544 &vpm_components_queued,
1545 &num_components,
1546 loc * 4 + i);
1547
1548 }
1549 }
1550
1551 if (c->devinfo->ver >= 40) {
1552 assert(vpm_components_queued == num_components);
1553 } else {
1554 assert(vpm_components_queued == 0);
1555 assert(num_components == 0);
1556 }
1557 }
1558
1559 static void
1560 ntq_setup_fs_inputs(struct v3d_compile *c)
1561 {
1562 unsigned num_entries = 0;
1563 unsigned num_components = 0;
1564 nir_foreach_variable(var, &c->s->inputs) {
1565 num_entries++;
1566 num_components += glsl_get_components(var->type);
1567 }
1568
1569 nir_variable *vars[num_entries];
1570
1571 unsigned i = 0;
1572 nir_foreach_variable(var, &c->s->inputs)
1573 vars[i++] = var;
1574
1575 /* Sort the variables so that we emit the input setup in
1576 * driver_location order. This is required for VPM reads, whose data
1577 * is fetched into the VPM in driver_location (TGSI register index)
1578 * order.
1579 */
1580 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1581
1582 for (unsigned i = 0; i < num_entries; i++) {
1583 nir_variable *var = vars[i];
1584 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1585 unsigned loc = var->data.driver_location;
1586
1587 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1588 (loc + array_len) * 4);
1589
1590 if (var->data.location == VARYING_SLOT_POS) {
1591 emit_fragcoord_input(c, loc);
1592 } else if (var->data.location == VARYING_SLOT_PNTC ||
1593 (var->data.location >= VARYING_SLOT_VAR0 &&
1594 (c->fs_key->point_sprite_mask &
1595 (1 << (var->data.location -
1596 VARYING_SLOT_VAR0))))) {
1597 c->inputs[loc * 4 + 0] = c->point_x;
1598 c->inputs[loc * 4 + 1] = c->point_y;
1599 } else {
1600 for (int j = 0; j < array_len; j++)
1601 emit_fragment_input(c, loc + j, var, j);
1602 }
1603 }
1604 }
1605
1606 static void
1607 ntq_setup_outputs(struct v3d_compile *c)
1608 {
1609 nir_foreach_variable(var, &c->s->outputs) {
1610 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1611 unsigned loc = var->data.driver_location * 4;
1612
1613 assert(array_len == 1);
1614 (void)array_len;
1615
1616 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1617 add_output(c, loc + var->data.location_frac + i,
1618 var->data.location,
1619 var->data.location_frac + i);
1620 }
1621
1622 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1623 switch (var->data.location) {
1624 case FRAG_RESULT_COLOR:
1625 c->output_color_var[0] = var;
1626 c->output_color_var[1] = var;
1627 c->output_color_var[2] = var;
1628 c->output_color_var[3] = var;
1629 break;
1630 case FRAG_RESULT_DATA0:
1631 case FRAG_RESULT_DATA1:
1632 case FRAG_RESULT_DATA2:
1633 case FRAG_RESULT_DATA3:
1634 c->output_color_var[var->data.location -
1635 FRAG_RESULT_DATA0] = var;
1636 break;
1637 case FRAG_RESULT_DEPTH:
1638 c->output_position_index = loc;
1639 break;
1640 case FRAG_RESULT_SAMPLE_MASK:
1641 c->output_sample_mask_index = loc;
1642 break;
1643 }
1644 } else {
1645 switch (var->data.location) {
1646 case VARYING_SLOT_POS:
1647 c->output_position_index = loc;
1648 break;
1649 case VARYING_SLOT_PSIZ:
1650 c->output_point_size_index = loc;
1651 break;
1652 }
1653 }
1654 }
1655 }
1656
1657 static void
1658 ntq_setup_uniforms(struct v3d_compile *c)
1659 {
1660 nir_foreach_variable(var, &c->s->uniforms) {
1661 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1662 false);
1663 unsigned vec4_size = 4 * sizeof(float);
1664
1665 if (var->data.mode != nir_var_uniform)
1666 continue;
1667
1668 declare_uniform_range(c, var->data.driver_location * vec4_size,
1669 vec4_count * vec4_size);
1670
1671 }
1672 }
1673
1674 /**
1675 * Sets up the mapping from nir_register to struct qreg *.
1676 *
1677 * Each nir_register gets a struct qreg per 32-bit component being stored.
1678 */
1679 static void
1680 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1681 {
1682 foreach_list_typed(nir_register, nir_reg, node, list) {
1683 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1684 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1685 array_len *
1686 nir_reg->num_components);
1687
1688 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1689
1690 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1691 qregs[i] = vir_get_temp(c);
1692 }
1693 }
1694
1695 static void
1696 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1697 {
1698 /* XXX perf: Experiment with using immediate loads to avoid having
1699 * these end up in the uniform stream. Watch out for breaking the
1700 * small immediates optimization in the process!
1701 */
1702 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1703 for (int i = 0; i < instr->def.num_components; i++)
1704 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1705
1706 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1707 }
1708
1709 static void
1710 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1711 {
1712 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1713
1714 /* VIR needs there to be *some* value, so pick 0 (same as for
1715 * ntq_setup_registers().
1716 */
1717 for (int i = 0; i < instr->def.num_components; i++)
1718 qregs[i] = vir_uniform_ui(c, 0);
1719 }
1720
1721 static void
1722 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1723 {
1724 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1725 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1726 unsigned image_index = var->data.driver_location;
1727 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1728 bool is_array = glsl_sampler_type_is_array(sampler_type);
1729
1730 ntq_store_dest(c, &instr->dest, 0,
1731 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1732 if (instr->num_components > 1) {
1733 ntq_store_dest(c, &instr->dest, 1,
1734 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1735 image_index));
1736 }
1737 if (instr->num_components > 2) {
1738 ntq_store_dest(c, &instr->dest, 2,
1739 vir_uniform(c,
1740 is_array ?
1741 QUNIFORM_IMAGE_ARRAY_SIZE :
1742 QUNIFORM_IMAGE_DEPTH,
1743 image_index));
1744 }
1745 }
1746
1747 static void
1748 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1749 {
1750 unsigned offset;
1751
1752 switch (instr->intrinsic) {
1753 case nir_intrinsic_load_uniform:
1754 if (nir_src_is_const(instr->src[0])) {
1755 int offset = (nir_intrinsic_base(instr) +
1756 nir_src_as_uint(instr->src[0]));
1757 assert(offset % 4 == 0);
1758 /* We need dwords */
1759 offset = offset / 4;
1760 for (int i = 0; i < instr->num_components; i++) {
1761 ntq_store_dest(c, &instr->dest, i,
1762 vir_uniform(c, QUNIFORM_UNIFORM,
1763 offset + i));
1764 }
1765 } else {
1766 ntq_emit_tmu_general(c, instr, false);
1767 }
1768 break;
1769
1770 case nir_intrinsic_load_ubo:
1771 ntq_emit_tmu_general(c, instr, false);
1772 break;
1773
1774 case nir_intrinsic_ssbo_atomic_add:
1775 case nir_intrinsic_ssbo_atomic_imin:
1776 case nir_intrinsic_ssbo_atomic_umin:
1777 case nir_intrinsic_ssbo_atomic_imax:
1778 case nir_intrinsic_ssbo_atomic_umax:
1779 case nir_intrinsic_ssbo_atomic_and:
1780 case nir_intrinsic_ssbo_atomic_or:
1781 case nir_intrinsic_ssbo_atomic_xor:
1782 case nir_intrinsic_ssbo_atomic_exchange:
1783 case nir_intrinsic_ssbo_atomic_comp_swap:
1784 case nir_intrinsic_load_ssbo:
1785 case nir_intrinsic_store_ssbo:
1786 ntq_emit_tmu_general(c, instr, false);
1787 break;
1788
1789 case nir_intrinsic_shared_atomic_add:
1790 case nir_intrinsic_shared_atomic_imin:
1791 case nir_intrinsic_shared_atomic_umin:
1792 case nir_intrinsic_shared_atomic_imax:
1793 case nir_intrinsic_shared_atomic_umax:
1794 case nir_intrinsic_shared_atomic_and:
1795 case nir_intrinsic_shared_atomic_or:
1796 case nir_intrinsic_shared_atomic_xor:
1797 case nir_intrinsic_shared_atomic_exchange:
1798 case nir_intrinsic_shared_atomic_comp_swap:
1799 case nir_intrinsic_load_shared:
1800 case nir_intrinsic_store_shared:
1801 ntq_emit_tmu_general(c, instr, true);
1802 break;
1803
1804 case nir_intrinsic_image_deref_load:
1805 case nir_intrinsic_image_deref_store:
1806 case nir_intrinsic_image_deref_atomic_add:
1807 case nir_intrinsic_image_deref_atomic_min:
1808 case nir_intrinsic_image_deref_atomic_max:
1809 case nir_intrinsic_image_deref_atomic_and:
1810 case nir_intrinsic_image_deref_atomic_or:
1811 case nir_intrinsic_image_deref_atomic_xor:
1812 case nir_intrinsic_image_deref_atomic_exchange:
1813 case nir_intrinsic_image_deref_atomic_comp_swap:
1814 v3d40_vir_emit_image_load_store(c, instr);
1815 break;
1816
1817 case nir_intrinsic_get_buffer_size:
1818 ntq_store_dest(c, &instr->dest, 0,
1819 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1820 nir_src_as_uint(instr->src[0])));
1821 break;
1822
1823 case nir_intrinsic_load_user_clip_plane:
1824 for (int i = 0; i < instr->num_components; i++) {
1825 ntq_store_dest(c, &instr->dest, i,
1826 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1827 nir_intrinsic_ucp_id(instr) *
1828 4 + i));
1829 }
1830 break;
1831
1832 case nir_intrinsic_load_alpha_ref_float:
1833 ntq_store_dest(c, &instr->dest, 0,
1834 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1835 break;
1836
1837 case nir_intrinsic_load_sample_mask_in:
1838 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1839 break;
1840
1841 case nir_intrinsic_load_helper_invocation:
1842 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1843 ntq_store_dest(c, &instr->dest, 0,
1844 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1845 vir_uniform_ui(c, ~0),
1846 vir_uniform_ui(c, 0))));
1847 break;
1848
1849 case nir_intrinsic_load_front_face:
1850 /* The register contains 0 (front) or 1 (back), and we need to
1851 * turn it into a NIR bool where true means front.
1852 */
1853 ntq_store_dest(c, &instr->dest, 0,
1854 vir_ADD(c,
1855 vir_uniform_ui(c, -1),
1856 vir_REVF(c)));
1857 break;
1858
1859 case nir_intrinsic_load_instance_id:
1860 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1861 break;
1862
1863 case nir_intrinsic_load_vertex_id:
1864 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1865 break;
1866
1867 case nir_intrinsic_load_input:
1868 for (int i = 0; i < instr->num_components; i++) {
1869 offset = (nir_intrinsic_base(instr) +
1870 nir_src_as_uint(instr->src[0]));
1871 int comp = nir_intrinsic_component(instr) + i;
1872 ntq_store_dest(c, &instr->dest, i,
1873 vir_MOV(c, c->inputs[offset * 4 + comp]));
1874 }
1875 break;
1876
1877 case nir_intrinsic_store_output:
1878 offset = ((nir_intrinsic_base(instr) +
1879 nir_src_as_uint(instr->src[1])) * 4 +
1880 nir_intrinsic_component(instr));
1881
1882 for (int i = 0; i < instr->num_components; i++) {
1883 c->outputs[offset + i] =
1884 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1885 }
1886 c->num_outputs = MAX2(c->num_outputs,
1887 offset + instr->num_components);
1888 break;
1889
1890 case nir_intrinsic_image_deref_size:
1891 ntq_emit_image_size(c, instr);
1892 break;
1893
1894 case nir_intrinsic_discard:
1895 if (c->execute.file != QFILE_NULL) {
1896 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1897 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1898 vir_uniform_ui(c, 0)),
1899 V3D_QPU_COND_IFA);
1900 } else {
1901 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1902 vir_uniform_ui(c, 0));
1903 }
1904 break;
1905
1906 case nir_intrinsic_discard_if: {
1907 /* true (~0) if we're discarding */
1908 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1909
1910 if (c->execute.file != QFILE_NULL) {
1911 /* execute == 0 means the channel is active. Invert
1912 * the condition so that we can use zero as "executing
1913 * and discarding."
1914 */
1915 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1916 V3D_QPU_PF_PUSHZ);
1917 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1918 vir_uniform_ui(c, 0)),
1919 V3D_QPU_COND_IFA);
1920 } else {
1921 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1922 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1923 vir_uniform_ui(c, 0)),
1924 V3D_QPU_COND_IFNA);
1925 }
1926
1927 break;
1928 }
1929
1930 case nir_intrinsic_memory_barrier:
1931 case nir_intrinsic_memory_barrier_atomic_counter:
1932 case nir_intrinsic_memory_barrier_buffer:
1933 case nir_intrinsic_memory_barrier_image:
1934 case nir_intrinsic_memory_barrier_shared:
1935 /* We don't do any instruction scheduling of these NIR
1936 * instructions between each other, so we just need to make
1937 * sure that the TMU operations before the barrier are flushed
1938 * before the ones after the barrier. That is currently
1939 * handled by having a THRSW in each of them and a LDTMU
1940 * series or a TMUWT after.
1941 */
1942 break;
1943
1944 case nir_intrinsic_barrier:
1945 /* Emit a TSY op to get all invocations in the workgroup
1946 * (actually supergroup) to block until the last invocation
1947 * reaches the TSY op.
1948 */
1949 if (c->devinfo->ver >= 42) {
1950 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1951 V3D_QPU_WADDR_SYNCB));
1952 } else {
1953 struct qinst *sync =
1954 vir_BARRIERID_dest(c,
1955 vir_reg(QFILE_MAGIC,
1956 V3D_QPU_WADDR_SYNCU));
1957 sync->src[vir_get_implicit_uniform_src(sync)] =
1958 vir_uniform_ui(c,
1959 0xffffff00 |
1960 V3D_TSY_WAIT_INC_CHECK);
1961
1962 }
1963
1964 /* The blocking of a TSY op only happens at the next thread
1965 * switch. No texturing may be outstanding at the time of a
1966 * TSY blocking operation.
1967 */
1968 vir_emit_thrsw(c);
1969 break;
1970
1971 case nir_intrinsic_load_num_work_groups:
1972 for (int i = 0; i < 3; i++) {
1973 ntq_store_dest(c, &instr->dest, i,
1974 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1975 i));
1976 }
1977 break;
1978
1979 case nir_intrinsic_load_local_invocation_index:
1980 ntq_store_dest(c, &instr->dest, 0,
1981 vir_SHR(c, c->cs_payload[1],
1982 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1983 break;
1984
1985 case nir_intrinsic_load_work_group_id:
1986 ntq_store_dest(c, &instr->dest, 0,
1987 vir_AND(c, c->cs_payload[0],
1988 vir_uniform_ui(c, 0xffff)));
1989 ntq_store_dest(c, &instr->dest, 1,
1990 vir_SHR(c, c->cs_payload[0],
1991 vir_uniform_ui(c, 16)));
1992 ntq_store_dest(c, &instr->dest, 2,
1993 vir_AND(c, c->cs_payload[1],
1994 vir_uniform_ui(c, 0xffff)));
1995 break;
1996
1997 default:
1998 fprintf(stderr, "Unknown intrinsic: ");
1999 nir_print_instr(&instr->instr, stderr);
2000 fprintf(stderr, "\n");
2001 break;
2002 }
2003 }
2004
2005 /* Clears (activates) the execute flags for any channels whose jump target
2006 * matches this block.
2007 *
2008 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2009 * enabling?
2010 *
2011 * XXX perf: For uniform control flow, we should be able to skip c->execute
2012 * handling entirely.
2013 */
2014 static void
2015 ntq_activate_execute_for_block(struct v3d_compile *c)
2016 {
2017 vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0),
2018 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2019 V3D_QPU_PF_PUSHZ);
2020
2021 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2022 }
2023
2024 static void
2025 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2026 {
2027 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2028 bool empty_else_block =
2029 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2030 exec_list_is_empty(&nir_else_block->instr_list));
2031
2032 struct qblock *then_block = vir_new_block(c);
2033 struct qblock *after_block = vir_new_block(c);
2034 struct qblock *else_block;
2035 if (empty_else_block)
2036 else_block = after_block;
2037 else
2038 else_block = vir_new_block(c);
2039
2040 /* Set up the flags for the IF condition (taking the THEN branch). */
2041 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2042 enum v3d_qpu_cond cond;
2043 if (!if_condition_alu ||
2044 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2045 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2046 V3D_QPU_PF_PUSHZ);
2047 cond = V3D_QPU_COND_IFNA;
2048 }
2049
2050 /* Jump to ELSE. */
2051 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2052 V3D_QPU_BRANCH_COND_ALLNA :
2053 V3D_QPU_BRANCH_COND_ALLA);
2054 vir_link_blocks(c->cur_block, else_block);
2055 vir_link_blocks(c->cur_block, then_block);
2056
2057 /* Process the THEN block. */
2058 vir_set_emit_block(c, then_block);
2059 ntq_emit_cf_list(c, &if_stmt->then_list);
2060
2061 if (!empty_else_block) {
2062 /* At the end of the THEN block, jump to ENDIF */
2063 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2064 vir_link_blocks(c->cur_block, after_block);
2065
2066 /* Emit the else block. */
2067 vir_set_emit_block(c, else_block);
2068 ntq_activate_execute_for_block(c);
2069 ntq_emit_cf_list(c, &if_stmt->else_list);
2070 }
2071
2072 vir_link_blocks(c->cur_block, after_block);
2073
2074 vir_set_emit_block(c, after_block);
2075 }
2076
2077 static void
2078 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2079 {
2080 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2081 bool empty_else_block =
2082 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2083 exec_list_is_empty(&nir_else_block->instr_list));
2084
2085 struct qblock *then_block = vir_new_block(c);
2086 struct qblock *after_block = vir_new_block(c);
2087 struct qblock *else_block;
2088 if (empty_else_block)
2089 else_block = after_block;
2090 else
2091 else_block = vir_new_block(c);
2092
2093 bool was_top_level = false;
2094 if (c->execute.file == QFILE_NULL) {
2095 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2096 was_top_level = true;
2097 }
2098
2099 /* Set up the flags for the IF condition (taking the THEN branch). */
2100 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2101 enum v3d_qpu_cond cond;
2102 if (!if_condition_alu ||
2103 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2104 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2105 V3D_QPU_PF_PUSHZ);
2106 cond = V3D_QPU_COND_IFNA;
2107 }
2108
2109 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2110 * was previously active (execute Z) for updating the exec flags.
2111 */
2112 if (was_top_level) {
2113 cond = v3d_qpu_cond_invert(cond);
2114 } else {
2115 struct qinst *inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0),
2116 c->execute);
2117 if (cond == V3D_QPU_COND_IFA) {
2118 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2119 } else {
2120 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2121 cond = V3D_QPU_COND_IFA;
2122 }
2123 }
2124
2125 vir_MOV_cond(c, cond,
2126 c->execute,
2127 vir_uniform_ui(c, else_block->index));
2128
2129 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2130 * through.
2131 */
2132 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2133 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2134 vir_link_blocks(c->cur_block, else_block);
2135 vir_link_blocks(c->cur_block, then_block);
2136
2137 /* Process the THEN block. */
2138 vir_set_emit_block(c, then_block);
2139 ntq_emit_cf_list(c, &if_stmt->then_list);
2140
2141 if (!empty_else_block) {
2142 /* Handle the end of the THEN block. First, all currently
2143 * active channels update their execute flags to point to
2144 * ENDIF
2145 */
2146 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2147 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2148 vir_uniform_ui(c, after_block->index));
2149
2150 /* If everything points at ENDIF, then jump there immediately. */
2151 vir_PF(c, vir_XOR(c, c->execute,
2152 vir_uniform_ui(c, after_block->index)),
2153 V3D_QPU_PF_PUSHZ);
2154 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2155 vir_link_blocks(c->cur_block, after_block);
2156 vir_link_blocks(c->cur_block, else_block);
2157
2158 vir_set_emit_block(c, else_block);
2159 ntq_activate_execute_for_block(c);
2160 ntq_emit_cf_list(c, &if_stmt->else_list);
2161 }
2162
2163 vir_link_blocks(c->cur_block, after_block);
2164
2165 vir_set_emit_block(c, after_block);
2166 if (was_top_level)
2167 c->execute = c->undef;
2168 else
2169 ntq_activate_execute_for_block(c);
2170 }
2171
2172 static void
2173 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2174 {
2175 if (c->execute.file == QFILE_NULL &&
2176 nir_src_is_dynamically_uniform(nif->condition)) {
2177 ntq_emit_uniform_if(c, nif);
2178 } else {
2179 ntq_emit_nonuniform_if(c, nif);
2180 }
2181 }
2182
2183 static void
2184 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2185 {
2186 switch (jump->type) {
2187 case nir_jump_break:
2188 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2189 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2190 vir_uniform_ui(c, c->loop_break_block->index));
2191 break;
2192
2193 case nir_jump_continue:
2194 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2195 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2196 vir_uniform_ui(c, c->loop_cont_block->index));
2197 break;
2198
2199 case nir_jump_return:
2200 unreachable("All returns shouold be lowered\n");
2201 }
2202 }
2203
2204 static void
2205 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2206 {
2207 switch (instr->type) {
2208 case nir_instr_type_deref:
2209 /* ignored, will be walked by the intrinsic using it. */
2210 break;
2211
2212 case nir_instr_type_alu:
2213 ntq_emit_alu(c, nir_instr_as_alu(instr));
2214 break;
2215
2216 case nir_instr_type_intrinsic:
2217 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2218 break;
2219
2220 case nir_instr_type_load_const:
2221 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2222 break;
2223
2224 case nir_instr_type_ssa_undef:
2225 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2226 break;
2227
2228 case nir_instr_type_tex:
2229 ntq_emit_tex(c, nir_instr_as_tex(instr));
2230 break;
2231
2232 case nir_instr_type_jump:
2233 ntq_emit_jump(c, nir_instr_as_jump(instr));
2234 break;
2235
2236 default:
2237 fprintf(stderr, "Unknown NIR instr type: ");
2238 nir_print_instr(instr, stderr);
2239 fprintf(stderr, "\n");
2240 abort();
2241 }
2242 }
2243
2244 static void
2245 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2246 {
2247 nir_foreach_instr(instr, block) {
2248 ntq_emit_instr(c, instr);
2249 }
2250 }
2251
2252 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2253
2254 static void
2255 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2256 {
2257 bool was_top_level = false;
2258 if (c->execute.file == QFILE_NULL) {
2259 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2260 was_top_level = true;
2261 }
2262
2263 struct qblock *save_loop_cont_block = c->loop_cont_block;
2264 struct qblock *save_loop_break_block = c->loop_break_block;
2265
2266 c->loop_cont_block = vir_new_block(c);
2267 c->loop_break_block = vir_new_block(c);
2268
2269 vir_link_blocks(c->cur_block, c->loop_cont_block);
2270 vir_set_emit_block(c, c->loop_cont_block);
2271 ntq_activate_execute_for_block(c);
2272
2273 ntq_emit_cf_list(c, &loop->body);
2274
2275 /* Re-enable any previous continues now, so our ANYA check below
2276 * works.
2277 *
2278 * XXX: Use the .ORZ flags update, instead.
2279 */
2280 vir_PF(c, vir_XOR(c,
2281 c->execute,
2282 vir_uniform_ui(c, c->loop_cont_block->index)),
2283 V3D_QPU_PF_PUSHZ);
2284 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2285
2286 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2287
2288 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2289 /* Pixels that were not dispatched or have been discarded should not
2290 * contribute to looping again.
2291 */
2292 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2293 vir_link_blocks(c->cur_block, c->loop_cont_block);
2294 vir_link_blocks(c->cur_block, c->loop_break_block);
2295
2296 vir_set_emit_block(c, c->loop_break_block);
2297 if (was_top_level)
2298 c->execute = c->undef;
2299 else
2300 ntq_activate_execute_for_block(c);
2301
2302 c->loop_break_block = save_loop_break_block;
2303 c->loop_cont_block = save_loop_cont_block;
2304
2305 c->loops++;
2306 }
2307
2308 static void
2309 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2310 {
2311 fprintf(stderr, "FUNCTIONS not handled.\n");
2312 abort();
2313 }
2314
2315 static void
2316 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2317 {
2318 foreach_list_typed(nir_cf_node, node, node, list) {
2319 switch (node->type) {
2320 case nir_cf_node_block:
2321 ntq_emit_block(c, nir_cf_node_as_block(node));
2322 break;
2323
2324 case nir_cf_node_if:
2325 ntq_emit_if(c, nir_cf_node_as_if(node));
2326 break;
2327
2328 case nir_cf_node_loop:
2329 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2330 break;
2331
2332 case nir_cf_node_function:
2333 ntq_emit_function(c, nir_cf_node_as_function(node));
2334 break;
2335
2336 default:
2337 fprintf(stderr, "Unknown NIR node type\n");
2338 abort();
2339 }
2340 }
2341 }
2342
2343 static void
2344 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2345 {
2346 ntq_setup_registers(c, &impl->registers);
2347 ntq_emit_cf_list(c, &impl->body);
2348 }
2349
2350 static void
2351 nir_to_vir(struct v3d_compile *c)
2352 {
2353 switch (c->s->info.stage) {
2354 case MESA_SHADER_FRAGMENT:
2355 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2356 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2357 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2358
2359 /* XXX perf: We could set the "disable implicit point/line
2360 * varyings" field in the shader record and not emit these, if
2361 * they're not going to be used.
2362 */
2363 if (c->fs_key->is_points) {
2364 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2365 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2366 } else if (c->fs_key->is_lines) {
2367 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2368 }
2369 break;
2370 case MESA_SHADER_COMPUTE:
2371 /* Set up the TSO for barriers, assuming we do some. */
2372 if (c->devinfo->ver < 42) {
2373 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2374 V3D_QPU_WADDR_SYNC));
2375 }
2376
2377 if (c->s->info.system_values_read &
2378 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2379 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2380 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2381 }
2382 if ((c->s->info.system_values_read &
2383 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2384 c->s->info.cs.shared_size) {
2385 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2386 }
2387
2388 /* Set up the division between gl_LocalInvocationIndex and
2389 * wg_in_mem in the payload reg.
2390 */
2391 int wg_size = (c->s->info.cs.local_size[0] *
2392 c->s->info.cs.local_size[1] *
2393 c->s->info.cs.local_size[2]);
2394 c->local_invocation_index_bits =
2395 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2396 assert(c->local_invocation_index_bits <= 8);
2397
2398 if (c->s->info.cs.shared_size) {
2399 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2400 vir_uniform_ui(c, 16));
2401 if (c->s->info.cs.local_size[0] != 1 ||
2402 c->s->info.cs.local_size[1] != 1 ||
2403 c->s->info.cs.local_size[2] != 1) {
2404 int wg_bits = (16 -
2405 c->local_invocation_index_bits);
2406 int wg_mask = (1 << wg_bits) - 1;
2407 wg_in_mem = vir_AND(c, wg_in_mem,
2408 vir_uniform_ui(c, wg_mask));
2409 }
2410 struct qreg shared_per_wg =
2411 vir_uniform_ui(c, c->s->info.cs.shared_size);
2412
2413 c->cs_shared_offset =
2414 vir_ADD(c,
2415 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2416 vir_UMUL(c, wg_in_mem, shared_per_wg));
2417 }
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2424 ntq_setup_fs_inputs(c);
2425 else
2426 ntq_setup_vpm_inputs(c);
2427
2428 ntq_setup_outputs(c);
2429 ntq_setup_uniforms(c);
2430 ntq_setup_registers(c, &c->s->registers);
2431
2432 /* Find the main function and emit the body. */
2433 nir_foreach_function(function, c->s) {
2434 assert(strcmp(function->name, "main") == 0);
2435 assert(function->impl);
2436 ntq_emit_impl(c, function->impl);
2437 }
2438 }
2439
2440 const nir_shader_compiler_options v3d_nir_options = {
2441 .lower_all_io_to_temps = true,
2442 .lower_extract_byte = true,
2443 .lower_extract_word = true,
2444 .lower_bfm = true,
2445 .lower_bitfield_insert_to_shifts = true,
2446 .lower_bitfield_extract_to_shifts = true,
2447 .lower_bitfield_reverse = true,
2448 .lower_bit_count = true,
2449 .lower_cs_local_id_from_index = true,
2450 .lower_pack_unorm_2x16 = true,
2451 .lower_pack_snorm_2x16 = true,
2452 .lower_pack_unorm_4x8 = true,
2453 .lower_pack_snorm_4x8 = true,
2454 .lower_unpack_unorm_4x8 = true,
2455 .lower_unpack_snorm_4x8 = true,
2456 .lower_pack_half_2x16 = true,
2457 .lower_unpack_half_2x16 = true,
2458 .lower_fdiv = true,
2459 .lower_find_lsb = true,
2460 .lower_ffma = true,
2461 .lower_flrp32 = true,
2462 .lower_fpow = true,
2463 .lower_fsat = true,
2464 .lower_fsqrt = true,
2465 .lower_ifind_msb = true,
2466 .lower_isign = true,
2467 .lower_ldexp = true,
2468 .lower_mul_high = true,
2469 .lower_wpos_pntc = true,
2470 .native_integers = true,
2471 };
2472
2473 /**
2474 * When demoting a shader down to single-threaded, removes the THRSW
2475 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2476 * program end).
2477 */
2478 static void
2479 vir_remove_thrsw(struct v3d_compile *c)
2480 {
2481 vir_for_each_block(block, c) {
2482 vir_for_each_inst_safe(inst, block) {
2483 if (inst->qpu.sig.thrsw)
2484 vir_remove_instruction(c, inst);
2485 }
2486 }
2487
2488 c->last_thrsw = NULL;
2489 }
2490
2491 void
2492 vir_emit_last_thrsw(struct v3d_compile *c)
2493 {
2494 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2495 * switching, so disable threads if we didn't do any TMU ops (each of
2496 * which would have emitted a THRSW).
2497 */
2498 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2499 c->threads = 1;
2500 if (c->last_thrsw)
2501 vir_remove_thrsw(c);
2502 return;
2503 }
2504
2505 /* If we're threaded and the last THRSW was in conditional code, then
2506 * we need to emit another one so that we can flag it as the last
2507 * thrsw.
2508 */
2509 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2510 assert(c->devinfo->ver >= 41);
2511 vir_emit_thrsw(c);
2512 }
2513
2514 /* If we're threaded, then we need to mark the last THRSW instruction
2515 * so we can emit a pair of them at QPU emit time.
2516 *
2517 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2518 * post-last-THRSW state, so we can skip this.
2519 */
2520 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2521 assert(c->devinfo->ver >= 41);
2522 vir_emit_thrsw(c);
2523 }
2524
2525 if (c->last_thrsw)
2526 c->last_thrsw->is_last_thrsw = true;
2527 }
2528
2529 /* There's a flag in the shader for "center W is needed for reasons other than
2530 * non-centroid varyings", so we just walk the program after VIR optimization
2531 * to see if it's used. It should be harmless to set even if we only use
2532 * center W for varyings.
2533 */
2534 static void
2535 vir_check_payload_w(struct v3d_compile *c)
2536 {
2537 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2538 return;
2539
2540 vir_for_each_inst_inorder(inst, c) {
2541 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2542 if (inst->src[i].file == QFILE_REG &&
2543 inst->src[i].index == 0) {
2544 c->uses_center_w = true;
2545 return;
2546 }
2547 }
2548 }
2549
2550 }
2551
2552 void
2553 v3d_nir_to_vir(struct v3d_compile *c)
2554 {
2555 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2556 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2557 fprintf(stderr, "%s prog %d/%d NIR:\n",
2558 vir_get_stage_name(c),
2559 c->program_id, c->variant_id);
2560 nir_print_shader(c->s, stderr);
2561 }
2562
2563 nir_to_vir(c);
2564
2565 /* Emit the last THRSW before STVPM and TLB writes. */
2566 vir_emit_last_thrsw(c);
2567
2568 switch (c->s->info.stage) {
2569 case MESA_SHADER_FRAGMENT:
2570 emit_frag_end(c);
2571 break;
2572 case MESA_SHADER_VERTEX:
2573 emit_vert_end(c);
2574 break;
2575 default:
2576 unreachable("bad stage");
2577 }
2578
2579 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2580 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2581 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2582 vir_get_stage_name(c),
2583 c->program_id, c->variant_id);
2584 vir_dump(c);
2585 fprintf(stderr, "\n");
2586 }
2587
2588 vir_optimize(c);
2589 vir_lower_uniforms(c);
2590
2591 vir_check_payload_w(c);
2592
2593 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2594 * We used that on that platform to pipeline TMU writes and reduce the
2595 * number of thread switches, as well as try (mostly successfully) to
2596 * reduce maximum register pressure to allow more threads. We should
2597 * do something of that sort for V3D -- either instruction scheduling
2598 * here, or delay the the THRSW and LDTMUs from our texture
2599 * instructions until the results are needed.
2600 */
2601
2602 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2603 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2604 fprintf(stderr, "%s prog %d/%d VIR:\n",
2605 vir_get_stage_name(c),
2606 c->program_id, c->variant_id);
2607 vir_dump(c);
2608 fprintf(stderr, "\n");
2609 }
2610
2611 /* Attempt to allocate registers for the temporaries. If we fail,
2612 * reduce thread count and try again.
2613 */
2614 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2615 struct qpu_reg *temp_registers;
2616 while (true) {
2617 bool spilled;
2618 temp_registers = v3d_register_allocate(c, &spilled);
2619 if (spilled)
2620 continue;
2621
2622 if (temp_registers)
2623 break;
2624
2625 if (c->threads == min_threads) {
2626 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2627 c->threads);
2628 vir_dump(c);
2629 c->failed = true;
2630 return;
2631 }
2632
2633 c->threads /= 2;
2634
2635 if (c->threads == 1)
2636 vir_remove_thrsw(c);
2637 }
2638
2639 v3d_vir_to_qpu(c, temp_registers);
2640 }