projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
78 {
79 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
80 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
81 }
82
83 static struct qreg
84 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
85 {
86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
87 uint32_t offset = nir_intrinsic_base(intr);
88 struct v3d_ubo_range *range = NULL;
89 unsigned i;
90
91 for (i = 0; i < c->num_ubo_ranges; i++) {
92 range = &c->ubo_ranges[i];
93 if (offset >= range->src_offset &&
94 offset < range->src_offset + range->size) {
95 break;
96 }
97 }
98 /* The driver-location-based offset always has to be within a declared
99 * uniform range.
100 */
101 assert(i != c->num_ubo_ranges);
102 if (!c->ubo_range_used[i]) {
103 c->ubo_range_used[i] = true;
104 range->dst_offset = c->next_ubo_dst_offset;
105 c->next_ubo_dst_offset += range->size;
106 }
107
108 offset -= range->src_offset;
109
110 if (range->dst_offset + offset != 0) {
111 indirect_offset = vir_ADD(c, indirect_offset,
112 vir_uniform_ui(c, range->dst_offset +
113 offset));
114 }
115
116 /* Adjust for where we stored the TGSI register base. */
117 vir_ADD_dest(c,
118 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
119 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
120 indirect_offset);
121
122 vir_emit_thrsw(c);
123 return vir_LDTMU(c);
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 /**
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
138 *
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
140 * the new result.
141 *
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
149 */
150 void
151 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
152 struct qreg result)
153 {
154 struct qinst *last_inst = NULL;
155 if (!list_empty(&c->cur_block->instructions))
156 last_inst = (struct qinst *)c->cur_block->instructions.prev;
157
158 assert(result.file == QFILE_UNIF ||
159 (result.file == QFILE_TEMP &&
160 last_inst && last_inst == c->defs[result.index]));
161
162 if (dest->is_ssa) {
163 assert(chan < dest->ssa.num_components);
164
165 struct qreg *qregs;
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, &dest->ssa);
168
169 if (entry)
170 qregs = entry->data;
171 else
172 qregs = ntq_init_ssa_def(c, &dest->ssa);
173
174 qregs[chan] = result;
175 } else {
176 nir_register *reg = dest->reg.reg;
177 assert(dest->reg.base_offset == 0);
178 assert(reg->num_array_elems == 0);
179 struct hash_entry *entry =
180 _mesa_hash_table_search(c->def_ht, reg);
181 struct qreg *qregs = entry->data;
182
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
185 */
186 if (result.file == QFILE_UNIF) {
187 result = vir_MOV(c, result);
188 last_inst = c->defs[result.index];
189 }
190
191 /* We know they're both temps, so just rewrite index. */
192 c->defs[last_inst->dst.index] = NULL;
193 last_inst->dst.index = qregs[chan].index;
194
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
197 */
198 if (c->execute.file != QFILE_NULL) {
199 last_inst->dst.index = qregs[chan].index;
200
201 /* Set the flags to the current exec mask.
202 */
203 c->cursor = vir_before_inst(last_inst);
204 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
205 c->cursor = vir_after_inst(last_inst);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
257 {
258 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
259 }
260
261 static void
262 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
263 {
264 unsigned unit = instr->texture_index;
265 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
266 int dest_size = nir_tex_instr_dest_size(instr);
267
268 struct qreg lod = c->undef;
269 if (lod_index != -1)
270 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
271
272 for (int i = 0; i < dest_size; i++) {
273 assert(i < 3);
274 enum quniform_contents contents;
275
276 if (instr->is_array && i == dest_size - 1)
277 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
278 else
279 contents = QUNIFORM_TEXTURE_WIDTH + i;
280
281 struct qreg size = vir_uniform(c, contents, unit);
282
283 switch (instr->sampler_dim) {
284 case GLSL_SAMPLER_DIM_1D:
285 case GLSL_SAMPLER_DIM_2D:
286 case GLSL_SAMPLER_DIM_3D:
287 case GLSL_SAMPLER_DIM_CUBE:
288 /* Don't minify the array size. */
289 if (!(instr->is_array && i == dest_size - 1)) {
290 size = ntq_minify(c, size, lod);
291 }
292 break;
293
294 case GLSL_SAMPLER_DIM_RECT:
295 /* There's no LOD field for rects */
296 break;
297
298 default:
299 unreachable("Bad sampler type");
300 }
301
302 ntq_store_dest(c, &instr->dest, i, size);
303 }
304 }
305
306 static void
307 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
308 {
309 unsigned unit = instr->texture_index;
310
311 /* Since each texture sampling op requires uploading uniforms to
312 * reference the texture, there's no HW support for texture size and
313 * you just upload uniforms containing the size.
314 */
315 switch (instr->op) {
316 case nir_texop_query_levels:
317 ntq_store_dest(c, &instr->dest, 0,
318 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
319 return;
320 case nir_texop_txs:
321 ntq_emit_txs(c, instr);
322 return;
323 default:
324 break;
325 }
326
327 if (c->devinfo->ver >= 40)
328 v3d40_vir_emit_tex(c, instr);
329 else
330 v3d33_vir_emit_tex(c, instr);
331 }
332
333 static struct qreg
334 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
335 {
336 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
337 if (is_cos)
338 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
339
340 struct qreg periods = vir_FROUND(c, input);
341 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
342 vir_FSUB(c, input, periods));
343 return vir_XOR(c, sin_output, vir_SHL(c,
344 vir_FTOIN(c, periods),
345 vir_uniform_ui(c, -1)));
346 }
347
348 static struct qreg
349 ntq_fsign(struct v3d_compile *c, struct qreg src)
350 {
351 struct qreg t = vir_get_temp(c);
352
353 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
354 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
355 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
356 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
357 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
358 return vir_MOV(c, t);
359 }
360
361 static struct qreg
362 ntq_isign(struct v3d_compile *c, struct qreg src)
363 {
364 struct qreg t = vir_get_temp(c);
365
366 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
367 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
368 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
369 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
370 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
371 return vir_MOV(c, t);
372 }
373
374 static void
375 emit_fragcoord_input(struct v3d_compile *c, int attr)
376 {
377 c->inputs[attr * 4 + 0] = vir_FXCD(c);
378 c->inputs[attr * 4 + 1] = vir_FYCD(c);
379 c->inputs[attr * 4 + 2] = c->payload_z;
380 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
381 c->payload_w);
382 }
383
384 static struct qreg
385 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
386 uint8_t swizzle)
387 {
388 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
389 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
390
391 struct qreg vary;
392 if (c->devinfo->ver >= 41) {
393 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
394 c->undef, c->undef);
395 ldvary->qpu.sig.ldvary = true;
396 vary = vir_emit_def(c, ldvary);
397 } else {
398 vir_NOP(c)->qpu.sig.ldvary = true;
399 vary = r3;
400 }
401
402 /* For gl_PointCoord input or distance along a line, we'll be called
403 * with no nir_variable, and we don't count toward VPM size so we
404 * don't track an input slot.
405 */
406 if (!var) {
407 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
408 }
409
410 int i = c->num_inputs++;
411 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
412 swizzle);
413
414 switch (var->data.interpolation) {
415 case INTERP_MODE_NONE:
416 /* If a gl_FrontColor or gl_BackColor input has no interp
417 * qualifier, then if we're using glShadeModel(GL_FLAT) it
418 * needs to be flat shaded.
419 */
420 switch (var->data.location) {
421 case VARYING_SLOT_COL0:
422 case VARYING_SLOT_COL1:
423 case VARYING_SLOT_BFC0:
424 case VARYING_SLOT_BFC1:
425 if (c->fs_key->shade_model_flat) {
426 BITSET_SET(c->flat_shade_flags, i);
427 vir_MOV_dest(c, c->undef, vary);
428 return vir_MOV(c, r5);
429 } else {
430 return vir_FADD(c, vir_FMUL(c, vary,
431 c->payload_w), r5);
432 }
433 default:
434 break;
435 }
436 /* FALLTHROUGH */
437 case INTERP_MODE_SMOOTH:
438 if (var->data.centroid) {
439 return vir_FADD(c, vir_FMUL(c, vary,
440 c->payload_w_centroid), r5);
441 } else {
442 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
443 }
444 case INTERP_MODE_NOPERSPECTIVE:
445 /* C appears after the mov from the varying.
446 XXX: improve ldvary setup.
447 */
448 return vir_FADD(c, vir_MOV(c, vary), r5);
449 case INTERP_MODE_FLAT:
450 BITSET_SET(c->flat_shade_flags, i);
451 vir_MOV_dest(c, c->undef, vary);
452 return vir_MOV(c, r5);
453 default:
454 unreachable("Bad interp mode");
455 }
456 }
457
458 static void
459 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
460 {
461 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
462 int chan = var->data.location_frac + i;
463 c->inputs[attr * 4 + chan] =
464 emit_fragment_varying(c, var, chan);
465 }
466 }
467
468 static void
469 add_output(struct v3d_compile *c,
470 uint32_t decl_offset,
471 uint8_t slot,
472 uint8_t swizzle)
473 {
474 uint32_t old_array_size = c->outputs_array_size;
475 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
476 decl_offset + 1);
477
478 if (old_array_size != c->outputs_array_size) {
479 c->output_slots = reralloc(c,
480 c->output_slots,
481 struct v3d_varying_slot,
482 c->outputs_array_size);
483 }
484
485 c->output_slots[decl_offset] =
486 v3d_slot_from_slot_and_component(slot, swizzle);
487 }
488
489 static void
490 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
491 {
492 unsigned array_id = c->num_ubo_ranges++;
493 if (array_id >= c->ubo_ranges_array_size) {
494 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
495 array_id + 1);
496 c->ubo_ranges = reralloc(c, c->ubo_ranges,
497 struct v3d_ubo_range,
498 c->ubo_ranges_array_size);
499 c->ubo_range_used = reralloc(c, c->ubo_range_used,
500 bool,
501 c->ubo_ranges_array_size);
502 }
503
504 c->ubo_ranges[array_id].dst_offset = 0;
505 c->ubo_ranges[array_id].src_offset = start;
506 c->ubo_ranges[array_id].size = size;
507 c->ubo_range_used[array_id] = false;
508 }
509
510 /**
511 * If compare_instr is a valid comparison instruction, emits the
512 * compare_instr's comparison and returns the sel_instr's return value based
513 * on the compare_instr's result.
514 */
515 static bool
516 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
517 nir_alu_instr *compare_instr,
518 nir_alu_instr *sel_instr)
519 {
520 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
521 struct qreg src1;
522 if (nir_op_infos[compare_instr->op].num_inputs > 1)
523 src1 = ntq_get_alu_src(c, compare_instr, 1);
524 bool cond_invert = false;
525
526 switch (compare_instr->op) {
527 case nir_op_feq:
528 case nir_op_seq:
529 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
530 break;
531 case nir_op_ieq:
532 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
533 break;
534
535 case nir_op_fne:
536 case nir_op_sne:
537 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
538 cond_invert = true;
539 break;
540 case nir_op_ine:
541 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
542 cond_invert = true;
543 break;
544
545 case nir_op_fge:
546 case nir_op_sge:
547 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
548 break;
549 case nir_op_ige:
550 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
551 cond_invert = true;
552 break;
553 case nir_op_uge:
554 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
555 cond_invert = true;
556 break;
557
558 case nir_op_slt:
559 case nir_op_flt:
560 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
561 break;
562 case nir_op_ilt:
563 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
564 break;
565 case nir_op_ult:
566 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
567 break;
568
569 default:
570 return false;
571 }
572
573 enum v3d_qpu_cond cond = (cond_invert ?
574 V3D_QPU_COND_IFNA :
575 V3D_QPU_COND_IFA);
576
577 switch (sel_instr->op) {
578 case nir_op_seq:
579 case nir_op_sne:
580 case nir_op_sge:
581 case nir_op_slt:
582 *dest = vir_SEL(c, cond,
583 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
584 break;
585
586 case nir_op_bcsel:
587 *dest = vir_SEL(c, cond,
588 ntq_get_alu_src(c, sel_instr, 1),
589 ntq_get_alu_src(c, sel_instr, 2));
590 break;
591
592 default:
593 *dest = vir_SEL(c, cond,
594 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
595 break;
596 }
597
598 /* Make the temporary for nir_store_dest(). */
599 *dest = vir_MOV(c, *dest);
600
601 return true;
602 }
603
604 /**
605 * Attempts to fold a comparison generating a boolean result into the
606 * condition code for selecting between two values, instead of comparing the
607 * boolean result against 0 to generate the condition code.
608 */
609 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
610 struct qreg *src)
611 {
612 if (!instr->src[0].src.is_ssa)
613 goto out;
614 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
615 goto out;
616 nir_alu_instr *compare =
617 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
618 if (!compare)
619 goto out;
620
621 struct qreg dest;
622 if (ntq_emit_comparison(c, &dest, compare, instr))
623 return dest;
624
625 out:
626 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
627 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
628 }
629
630
631 static void
632 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
633 {
634 /* This should always be lowered to ALU operations for V3D. */
635 assert(!instr->dest.saturate);
636
637 /* Vectors are special in that they have non-scalarized writemasks,
638 * and just take the first swizzle channel for each argument in order
639 * into each writemask channel.
640 */
641 if (instr->op == nir_op_vec2 ||
642 instr->op == nir_op_vec3 ||
643 instr->op == nir_op_vec4) {
644 struct qreg srcs[4];
645 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
646 srcs[i] = ntq_get_src(c, instr->src[i].src,
647 instr->src[i].swizzle[0]);
648 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
649 ntq_store_dest(c, &instr->dest.dest, i,
650 vir_MOV(c, srcs[i]));
651 return;
652 }
653
654 /* General case: We can just grab the one used channel per src. */
655 struct qreg src[nir_op_infos[instr->op].num_inputs];
656 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
657 src[i] = ntq_get_alu_src(c, instr, i);
658 }
659
660 struct qreg result;
661
662 switch (instr->op) {
663 case nir_op_fmov:
664 case nir_op_imov:
665 result = vir_MOV(c, src[0]);
666 break;
667
668 case nir_op_fneg:
669 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
670 break;
671 case nir_op_ineg:
672 result = vir_NEG(c, src[0]);
673 break;
674
675 case nir_op_fmul:
676 result = vir_FMUL(c, src[0], src[1]);
677 break;
678 case nir_op_fadd:
679 result = vir_FADD(c, src[0], src[1]);
680 break;
681 case nir_op_fsub:
682 result = vir_FSUB(c, src[0], src[1]);
683 break;
684 case nir_op_fmin:
685 result = vir_FMIN(c, src[0], src[1]);
686 break;
687 case nir_op_fmax:
688 result = vir_FMAX(c, src[0], src[1]);
689 break;
690
691 case nir_op_f2i32:
692 result = vir_FTOIZ(c, src[0]);
693 break;
694 case nir_op_f2u32:
695 result = vir_FTOUZ(c, src[0]);
696 break;
697 case nir_op_i2f32:
698 result = vir_ITOF(c, src[0]);
699 break;
700 case nir_op_u2f32:
701 result = vir_UTOF(c, src[0]);
702 break;
703 case nir_op_b2f:
704 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
705 break;
706 case nir_op_b2i:
707 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
708 break;
709 case nir_op_i2b:
710 case nir_op_f2b:
711 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
712 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
713 vir_uniform_ui(c, ~0),
714 vir_uniform_ui(c, 0)));
715 break;
716
717 case nir_op_iadd:
718 result = vir_ADD(c, src[0], src[1]);
719 break;
720 case nir_op_ushr:
721 result = vir_SHR(c, src[0], src[1]);
722 break;
723 case nir_op_isub:
724 result = vir_SUB(c, src[0], src[1]);
725 break;
726 case nir_op_ishr:
727 result = vir_ASR(c, src[0], src[1]);
728 break;
729 case nir_op_ishl:
730 result = vir_SHL(c, src[0], src[1]);
731 break;
732 case nir_op_imin:
733 result = vir_MIN(c, src[0], src[1]);
734 break;
735 case nir_op_umin:
736 result = vir_UMIN(c, src[0], src[1]);
737 break;
738 case nir_op_imax:
739 result = vir_MAX(c, src[0], src[1]);
740 break;
741 case nir_op_umax:
742 result = vir_UMAX(c, src[0], src[1]);
743 break;
744 case nir_op_iand:
745 result = vir_AND(c, src[0], src[1]);
746 break;
747 case nir_op_ior:
748 result = vir_OR(c, src[0], src[1]);
749 break;
750 case nir_op_ixor:
751 result = vir_XOR(c, src[0], src[1]);
752 break;
753 case nir_op_inot:
754 result = vir_NOT(c, src[0]);
755 break;
756
757 case nir_op_imul:
758 result = vir_UMUL(c, src[0], src[1]);
759 break;
760
761 case nir_op_seq:
762 case nir_op_sne:
763 case nir_op_sge:
764 case nir_op_slt:
765 case nir_op_feq:
766 case nir_op_fne:
767 case nir_op_fge:
768 case nir_op_flt:
769 case nir_op_ieq:
770 case nir_op_ine:
771 case nir_op_ige:
772 case nir_op_uge:
773 case nir_op_ilt:
774 case nir_op_ult:
775 if (!ntq_emit_comparison(c, &result, instr, instr)) {
776 fprintf(stderr, "Bad comparison instruction\n");
777 }
778 break;
779
780 case nir_op_bcsel:
781 result = ntq_emit_bcsel(c, instr, src);
782 break;
783 case nir_op_fcsel:
784 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
785 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
786 src[1], src[2]));
787 break;
788
789 case nir_op_frcp:
790 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
791 break;
792 case nir_op_frsq:
793 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
794 break;
795 case nir_op_fexp2:
796 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
797 break;
798 case nir_op_flog2:
799 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
800 break;
801
802 case nir_op_fceil:
803 result = vir_FCEIL(c, src[0]);
804 break;
805 case nir_op_ffloor:
806 result = vir_FFLOOR(c, src[0]);
807 break;
808 case nir_op_fround_even:
809 result = vir_FROUND(c, src[0]);
810 break;
811 case nir_op_ftrunc:
812 result = vir_FTRUNC(c, src[0]);
813 break;
814 case nir_op_ffract:
815 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
816 break;
817
818 case nir_op_fsin:
819 result = ntq_fsincos(c, src[0], false);
820 break;
821 case nir_op_fcos:
822 result = ntq_fsincos(c, src[0], true);
823 break;
824
825 case nir_op_fsign:
826 result = ntq_fsign(c, src[0]);
827 break;
828 case nir_op_isign:
829 result = ntq_isign(c, src[0]);
830 break;
831
832 case nir_op_fabs: {
833 result = vir_FMOV(c, src[0]);
834 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
835 break;
836 }
837
838 case nir_op_iabs:
839 result = vir_MAX(c, src[0],
840 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
841 break;
842
843 case nir_op_fddx:
844 case nir_op_fddx_coarse:
845 case nir_op_fddx_fine:
846 result = vir_FDX(c, src[0]);
847 break;
848
849 case nir_op_fddy:
850 case nir_op_fddy_coarse:
851 case nir_op_fddy_fine:
852 result = vir_FDY(c, src[0]);
853 break;
854
855 default:
856 fprintf(stderr, "unknown NIR ALU inst: ");
857 nir_print_instr(&instr->instr, stderr);
858 fprintf(stderr, "\n");
859 abort();
860 }
861
862 /* We have a scalar result, so the instruction should only have a
863 * single channel written to.
864 */
865 assert(util_is_power_of_two(instr->dest.write_mask));
866 ntq_store_dest(c, &instr->dest.dest,
867 ffs(instr->dest.write_mask) - 1, result);
868 }
869
870 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
871 * specifier. They come from a register that's preloaded with 0xffffffff
872 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
873 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
874 */
875 #define TLB_TYPE_F16_COLOR (3 << 6)
876 #define TLB_TYPE_I32_COLOR (1 << 6)
877 #define TLB_TYPE_F32_COLOR (0 << 6)
878 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
879 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
880 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
881 #define TLB_F16_SWAP_HI_LO (1 << 1)
882 #define TLB_VEC_SIZE_4_F16 (1 << 0)
883 #define TLB_VEC_SIZE_2_F16 (0 << 0)
884 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
885
886 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
887 * flag is set.
888 */
889 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
890 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
891 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
892
893 /* Stencil is a single 32-bit write. */
894 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
895
896 static void
897 emit_frag_end(struct v3d_compile *c)
898 {
899 /* XXX
900 if (c->output_sample_mask_index != -1) {
901 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
902 }
903 */
904
905 bool has_any_tlb_color_write = false;
906 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
907 if (c->output_color_var[rt])
908 has_any_tlb_color_write = true;
909 }
910
911 if (c->output_position_index != -1) {
912 struct qinst *inst = vir_MOV_dest(c,
913 vir_reg(QFILE_TLBU, 0),
914 c->outputs[c->output_position_index]);
915
916 inst->src[vir_get_implicit_uniform_src(inst)] =
917 vir_uniform_ui(c,
918 TLB_TYPE_DEPTH |
919 TLB_DEPTH_TYPE_PER_PIXEL |
920 0xffffff00);
921 } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
922 /* Emit passthrough Z if it needed to be delayed until shader
923 * end due to potential discards.
924 *
925 * Since (single-threaded) fragment shaders always need a TLB
926 * write, emit passthrouh Z if we didn't have any color
927 * buffers and flag us as potentially discarding, so that we
928 * can use Z as the TLB write.
929 */
930 c->s->info.fs.uses_discard = true;
931
932 struct qinst *inst = vir_MOV_dest(c,
933 vir_reg(QFILE_TLBU, 0),
934 vir_reg(QFILE_NULL, 0));
935
936 inst->src[vir_get_implicit_uniform_src(inst)] =
937 vir_uniform_ui(c,
938 TLB_TYPE_DEPTH |
939 TLB_DEPTH_TYPE_INVARIANT |
940 0xffffff00);
941 }
942
943 /* XXX: Performance improvement: Merge Z write and color writes TLB
944 * uniform setup
945 */
946
947 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
948 if (!c->output_color_var[rt])
949 continue;
950
951 nir_variable *var = c->output_color_var[rt];
952 struct qreg *color = &c->outputs[var->data.driver_location * 4];
953 int num_components = glsl_get_vector_elements(var->type);
954 uint32_t conf = 0xffffff00;
955 struct qinst *inst;
956
957 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
958 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
959
960 assert(num_components != 0);
961 switch (glsl_get_base_type(var->type)) {
962 case GLSL_TYPE_UINT:
963 case GLSL_TYPE_INT:
964 /* The F32 vs I32 distinction was dropped in 4.2. */
965 if (c->devinfo->ver < 42)
966 conf |= TLB_TYPE_I32_COLOR;
967 else
968 conf |= TLB_TYPE_F32_COLOR;
969 conf |= ((num_components - 1) <<
970 TLB_VEC_SIZE_MINUS_1_SHIFT);
971
972 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
973 inst->src[vir_get_implicit_uniform_src(inst)] =
974 vir_uniform_ui(c, conf);
975
976 for (int i = 1; i < num_components; i++) {
977 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
978 color[i]);
979 }
980 break;
981
982 default: {
983 struct qreg r = color[0];
984 struct qreg g = color[1];
985 struct qreg b = color[2];
986 struct qreg a = color[3];
987
988 if (c->fs_key->f32_color_rb) {
989 conf |= TLB_TYPE_F32_COLOR;
990 conf |= ((num_components - 1) <<
991 TLB_VEC_SIZE_MINUS_1_SHIFT);
992 } else {
993 conf |= TLB_TYPE_F16_COLOR;
994 conf |= TLB_F16_SWAP_HI_LO;
995 if (num_components >= 3)
996 conf |= TLB_VEC_SIZE_4_F16;
997 else
998 conf |= TLB_VEC_SIZE_2_F16;
999 }
1000
1001 if (c->fs_key->swap_color_rb & (1 << rt)) {
1002 r = color[2];
1003 b = color[0];
1004 }
1005
1006 if (c->fs_key->f32_color_rb & (1 << rt)) {
1007 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1008 inst->src[vir_get_implicit_uniform_src(inst)] =
1009 vir_uniform_ui(c, conf);
1010
1011 for (int i = 1; i < num_components; i++) {
1012 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1013 color[i]);
1014 }
1015 } else {
1016 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1017 if (conf != ~0) {
1018 inst->dst.file = QFILE_TLBU;
1019 inst->src[vir_get_implicit_uniform_src(inst)] =
1020 vir_uniform_ui(c, conf);
1021 }
1022
1023 if (num_components >= 3)
1024 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1025 }
1026 break;
1027 }
1028 }
1029 }
1030 }
1031
1032 static void
1033 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1034 {
1035 if (c->devinfo->ver >= 40) {
1036 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1037 *vpm_index = *vpm_index + 1;
1038 } else {
1039 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1040 }
1041
1042 c->num_vpm_writes++;
1043 }
1044
1045 static void
1046 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1047 uint32_t *vpm_index)
1048 {
1049 for (int i = 0; i < 2; i++) {
1050 struct qreg coord = c->outputs[c->output_position_index + i];
1051 coord = vir_FMUL(c, coord,
1052 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1053 0));
1054 coord = vir_FMUL(c, coord, rcp_w);
1055 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1056 }
1057
1058 }
1059
1060 static void
1061 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1062 {
1063 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1064 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1065
1066 struct qreg z = c->outputs[c->output_position_index + 2];
1067 z = vir_FMUL(c, z, zscale);
1068 z = vir_FMUL(c, z, rcp_w);
1069 z = vir_FADD(c, z, zoffset);
1070 vir_VPM_WRITE(c, z, vpm_index);
1071 }
1072
1073 static void
1074 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1075 {
1076 vir_VPM_WRITE(c, rcp_w, vpm_index);
1077 }
1078
1079 static void
1080 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1081 {
1082 struct qreg point_size;
1083
1084 if (c->output_point_size_index != -1)
1085 point_size = c->outputs[c->output_point_size_index];
1086 else
1087 point_size = vir_uniform_f(c, 1.0);
1088
1089 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1090 * BCM21553).
1091 */
1092 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1093
1094 vir_VPM_WRITE(c, point_size, vpm_index);
1095 }
1096
1097 static void
1098 emit_vpm_write_setup(struct v3d_compile *c)
1099 {
1100 if (c->devinfo->ver >= 40)
1101 return;
1102
1103 v3d33_vir_vpm_write_setup(c);
1104 }
1105
1106 static void
1107 emit_vert_end(struct v3d_compile *c)
1108 {
1109 uint32_t vpm_index = 0;
1110 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1111 c->outputs[c->output_position_index + 3]);
1112
1113 emit_vpm_write_setup(c);
1114
1115 if (c->vs_key->is_coord) {
1116 for (int i = 0; i < 4; i++)
1117 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1118 &vpm_index);
1119 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1120 if (c->vs_key->per_vertex_point_size) {
1121 emit_point_size_write(c, &vpm_index);
1122 /* emit_rcp_wc_write(c, rcp_w); */
1123 }
1124 /* XXX: Z-only rendering */
1125 if (0)
1126 emit_zs_write(c, rcp_w, &vpm_index);
1127 } else {
1128 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1129 emit_zs_write(c, rcp_w, &vpm_index);
1130 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1131 if (c->vs_key->per_vertex_point_size)
1132 emit_point_size_write(c, &vpm_index);
1133 }
1134
1135 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1136 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1137 int j;
1138
1139 for (j = 0; j < c->num_outputs; j++) {
1140 struct v3d_varying_slot output = c->output_slots[j];
1141
1142 if (!memcmp(&input, &output, sizeof(input))) {
1143 vir_VPM_WRITE(c, c->outputs[j],
1144 &vpm_index);
1145 break;
1146 }
1147 }
1148 /* Emit padding if we didn't find a declared VS output for
1149 * this FS input.
1150 */
1151 if (j == c->num_outputs)
1152 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1153 &vpm_index);
1154 }
1155
1156 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1157 */
1158 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1159 vir_VPMWT(c);
1160 }
1161
1162 void
1163 v3d_optimize_nir(struct nir_shader *s)
1164 {
1165 bool progress;
1166
1167 do {
1168 progress = false;
1169
1170 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1171 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1172 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1173 NIR_PASS(progress, s, nir_copy_prop);
1174 NIR_PASS(progress, s, nir_opt_remove_phis);
1175 NIR_PASS(progress, s, nir_opt_dce);
1176 NIR_PASS(progress, s, nir_opt_dead_cf);
1177 NIR_PASS(progress, s, nir_opt_cse);
1178 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1179 NIR_PASS(progress, s, nir_opt_algebraic);
1180 NIR_PASS(progress, s, nir_opt_constant_folding);
1181 NIR_PASS(progress, s, nir_opt_undef);
1182 } while (progress);
1183 }
1184
1185 static int
1186 driver_location_compare(const void *in_a, const void *in_b)
1187 {
1188 const nir_variable *const *a = in_a;
1189 const nir_variable *const *b = in_b;
1190
1191 return (*a)->data.driver_location - (*b)->data.driver_location;
1192 }
1193
1194 static struct qreg
1195 ntq_emit_vpm_read(struct v3d_compile *c,
1196 uint32_t *num_components_queued,
1197 uint32_t *remaining,
1198 uint32_t vpm_index)
1199 {
1200 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1201
1202 if (c->devinfo->ver >= 40 ) {
1203 return vir_LDVPMV_IN(c,
1204 vir_uniform_ui(c,
1205 (*num_components_queued)++));
1206 }
1207
1208 if (*num_components_queued != 0) {
1209 (*num_components_queued)--;
1210 c->num_inputs++;
1211 return vir_MOV(c, vpm);
1212 }
1213
1214 uint32_t num_components = MIN2(*remaining, 32);
1215
1216 v3d33_vir_vpm_read_setup(c, num_components);
1217
1218 *num_components_queued = num_components - 1;
1219 *remaining -= num_components;
1220 c->num_inputs++;
1221
1222 return vir_MOV(c, vpm);
1223 }
1224
1225 static void
1226 ntq_setup_inputs(struct v3d_compile *c)
1227 {
1228 unsigned num_entries = 0;
1229 unsigned num_components = 0;
1230 nir_foreach_variable(var, &c->s->inputs) {
1231 num_entries++;
1232 num_components += glsl_get_components(var->type);
1233 }
1234
1235 nir_variable *vars[num_entries];
1236
1237 unsigned i = 0;
1238 nir_foreach_variable(var, &c->s->inputs)
1239 vars[i++] = var;
1240
1241 /* Sort the variables so that we emit the input setup in
1242 * driver_location order. This is required for VPM reads, whose data
1243 * is fetched into the VPM in driver_location (TGSI register index)
1244 * order.
1245 */
1246 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1247
1248 uint32_t vpm_components_queued = 0;
1249 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1250 bool uses_iid = c->s->info.system_values_read &
1251 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1252 bool uses_vid = c->s->info.system_values_read &
1253 (1ull << SYSTEM_VALUE_VERTEX_ID);
1254
1255 num_components += uses_iid;
1256 num_components += uses_vid;
1257
1258 if (uses_iid) {
1259 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1260 &num_components, ~0);
1261 }
1262
1263 if (uses_vid) {
1264 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1265 &num_components, ~0);
1266 }
1267 }
1268
1269 for (unsigned i = 0; i < num_entries; i++) {
1270 nir_variable *var = vars[i];
1271 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1272 unsigned loc = var->data.driver_location;
1273
1274 assert(array_len == 1);
1275 (void)array_len;
1276 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1277 (loc + 1) * 4);
1278
1279 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1280 if (var->data.location == VARYING_SLOT_POS) {
1281 emit_fragcoord_input(c, loc);
1282 } else if (var->data.location == VARYING_SLOT_PNTC ||
1283 (var->data.location >= VARYING_SLOT_VAR0 &&
1284 (c->fs_key->point_sprite_mask &
1285 (1 << (var->data.location -
1286 VARYING_SLOT_VAR0))))) {
1287 c->inputs[loc * 4 + 0] = c->point_x;
1288 c->inputs[loc * 4 + 1] = c->point_y;
1289 } else {
1290 emit_fragment_input(c, loc, var);
1291 }
1292 } else {
1293 int var_components = glsl_get_components(var->type);
1294
1295 for (int i = 0; i < var_components; i++) {
1296 c->inputs[loc * 4 + i] =
1297 ntq_emit_vpm_read(c,
1298 &vpm_components_queued,
1299 &num_components,
1300 loc * 4 + i);
1301
1302 }
1303 c->vattr_sizes[loc] = var_components;
1304 }
1305 }
1306
1307 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1308 if (c->devinfo->ver >= 40) {
1309 assert(vpm_components_queued == num_components);
1310 } else {
1311 assert(vpm_components_queued == 0);
1312 assert(num_components == 0);
1313 }
1314 }
1315 }
1316
1317 static void
1318 ntq_setup_outputs(struct v3d_compile *c)
1319 {
1320 nir_foreach_variable(var, &c->s->outputs) {
1321 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1322 unsigned loc = var->data.driver_location * 4;
1323
1324 assert(array_len == 1);
1325 (void)array_len;
1326
1327 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
1328 add_output(c, loc + var->data.location_frac + i,
1329 var->data.location,
1330 var->data.location_frac + i);
1331 }
1332
1333 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1334 switch (var->data.location) {
1335 case FRAG_RESULT_COLOR:
1336 c->output_color_var[0] = var;
1337 c->output_color_var[1] = var;
1338 c->output_color_var[2] = var;
1339 c->output_color_var[3] = var;
1340 break;
1341 case FRAG_RESULT_DATA0:
1342 case FRAG_RESULT_DATA1:
1343 case FRAG_RESULT_DATA2:
1344 case FRAG_RESULT_DATA3:
1345 c->output_color_var[var->data.location -
1346 FRAG_RESULT_DATA0] = var;
1347 break;
1348 case FRAG_RESULT_DEPTH:
1349 c->output_position_index = loc;
1350 break;
1351 case FRAG_RESULT_SAMPLE_MASK:
1352 c->output_sample_mask_index = loc;
1353 break;
1354 }
1355 } else {
1356 switch (var->data.location) {
1357 case VARYING_SLOT_POS:
1358 c->output_position_index = loc;
1359 break;
1360 case VARYING_SLOT_PSIZ:
1361 c->output_point_size_index = loc;
1362 break;
1363 }
1364 }
1365 }
1366 }
1367
1368 static void
1369 ntq_setup_uniforms(struct v3d_compile *c)
1370 {
1371 nir_foreach_variable(var, &c->s->uniforms) {
1372 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1373 false);
1374 unsigned vec4_size = 4 * sizeof(float);
1375
1376 declare_uniform_range(c, var->data.driver_location * vec4_size,
1377 vec4_count * vec4_size);
1378
1379 }
1380 }
1381
1382 /**
1383 * Sets up the mapping from nir_register to struct qreg *.
1384 *
1385 * Each nir_register gets a struct qreg per 32-bit component being stored.
1386 */
1387 static void
1388 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1389 {
1390 foreach_list_typed(nir_register, nir_reg, node, list) {
1391 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1392 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1393 array_len *
1394 nir_reg->num_components);
1395
1396 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1397
1398 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1399 qregs[i] = vir_get_temp(c);
1400 }
1401 }
1402
1403 static void
1404 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1405 {
1406 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1407 for (int i = 0; i < instr->def.num_components; i++)
1408 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1409
1410 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1411 }
1412
1413 static void
1414 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1415 {
1416 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1417
1418 /* VIR needs there to be *some* value, so pick 0 (same as for
1419 * ntq_setup_registers().
1420 */
1421 for (int i = 0; i < instr->def.num_components; i++)
1422 qregs[i] = vir_uniform_ui(c, 0);
1423 }
1424
1425 static void
1426 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1427 {
1428 nir_const_value *const_offset;
1429 unsigned offset;
1430
1431 switch (instr->intrinsic) {
1432 case nir_intrinsic_load_uniform:
1433 assert(instr->num_components == 1);
1434 const_offset = nir_src_as_const_value(instr->src[0]);
1435 if (const_offset) {
1436 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1437 assert(offset % 4 == 0);
1438 /* We need dwords */
1439 offset = offset / 4;
1440 ntq_store_dest(c, &instr->dest, 0,
1441 vir_uniform(c, QUNIFORM_UNIFORM,
1442 offset));
1443 } else {
1444 ntq_store_dest(c, &instr->dest, 0,
1445 indirect_uniform_load(c, instr));
1446 }
1447 break;
1448
1449 case nir_intrinsic_load_ubo:
1450 for (int i = 0; i < instr->num_components; i++) {
1451 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1452
1453 /* Adjust for where we stored the TGSI register base. */
1454 vir_ADD_dest(c,
1455 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1456 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1457 vir_ADD(c,
1458 ntq_get_src(c, instr->src[1], 0),
1459 vir_uniform_ui(c, i * 4)));
1460
1461 vir_emit_thrsw(c);
1462
1463 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1464 }
1465 break;
1466
1467 const_offset = nir_src_as_const_value(instr->src[0]);
1468 if (const_offset) {
1469 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1470 assert(offset % 4 == 0);
1471 /* We need dwords */
1472 offset = offset / 4;
1473 ntq_store_dest(c, &instr->dest, 0,
1474 vir_uniform(c, QUNIFORM_UNIFORM,
1475 offset));
1476 } else {
1477 ntq_store_dest(c, &instr->dest, 0,
1478 indirect_uniform_load(c, instr));
1479 }
1480 break;
1481
1482 case nir_intrinsic_load_user_clip_plane:
1483 for (int i = 0; i < instr->num_components; i++) {
1484 ntq_store_dest(c, &instr->dest, i,
1485 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1486 nir_intrinsic_ucp_id(instr) *
1487 4 + i));
1488 }
1489 break;
1490
1491 case nir_intrinsic_load_alpha_ref_float:
1492 ntq_store_dest(c, &instr->dest, 0,
1493 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1494 break;
1495
1496 case nir_intrinsic_load_sample_mask_in:
1497 ntq_store_dest(c, &instr->dest, 0,
1498 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1499 break;
1500
1501 case nir_intrinsic_load_front_face:
1502 /* The register contains 0 (front) or 1 (back), and we need to
1503 * turn it into a NIR bool where true means front.
1504 */
1505 ntq_store_dest(c, &instr->dest, 0,
1506 vir_ADD(c,
1507 vir_uniform_ui(c, -1),
1508 vir_REVF(c)));
1509 break;
1510
1511 case nir_intrinsic_load_instance_id:
1512 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1513 break;
1514
1515 case nir_intrinsic_load_vertex_id:
1516 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1517 break;
1518
1519 case nir_intrinsic_load_input:
1520 const_offset = nir_src_as_const_value(instr->src[0]);
1521 assert(const_offset && "v3d doesn't support indirect inputs");
1522 for (int i = 0; i < instr->num_components; i++) {
1523 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1524 int comp = nir_intrinsic_component(instr) + i;
1525 ntq_store_dest(c, &instr->dest, i,
1526 vir_MOV(c, c->inputs[offset * 4 + comp]));
1527 }
1528 break;
1529
1530 case nir_intrinsic_store_output:
1531 const_offset = nir_src_as_const_value(instr->src[1]);
1532 assert(const_offset && "v3d doesn't support indirect outputs");
1533 offset = ((nir_intrinsic_base(instr) +
1534 const_offset->u32[0]) * 4 +
1535 nir_intrinsic_component(instr));
1536
1537 for (int i = 0; i < instr->num_components; i++) {
1538 c->outputs[offset + i] =
1539 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1540 }
1541 c->num_outputs = MAX2(c->num_outputs,
1542 offset + instr->num_components);
1543 break;
1544
1545 case nir_intrinsic_discard:
1546 if (c->execute.file != QFILE_NULL) {
1547 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1548 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1549 vir_uniform_ui(c, 0)),
1550 V3D_QPU_COND_IFA);
1551 } else {
1552 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1553 vir_uniform_ui(c, 0));
1554 }
1555 break;
1556
1557 case nir_intrinsic_discard_if: {
1558 /* true (~0) if we're discarding */
1559 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1560
1561 if (c->execute.file != QFILE_NULL) {
1562 /* execute == 0 means the channel is active. Invert
1563 * the condition so that we can use zero as "executing
1564 * and discarding."
1565 */
1566 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1567 V3D_QPU_PF_PUSHZ);
1568 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1569 vir_uniform_ui(c, 0)),
1570 V3D_QPU_COND_IFA);
1571 } else {
1572 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1573 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1574 vir_uniform_ui(c, 0)),
1575 V3D_QPU_COND_IFNA);
1576 }
1577
1578 break;
1579 }
1580
1581 default:
1582 fprintf(stderr, "Unknown intrinsic: ");
1583 nir_print_instr(&instr->instr, stderr);
1584 fprintf(stderr, "\n");
1585 break;
1586 }
1587 }
1588
1589 /* Clears (activates) the execute flags for any channels whose jump target
1590 * matches this block.
1591 */
1592 static void
1593 ntq_activate_execute_for_block(struct v3d_compile *c)
1594 {
1595 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1596 V3D_QPU_PF_PUSHZ);
1597
1598 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1599 }
1600
1601 static void
1602 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1603 {
1604 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1605 bool empty_else_block =
1606 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1607 exec_list_is_empty(&nir_else_block->instr_list));
1608
1609 struct qblock *then_block = vir_new_block(c);
1610 struct qblock *after_block = vir_new_block(c);
1611 struct qblock *else_block;
1612 if (empty_else_block)
1613 else_block = after_block;
1614 else
1615 else_block = vir_new_block(c);
1616
1617 bool was_top_level = false;
1618 if (c->execute.file == QFILE_NULL) {
1619 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1620 was_top_level = true;
1621 }
1622
1623 /* Set A for executing (execute == 0) and jumping (if->condition ==
1624 * 0) channels, and then update execute flags for those to point to
1625 * the ELSE block.
1626 */
1627 vir_PF(c, vir_OR(c,
1628 c->execute,
1629 ntq_get_src(c, if_stmt->condition, 0)),
1630 V3D_QPU_PF_PUSHZ);
1631 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1632 c->execute,
1633 vir_uniform_ui(c, else_block->index));
1634
1635 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1636 * through.
1637 */
1638 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1639 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1640 vir_link_blocks(c->cur_block, else_block);
1641 vir_link_blocks(c->cur_block, then_block);
1642
1643 /* Process the THEN block. */
1644 vir_set_emit_block(c, then_block);
1645 ntq_emit_cf_list(c, &if_stmt->then_list);
1646
1647 if (!empty_else_block) {
1648 /* Handle the end of the THEN block. First, all currently
1649 * active channels update their execute flags to point to
1650 * ENDIF
1651 */
1652 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1653 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1654 vir_uniform_ui(c, after_block->index));
1655
1656 /* If everything points at ENDIF, then jump there immediately. */
1657 vir_PF(c, vir_XOR(c, c->execute,
1658 vir_uniform_ui(c, after_block->index)),
1659 V3D_QPU_PF_PUSHZ);
1660 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1661 vir_link_blocks(c->cur_block, after_block);
1662 vir_link_blocks(c->cur_block, else_block);
1663
1664 vir_set_emit_block(c, else_block);
1665 ntq_activate_execute_for_block(c);
1666 ntq_emit_cf_list(c, &if_stmt->else_list);
1667 }
1668
1669 vir_link_blocks(c->cur_block, after_block);
1670
1671 vir_set_emit_block(c, after_block);
1672 if (was_top_level)
1673 c->execute = c->undef;
1674 else
1675 ntq_activate_execute_for_block(c);
1676 }
1677
1678 static void
1679 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1680 {
1681 switch (jump->type) {
1682 case nir_jump_break:
1683 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1684 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1685 vir_uniform_ui(c, c->loop_break_block->index));
1686 break;
1687
1688 case nir_jump_continue:
1689 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1690 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1691 vir_uniform_ui(c, c->loop_cont_block->index));
1692 break;
1693
1694 case nir_jump_return:
1695 unreachable("All returns shouold be lowered\n");
1696 }
1697 }
1698
1699 static void
1700 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1701 {
1702 switch (instr->type) {
1703 case nir_instr_type_alu:
1704 ntq_emit_alu(c, nir_instr_as_alu(instr));
1705 break;
1706
1707 case nir_instr_type_intrinsic:
1708 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1709 break;
1710
1711 case nir_instr_type_load_const:
1712 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1713 break;
1714
1715 case nir_instr_type_ssa_undef:
1716 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1717 break;
1718
1719 case nir_instr_type_tex:
1720 ntq_emit_tex(c, nir_instr_as_tex(instr));
1721 break;
1722
1723 case nir_instr_type_jump:
1724 ntq_emit_jump(c, nir_instr_as_jump(instr));
1725 break;
1726
1727 default:
1728 fprintf(stderr, "Unknown NIR instr type: ");
1729 nir_print_instr(instr, stderr);
1730 fprintf(stderr, "\n");
1731 abort();
1732 }
1733 }
1734
1735 static void
1736 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1737 {
1738 nir_foreach_instr(instr, block) {
1739 ntq_emit_instr(c, instr);
1740 }
1741 }
1742
1743 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1744
1745 static void
1746 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1747 {
1748 bool was_top_level = false;
1749 if (c->execute.file == QFILE_NULL) {
1750 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1751 was_top_level = true;
1752 }
1753
1754 struct qblock *save_loop_cont_block = c->loop_cont_block;
1755 struct qblock *save_loop_break_block = c->loop_break_block;
1756
1757 c->loop_cont_block = vir_new_block(c);
1758 c->loop_break_block = vir_new_block(c);
1759
1760 vir_link_blocks(c->cur_block, c->loop_cont_block);
1761 vir_set_emit_block(c, c->loop_cont_block);
1762 ntq_activate_execute_for_block(c);
1763
1764 ntq_emit_cf_list(c, &loop->body);
1765
1766 /* Re-enable any previous continues now, so our ANYA check below
1767 * works.
1768 *
1769 * XXX: Use the .ORZ flags update, instead.
1770 */
1771 vir_PF(c, vir_XOR(c,
1772 c->execute,
1773 vir_uniform_ui(c, c->loop_cont_block->index)),
1774 V3D_QPU_PF_PUSHZ);
1775 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1776
1777 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1778
1779 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1780 /* Pixels that were not dispatched or have been discarded should not
1781 * contribute to looping again.
1782 */
1783 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1784 vir_link_blocks(c->cur_block, c->loop_cont_block);
1785 vir_link_blocks(c->cur_block, c->loop_break_block);
1786
1787 vir_set_emit_block(c, c->loop_break_block);
1788 if (was_top_level)
1789 c->execute = c->undef;
1790 else
1791 ntq_activate_execute_for_block(c);
1792
1793 c->loop_break_block = save_loop_break_block;
1794 c->loop_cont_block = save_loop_cont_block;
1795 }
1796
1797 static void
1798 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1799 {
1800 fprintf(stderr, "FUNCTIONS not handled.\n");
1801 abort();
1802 }
1803
1804 static void
1805 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1806 {
1807 foreach_list_typed(nir_cf_node, node, node, list) {
1808 switch (node->type) {
1809 case nir_cf_node_block:
1810 ntq_emit_block(c, nir_cf_node_as_block(node));
1811 break;
1812
1813 case nir_cf_node_if:
1814 ntq_emit_if(c, nir_cf_node_as_if(node));
1815 break;
1816
1817 case nir_cf_node_loop:
1818 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1819 break;
1820
1821 case nir_cf_node_function:
1822 ntq_emit_function(c, nir_cf_node_as_function(node));
1823 break;
1824
1825 default:
1826 fprintf(stderr, "Unknown NIR node type\n");
1827 abort();
1828 }
1829 }
1830 }
1831
1832 static void
1833 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1834 {
1835 ntq_setup_registers(c, &impl->registers);
1836 ntq_emit_cf_list(c, &impl->body);
1837 }
1838
1839 static void
1840 nir_to_vir(struct v3d_compile *c)
1841 {
1842 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1843 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1844 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1845 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1846
1847 if (c->fs_key->is_points) {
1848 c->point_x = emit_fragment_varying(c, NULL, 0);
1849 c->point_y = emit_fragment_varying(c, NULL, 0);
1850 } else if (c->fs_key->is_lines) {
1851 c->line_x = emit_fragment_varying(c, NULL, 0);
1852 }
1853 }
1854
1855 ntq_setup_inputs(c);
1856 ntq_setup_outputs(c);
1857 ntq_setup_uniforms(c);
1858 ntq_setup_registers(c, &c->s->registers);
1859
1860 /* Find the main function and emit the body. */
1861 nir_foreach_function(function, c->s) {
1862 assert(strcmp(function->name, "main") == 0);
1863 assert(function->impl);
1864 ntq_emit_impl(c, function->impl);
1865 }
1866 }
1867
1868 const nir_shader_compiler_options v3d_nir_options = {
1869 .lower_all_io_to_temps = true,
1870 .lower_extract_byte = true,
1871 .lower_extract_word = true,
1872 .lower_bitfield_insert = true,
1873 .lower_bitfield_extract = true,
1874 .lower_pack_unorm_2x16 = true,
1875 .lower_pack_snorm_2x16 = true,
1876 .lower_pack_unorm_4x8 = true,
1877 .lower_pack_snorm_4x8 = true,
1878 .lower_unpack_unorm_4x8 = true,
1879 .lower_unpack_snorm_4x8 = true,
1880 .lower_fdiv = true,
1881 .lower_ffma = true,
1882 .lower_flrp32 = true,
1883 .lower_fpow = true,
1884 .lower_fsat = true,
1885 .lower_fsqrt = true,
1886 .lower_ldexp = true,
1887 .native_integers = true,
1888 };
1889
1890
1891 #if 0
1892 static int
1893 count_nir_instrs(nir_shader *nir)
1894 {
1895 int count = 0;
1896 nir_foreach_function(function, nir) {
1897 if (!function->impl)
1898 continue;
1899 nir_foreach_block(block, function->impl) {
1900 nir_foreach_instr(instr, block)
1901 count++;
1902 }
1903 }
1904 return count;
1905 }
1906 #endif
1907
1908 /**
1909 * When demoting a shader down to single-threaded, removes the THRSW
1910 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1911 * program end).
1912 */
1913 static void
1914 vir_remove_thrsw(struct v3d_compile *c)
1915 {
1916 vir_for_each_block(block, c) {
1917 vir_for_each_inst_safe(inst, block) {
1918 if (inst->qpu.sig.thrsw)
1919 vir_remove_instruction(c, inst);
1920 }
1921 }
1922 vir_calculate_live_intervals(c);
1923
1924 c->last_thrsw = NULL;
1925 }
1926
1927 static void
1928 vir_emit_last_thrsw(struct v3d_compile *c)
1929 {
1930 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1931 * switching, so disable threads if we didn't do any TMU ops (each of
1932 * which would have emitted a THRSW).
1933 */
1934 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
1935 c->threads = 1;
1936 if (c->last_thrsw)
1937 vir_remove_thrsw(c);
1938 return;
1939 }
1940
1941 /* If we're threaded and the last THRSW was in conditional code, then
1942 * we need to emit another one so that we can flag it as the last
1943 * thrsw.
1944 */
1945 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
1946 assert(c->devinfo->ver >= 41);
1947 vir_emit_thrsw(c);
1948 }
1949
1950 /* If we're threaded, then we need to mark the last THRSW instruction
1951 * so we can emit a pair of them at QPU emit time.
1952 *
1953 * For V3D 4.x, we can spawn the non-fragment shaders already in the
1954 * post-last-THRSW state, so we can skip this.
1955 */
1956 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
1957 assert(c->devinfo->ver >= 41);
1958 vir_emit_thrsw(c);
1959 }
1960
1961 if (c->last_thrsw)
1962 c->last_thrsw->is_last_thrsw = true;
1963 }
1964
1965 void
1966 v3d_nir_to_vir(struct v3d_compile *c)
1967 {
1968 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1969 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
1970 fprintf(stderr, "%s prog %d/%d NIR:\n",
1971 vir_get_stage_name(c),
1972 c->program_id, c->variant_id);
1973 nir_print_shader(c->s, stderr);
1974 }
1975
1976 nir_to_vir(c);
1977
1978 /* Emit the last THRSW before STVPM and TLB writes. */
1979 vir_emit_last_thrsw(c);
1980
1981 switch (c->s->info.stage) {
1982 case MESA_SHADER_FRAGMENT:
1983 emit_frag_end(c);
1984 break;
1985 case MESA_SHADER_VERTEX:
1986 emit_vert_end(c);
1987 break;
1988 default:
1989 unreachable("bad stage");
1990 }
1991
1992 if (V3D_DEBUG & (V3D_DEBUG_VIR |
1993 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
1994 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
1995 vir_get_stage_name(c),
1996 c->program_id, c->variant_id);
1997 vir_dump(c);
1998 fprintf(stderr, "\n");
1999 }
2000
2001 vir_optimize(c);
2002 vir_lower_uniforms(c);
2003
2004 /* XXX: vir_schedule_instructions(c); */
2005
2006 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2007 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2008 fprintf(stderr, "%s prog %d/%d VIR:\n",
2009 vir_get_stage_name(c),
2010 c->program_id, c->variant_id);
2011 vir_dump(c);
2012 fprintf(stderr, "\n");
2013 }
2014
2015 /* Compute the live ranges so we can figure out interference. */
2016 vir_calculate_live_intervals(c);
2017
2018 /* Attempt to allocate registers for the temporaries. If we fail,
2019 * reduce thread count and try again.
2020 */
2021 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2022 struct qpu_reg *temp_registers;
2023 while (true) {
2024 temp_registers = v3d_register_allocate(c);
2025
2026 if (temp_registers)
2027 break;
2028
2029 if (c->threads == min_threads) {
2030 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2031 c->threads);
2032 vir_dump(c);
2033 c->failed = true;
2034 return;
2035 }
2036
2037 c->threads /= 2;
2038
2039 if (c->threads == 1)
2040 vir_remove_thrsw(c);
2041 }
2042
2043 v3d_vir_to_qpu(c, temp_registers);
2044 }