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v3d: Stop treating exec masking specially.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (vir_in_nonuniform_control_flow(c)) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->src[vir_get_implicit_uniform_src(tmu)] =
309 vir_uniform_ui(c, config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert(result.file == QFILE_UNIF ||
358 (result.file == QFILE_TEMP &&
359 last_inst && last_inst == c->defs[result.index]));
360
361 if (dest->is_ssa) {
362 assert(chan < dest->ssa.num_components);
363
364 struct qreg *qregs;
365 struct hash_entry *entry =
366 _mesa_hash_table_search(c->def_ht, &dest->ssa);
367
368 if (entry)
369 qregs = entry->data;
370 else
371 qregs = ntq_init_ssa_def(c, &dest->ssa);
372
373 qregs[chan] = result;
374 } else {
375 nir_register *reg = dest->reg.reg;
376 assert(dest->reg.base_offset == 0);
377 assert(reg->num_array_elems == 0);
378 struct hash_entry *entry =
379 _mesa_hash_table_search(c->def_ht, reg);
380 struct qreg *qregs = entry->data;
381
382 /* Insert a MOV if the source wasn't an SSA def in the
383 * previous instruction.
384 */
385 if (result.file == QFILE_UNIF) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 }
409 }
410 }
411
412 struct qreg
413 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
414 {
415 struct hash_entry *entry;
416 if (src.is_ssa) {
417 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
418 assert(i < src.ssa->num_components);
419 } else {
420 nir_register *reg = src.reg.reg;
421 entry = _mesa_hash_table_search(c->def_ht, reg);
422 assert(reg->num_array_elems == 0);
423 assert(src.reg.base_offset == 0);
424 assert(i < reg->num_components);
425 }
426
427 struct qreg *qregs = entry->data;
428 return qregs[i];
429 }
430
431 static struct qreg
432 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
433 unsigned src)
434 {
435 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
436 unsigned chan = ffs(instr->dest.write_mask) - 1;
437 struct qreg r = ntq_get_src(c, instr->src[src].src,
438 instr->src[src].swizzle[chan]);
439
440 assert(!instr->src[src].abs);
441 assert(!instr->src[src].negate);
442
443 return r;
444 };
445
446 static struct qreg
447 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
448 {
449 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
450 }
451
452 static void
453 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
454 {
455 unsigned unit = instr->texture_index;
456 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
457 int dest_size = nir_tex_instr_dest_size(instr);
458
459 struct qreg lod = c->undef;
460 if (lod_index != -1)
461 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
462
463 for (int i = 0; i < dest_size; i++) {
464 assert(i < 3);
465 enum quniform_contents contents;
466
467 if (instr->is_array && i == dest_size - 1)
468 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
469 else
470 contents = QUNIFORM_TEXTURE_WIDTH + i;
471
472 struct qreg size = vir_uniform(c, contents, unit);
473
474 switch (instr->sampler_dim) {
475 case GLSL_SAMPLER_DIM_1D:
476 case GLSL_SAMPLER_DIM_2D:
477 case GLSL_SAMPLER_DIM_MS:
478 case GLSL_SAMPLER_DIM_3D:
479 case GLSL_SAMPLER_DIM_CUBE:
480 /* Don't minify the array size. */
481 if (!(instr->is_array && i == dest_size - 1)) {
482 size = ntq_minify(c, size, lod);
483 }
484 break;
485
486 case GLSL_SAMPLER_DIM_RECT:
487 /* There's no LOD field for rects */
488 break;
489
490 default:
491 unreachable("Bad sampler type");
492 }
493
494 ntq_store_dest(c, &instr->dest, i, size);
495 }
496 }
497
498 static void
499 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
500 {
501 unsigned unit = instr->texture_index;
502
503 /* Since each texture sampling op requires uploading uniforms to
504 * reference the texture, there's no HW support for texture size and
505 * you just upload uniforms containing the size.
506 */
507 switch (instr->op) {
508 case nir_texop_query_levels:
509 ntq_store_dest(c, &instr->dest, 0,
510 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
511 return;
512 case nir_texop_txs:
513 ntq_emit_txs(c, instr);
514 return;
515 default:
516 break;
517 }
518
519 if (c->devinfo->ver >= 40)
520 v3d40_vir_emit_tex(c, instr);
521 else
522 v3d33_vir_emit_tex(c, instr);
523 }
524
525 static struct qreg
526 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
527 {
528 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
529 if (is_cos)
530 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
531
532 struct qreg periods = vir_FROUND(c, input);
533 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
534 return vir_XOR(c, sin_output, vir_SHL(c,
535 vir_FTOIN(c, periods),
536 vir_uniform_ui(c, -1)));
537 }
538
539 static struct qreg
540 ntq_fsign(struct v3d_compile *c, struct qreg src)
541 {
542 struct qreg t = vir_get_temp(c);
543
544 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
545 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
546 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
547 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
548 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
549 return vir_MOV(c, t);
550 }
551
552 static void
553 emit_fragcoord_input(struct v3d_compile *c, int attr)
554 {
555 c->inputs[attr * 4 + 0] = vir_FXCD(c);
556 c->inputs[attr * 4 + 1] = vir_FYCD(c);
557 c->inputs[attr * 4 + 2] = c->payload_z;
558 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
559 }
560
561 static struct qreg
562 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
563 uint8_t swizzle, int array_index)
564 {
565 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
566 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
567
568 struct qreg vary;
569 if (c->devinfo->ver >= 41) {
570 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
571 c->undef, c->undef);
572 ldvary->qpu.sig.ldvary = true;
573 vary = vir_emit_def(c, ldvary);
574 } else {
575 vir_NOP(c)->qpu.sig.ldvary = true;
576 vary = r3;
577 }
578
579 /* For gl_PointCoord input or distance along a line, we'll be called
580 * with no nir_variable, and we don't count toward VPM size so we
581 * don't track an input slot.
582 */
583 if (!var) {
584 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
585 }
586
587 int i = c->num_inputs++;
588 c->input_slots[i] =
589 v3d_slot_from_slot_and_component(var->data.location +
590 array_index, swizzle);
591
592 switch (var->data.interpolation) {
593 case INTERP_MODE_NONE:
594 /* If a gl_FrontColor or gl_BackColor input has no interp
595 * qualifier, then if we're using glShadeModel(GL_FLAT) it
596 * needs to be flat shaded.
597 */
598 switch (var->data.location + array_index) {
599 case VARYING_SLOT_COL0:
600 case VARYING_SLOT_COL1:
601 case VARYING_SLOT_BFC0:
602 case VARYING_SLOT_BFC1:
603 if (c->fs_key->shade_model_flat) {
604 BITSET_SET(c->flat_shade_flags, i);
605 vir_MOV_dest(c, c->undef, vary);
606 return vir_MOV(c, r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary,
609 c->payload_w), r5);
610 }
611 default:
612 break;
613 }
614 /* FALLTHROUGH */
615 case INTERP_MODE_SMOOTH:
616 if (var->data.centroid) {
617 BITSET_SET(c->centroid_flags, i);
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w_centroid), r5);
620 } else {
621 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
622 }
623 case INTERP_MODE_NOPERSPECTIVE:
624 BITSET_SET(c->noperspective_flags, i);
625 return vir_FADD(c, vir_MOV(c, vary), r5);
626 case INTERP_MODE_FLAT:
627 BITSET_SET(c->flat_shade_flags, i);
628 vir_MOV_dest(c, c->undef, vary);
629 return vir_MOV(c, r5);
630 default:
631 unreachable("Bad interp mode");
632 }
633 }
634
635 static void
636 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
637 int array_index)
638 {
639 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
640 int chan = var->data.location_frac + i;
641 c->inputs[attr * 4 + chan] =
642 emit_fragment_varying(c, var, chan, array_index);
643 }
644 }
645
646 static void
647 add_output(struct v3d_compile *c,
648 uint32_t decl_offset,
649 uint8_t slot,
650 uint8_t swizzle)
651 {
652 uint32_t old_array_size = c->outputs_array_size;
653 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
654 decl_offset + 1);
655
656 if (old_array_size != c->outputs_array_size) {
657 c->output_slots = reralloc(c,
658 c->output_slots,
659 struct v3d_varying_slot,
660 c->outputs_array_size);
661 }
662
663 c->output_slots[decl_offset] =
664 v3d_slot_from_slot_and_component(slot, swizzle);
665 }
666
667 static void
668 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
669 {
670 unsigned array_id = c->num_ubo_ranges++;
671 if (array_id >= c->ubo_ranges_array_size) {
672 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
673 array_id + 1);
674 c->ubo_ranges = reralloc(c, c->ubo_ranges,
675 struct v3d_ubo_range,
676 c->ubo_ranges_array_size);
677 c->ubo_range_used = reralloc(c, c->ubo_range_used,
678 bool,
679 c->ubo_ranges_array_size);
680 }
681
682 c->ubo_ranges[array_id].dst_offset = 0;
683 c->ubo_ranges[array_id].src_offset = start;
684 c->ubo_ranges[array_id].size = size;
685 c->ubo_range_used[array_id] = false;
686 }
687
688 /**
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
692 */
693 static bool
694 ntq_emit_comparison(struct v3d_compile *c,
695 nir_alu_instr *compare_instr,
696 enum v3d_qpu_cond *out_cond)
697 {
698 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
699 struct qreg src1;
700 if (nir_op_infos[compare_instr->op].num_inputs > 1)
701 src1 = ntq_get_alu_src(c, compare_instr, 1);
702 bool cond_invert = false;
703 struct qreg nop = vir_nop_reg();
704
705 switch (compare_instr->op) {
706 case nir_op_feq32:
707 case nir_op_seq:
708 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
709 break;
710 case nir_op_ieq32:
711 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
712 break;
713
714 case nir_op_fne32:
715 case nir_op_sne:
716 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719 case nir_op_ine32:
720 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
721 cond_invert = true;
722 break;
723
724 case nir_op_fge32:
725 case nir_op_sge:
726 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ige32:
729 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732 case nir_op_uge32:
733 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
734 cond_invert = true;
735 break;
736
737 case nir_op_slt:
738 case nir_op_flt32:
739 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
740 break;
741 case nir_op_ilt32:
742 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
743 break;
744 case nir_op_ult32:
745 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
746 break;
747
748 case nir_op_i2b32:
749 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
750 cond_invert = true;
751 break;
752
753 case nir_op_f2b32:
754 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
755 cond_invert = true;
756 break;
757
758 default:
759 return false;
760 }
761
762 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
763
764 return true;
765 }
766
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
769 */
770 static struct nir_alu_instr *
771 ntq_get_alu_parent(nir_src src)
772 {
773 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
774 return NULL;
775 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
776 if (!instr)
777 return NULL;
778
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
781 * src.
782 */
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 if (!instr->src[i].src.is_ssa)
785 return NULL;
786 }
787
788 return instr;
789 }
790
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
794 {
795 nir_alu_instr *compare = ntq_get_alu_parent(src);
796 if (!compare)
797 goto out;
798
799 enum v3d_qpu_cond cond;
800 if (ntq_emit_comparison(c, compare, &cond))
801 return cond;
802
803 out:
804 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
805 V3D_QPU_PF_PUSHZ);
806 return V3D_QPU_COND_IFNA;
807 }
808
809 static void
810 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
811 {
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr->dest.saturate);
814
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
818 */
819 if (instr->op == nir_op_vec2 ||
820 instr->op == nir_op_vec3 ||
821 instr->op == nir_op_vec4) {
822 struct qreg srcs[4];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
824 srcs[i] = ntq_get_src(c, instr->src[i].src,
825 instr->src[i].swizzle[0]);
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
827 ntq_store_dest(c, &instr->dest.dest, i,
828 vir_MOV(c, srcs[i]));
829 return;
830 }
831
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src[nir_op_infos[instr->op].num_inputs];
834 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
835 src[i] = ntq_get_alu_src(c, instr, i);
836 }
837
838 struct qreg result;
839
840 switch (instr->op) {
841 case nir_op_fmov:
842 case nir_op_imov:
843 result = vir_MOV(c, src[0]);
844 break;
845
846 case nir_op_fneg:
847 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
848 break;
849 case nir_op_ineg:
850 result = vir_NEG(c, src[0]);
851 break;
852
853 case nir_op_fmul:
854 result = vir_FMUL(c, src[0], src[1]);
855 break;
856 case nir_op_fadd:
857 result = vir_FADD(c, src[0], src[1]);
858 break;
859 case nir_op_fsub:
860 result = vir_FSUB(c, src[0], src[1]);
861 break;
862 case nir_op_fmin:
863 result = vir_FMIN(c, src[0], src[1]);
864 break;
865 case nir_op_fmax:
866 result = vir_FMAX(c, src[0], src[1]);
867 break;
868
869 case nir_op_f2i32:
870 result = vir_FTOIZ(c, src[0]);
871 break;
872 case nir_op_f2u32:
873 result = vir_FTOUZ(c, src[0]);
874 break;
875 case nir_op_i2f32:
876 result = vir_ITOF(c, src[0]);
877 break;
878 case nir_op_u2f32:
879 result = vir_UTOF(c, src[0]);
880 break;
881 case nir_op_b2f32:
882 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
883 break;
884 case nir_op_b2i32:
885 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
886 break;
887
888 case nir_op_iadd:
889 result = vir_ADD(c, src[0], src[1]);
890 break;
891 case nir_op_ushr:
892 result = vir_SHR(c, src[0], src[1]);
893 break;
894 case nir_op_isub:
895 result = vir_SUB(c, src[0], src[1]);
896 break;
897 case nir_op_ishr:
898 result = vir_ASR(c, src[0], src[1]);
899 break;
900 case nir_op_ishl:
901 result = vir_SHL(c, src[0], src[1]);
902 break;
903 case nir_op_imin:
904 result = vir_MIN(c, src[0], src[1]);
905 break;
906 case nir_op_umin:
907 result = vir_UMIN(c, src[0], src[1]);
908 break;
909 case nir_op_imax:
910 result = vir_MAX(c, src[0], src[1]);
911 break;
912 case nir_op_umax:
913 result = vir_UMAX(c, src[0], src[1]);
914 break;
915 case nir_op_iand:
916 result = vir_AND(c, src[0], src[1]);
917 break;
918 case nir_op_ior:
919 result = vir_OR(c, src[0], src[1]);
920 break;
921 case nir_op_ixor:
922 result = vir_XOR(c, src[0], src[1]);
923 break;
924 case nir_op_inot:
925 result = vir_NOT(c, src[0]);
926 break;
927
928 case nir_op_ufind_msb:
929 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
930 break;
931
932 case nir_op_imul:
933 result = vir_UMUL(c, src[0], src[1]);
934 break;
935
936 case nir_op_seq:
937 case nir_op_sne:
938 case nir_op_sge:
939 case nir_op_slt: {
940 enum v3d_qpu_cond cond;
941 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
942 assert(ok);
943 result = vir_MOV(c, vir_SEL(c, cond,
944 vir_uniform_f(c, 1.0),
945 vir_uniform_f(c, 0.0)));
946 break;
947 }
948
949 case nir_op_i2b32:
950 case nir_op_f2b32:
951 case nir_op_feq32:
952 case nir_op_fne32:
953 case nir_op_fge32:
954 case nir_op_flt32:
955 case nir_op_ieq32:
956 case nir_op_ine32:
957 case nir_op_ige32:
958 case nir_op_uge32:
959 case nir_op_ilt32:
960 case nir_op_ult32: {
961 enum v3d_qpu_cond cond;
962 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
963 assert(ok);
964 result = vir_MOV(c, vir_SEL(c, cond,
965 vir_uniform_ui(c, ~0),
966 vir_uniform_ui(c, 0)));
967 break;
968 }
969
970 case nir_op_b32csel:
971 result = vir_MOV(c,
972 vir_SEL(c,
973 ntq_emit_bool_to_cond(c, instr->src[0].src),
974 src[1], src[2]));
975 break;
976
977 case nir_op_fcsel:
978 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
979 V3D_QPU_PF_PUSHZ);
980 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
981 src[1], src[2]));
982 break;
983
984 case nir_op_frcp:
985 result = vir_RECIP(c, src[0]);
986 break;
987 case nir_op_frsq:
988 result = vir_RSQRT(c, src[0]);
989 break;
990 case nir_op_fexp2:
991 result = vir_EXP(c, src[0]);
992 break;
993 case nir_op_flog2:
994 result = vir_LOG(c, src[0]);
995 break;
996
997 case nir_op_fceil:
998 result = vir_FCEIL(c, src[0]);
999 break;
1000 case nir_op_ffloor:
1001 result = vir_FFLOOR(c, src[0]);
1002 break;
1003 case nir_op_fround_even:
1004 result = vir_FROUND(c, src[0]);
1005 break;
1006 case nir_op_ftrunc:
1007 result = vir_FTRUNC(c, src[0]);
1008 break;
1009
1010 case nir_op_fsin:
1011 result = ntq_fsincos(c, src[0], false);
1012 break;
1013 case nir_op_fcos:
1014 result = ntq_fsincos(c, src[0], true);
1015 break;
1016
1017 case nir_op_fsign:
1018 result = ntq_fsign(c, src[0]);
1019 break;
1020
1021 case nir_op_fabs: {
1022 result = vir_FMOV(c, src[0]);
1023 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1024 break;
1025 }
1026
1027 case nir_op_iabs:
1028 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1029 break;
1030
1031 case nir_op_fddx:
1032 case nir_op_fddx_coarse:
1033 case nir_op_fddx_fine:
1034 result = vir_FDX(c, src[0]);
1035 break;
1036
1037 case nir_op_fddy:
1038 case nir_op_fddy_coarse:
1039 case nir_op_fddy_fine:
1040 result = vir_FDY(c, src[0]);
1041 break;
1042
1043 case nir_op_uadd_carry:
1044 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1045 V3D_QPU_PF_PUSHC);
1046 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1047 vir_uniform_ui(c, ~0),
1048 vir_uniform_ui(c, 0)));
1049 break;
1050
1051 case nir_op_pack_half_2x16_split:
1052 result = vir_VFPACK(c, src[0], src[1]);
1053 break;
1054
1055 case nir_op_unpack_half_2x16_split_x:
1056 result = vir_FMOV(c, src[0]);
1057 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1058 break;
1059
1060 case nir_op_unpack_half_2x16_split_y:
1061 result = vir_FMOV(c, src[0]);
1062 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1063 break;
1064
1065 default:
1066 fprintf(stderr, "unknown NIR ALU inst: ");
1067 nir_print_instr(&instr->instr, stderr);
1068 fprintf(stderr, "\n");
1069 abort();
1070 }
1071
1072 /* We have a scalar result, so the instruction should only have a
1073 * single channel written to.
1074 */
1075 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1076 ntq_store_dest(c, &instr->dest.dest,
1077 ffs(instr->dest.write_mask) - 1, result);
1078 }
1079
1080 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1081 * specifier. They come from a register that's preloaded with 0xffffffff
1082 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1083 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1084 */
1085 #define TLB_TYPE_F16_COLOR (3 << 6)
1086 #define TLB_TYPE_I32_COLOR (1 << 6)
1087 #define TLB_TYPE_F32_COLOR (0 << 6)
1088 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1089 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1090 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1091 #define TLB_F16_SWAP_HI_LO (1 << 1)
1092 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1093 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1094 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1095
1096 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1097 * flag is set.
1098 */
1099 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1100 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1101 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1102 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1103 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1104
1105 /* Stencil is a single 32-bit write. */
1106 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1107
1108 static void
1109 emit_frag_end(struct v3d_compile *c)
1110 {
1111 /* XXX
1112 if (c->output_sample_mask_index != -1) {
1113 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1114 }
1115 */
1116
1117 bool has_any_tlb_color_write = false;
1118 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1119 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1120 has_any_tlb_color_write = true;
1121 }
1122
1123 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1124 struct nir_variable *var = c->output_color_var[0];
1125 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1126
1127 vir_SETMSF_dest(c, vir_nop_reg(),
1128 vir_AND(c,
1129 vir_MSF(c),
1130 vir_FTOC(c, color[3])));
1131 }
1132
1133 if (c->output_position_index != -1) {
1134 struct qinst *inst = vir_MOV_dest(c,
1135 vir_reg(QFILE_TLBU, 0),
1136 c->outputs[c->output_position_index]);
1137 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1138
1139 if (c->devinfo->ver >= 42) {
1140 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1141 TLB_SAMPLE_MODE_PER_PIXEL);
1142 } else
1143 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1144
1145 inst->src[vir_get_implicit_uniform_src(inst)] =
1146 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1147 c->writes_z = true;
1148 } else if (c->s->info.fs.uses_discard ||
1149 !c->s->info.fs.early_fragment_tests ||
1150 c->fs_key->sample_alpha_to_coverage ||
1151 !has_any_tlb_color_write) {
1152 /* Emit passthrough Z if it needed to be delayed until shader
1153 * end due to potential discards.
1154 *
1155 * Since (single-threaded) fragment shaders always need a TLB
1156 * write, emit passthrouh Z if we didn't have any color
1157 * buffers and flag us as potentially discarding, so that we
1158 * can use Z as the TLB write.
1159 */
1160 c->s->info.fs.uses_discard = true;
1161
1162 struct qinst *inst = vir_MOV_dest(c,
1163 vir_reg(QFILE_TLBU, 0),
1164 vir_nop_reg());
1165 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1166
1167 if (c->devinfo->ver >= 42) {
1168 /* The spec says the PER_PIXEL flag is ignored for
1169 * invariant writes, but the simulator demands it.
1170 */
1171 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1172 TLB_SAMPLE_MODE_PER_PIXEL);
1173 } else {
1174 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1175 }
1176
1177 inst->src[vir_get_implicit_uniform_src(inst)] =
1178 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1179 c->writes_z = true;
1180 }
1181
1182 /* XXX: Performance improvement: Merge Z write and color writes TLB
1183 * uniform setup
1184 */
1185
1186 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1187 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1188 continue;
1189
1190 nir_variable *var = c->output_color_var[rt];
1191 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1192 int num_components = glsl_get_vector_elements(var->type);
1193 uint32_t conf = 0xffffff00;
1194 struct qinst *inst;
1195
1196 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1197 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1198
1199 if (c->fs_key->swap_color_rb & (1 << rt))
1200 num_components = MAX2(num_components, 3);
1201
1202 assert(num_components != 0);
1203 switch (glsl_get_base_type(var->type)) {
1204 case GLSL_TYPE_UINT:
1205 case GLSL_TYPE_INT:
1206 /* The F32 vs I32 distinction was dropped in 4.2. */
1207 if (c->devinfo->ver < 42)
1208 conf |= TLB_TYPE_I32_COLOR;
1209 else
1210 conf |= TLB_TYPE_F32_COLOR;
1211 conf |= ((num_components - 1) <<
1212 TLB_VEC_SIZE_MINUS_1_SHIFT);
1213
1214 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1215 inst->src[vir_get_implicit_uniform_src(inst)] =
1216 vir_uniform_ui(c, conf);
1217
1218 for (int i = 1; i < num_components; i++) {
1219 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1220 color[i]);
1221 }
1222 break;
1223
1224 default: {
1225 struct qreg r = color[0];
1226 struct qreg g = color[1];
1227 struct qreg b = color[2];
1228 struct qreg a = color[3];
1229
1230 if (c->fs_key->f32_color_rb & (1 << rt)) {
1231 conf |= TLB_TYPE_F32_COLOR;
1232 conf |= ((num_components - 1) <<
1233 TLB_VEC_SIZE_MINUS_1_SHIFT);
1234 } else {
1235 conf |= TLB_TYPE_F16_COLOR;
1236 conf |= TLB_F16_SWAP_HI_LO;
1237 if (num_components >= 3)
1238 conf |= TLB_VEC_SIZE_4_F16;
1239 else
1240 conf |= TLB_VEC_SIZE_2_F16;
1241 }
1242
1243 if (c->fs_key->swap_color_rb & (1 << rt)) {
1244 r = color[2];
1245 b = color[0];
1246 }
1247
1248 if (c->fs_key->sample_alpha_to_one)
1249 a = vir_uniform_f(c, 1.0);
1250
1251 if (c->fs_key->f32_color_rb & (1 << rt)) {
1252 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1253 inst->src[vir_get_implicit_uniform_src(inst)] =
1254 vir_uniform_ui(c, conf);
1255
1256 if (num_components >= 2)
1257 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1258 if (num_components >= 3)
1259 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1260 if (num_components >= 4)
1261 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1262 } else {
1263 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1264 if (conf != ~0) {
1265 inst->dst.file = QFILE_TLBU;
1266 inst->src[vir_get_implicit_uniform_src(inst)] =
1267 vir_uniform_ui(c, conf);
1268 }
1269
1270 if (num_components >= 3)
1271 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1272 }
1273 break;
1274 }
1275 }
1276 }
1277 }
1278
1279 static void
1280 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1281 {
1282 if (c->devinfo->ver >= 40) {
1283 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1284 *vpm_index = *vpm_index + 1;
1285 } else {
1286 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1287 }
1288
1289 c->num_vpm_writes++;
1290 }
1291
1292 static void
1293 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1294 uint32_t *vpm_index)
1295 {
1296 for (int i = 0; i < 2; i++) {
1297 struct qreg coord = c->outputs[c->output_position_index + i];
1298 coord = vir_FMUL(c, coord,
1299 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1300 0));
1301 coord = vir_FMUL(c, coord, rcp_w);
1302 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1303 }
1304
1305 }
1306
1307 static void
1308 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1309 {
1310 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1311 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1312
1313 struct qreg z = c->outputs[c->output_position_index + 2];
1314 z = vir_FMUL(c, z, zscale);
1315 z = vir_FMUL(c, z, rcp_w);
1316 z = vir_FADD(c, z, zoffset);
1317 vir_VPM_WRITE(c, z, vpm_index);
1318 }
1319
1320 static void
1321 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1322 {
1323 vir_VPM_WRITE(c, rcp_w, vpm_index);
1324 }
1325
1326 static void
1327 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1328 {
1329 struct qreg point_size;
1330
1331 if (c->output_point_size_index != -1)
1332 point_size = c->outputs[c->output_point_size_index];
1333 else
1334 point_size = vir_uniform_f(c, 1.0);
1335
1336 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1337 * BCM21553).
1338 */
1339 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1340
1341 vir_VPM_WRITE(c, point_size, vpm_index);
1342 }
1343
1344 static void
1345 emit_vpm_write_setup(struct v3d_compile *c)
1346 {
1347 if (c->devinfo->ver >= 40)
1348 return;
1349
1350 v3d33_vir_vpm_write_setup(c);
1351 }
1352
1353 /**
1354 * Sets up c->outputs[c->output_position_index] for the vertex shader
1355 * epilogue, if an output vertex position wasn't specified in the user's
1356 * shader. This may be the case for transform feedback with rasterizer
1357 * discard enabled.
1358 */
1359 static void
1360 setup_default_position(struct v3d_compile *c)
1361 {
1362 if (c->output_position_index != -1)
1363 return;
1364
1365 c->output_position_index = c->outputs_array_size;
1366 for (int i = 0; i < 4; i++) {
1367 add_output(c,
1368 c->output_position_index + i,
1369 VARYING_SLOT_POS, i);
1370 }
1371 }
1372
1373 static void
1374 emit_vert_end(struct v3d_compile *c)
1375 {
1376 setup_default_position(c);
1377
1378 uint32_t vpm_index = 0;
1379 struct qreg rcp_w = vir_RECIP(c,
1380 c->outputs[c->output_position_index + 3]);
1381
1382 emit_vpm_write_setup(c);
1383
1384 if (c->vs_key->is_coord) {
1385 for (int i = 0; i < 4; i++)
1386 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1387 &vpm_index);
1388 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1389 if (c->vs_key->per_vertex_point_size) {
1390 emit_point_size_write(c, &vpm_index);
1391 /* emit_rcp_wc_write(c, rcp_w); */
1392 }
1393 /* XXX: Z-only rendering */
1394 if (0)
1395 emit_zs_write(c, rcp_w, &vpm_index);
1396 } else {
1397 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1398 emit_zs_write(c, rcp_w, &vpm_index);
1399 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1400 if (c->vs_key->per_vertex_point_size)
1401 emit_point_size_write(c, &vpm_index);
1402 }
1403
1404 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1405 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1406 int j;
1407
1408 for (j = 0; j < c->num_outputs; j++) {
1409 struct v3d_varying_slot output = c->output_slots[j];
1410
1411 if (!memcmp(&input, &output, sizeof(input))) {
1412 vir_VPM_WRITE(c, c->outputs[j],
1413 &vpm_index);
1414 break;
1415 }
1416 }
1417 /* Emit padding if we didn't find a declared VS output for
1418 * this FS input.
1419 */
1420 if (j == c->num_outputs)
1421 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1422 &vpm_index);
1423 }
1424
1425 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1426 */
1427 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1428 vir_VPMWT(c);
1429 }
1430
1431 void
1432 v3d_optimize_nir(struct nir_shader *s)
1433 {
1434 bool progress;
1435
1436 do {
1437 progress = false;
1438
1439 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1440 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1441 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1442 NIR_PASS(progress, s, nir_copy_prop);
1443 NIR_PASS(progress, s, nir_opt_remove_phis);
1444 NIR_PASS(progress, s, nir_opt_dce);
1445 NIR_PASS(progress, s, nir_opt_dead_cf);
1446 NIR_PASS(progress, s, nir_opt_cse);
1447 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1448 NIR_PASS(progress, s, nir_opt_algebraic);
1449 NIR_PASS(progress, s, nir_opt_constant_folding);
1450 NIR_PASS(progress, s, nir_opt_undef);
1451 } while (progress);
1452
1453 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1454 }
1455
1456 static int
1457 driver_location_compare(const void *in_a, const void *in_b)
1458 {
1459 const nir_variable *const *a = in_a;
1460 const nir_variable *const *b = in_b;
1461
1462 return (*a)->data.driver_location - (*b)->data.driver_location;
1463 }
1464
1465 static struct qreg
1466 ntq_emit_vpm_read(struct v3d_compile *c,
1467 uint32_t *num_components_queued,
1468 uint32_t *remaining,
1469 uint32_t vpm_index)
1470 {
1471 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1472
1473 if (c->devinfo->ver >= 40 ) {
1474 return vir_LDVPMV_IN(c,
1475 vir_uniform_ui(c,
1476 (*num_components_queued)++));
1477 }
1478
1479 if (*num_components_queued != 0) {
1480 (*num_components_queued)--;
1481 return vir_MOV(c, vpm);
1482 }
1483
1484 uint32_t num_components = MIN2(*remaining, 32);
1485
1486 v3d33_vir_vpm_read_setup(c, num_components);
1487
1488 *num_components_queued = num_components - 1;
1489 *remaining -= num_components;
1490
1491 return vir_MOV(c, vpm);
1492 }
1493
1494 static void
1495 ntq_setup_vpm_inputs(struct v3d_compile *c)
1496 {
1497 /* Figure out how many components of each vertex attribute the shader
1498 * uses. Each variable should have been split to individual
1499 * components and unused ones DCEed. The vertex fetcher will load
1500 * from the start of the attribute to the number of components we
1501 * declare we need in c->vattr_sizes[].
1502 */
1503 nir_foreach_variable(var, &c->s->inputs) {
1504 /* No VS attribute array support. */
1505 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1506
1507 unsigned loc = var->data.driver_location;
1508 int start_component = var->data.location_frac;
1509 int num_components = glsl_get_components(var->type);
1510
1511 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1512 start_component + num_components);
1513 }
1514
1515 unsigned num_components = 0;
1516 uint32_t vpm_components_queued = 0;
1517 bool uses_iid = c->s->info.system_values_read &
1518 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1519 bool uses_vid = c->s->info.system_values_read &
1520 (1ull << SYSTEM_VALUE_VERTEX_ID);
1521 num_components += uses_iid;
1522 num_components += uses_vid;
1523
1524 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1525 num_components += c->vattr_sizes[i];
1526
1527 if (uses_iid) {
1528 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1529 &num_components, ~0);
1530 }
1531
1532 if (uses_vid) {
1533 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1534 &num_components, ~0);
1535 }
1536
1537 /* The actual loads will happen directly in nir_intrinsic_load_input
1538 * on newer versions.
1539 */
1540 if (c->devinfo->ver >= 40)
1541 return;
1542
1543 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1544 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1545 (loc + 1) * 4);
1546
1547 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1548 c->inputs[loc * 4 + i] =
1549 ntq_emit_vpm_read(c,
1550 &vpm_components_queued,
1551 &num_components,
1552 loc * 4 + i);
1553
1554 }
1555 }
1556
1557 if (c->devinfo->ver >= 40) {
1558 assert(vpm_components_queued == num_components);
1559 } else {
1560 assert(vpm_components_queued == 0);
1561 assert(num_components == 0);
1562 }
1563 }
1564
1565 static void
1566 ntq_setup_fs_inputs(struct v3d_compile *c)
1567 {
1568 unsigned num_entries = 0;
1569 unsigned num_components = 0;
1570 nir_foreach_variable(var, &c->s->inputs) {
1571 num_entries++;
1572 num_components += glsl_get_components(var->type);
1573 }
1574
1575 nir_variable *vars[num_entries];
1576
1577 unsigned i = 0;
1578 nir_foreach_variable(var, &c->s->inputs)
1579 vars[i++] = var;
1580
1581 /* Sort the variables so that we emit the input setup in
1582 * driver_location order. This is required for VPM reads, whose data
1583 * is fetched into the VPM in driver_location (TGSI register index)
1584 * order.
1585 */
1586 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1587
1588 for (unsigned i = 0; i < num_entries; i++) {
1589 nir_variable *var = vars[i];
1590 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1591 unsigned loc = var->data.driver_location;
1592
1593 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1594 (loc + array_len) * 4);
1595
1596 if (var->data.location == VARYING_SLOT_POS) {
1597 emit_fragcoord_input(c, loc);
1598 } else if (var->data.location == VARYING_SLOT_PNTC ||
1599 (var->data.location >= VARYING_SLOT_VAR0 &&
1600 (c->fs_key->point_sprite_mask &
1601 (1 << (var->data.location -
1602 VARYING_SLOT_VAR0))))) {
1603 c->inputs[loc * 4 + 0] = c->point_x;
1604 c->inputs[loc * 4 + 1] = c->point_y;
1605 } else {
1606 for (int j = 0; j < array_len; j++)
1607 emit_fragment_input(c, loc + j, var, j);
1608 }
1609 }
1610 }
1611
1612 static void
1613 ntq_setup_outputs(struct v3d_compile *c)
1614 {
1615 nir_foreach_variable(var, &c->s->outputs) {
1616 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1617 unsigned loc = var->data.driver_location * 4;
1618
1619 assert(array_len == 1);
1620 (void)array_len;
1621
1622 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1623 add_output(c, loc + var->data.location_frac + i,
1624 var->data.location,
1625 var->data.location_frac + i);
1626 }
1627
1628 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1629 switch (var->data.location) {
1630 case FRAG_RESULT_COLOR:
1631 c->output_color_var[0] = var;
1632 c->output_color_var[1] = var;
1633 c->output_color_var[2] = var;
1634 c->output_color_var[3] = var;
1635 break;
1636 case FRAG_RESULT_DATA0:
1637 case FRAG_RESULT_DATA1:
1638 case FRAG_RESULT_DATA2:
1639 case FRAG_RESULT_DATA3:
1640 c->output_color_var[var->data.location -
1641 FRAG_RESULT_DATA0] = var;
1642 break;
1643 case FRAG_RESULT_DEPTH:
1644 c->output_position_index = loc;
1645 break;
1646 case FRAG_RESULT_SAMPLE_MASK:
1647 c->output_sample_mask_index = loc;
1648 break;
1649 }
1650 } else {
1651 switch (var->data.location) {
1652 case VARYING_SLOT_POS:
1653 c->output_position_index = loc;
1654 break;
1655 case VARYING_SLOT_PSIZ:
1656 c->output_point_size_index = loc;
1657 break;
1658 }
1659 }
1660 }
1661 }
1662
1663 static void
1664 ntq_setup_uniforms(struct v3d_compile *c)
1665 {
1666 nir_foreach_variable(var, &c->s->uniforms) {
1667 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1668 false);
1669 unsigned vec4_size = 4 * sizeof(float);
1670
1671 if (var->data.mode != nir_var_uniform)
1672 continue;
1673
1674 declare_uniform_range(c, var->data.driver_location * vec4_size,
1675 vec4_count * vec4_size);
1676
1677 }
1678 }
1679
1680 /**
1681 * Sets up the mapping from nir_register to struct qreg *.
1682 *
1683 * Each nir_register gets a struct qreg per 32-bit component being stored.
1684 */
1685 static void
1686 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1687 {
1688 foreach_list_typed(nir_register, nir_reg, node, list) {
1689 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1690 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1691 array_len *
1692 nir_reg->num_components);
1693
1694 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1695
1696 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1697 qregs[i] = vir_get_temp(c);
1698 }
1699 }
1700
1701 static void
1702 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1703 {
1704 /* XXX perf: Experiment with using immediate loads to avoid having
1705 * these end up in the uniform stream. Watch out for breaking the
1706 * small immediates optimization in the process!
1707 */
1708 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1709 for (int i = 0; i < instr->def.num_components; i++)
1710 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1711
1712 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1713 }
1714
1715 static void
1716 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1717 {
1718 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1719
1720 /* VIR needs there to be *some* value, so pick 0 (same as for
1721 * ntq_setup_registers().
1722 */
1723 for (int i = 0; i < instr->def.num_components; i++)
1724 qregs[i] = vir_uniform_ui(c, 0);
1725 }
1726
1727 static void
1728 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1729 {
1730 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1731 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1732 unsigned image_index = var->data.driver_location;
1733 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1734 bool is_array = glsl_sampler_type_is_array(sampler_type);
1735
1736 ntq_store_dest(c, &instr->dest, 0,
1737 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1738 if (instr->num_components > 1) {
1739 ntq_store_dest(c, &instr->dest, 1,
1740 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1741 image_index));
1742 }
1743 if (instr->num_components > 2) {
1744 ntq_store_dest(c, &instr->dest, 2,
1745 vir_uniform(c,
1746 is_array ?
1747 QUNIFORM_IMAGE_ARRAY_SIZE :
1748 QUNIFORM_IMAGE_DEPTH,
1749 image_index));
1750 }
1751 }
1752
1753 static void
1754 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1755 {
1756 unsigned offset;
1757
1758 switch (instr->intrinsic) {
1759 case nir_intrinsic_load_uniform:
1760 if (nir_src_is_const(instr->src[0])) {
1761 int offset = (nir_intrinsic_base(instr) +
1762 nir_src_as_uint(instr->src[0]));
1763 assert(offset % 4 == 0);
1764 /* We need dwords */
1765 offset = offset / 4;
1766 for (int i = 0; i < instr->num_components; i++) {
1767 ntq_store_dest(c, &instr->dest, i,
1768 vir_uniform(c, QUNIFORM_UNIFORM,
1769 offset + i));
1770 }
1771 } else {
1772 ntq_emit_tmu_general(c, instr, false);
1773 }
1774 break;
1775
1776 case nir_intrinsic_load_ubo:
1777 ntq_emit_tmu_general(c, instr, false);
1778 break;
1779
1780 case nir_intrinsic_ssbo_atomic_add:
1781 case nir_intrinsic_ssbo_atomic_imin:
1782 case nir_intrinsic_ssbo_atomic_umin:
1783 case nir_intrinsic_ssbo_atomic_imax:
1784 case nir_intrinsic_ssbo_atomic_umax:
1785 case nir_intrinsic_ssbo_atomic_and:
1786 case nir_intrinsic_ssbo_atomic_or:
1787 case nir_intrinsic_ssbo_atomic_xor:
1788 case nir_intrinsic_ssbo_atomic_exchange:
1789 case nir_intrinsic_ssbo_atomic_comp_swap:
1790 case nir_intrinsic_load_ssbo:
1791 case nir_intrinsic_store_ssbo:
1792 ntq_emit_tmu_general(c, instr, false);
1793 break;
1794
1795 case nir_intrinsic_shared_atomic_add:
1796 case nir_intrinsic_shared_atomic_imin:
1797 case nir_intrinsic_shared_atomic_umin:
1798 case nir_intrinsic_shared_atomic_imax:
1799 case nir_intrinsic_shared_atomic_umax:
1800 case nir_intrinsic_shared_atomic_and:
1801 case nir_intrinsic_shared_atomic_or:
1802 case nir_intrinsic_shared_atomic_xor:
1803 case nir_intrinsic_shared_atomic_exchange:
1804 case nir_intrinsic_shared_atomic_comp_swap:
1805 case nir_intrinsic_load_shared:
1806 case nir_intrinsic_store_shared:
1807 ntq_emit_tmu_general(c, instr, true);
1808 break;
1809
1810 case nir_intrinsic_image_deref_load:
1811 case nir_intrinsic_image_deref_store:
1812 case nir_intrinsic_image_deref_atomic_add:
1813 case nir_intrinsic_image_deref_atomic_min:
1814 case nir_intrinsic_image_deref_atomic_max:
1815 case nir_intrinsic_image_deref_atomic_and:
1816 case nir_intrinsic_image_deref_atomic_or:
1817 case nir_intrinsic_image_deref_atomic_xor:
1818 case nir_intrinsic_image_deref_atomic_exchange:
1819 case nir_intrinsic_image_deref_atomic_comp_swap:
1820 v3d40_vir_emit_image_load_store(c, instr);
1821 break;
1822
1823 case nir_intrinsic_get_buffer_size:
1824 ntq_store_dest(c, &instr->dest, 0,
1825 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1826 nir_src_as_uint(instr->src[0])));
1827 break;
1828
1829 case nir_intrinsic_load_user_clip_plane:
1830 for (int i = 0; i < instr->num_components; i++) {
1831 ntq_store_dest(c, &instr->dest, i,
1832 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1833 nir_intrinsic_ucp_id(instr) *
1834 4 + i));
1835 }
1836 break;
1837
1838 case nir_intrinsic_load_alpha_ref_float:
1839 ntq_store_dest(c, &instr->dest, 0,
1840 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1841 break;
1842
1843 case nir_intrinsic_load_sample_mask_in:
1844 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1845 break;
1846
1847 case nir_intrinsic_load_helper_invocation:
1848 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1849 ntq_store_dest(c, &instr->dest, 0,
1850 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1851 vir_uniform_ui(c, ~0),
1852 vir_uniform_ui(c, 0))));
1853 break;
1854
1855 case nir_intrinsic_load_front_face:
1856 /* The register contains 0 (front) or 1 (back), and we need to
1857 * turn it into a NIR bool where true means front.
1858 */
1859 ntq_store_dest(c, &instr->dest, 0,
1860 vir_ADD(c,
1861 vir_uniform_ui(c, -1),
1862 vir_REVF(c)));
1863 break;
1864
1865 case nir_intrinsic_load_instance_id:
1866 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1867 break;
1868
1869 case nir_intrinsic_load_vertex_id:
1870 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1871 break;
1872
1873 case nir_intrinsic_load_input:
1874 offset = (nir_intrinsic_base(instr) +
1875 nir_src_as_uint(instr->src[0]));
1876 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1877 c->devinfo->ver >= 40) {
1878 /* Emit the LDVPM directly now, rather than at the top
1879 * of the shader like we did for V3D 3.x (which needs
1880 * vpmsetup when not just taking the next offset).
1881 *
1882 * Note that delaying like this may introduce stalls,
1883 * as LDVPMV takes a minimum of 1 instruction but may
1884 * be slower if the VPM unit is busy with another QPU.
1885 */
1886 int index = 0;
1887 if (c->s->info.system_values_read &
1888 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1889 index++;
1890 }
1891 if (c->s->info.system_values_read &
1892 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1893 index++;
1894 }
1895 for (int i = 0; i < offset; i++)
1896 index += c->vattr_sizes[i];
1897 index += nir_intrinsic_component(instr);
1898 for (int i = 0; i < instr->num_components; i++) {
1899 struct qreg vpm_offset =
1900 vir_uniform_ui(c, index++);
1901 ntq_store_dest(c, &instr->dest, i,
1902 vir_LDVPMV_IN(c, vpm_offset));
1903 }
1904 } else {
1905 for (int i = 0; i < instr->num_components; i++) {
1906 int comp = nir_intrinsic_component(instr) + i;
1907 ntq_store_dest(c, &instr->dest, i,
1908 vir_MOV(c, c->inputs[offset * 4 +
1909 comp]));
1910 }
1911 }
1912 break;
1913
1914 case nir_intrinsic_store_output:
1915 offset = ((nir_intrinsic_base(instr) +
1916 nir_src_as_uint(instr->src[1])) * 4 +
1917 nir_intrinsic_component(instr));
1918
1919 for (int i = 0; i < instr->num_components; i++) {
1920 c->outputs[offset + i] =
1921 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1922 }
1923 c->num_outputs = MAX2(c->num_outputs,
1924 offset + instr->num_components);
1925 break;
1926
1927 case nir_intrinsic_image_deref_size:
1928 ntq_emit_image_size(c, instr);
1929 break;
1930
1931 case nir_intrinsic_discard:
1932 if (vir_in_nonuniform_control_flow(c)) {
1933 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1934 V3D_QPU_PF_PUSHZ);
1935 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1936 vir_uniform_ui(c, 0)),
1937 V3D_QPU_COND_IFA);
1938 } else {
1939 vir_SETMSF_dest(c, vir_nop_reg(),
1940 vir_uniform_ui(c, 0));
1941 }
1942 break;
1943
1944 case nir_intrinsic_discard_if: {
1945 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1946
1947 if (vir_in_nonuniform_control_flow(c)) {
1948 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1949 c->execute);
1950 if (cond == V3D_QPU_COND_IFA) {
1951 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1952 } else {
1953 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1954 cond = V3D_QPU_COND_IFA;
1955 }
1956 }
1957
1958 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1959 vir_uniform_ui(c, 0)), cond);
1960
1961 break;
1962 }
1963
1964 case nir_intrinsic_memory_barrier:
1965 case nir_intrinsic_memory_barrier_atomic_counter:
1966 case nir_intrinsic_memory_barrier_buffer:
1967 case nir_intrinsic_memory_barrier_image:
1968 case nir_intrinsic_memory_barrier_shared:
1969 /* We don't do any instruction scheduling of these NIR
1970 * instructions between each other, so we just need to make
1971 * sure that the TMU operations before the barrier are flushed
1972 * before the ones after the barrier. That is currently
1973 * handled by having a THRSW in each of them and a LDTMU
1974 * series or a TMUWT after.
1975 */
1976 break;
1977
1978 case nir_intrinsic_barrier:
1979 /* Emit a TSY op to get all invocations in the workgroup
1980 * (actually supergroup) to block until the last invocation
1981 * reaches the TSY op.
1982 */
1983 if (c->devinfo->ver >= 42) {
1984 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1985 V3D_QPU_WADDR_SYNCB));
1986 } else {
1987 struct qinst *sync =
1988 vir_BARRIERID_dest(c,
1989 vir_reg(QFILE_MAGIC,
1990 V3D_QPU_WADDR_SYNCU));
1991 sync->src[vir_get_implicit_uniform_src(sync)] =
1992 vir_uniform_ui(c,
1993 0xffffff00 |
1994 V3D_TSY_WAIT_INC_CHECK);
1995
1996 }
1997
1998 /* The blocking of a TSY op only happens at the next thread
1999 * switch. No texturing may be outstanding at the time of a
2000 * TSY blocking operation.
2001 */
2002 vir_emit_thrsw(c);
2003 break;
2004
2005 case nir_intrinsic_load_num_work_groups:
2006 for (int i = 0; i < 3; i++) {
2007 ntq_store_dest(c, &instr->dest, i,
2008 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2009 i));
2010 }
2011 break;
2012
2013 case nir_intrinsic_load_local_invocation_index:
2014 ntq_store_dest(c, &instr->dest, 0,
2015 vir_SHR(c, c->cs_payload[1],
2016 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2017 break;
2018
2019 case nir_intrinsic_load_work_group_id:
2020 ntq_store_dest(c, &instr->dest, 0,
2021 vir_AND(c, c->cs_payload[0],
2022 vir_uniform_ui(c, 0xffff)));
2023 ntq_store_dest(c, &instr->dest, 1,
2024 vir_SHR(c, c->cs_payload[0],
2025 vir_uniform_ui(c, 16)));
2026 ntq_store_dest(c, &instr->dest, 2,
2027 vir_AND(c, c->cs_payload[1],
2028 vir_uniform_ui(c, 0xffff)));
2029 break;
2030
2031 default:
2032 fprintf(stderr, "Unknown intrinsic: ");
2033 nir_print_instr(&instr->instr, stderr);
2034 fprintf(stderr, "\n");
2035 break;
2036 }
2037 }
2038
2039 /* Clears (activates) the execute flags for any channels whose jump target
2040 * matches this block.
2041 *
2042 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2043 * enabling?
2044 *
2045 * XXX perf: For uniform control flow, we should be able to skip c->execute
2046 * handling entirely.
2047 */
2048 static void
2049 ntq_activate_execute_for_block(struct v3d_compile *c)
2050 {
2051 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2052 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2053 V3D_QPU_PF_PUSHZ);
2054
2055 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2056 }
2057
2058 static void
2059 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2060 {
2061 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2062 bool empty_else_block =
2063 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2064 exec_list_is_empty(&nir_else_block->instr_list));
2065
2066 struct qblock *then_block = vir_new_block(c);
2067 struct qblock *after_block = vir_new_block(c);
2068 struct qblock *else_block;
2069 if (empty_else_block)
2070 else_block = after_block;
2071 else
2072 else_block = vir_new_block(c);
2073
2074 /* Set up the flags for the IF condition (taking the THEN branch). */
2075 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2076
2077 /* Jump to ELSE. */
2078 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2079 V3D_QPU_BRANCH_COND_ALLNA :
2080 V3D_QPU_BRANCH_COND_ALLA);
2081 vir_link_blocks(c->cur_block, else_block);
2082 vir_link_blocks(c->cur_block, then_block);
2083
2084 /* Process the THEN block. */
2085 vir_set_emit_block(c, then_block);
2086 ntq_emit_cf_list(c, &if_stmt->then_list);
2087
2088 if (!empty_else_block) {
2089 /* At the end of the THEN block, jump to ENDIF */
2090 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2091 vir_link_blocks(c->cur_block, after_block);
2092
2093 /* Emit the else block. */
2094 vir_set_emit_block(c, else_block);
2095 ntq_activate_execute_for_block(c);
2096 ntq_emit_cf_list(c, &if_stmt->else_list);
2097 }
2098
2099 vir_link_blocks(c->cur_block, after_block);
2100
2101 vir_set_emit_block(c, after_block);
2102 }
2103
2104 static void
2105 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2106 {
2107 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2108 bool empty_else_block =
2109 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2110 exec_list_is_empty(&nir_else_block->instr_list));
2111
2112 struct qblock *then_block = vir_new_block(c);
2113 struct qblock *after_block = vir_new_block(c);
2114 struct qblock *else_block;
2115 if (empty_else_block)
2116 else_block = after_block;
2117 else
2118 else_block = vir_new_block(c);
2119
2120 bool was_uniform_control_flow = false;
2121 if (!vir_in_nonuniform_control_flow(c)) {
2122 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2123 was_uniform_control_flow = true;
2124 }
2125
2126 /* Set up the flags for the IF condition (taking the THEN branch). */
2127 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2128
2129 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2130 * was previously active (execute Z) for updating the exec flags.
2131 */
2132 if (was_uniform_control_flow) {
2133 cond = v3d_qpu_cond_invert(cond);
2134 } else {
2135 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2136 if (cond == V3D_QPU_COND_IFA) {
2137 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2138 } else {
2139 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2140 cond = V3D_QPU_COND_IFA;
2141 }
2142 }
2143
2144 vir_MOV_cond(c, cond,
2145 c->execute,
2146 vir_uniform_ui(c, else_block->index));
2147
2148 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2149 * through.
2150 */
2151 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2152 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2153 vir_link_blocks(c->cur_block, else_block);
2154 vir_link_blocks(c->cur_block, then_block);
2155
2156 /* Process the THEN block. */
2157 vir_set_emit_block(c, then_block);
2158 ntq_emit_cf_list(c, &if_stmt->then_list);
2159
2160 if (!empty_else_block) {
2161 /* Handle the end of the THEN block. First, all currently
2162 * active channels update their execute flags to point to
2163 * ENDIF
2164 */
2165 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2166 V3D_QPU_PF_PUSHZ);
2167 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2168 vir_uniform_ui(c, after_block->index));
2169
2170 /* If everything points at ENDIF, then jump there immediately. */
2171 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2172 c->execute,
2173 vir_uniform_ui(c, after_block->index)),
2174 V3D_QPU_PF_PUSHZ);
2175 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2176 vir_link_blocks(c->cur_block, after_block);
2177 vir_link_blocks(c->cur_block, else_block);
2178
2179 vir_set_emit_block(c, else_block);
2180 ntq_activate_execute_for_block(c);
2181 ntq_emit_cf_list(c, &if_stmt->else_list);
2182 }
2183
2184 vir_link_blocks(c->cur_block, after_block);
2185
2186 vir_set_emit_block(c, after_block);
2187 if (was_uniform_control_flow)
2188 c->execute = c->undef;
2189 else
2190 ntq_activate_execute_for_block(c);
2191 }
2192
2193 static void
2194 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2195 {
2196 bool was_in_control_flow = c->in_control_flow;
2197 c->in_control_flow = true;
2198 if (!vir_in_nonuniform_control_flow(c) &&
2199 nir_src_is_dynamically_uniform(nif->condition)) {
2200 ntq_emit_uniform_if(c, nif);
2201 } else {
2202 ntq_emit_nonuniform_if(c, nif);
2203 }
2204 c->in_control_flow = was_in_control_flow;
2205 }
2206
2207 static void
2208 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2209 {
2210 switch (jump->type) {
2211 case nir_jump_break:
2212 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2213 V3D_QPU_PF_PUSHZ);
2214 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2215 vir_uniform_ui(c, c->loop_break_block->index));
2216 break;
2217
2218 case nir_jump_continue:
2219 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2220 V3D_QPU_PF_PUSHZ);
2221 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2222 vir_uniform_ui(c, c->loop_cont_block->index));
2223 break;
2224
2225 case nir_jump_return:
2226 unreachable("All returns shouold be lowered\n");
2227 }
2228 }
2229
2230 static void
2231 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2232 {
2233 switch (instr->type) {
2234 case nir_instr_type_deref:
2235 /* ignored, will be walked by the intrinsic using it. */
2236 break;
2237
2238 case nir_instr_type_alu:
2239 ntq_emit_alu(c, nir_instr_as_alu(instr));
2240 break;
2241
2242 case nir_instr_type_intrinsic:
2243 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2244 break;
2245
2246 case nir_instr_type_load_const:
2247 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2248 break;
2249
2250 case nir_instr_type_ssa_undef:
2251 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2252 break;
2253
2254 case nir_instr_type_tex:
2255 ntq_emit_tex(c, nir_instr_as_tex(instr));
2256 break;
2257
2258 case nir_instr_type_jump:
2259 ntq_emit_jump(c, nir_instr_as_jump(instr));
2260 break;
2261
2262 default:
2263 fprintf(stderr, "Unknown NIR instr type: ");
2264 nir_print_instr(instr, stderr);
2265 fprintf(stderr, "\n");
2266 abort();
2267 }
2268 }
2269
2270 static void
2271 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2272 {
2273 nir_foreach_instr(instr, block) {
2274 ntq_emit_instr(c, instr);
2275 }
2276 }
2277
2278 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2279
2280 static void
2281 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2282 {
2283 bool was_in_control_flow = c->in_control_flow;
2284 c->in_control_flow = true;
2285
2286 bool was_uniform_control_flow = false;
2287 if (!vir_in_nonuniform_control_flow(c)) {
2288 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2289 was_uniform_control_flow = true;
2290 }
2291
2292 struct qblock *save_loop_cont_block = c->loop_cont_block;
2293 struct qblock *save_loop_break_block = c->loop_break_block;
2294
2295 c->loop_cont_block = vir_new_block(c);
2296 c->loop_break_block = vir_new_block(c);
2297
2298 vir_link_blocks(c->cur_block, c->loop_cont_block);
2299 vir_set_emit_block(c, c->loop_cont_block);
2300 ntq_activate_execute_for_block(c);
2301
2302 ntq_emit_cf_list(c, &loop->body);
2303
2304 /* Re-enable any previous continues now, so our ANYA check below
2305 * works.
2306 *
2307 * XXX: Use the .ORZ flags update, instead.
2308 */
2309 vir_set_pf(vir_XOR_dest(c,
2310 vir_nop_reg(),
2311 c->execute,
2312 vir_uniform_ui(c, c->loop_cont_block->index)),
2313 V3D_QPU_PF_PUSHZ);
2314 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2315
2316 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2317
2318 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2319 /* Pixels that were not dispatched or have been discarded should not
2320 * contribute to looping again.
2321 */
2322 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2323 vir_link_blocks(c->cur_block, c->loop_cont_block);
2324 vir_link_blocks(c->cur_block, c->loop_break_block);
2325
2326 vir_set_emit_block(c, c->loop_break_block);
2327 if (was_uniform_control_flow)
2328 c->execute = c->undef;
2329 else
2330 ntq_activate_execute_for_block(c);
2331
2332 c->loop_break_block = save_loop_break_block;
2333 c->loop_cont_block = save_loop_cont_block;
2334
2335 c->loops++;
2336
2337 c->in_control_flow = was_in_control_flow;
2338 }
2339
2340 static void
2341 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2342 {
2343 fprintf(stderr, "FUNCTIONS not handled.\n");
2344 abort();
2345 }
2346
2347 static void
2348 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2349 {
2350 foreach_list_typed(nir_cf_node, node, node, list) {
2351 switch (node->type) {
2352 case nir_cf_node_block:
2353 ntq_emit_block(c, nir_cf_node_as_block(node));
2354 break;
2355
2356 case nir_cf_node_if:
2357 ntq_emit_if(c, nir_cf_node_as_if(node));
2358 break;
2359
2360 case nir_cf_node_loop:
2361 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2362 break;
2363
2364 case nir_cf_node_function:
2365 ntq_emit_function(c, nir_cf_node_as_function(node));
2366 break;
2367
2368 default:
2369 fprintf(stderr, "Unknown NIR node type\n");
2370 abort();
2371 }
2372 }
2373 }
2374
2375 static void
2376 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2377 {
2378 ntq_setup_registers(c, &impl->registers);
2379 ntq_emit_cf_list(c, &impl->body);
2380 }
2381
2382 static void
2383 nir_to_vir(struct v3d_compile *c)
2384 {
2385 switch (c->s->info.stage) {
2386 case MESA_SHADER_FRAGMENT:
2387 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2388 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2389 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2390
2391 /* XXX perf: We could set the "disable implicit point/line
2392 * varyings" field in the shader record and not emit these, if
2393 * they're not going to be used.
2394 */
2395 if (c->fs_key->is_points) {
2396 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2397 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2398 } else if (c->fs_key->is_lines) {
2399 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2400 }
2401 break;
2402 case MESA_SHADER_COMPUTE:
2403 /* Set up the TSO for barriers, assuming we do some. */
2404 if (c->devinfo->ver < 42) {
2405 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2406 V3D_QPU_WADDR_SYNC));
2407 }
2408
2409 if (c->s->info.system_values_read &
2410 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2411 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2412 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2413 }
2414 if ((c->s->info.system_values_read &
2415 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2416 c->s->info.cs.shared_size) {
2417 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2418 }
2419
2420 /* Set up the division between gl_LocalInvocationIndex and
2421 * wg_in_mem in the payload reg.
2422 */
2423 int wg_size = (c->s->info.cs.local_size[0] *
2424 c->s->info.cs.local_size[1] *
2425 c->s->info.cs.local_size[2]);
2426 c->local_invocation_index_bits =
2427 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2428 assert(c->local_invocation_index_bits <= 8);
2429
2430 if (c->s->info.cs.shared_size) {
2431 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2432 vir_uniform_ui(c, 16));
2433 if (c->s->info.cs.local_size[0] != 1 ||
2434 c->s->info.cs.local_size[1] != 1 ||
2435 c->s->info.cs.local_size[2] != 1) {
2436 int wg_bits = (16 -
2437 c->local_invocation_index_bits);
2438 int wg_mask = (1 << wg_bits) - 1;
2439 wg_in_mem = vir_AND(c, wg_in_mem,
2440 vir_uniform_ui(c, wg_mask));
2441 }
2442 struct qreg shared_per_wg =
2443 vir_uniform_ui(c, c->s->info.cs.shared_size);
2444
2445 c->cs_shared_offset =
2446 vir_ADD(c,
2447 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2448 vir_UMUL(c, wg_in_mem, shared_per_wg));
2449 }
2450 break;
2451 default:
2452 break;
2453 }
2454
2455 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2456 ntq_setup_fs_inputs(c);
2457 else
2458 ntq_setup_vpm_inputs(c);
2459
2460 ntq_setup_outputs(c);
2461 ntq_setup_uniforms(c);
2462 ntq_setup_registers(c, &c->s->registers);
2463
2464 /* Find the main function and emit the body. */
2465 nir_foreach_function(function, c->s) {
2466 assert(strcmp(function->name, "main") == 0);
2467 assert(function->impl);
2468 ntq_emit_impl(c, function->impl);
2469 }
2470 }
2471
2472 const nir_shader_compiler_options v3d_nir_options = {
2473 .lower_all_io_to_temps = true,
2474 .lower_extract_byte = true,
2475 .lower_extract_word = true,
2476 .lower_bfm = true,
2477 .lower_bitfield_insert_to_shifts = true,
2478 .lower_bitfield_extract_to_shifts = true,
2479 .lower_bitfield_reverse = true,
2480 .lower_bit_count = true,
2481 .lower_cs_local_id_from_index = true,
2482 .lower_ffract = true,
2483 .lower_pack_unorm_2x16 = true,
2484 .lower_pack_snorm_2x16 = true,
2485 .lower_pack_unorm_4x8 = true,
2486 .lower_pack_snorm_4x8 = true,
2487 .lower_unpack_unorm_4x8 = true,
2488 .lower_unpack_snorm_4x8 = true,
2489 .lower_pack_half_2x16 = true,
2490 .lower_unpack_half_2x16 = true,
2491 .lower_fdiv = true,
2492 .lower_find_lsb = true,
2493 .lower_ffma = true,
2494 .lower_flrp32 = true,
2495 .lower_fpow = true,
2496 .lower_fsat = true,
2497 .lower_fsqrt = true,
2498 .lower_ifind_msb = true,
2499 .lower_isign = true,
2500 .lower_ldexp = true,
2501 .lower_mul_high = true,
2502 .lower_wpos_pntc = true,
2503 .native_integers = true,
2504 };
2505
2506 /**
2507 * When demoting a shader down to single-threaded, removes the THRSW
2508 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2509 * program end).
2510 */
2511 static void
2512 vir_remove_thrsw(struct v3d_compile *c)
2513 {
2514 vir_for_each_block(block, c) {
2515 vir_for_each_inst_safe(inst, block) {
2516 if (inst->qpu.sig.thrsw)
2517 vir_remove_instruction(c, inst);
2518 }
2519 }
2520
2521 c->last_thrsw = NULL;
2522 }
2523
2524 void
2525 vir_emit_last_thrsw(struct v3d_compile *c)
2526 {
2527 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2528 * switching, so disable threads if we didn't do any TMU ops (each of
2529 * which would have emitted a THRSW).
2530 */
2531 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2532 c->threads = 1;
2533 if (c->last_thrsw)
2534 vir_remove_thrsw(c);
2535 return;
2536 }
2537
2538 /* If we're threaded and the last THRSW was in conditional code, then
2539 * we need to emit another one so that we can flag it as the last
2540 * thrsw.
2541 */
2542 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2543 assert(c->devinfo->ver >= 41);
2544 vir_emit_thrsw(c);
2545 }
2546
2547 /* If we're threaded, then we need to mark the last THRSW instruction
2548 * so we can emit a pair of them at QPU emit time.
2549 *
2550 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2551 * post-last-THRSW state, so we can skip this.
2552 */
2553 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2554 assert(c->devinfo->ver >= 41);
2555 vir_emit_thrsw(c);
2556 }
2557
2558 if (c->last_thrsw)
2559 c->last_thrsw->is_last_thrsw = true;
2560 }
2561
2562 /* There's a flag in the shader for "center W is needed for reasons other than
2563 * non-centroid varyings", so we just walk the program after VIR optimization
2564 * to see if it's used. It should be harmless to set even if we only use
2565 * center W for varyings.
2566 */
2567 static void
2568 vir_check_payload_w(struct v3d_compile *c)
2569 {
2570 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2571 return;
2572
2573 vir_for_each_inst_inorder(inst, c) {
2574 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2575 if (inst->src[i].file == QFILE_REG &&
2576 inst->src[i].index == 0) {
2577 c->uses_center_w = true;
2578 return;
2579 }
2580 }
2581 }
2582
2583 }
2584
2585 void
2586 v3d_nir_to_vir(struct v3d_compile *c)
2587 {
2588 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2589 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2590 fprintf(stderr, "%s prog %d/%d NIR:\n",
2591 vir_get_stage_name(c),
2592 c->program_id, c->variant_id);
2593 nir_print_shader(c->s, stderr);
2594 }
2595
2596 nir_to_vir(c);
2597
2598 /* Emit the last THRSW before STVPM and TLB writes. */
2599 vir_emit_last_thrsw(c);
2600
2601 switch (c->s->info.stage) {
2602 case MESA_SHADER_FRAGMENT:
2603 emit_frag_end(c);
2604 break;
2605 case MESA_SHADER_VERTEX:
2606 emit_vert_end(c);
2607 break;
2608 default:
2609 unreachable("bad stage");
2610 }
2611
2612 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2613 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2614 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2615 vir_get_stage_name(c),
2616 c->program_id, c->variant_id);
2617 vir_dump(c);
2618 fprintf(stderr, "\n");
2619 }
2620
2621 vir_optimize(c);
2622 vir_lower_uniforms(c);
2623
2624 vir_check_payload_w(c);
2625
2626 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2627 * We used that on that platform to pipeline TMU writes and reduce the
2628 * number of thread switches, as well as try (mostly successfully) to
2629 * reduce maximum register pressure to allow more threads. We should
2630 * do something of that sort for V3D -- either instruction scheduling
2631 * here, or delay the the THRSW and LDTMUs from our texture
2632 * instructions until the results are needed.
2633 */
2634
2635 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2636 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2637 fprintf(stderr, "%s prog %d/%d VIR:\n",
2638 vir_get_stage_name(c),
2639 c->program_id, c->variant_id);
2640 vir_dump(c);
2641 fprintf(stderr, "\n");
2642 }
2643
2644 /* Attempt to allocate registers for the temporaries. If we fail,
2645 * reduce thread count and try again.
2646 */
2647 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2648 struct qpu_reg *temp_registers;
2649 while (true) {
2650 bool spilled;
2651 temp_registers = v3d_register_allocate(c, &spilled);
2652 if (spilled)
2653 continue;
2654
2655 if (temp_registers)
2656 break;
2657
2658 if (c->threads == min_threads) {
2659 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2660 c->threads);
2661 vir_dump(c);
2662 c->failed = true;
2663 return;
2664 }
2665
2666 c->threads /= 2;
2667
2668 if (c->threads == 1)
2669 vir_remove_thrsw(c);
2670 }
2671
2672 if (c->spill_size &&
2673 (V3D_DEBUG & (V3D_DEBUG_VIR |
2674 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2675 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2676 vir_get_stage_name(c),
2677 c->program_id, c->variant_id);
2678 vir_dump(c);
2679 fprintf(stderr, "\n");
2680 }
2681
2682 v3d_vir_to_qpu(c, temp_registers);
2683 }