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[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct qinst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68 };
69
70 struct schedule_node_child {
71 struct schedule_node *node;
72 bool write_after_read;
73 };
74
75 /* When walking the instructions in reverse, we need to swap before/after in
76 * add_dep().
77 */
78 enum direction { F, R };
79
80 struct schedule_state {
81 const struct v3d_device_info *devinfo;
82 struct schedule_node *last_r[6];
83 struct schedule_node *last_rf[64];
84 struct schedule_node *last_sf;
85 struct schedule_node *last_vpm_read;
86 struct schedule_node *last_tmu_write;
87 struct schedule_node *last_tmu_config;
88 struct schedule_node *last_tlb;
89 struct schedule_node *last_vpm;
90 struct schedule_node *last_unif;
91 struct schedule_node *last_rtop;
92 enum direction dir;
93 /* Estimated cycle when the current instruction would start. */
94 uint32_t time;
95 };
96
97 static void
98 add_dep(struct schedule_state *state,
99 struct schedule_node *before,
100 struct schedule_node *after,
101 bool write)
102 {
103 bool write_after_read = !write && state->dir == R;
104
105 if (!before || !after)
106 return;
107
108 assert(before != after);
109
110 if (state->dir == R) {
111 struct schedule_node *t = before;
112 before = after;
113 after = t;
114 }
115
116 for (int i = 0; i < before->child_count; i++) {
117 if (before->children[i].node == after &&
118 (before->children[i].write_after_read == write_after_read)) {
119 return;
120 }
121 }
122
123 if (before->child_array_size <= before->child_count) {
124 before->child_array_size = MAX2(before->child_array_size * 2, 16);
125 before->children = reralloc(before, before->children,
126 struct schedule_node_child,
127 before->child_array_size);
128 }
129
130 before->children[before->child_count].node = after;
131 before->children[before->child_count].write_after_read =
132 write_after_read;
133 before->child_count++;
134 after->parent_count++;
135 }
136
137 static void
138 add_read_dep(struct schedule_state *state,
139 struct schedule_node *before,
140 struct schedule_node *after)
141 {
142 add_dep(state, before, after, false);
143 }
144
145 static void
146 add_write_dep(struct schedule_state *state,
147 struct schedule_node **before,
148 struct schedule_node *after)
149 {
150 add_dep(state, *before, after, true);
151 *before = after;
152 }
153
154 static bool
155 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
156 {
157 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
158 return false;
159
160 if (inst->alu.add.magic_write &&
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
163 return true;
164
165 if (inst->alu.mul.magic_write &&
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
168 return true;
169
170 return false;
171 }
172
173 static void
174 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
175 enum v3d_qpu_mux mux)
176 {
177 switch (mux) {
178 case V3D_QPU_MUX_A:
179 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
180 break;
181 case V3D_QPU_MUX_B:
182 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
183 break;
184 default:
185 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
186 break;
187 }
188 }
189
190
191 static void
192 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
193 uint32_t waddr, bool magic)
194 {
195 if (!magic) {
196 add_write_dep(state, &state->last_rf[waddr], n);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
198 add_write_dep(state, &state->last_tmu_write, n);
199 switch (waddr) {
200 case V3D_QPU_WADDR_TMUS:
201 case V3D_QPU_WADDR_TMUSCM:
202 case V3D_QPU_WADDR_TMUSF:
203 case V3D_QPU_WADDR_TMUSLOD:
204 add_write_dep(state, &state->last_tmu_config, n);
205 break;
206 default:
207 break;
208 }
209 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
210 /* Handled by v3d_qpu_writes_r4() check. */
211 } else {
212 switch (waddr) {
213 case V3D_QPU_WADDR_R0:
214 case V3D_QPU_WADDR_R1:
215 case V3D_QPU_WADDR_R2:
216 add_write_dep(state,
217 &state->last_r[waddr - V3D_QPU_WADDR_R0],
218 n);
219 break;
220 case V3D_QPU_WADDR_R3:
221 case V3D_QPU_WADDR_R4:
222 case V3D_QPU_WADDR_R5:
223 /* Handled by v3d_qpu_writes_r*() checks below. */
224 break;
225
226 case V3D_QPU_WADDR_VPM:
227 case V3D_QPU_WADDR_VPMU:
228 add_write_dep(state, &state->last_vpm, n);
229 break;
230
231 case V3D_QPU_WADDR_TLB:
232 case V3D_QPU_WADDR_TLBU:
233 add_write_dep(state, &state->last_tlb, n);
234 break;
235
236 case V3D_QPU_WADDR_NOP:
237 break;
238
239 default:
240 fprintf(stderr, "Unknown waddr %d\n", waddr);
241 abort();
242 }
243 }
244 }
245
246 static void
247 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
248 enum v3d_qpu_cond cond)
249 {
250 if (cond != V3D_QPU_COND_NONE)
251 add_read_dep(state, state->last_sf, n);
252 }
253
254 static void
255 process_pf_deps(struct schedule_state *state, struct schedule_node *n,
256 enum v3d_qpu_pf pf)
257 {
258 if (pf != V3D_QPU_PF_NONE)
259 add_write_dep(state, &state->last_sf, n);
260 }
261
262 static void
263 process_uf_deps(struct schedule_state *state, struct schedule_node *n,
264 enum v3d_qpu_uf uf)
265 {
266 if (uf != V3D_QPU_UF_NONE)
267 add_write_dep(state, &state->last_sf, n);
268 }
269
270 /**
271 * Common code for dependencies that need to be tracked both forward and
272 * backward.
273 *
274 * This is for things like "all reads of r4 have to happen between the r4
275 * writes that surround them".
276 */
277 static void
278 calculate_deps(struct schedule_state *state, struct schedule_node *n)
279 {
280 const struct v3d_device_info *devinfo = state->devinfo;
281 struct qinst *qinst = n->inst;
282 struct v3d_qpu_instr *inst = &qinst->qpu;
283
284 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
285 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
286 add_read_dep(state, state->last_sf, n);
287
288 /* XXX: BDI */
289 /* XXX: BDU */
290 /* XXX: ub */
291 /* XXX: raddr_a */
292
293 add_write_dep(state, &state->last_unif, n);
294 return;
295 }
296
297 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
298
299 /* XXX: LOAD_IMM */
300
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
302 process_mux_deps(state, n, inst->alu.add.a);
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
304 process_mux_deps(state, n, inst->alu.add.b);
305
306 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
307 process_mux_deps(state, n, inst->alu.mul.a);
308 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
309 process_mux_deps(state, n, inst->alu.mul.b);
310
311 switch (inst->alu.add.op) {
312 case V3D_QPU_A_VPMSETUP:
313 /* Could distinguish read/write by unpacking the uniform. */
314 add_write_dep(state, &state->last_vpm, n);
315 add_write_dep(state, &state->last_vpm_read, n);
316 break;
317
318 case V3D_QPU_A_STVPMV:
319 case V3D_QPU_A_STVPMD:
320 case V3D_QPU_A_STVPMP:
321 add_write_dep(state, &state->last_vpm, n);
322 break;
323
324 case V3D_QPU_A_VPMWT:
325 add_read_dep(state, state->last_vpm, n);
326 break;
327
328 case V3D_QPU_A_MSF:
329 add_read_dep(state, state->last_tlb, n);
330 break;
331
332 case V3D_QPU_A_SETMSF:
333 case V3D_QPU_A_SETREVF:
334 add_write_dep(state, &state->last_tlb, n);
335 break;
336
337 case V3D_QPU_A_FLAPUSH:
338 case V3D_QPU_A_FLBPUSH:
339 case V3D_QPU_A_VFLA:
340 case V3D_QPU_A_VFLNA:
341 case V3D_QPU_A_VFLB:
342 case V3D_QPU_A_VFLNB:
343 add_read_dep(state, state->last_sf, n);
344 break;
345
346 case V3D_QPU_A_FLBPOP:
347 add_write_dep(state, &state->last_sf, n);
348 break;
349
350 default:
351 break;
352 }
353
354 switch (inst->alu.mul.op) {
355 case V3D_QPU_M_MULTOP:
356 case V3D_QPU_M_UMUL24:
357 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
358 * resets it to 0. We could possibly reorder umul24s relative
359 * to each other, but for now just keep all the MUL parts in
360 * order.
361 */
362 add_write_dep(state, &state->last_rtop, n);
363 break;
364 default:
365 break;
366 }
367
368 if (inst->alu.add.op != V3D_QPU_A_NOP) {
369 process_waddr_deps(state, n, inst->alu.add.waddr,
370 inst->alu.add.magic_write);
371 }
372 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
374 inst->alu.mul.magic_write);
375 }
376 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
377 process_waddr_deps(state, n, inst->sig_addr,
378 inst->sig_magic);
379 }
380
381 if (v3d_qpu_writes_r3(devinfo, inst))
382 add_write_dep(state, &state->last_r[3], n);
383 if (v3d_qpu_writes_r4(devinfo, inst))
384 add_write_dep(state, &state->last_r[4], n);
385 if (v3d_qpu_writes_r5(devinfo, inst))
386 add_write_dep(state, &state->last_r[5], n);
387
388 if (inst->sig.thrsw) {
389 /* All accumulator contents and flags are undefined after the
390 * switch.
391 */
392 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
393 add_write_dep(state, &state->last_r[i], n);
394 add_write_dep(state, &state->last_sf, n);
395
396 /* Scoreboard-locking operations have to stay after the last
397 * thread switch.
398 */
399 add_write_dep(state, &state->last_tlb, n);
400
401 add_write_dep(state, &state->last_tmu_write, n);
402 add_write_dep(state, &state->last_tmu_config, n);
403 }
404
405 if (inst->sig.ldtmu) {
406 /* TMU loads are coming from a FIFO, so ordering is important.
407 */
408 add_write_dep(state, &state->last_tmu_write, n);
409 }
410
411 if (inst->sig.wrtmuc)
412 add_write_dep(state, &state->last_tmu_config, n);
413
414 if (inst->sig.ldtlb | inst->sig.ldtlbu)
415 add_read_dep(state, state->last_tlb, n);
416
417 if (inst->sig.ldvpm)
418 add_write_dep(state, &state->last_vpm_read, n);
419
420 /* inst->sig.ldunif or sideband uniform read */
421 if (qinst->uniform != ~0)
422 add_write_dep(state, &state->last_unif, n);
423
424 process_cond_deps(state, n, inst->flags.ac);
425 process_cond_deps(state, n, inst->flags.mc);
426 process_pf_deps(state, n, inst->flags.apf);
427 process_pf_deps(state, n, inst->flags.mpf);
428 process_uf_deps(state, n, inst->flags.auf);
429 process_uf_deps(state, n, inst->flags.muf);
430 }
431
432 static void
433 calculate_forward_deps(struct v3d_compile *c, struct list_head *schedule_list)
434 {
435 struct schedule_state state;
436
437 memset(&state, 0, sizeof(state));
438 state.devinfo = c->devinfo;
439 state.dir = F;
440
441 list_for_each_entry(struct schedule_node, node, schedule_list, link)
442 calculate_deps(&state, node);
443 }
444
445 static void
446 calculate_reverse_deps(struct v3d_compile *c, struct list_head *schedule_list)
447 {
448 struct list_head *node;
449 struct schedule_state state;
450
451 memset(&state, 0, sizeof(state));
452 state.devinfo = c->devinfo;
453 state.dir = R;
454
455 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
456 calculate_deps(&state, (struct schedule_node *)node);
457 }
458 }
459
460 struct choose_scoreboard {
461 int tick;
462 int last_sfu_write_tick;
463 int last_ldvary_tick;
464 int last_uniforms_reset_tick;
465 bool tlb_locked;
466 };
467
468 static bool
469 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
470 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
471 {
472 switch (mux) {
473 case V3D_QPU_MUX_R4:
474 if (scoreboard->tick - scoreboard->last_sfu_write_tick <= 2)
475 return true;
476 break;
477
478 case V3D_QPU_MUX_R5:
479 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
480 return true;
481 break;
482 default:
483 break;
484 }
485
486 return false;
487 }
488
489 static bool
490 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
491 struct qinst *qinst)
492 {
493 const struct v3d_qpu_instr *inst = &qinst->qpu;
494
495 /* XXX: Branching off of raddr. */
496 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
497 return false;
498
499 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
500
501 if (inst->alu.add.op != V3D_QPU_A_NOP) {
502 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
503 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
504 return true;
505 }
506 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
507 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
508 return true;
509 }
510 }
511
512 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
513 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
514 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
515 return true;
516 }
517 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
518 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
519 return true;
520 }
521 }
522
523 /* XXX: imm */
524
525 return false;
526 }
527
528 static bool
529 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
530 struct choose_scoreboard *scoreboard,
531 struct qinst *qinst)
532 {
533 const struct v3d_qpu_instr *inst = &qinst->qpu;
534
535 /* Don't schedule any other r4 write too soon after an SFU write.
536 * This would normally be prevented by dependency tracking, but might
537 * occur if a dead SFU computation makes it to scheduling.
538 */
539 if (scoreboard->tick - scoreboard->last_sfu_write_tick < 2 &&
540 v3d_qpu_writes_r4(devinfo, inst))
541 return true;
542
543 return false;
544 }
545
546 static bool
547 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
548 const struct v3d_qpu_instr *inst)
549 {
550 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
551 }
552
553 static int
554 get_instruction_priority(const struct v3d_qpu_instr *inst)
555 {
556 uint32_t baseline_score;
557 uint32_t next_score = 0;
558
559 /* Schedule TLB operations as late as possible, to get more
560 * parallelism between shaders.
561 */
562 if (qpu_inst_is_tlb(inst))
563 return next_score;
564 next_score++;
565
566 /* Schedule texture read results collection late to hide latency. */
567 if (inst->sig.ldtmu)
568 return next_score;
569 next_score++;
570
571 /* Default score for things that aren't otherwise special. */
572 baseline_score = next_score;
573 next_score++;
574
575 /* Schedule texture read setup early to hide their latency better. */
576 if (v3d_qpu_writes_tmu(inst))
577 return next_score;
578 next_score++;
579
580 return baseline_score;
581 }
582
583 static bool
584 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
585 {
586 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
587 v3d_qpu_magic_waddr_is_sfu(waddr) ||
588 v3d_qpu_magic_waddr_is_tlb(waddr) ||
589 v3d_qpu_magic_waddr_is_vpm(waddr) ||
590 v3d_qpu_magic_waddr_is_tsy(waddr));
591 }
592
593 static bool
594 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
595 {
596 if (v3d_qpu_uses_vpm(inst))
597 return true;
598
599 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
600 if (inst->alu.add.op != V3D_QPU_A_NOP &&
601 inst->alu.add.magic_write &&
602 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
603 return true;
604 }
605
606 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
607 inst->alu.mul.magic_write &&
608 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
609 return true;
610 }
611 }
612
613 return (inst->sig.ldvpm ||
614 inst->sig.ldtmu ||
615 inst->sig.ldtlb ||
616 inst->sig.ldtlbu ||
617 inst->sig.wrtmuc);
618 }
619
620 static bool
621 qpu_merge_inst(const struct v3d_device_info *devinfo,
622 struct v3d_qpu_instr *result,
623 const struct v3d_qpu_instr *a,
624 const struct v3d_qpu_instr *b)
625 {
626 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
627 b->type != V3D_QPU_INSTR_TYPE_ALU) {
628 return false;
629 }
630
631 /* Can't do more than one peripheral access in an instruction.
632 *
633 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
634 * WRTMUC with a TMU magic register write (other than tmuc).
635 */
636 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
637 return false;
638
639 struct v3d_qpu_instr merge = *a;
640
641 if (b->alu.add.op != V3D_QPU_A_NOP) {
642 if (a->alu.add.op != V3D_QPU_A_NOP)
643 return false;
644 merge.alu.add = b->alu.add;
645
646 merge.flags.ac = b->flags.ac;
647 merge.flags.apf = b->flags.apf;
648 merge.flags.auf = b->flags.auf;
649 }
650
651 if (b->alu.mul.op != V3D_QPU_M_NOP) {
652 if (a->alu.mul.op != V3D_QPU_M_NOP)
653 return false;
654 merge.alu.mul = b->alu.mul;
655
656 merge.flags.mc = b->flags.mc;
657 merge.flags.mpf = b->flags.mpf;
658 merge.flags.muf = b->flags.muf;
659 }
660
661 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
662 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
663 a->raddr_a != b->raddr_a) {
664 return false;
665 }
666 merge.raddr_a = b->raddr_a;
667 }
668
669 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
670 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
671 a->raddr_b != b->raddr_b) {
672 return false;
673 }
674 merge.raddr_b = b->raddr_b;
675 }
676
677 merge.sig.thrsw |= b->sig.thrsw;
678 merge.sig.ldunif |= b->sig.ldunif;
679 merge.sig.ldunifrf |= b->sig.ldunifrf;
680 merge.sig.ldunifa |= b->sig.ldunifa;
681 merge.sig.ldunifarf |= b->sig.ldunifarf;
682 merge.sig.ldtmu |= b->sig.ldtmu;
683 merge.sig.ldvary |= b->sig.ldvary;
684 merge.sig.ldvpm |= b->sig.ldvpm;
685 merge.sig.small_imm |= b->sig.small_imm;
686 merge.sig.ldtlb |= b->sig.ldtlb;
687 merge.sig.ldtlbu |= b->sig.ldtlbu;
688 merge.sig.ucb |= b->sig.ucb;
689 merge.sig.rotate |= b->sig.rotate;
690 merge.sig.wrtmuc |= b->sig.wrtmuc;
691
692 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
693 v3d_qpu_sig_writes_address(devinfo, &b->sig))
694 return false;
695 merge.sig_addr |= b->sig_addr;
696 merge.sig_magic |= b->sig_magic;
697
698 uint64_t packed;
699 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
700
701 *result = merge;
702 /* No modifying the real instructions on failure. */
703 assert(ok || (a != result && b != result));
704
705 return ok;
706 }
707
708 static struct schedule_node *
709 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
710 struct choose_scoreboard *scoreboard,
711 struct list_head *schedule_list,
712 struct schedule_node *prev_inst)
713 {
714 struct schedule_node *chosen = NULL;
715 int chosen_prio = 0;
716
717 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
718 * will handle pairing it along with filling the delay slots.
719 */
720 if (prev_inst) {
721 if (prev_inst->inst->qpu.sig.thrsw)
722 return NULL;
723 }
724
725 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
726 const struct v3d_qpu_instr *inst = &n->inst->qpu;
727
728 /* Don't choose the branch instruction until it's the last one
729 * left. We'll move it up to fit its delay slots after we
730 * choose it.
731 */
732 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
733 !list_is_singular(schedule_list)) {
734 continue;
735 }
736
737 /* "An instruction must not read from a location in physical
738 * regfile A or B that was written to by the previous
739 * instruction."
740 */
741 if (reads_too_soon_after_write(scoreboard, n->inst))
742 continue;
743
744 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
745 continue;
746
747 /* "A scoreboard wait must not occur in the first two
748 * instructions of a fragment shader. This is either the
749 * explicit Wait for Scoreboard signal or an implicit wait
750 * with the first tile-buffer read or write instruction."
751 */
752 if (pixel_scoreboard_too_soon(scoreboard, inst))
753 continue;
754
755 /* ldunif and ldvary both write r5, but ldunif does so a tick
756 * sooner. If the ldvary's r5 wasn't used, then ldunif might
757 * otherwise get scheduled so ldunif and ldvary try to update
758 * r5 in the same tick.
759 */
760 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
761 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
762 continue;
763 }
764
765 /* If we're trying to pair with another instruction, check
766 * that they're compatible.
767 */
768 if (prev_inst) {
769 /* Don't pair up a thread switch signal -- we'll
770 * handle pairing it when we pick it on its own.
771 */
772 if (inst->sig.thrsw)
773 continue;
774
775 if (prev_inst->inst->uniform != -1 &&
776 n->inst->uniform != -1)
777 continue;
778
779 /* Don't merge in something that will lock the TLB.
780 * Hopwefully what we have in inst will release some
781 * other instructions, allowing us to delay the
782 * TLB-locking instruction until later.
783 */
784 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
785 continue;
786
787 struct v3d_qpu_instr merged_inst;
788 if (!qpu_merge_inst(devinfo, &merged_inst,
789 &prev_inst->inst->qpu, inst)) {
790 continue;
791 }
792 }
793
794 int prio = get_instruction_priority(inst);
795
796 /* Found a valid instruction. If nothing better comes along,
797 * this one works.
798 */
799 if (!chosen) {
800 chosen = n;
801 chosen_prio = prio;
802 continue;
803 }
804
805 if (prio > chosen_prio) {
806 chosen = n;
807 chosen_prio = prio;
808 } else if (prio < chosen_prio) {
809 continue;
810 }
811
812 if (n->delay > chosen->delay) {
813 chosen = n;
814 chosen_prio = prio;
815 } else if (n->delay < chosen->delay) {
816 continue;
817 }
818 }
819
820 return chosen;
821 }
822
823 static void
824 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
825 enum v3d_qpu_waddr waddr)
826 {
827 if (v3d_qpu_magic_waddr_is_sfu(waddr))
828 scoreboard->last_sfu_write_tick = scoreboard->tick;
829 }
830
831 static void
832 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
833 const struct v3d_qpu_instr *inst)
834 {
835 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
836 return;
837
838 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
839
840 if (inst->alu.add.op != V3D_QPU_A_NOP) {
841 if (inst->alu.add.magic_write) {
842 update_scoreboard_for_magic_waddr(scoreboard,
843 inst->alu.add.waddr);
844 }
845 }
846
847 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
848 if (inst->alu.mul.magic_write) {
849 update_scoreboard_for_magic_waddr(scoreboard,
850 inst->alu.mul.waddr);
851 }
852 }
853
854 if (inst->sig.ldvary)
855 scoreboard->last_ldvary_tick = scoreboard->tick;
856
857 if (qpu_inst_is_tlb(inst))
858 scoreboard->tlb_locked = true;
859 }
860
861 static void
862 dump_state(const struct v3d_device_info *devinfo,
863 struct list_head *schedule_list)
864 {
865 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
866 fprintf(stderr, " t=%4d: ", n->unblocked_time);
867 v3d_qpu_dump(devinfo, &n->inst->qpu);
868 fprintf(stderr, "\n");
869
870 for (int i = 0; i < n->child_count; i++) {
871 struct schedule_node *child = n->children[i].node;
872 if (!child)
873 continue;
874
875 fprintf(stderr, " - ");
876 v3d_qpu_dump(devinfo, &child->inst->qpu);
877 fprintf(stderr, " (%d parents, %c)\n",
878 child->parent_count,
879 n->children[i].write_after_read ? 'w' : 'r');
880 }
881 }
882 }
883
884 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
885 const struct v3d_qpu_instr *after)
886 {
887 /* Apply some huge latency between texture fetch requests and getting
888 * their results back.
889 *
890 * FIXME: This is actually pretty bogus. If we do:
891 *
892 * mov tmu0_s, a
893 * <a bit of math>
894 * mov tmu0_s, b
895 * load_tmu0
896 * <more math>
897 * load_tmu0
898 *
899 * we count that as worse than
900 *
901 * mov tmu0_s, a
902 * mov tmu0_s, b
903 * <lots of math>
904 * load_tmu0
905 * <more math>
906 * load_tmu0
907 *
908 * because we associate the first load_tmu0 with the *second* tmu0_s.
909 */
910 if (v3d_qpu_magic_waddr_is_tmu(waddr) && after->sig.ldtmu)
911 return 100;
912
913 /* Assume that anything depending on us is consuming the SFU result. */
914 if (v3d_qpu_magic_waddr_is_sfu(waddr))
915 return 3;
916
917 return 1;
918 }
919
920 static uint32_t
921 instruction_latency(struct schedule_node *before, struct schedule_node *after)
922 {
923 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
924 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
925 uint32_t latency = 1;
926
927 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
928 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
929 return latency;
930
931 if (before_inst->alu.add.magic_write) {
932 latency = MAX2(latency,
933 magic_waddr_latency(before_inst->alu.add.waddr,
934 after_inst));
935 }
936
937 if (before_inst->alu.mul.magic_write) {
938 latency = MAX2(latency,
939 magic_waddr_latency(before_inst->alu.mul.waddr,
940 after_inst));
941 }
942
943 return latency;
944 }
945
946 /** Recursive computation of the delay member of a node. */
947 static void
948 compute_delay(struct schedule_node *n)
949 {
950 if (!n->child_count) {
951 n->delay = 1;
952 } else {
953 for (int i = 0; i < n->child_count; i++) {
954 if (!n->children[i].node->delay)
955 compute_delay(n->children[i].node);
956 n->delay = MAX2(n->delay,
957 n->children[i].node->delay +
958 instruction_latency(n, n->children[i].node));
959 }
960 }
961 }
962
963 static void
964 mark_instruction_scheduled(struct list_head *schedule_list,
965 uint32_t time,
966 struct schedule_node *node,
967 bool war_only)
968 {
969 if (!node)
970 return;
971
972 for (int i = node->child_count - 1; i >= 0; i--) {
973 struct schedule_node *child =
974 node->children[i].node;
975
976 if (!child)
977 continue;
978
979 if (war_only && !node->children[i].write_after_read)
980 continue;
981
982 /* If the requirement is only that the node not appear before
983 * the last read of its destination, then it can be scheduled
984 * immediately after (or paired with!) the thing reading the
985 * destination.
986 */
987 uint32_t latency = 0;
988 if (!war_only) {
989 latency = instruction_latency(node,
990 node->children[i].node);
991 }
992
993 child->unblocked_time = MAX2(child->unblocked_time,
994 time + latency);
995 child->parent_count--;
996 if (child->parent_count == 0)
997 list_add(&child->link, schedule_list);
998
999 node->children[i].node = NULL;
1000 }
1001 }
1002
1003 static void
1004 insert_scheduled_instruction(struct v3d_compile *c,
1005 struct qblock *block,
1006 struct choose_scoreboard *scoreboard,
1007 struct qinst *inst)
1008 {
1009 list_addtail(&inst->link, &block->instructions);
1010
1011 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1012 c->qpu_inst_count++;
1013 scoreboard->tick++;
1014 }
1015
1016 static struct qinst *
1017 vir_nop()
1018 {
1019 struct qreg undef = { QFILE_NULL, 0 };
1020 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1021
1022 return qinst;
1023 }
1024
1025 static void
1026 emit_nop(struct v3d_compile *c, struct qblock *block,
1027 struct choose_scoreboard *scoreboard)
1028 {
1029 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1030 }
1031
1032 static bool
1033 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1034 const struct qinst *qinst, int slot)
1035 {
1036 const struct v3d_qpu_instr *inst = &qinst->qpu;
1037
1038 /* Only TLB Z writes are prohibited in the last slot, but we don't
1039 * have those flagged so prohibit all TLB ops for now.
1040 */
1041 if (slot == 2 && qpu_inst_is_tlb(inst))
1042 return false;
1043
1044 if (slot > 0 && qinst->uniform != ~0)
1045 return false;
1046
1047 if (v3d_qpu_uses_vpm(inst))
1048 return false;
1049
1050 if (inst->sig.ldvary)
1051 return false;
1052
1053 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1054 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1055 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
1056 return false;
1057
1058 /* No writing physical registers at the end. */
1059 if (!inst->alu.add.magic_write ||
1060 !inst->alu.mul.magic_write) {
1061 return false;
1062 }
1063
1064 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1065 return false;
1066
1067 /* RF0-2 might be overwritten during the delay slots by
1068 * fragment shader setup.
1069 */
1070 if (inst->raddr_a < 3 &&
1071 (inst->alu.add.a == V3D_QPU_MUX_A ||
1072 inst->alu.add.b == V3D_QPU_MUX_A ||
1073 inst->alu.mul.a == V3D_QPU_MUX_A ||
1074 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1075 return false;
1076 }
1077
1078 if (inst->raddr_b < 3 &&
1079 !inst->sig.small_imm &&
1080 (inst->alu.add.a == V3D_QPU_MUX_B ||
1081 inst->alu.add.b == V3D_QPU_MUX_B ||
1082 inst->alu.mul.a == V3D_QPU_MUX_B ||
1083 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1084 return false;
1085 }
1086 }
1087
1088 return true;
1089 }
1090
1091 static bool
1092 valid_thrsw_sequence(struct v3d_compile *c,
1093 struct qinst *qinst, int instructions_in_sequence,
1094 bool is_thrend)
1095 {
1096 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1097 /* No scheduling SFU when the result would land in the other
1098 * thread. The simulator complains for safety, though it
1099 * would only occur for dead code in our case.
1100 */
1101 if (slot > 0 &&
1102 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1103 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1104 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1105 return false;
1106 }
1107
1108 if (slot > 0 && qinst->qpu.sig.ldvary)
1109 return false;
1110
1111 if (is_thrend &&
1112 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1113 return false;
1114 }
1115
1116 /* Note that the list is circular, so we can only do this up
1117 * to instructions_in_sequence.
1118 */
1119 qinst = (struct qinst *)qinst->link.next;
1120 }
1121
1122 return true;
1123 }
1124
1125 /**
1126 * Emits a THRSW signal in the stream, trying to move it up to pair with
1127 * another instruction.
1128 */
1129 static int
1130 emit_thrsw(struct v3d_compile *c,
1131 struct qblock *block,
1132 struct choose_scoreboard *scoreboard,
1133 struct qinst *inst,
1134 bool is_thrend)
1135 {
1136 int time = 0;
1137
1138 /* There should be nothing in a thrsw inst being scheduled other than
1139 * the signal bits.
1140 */
1141 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1142 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1143 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1144
1145 /* Find how far back into previous instructions we can put the THRSW. */
1146 int slots_filled = 0;
1147 struct qinst *merge_inst = NULL;
1148 vir_for_each_inst_rev(prev_inst, block) {
1149 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1150 sig.thrsw = true;
1151 uint32_t packed_sig;
1152
1153 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1154 break;
1155
1156 if (!valid_thrsw_sequence(c, prev_inst, slots_filled + 1,
1157 is_thrend)) {
1158 break;
1159 }
1160
1161 merge_inst = prev_inst;
1162 if (++slots_filled == 3)
1163 break;
1164 }
1165
1166 bool needs_free = false;
1167 if (merge_inst) {
1168 merge_inst->qpu.sig.thrsw = true;
1169 needs_free = true;
1170 } else {
1171 insert_scheduled_instruction(c, block, scoreboard, inst);
1172 time++;
1173 slots_filled++;
1174 merge_inst = inst;
1175 }
1176
1177 /* Insert any extra delay slot NOPs we need. */
1178 for (int i = 0; i < 3 - slots_filled; i++) {
1179 emit_nop(c, block, scoreboard);
1180 time++;
1181 }
1182
1183 /* If we're emitting the last THRSW (other than program end), then
1184 * signal that to the HW by emitting two THRSWs in a row.
1185 */
1186 if (inst->is_last_thrsw) {
1187 struct qinst *second_inst =
1188 (struct qinst *)merge_inst->link.next;
1189 second_inst->qpu.sig.thrsw = true;
1190 }
1191
1192 /* If we put our THRSW into another instruction, free up the
1193 * instruction that didn't end up scheduled into the list.
1194 */
1195 if (needs_free)
1196 free(inst);
1197
1198 return time;
1199 }
1200
1201 static uint32_t
1202 schedule_instructions(struct v3d_compile *c,
1203 struct choose_scoreboard *scoreboard,
1204 struct qblock *block,
1205 struct list_head *schedule_list,
1206 enum quniform_contents *orig_uniform_contents,
1207 uint32_t *orig_uniform_data,
1208 uint32_t *next_uniform)
1209 {
1210 const struct v3d_device_info *devinfo = c->devinfo;
1211 uint32_t time = 0;
1212
1213 if (debug) {
1214 fprintf(stderr, "initial deps:\n");
1215 dump_state(devinfo, schedule_list);
1216 fprintf(stderr, "\n");
1217 }
1218
1219 /* Remove non-DAG heads from the list. */
1220 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
1221 if (n->parent_count != 0)
1222 list_del(&n->link);
1223 }
1224
1225 while (!list_empty(schedule_list)) {
1226 struct schedule_node *chosen =
1227 choose_instruction_to_schedule(devinfo,
1228 scoreboard,
1229 schedule_list,
1230 NULL);
1231 struct schedule_node *merge = NULL;
1232
1233 /* If there are no valid instructions to schedule, drop a NOP
1234 * in.
1235 */
1236 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1237 struct v3d_qpu_instr *inst = &qinst->qpu;
1238
1239 if (debug) {
1240 fprintf(stderr, "t=%4d: current list:\n",
1241 time);
1242 dump_state(devinfo, schedule_list);
1243 fprintf(stderr, "t=%4d: chose: ", time);
1244 v3d_qpu_dump(devinfo, inst);
1245 fprintf(stderr, "\n");
1246 }
1247
1248 /* We can't mark_instruction_scheduled() the chosen inst until
1249 * we're done identifying instructions to merge, so put the
1250 * merged instructions on a list for a moment.
1251 */
1252 struct list_head merged_list;
1253 list_inithead(&merged_list);
1254
1255 /* Schedule this instruction onto the QPU list. Also try to
1256 * find an instruction to pair with it.
1257 */
1258 if (chosen) {
1259 time = MAX2(chosen->unblocked_time, time);
1260 list_del(&chosen->link);
1261 mark_instruction_scheduled(schedule_list, time,
1262 chosen, true);
1263
1264 while ((merge =
1265 choose_instruction_to_schedule(devinfo,
1266 scoreboard,
1267 schedule_list,
1268 chosen))) {
1269 time = MAX2(merge->unblocked_time, time);
1270 list_del(&merge->link);
1271 list_addtail(&merge->link, &merged_list);
1272 (void)qpu_merge_inst(devinfo, inst,
1273 inst, &merge->inst->qpu);
1274 if (merge->inst->uniform != -1) {
1275 chosen->inst->uniform =
1276 merge->inst->uniform;
1277 }
1278
1279 if (debug) {
1280 fprintf(stderr, "t=%4d: merging: ",
1281 time);
1282 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1283 fprintf(stderr, "\n");
1284 fprintf(stderr, " result: ");
1285 v3d_qpu_dump(devinfo, inst);
1286 fprintf(stderr, "\n");
1287 }
1288 }
1289 }
1290
1291 /* Update the uniform index for the rewritten location --
1292 * branch target updating will still need to change
1293 * c->uniform_data[] using this index.
1294 */
1295 if (qinst->uniform != -1) {
1296 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1297 block->branch_uniform = *next_uniform;
1298
1299 c->uniform_data[*next_uniform] =
1300 orig_uniform_data[qinst->uniform];
1301 c->uniform_contents[*next_uniform] =
1302 orig_uniform_contents[qinst->uniform];
1303 qinst->uniform = *next_uniform;
1304 (*next_uniform)++;
1305 }
1306
1307 if (debug) {
1308 fprintf(stderr, "\n");
1309 }
1310
1311 /* Now that we've scheduled a new instruction, some of its
1312 * children can be promoted to the list of instructions ready to
1313 * be scheduled. Update the children's unblocked time for this
1314 * DAG edge as we do so.
1315 */
1316 mark_instruction_scheduled(schedule_list, time, chosen, false);
1317 list_for_each_entry(struct schedule_node, merge, &merged_list,
1318 link) {
1319 mark_instruction_scheduled(schedule_list, time, merge,
1320 false);
1321
1322 /* The merged VIR instruction doesn't get re-added to the
1323 * block, so free it now.
1324 */
1325 free(merge->inst);
1326 }
1327
1328 if (inst->sig.thrsw) {
1329 time += emit_thrsw(c, block, scoreboard, qinst, false);
1330 } else {
1331 insert_scheduled_instruction(c, block,
1332 scoreboard, qinst);
1333
1334 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1335 block->branch_qpu_ip = c->qpu_inst_count - 1;
1336 /* Fill the delay slots.
1337 *
1338 * We should fill these with actual instructions,
1339 * instead, but that will probably need to be done
1340 * after this, once we know what the leading
1341 * instructions of the successors are (so we can
1342 * handle A/B register file write latency)
1343 */
1344 for (int i = 0; i < 3; i++)
1345 emit_nop(c, block, scoreboard);
1346 }
1347 }
1348 }
1349
1350 return time;
1351 }
1352
1353 static uint32_t
1354 qpu_schedule_instructions_block(struct v3d_compile *c,
1355 struct choose_scoreboard *scoreboard,
1356 struct qblock *block,
1357 enum quniform_contents *orig_uniform_contents,
1358 uint32_t *orig_uniform_data,
1359 uint32_t *next_uniform)
1360 {
1361 void *mem_ctx = ralloc_context(NULL);
1362 struct list_head schedule_list;
1363
1364 list_inithead(&schedule_list);
1365
1366 /* Wrap each instruction in a scheduler structure. */
1367 while (!list_empty(&block->instructions)) {
1368 struct qinst *qinst = (struct qinst *)block->instructions.next;
1369 struct schedule_node *n =
1370 rzalloc(mem_ctx, struct schedule_node);
1371
1372 n->inst = qinst;
1373
1374 list_del(&qinst->link);
1375 list_addtail(&n->link, &schedule_list);
1376 }
1377
1378 calculate_forward_deps(c, &schedule_list);
1379 calculate_reverse_deps(c, &schedule_list);
1380
1381 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
1382 compute_delay(n);
1383 }
1384
1385 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1386 &schedule_list,
1387 orig_uniform_contents,
1388 orig_uniform_data,
1389 next_uniform);
1390
1391 ralloc_free(mem_ctx);
1392
1393 return cycles;
1394 }
1395
1396 static void
1397 qpu_set_branch_targets(struct v3d_compile *c)
1398 {
1399 vir_for_each_block(block, c) {
1400 /* The end block of the program has no branch. */
1401 if (!block->successors[0])
1402 continue;
1403
1404 /* If there was no branch instruction, then the successor
1405 * block must follow immediately after this one.
1406 */
1407 if (block->branch_qpu_ip == ~0) {
1408 assert(block->end_qpu_ip + 1 ==
1409 block->successors[0]->start_qpu_ip);
1410 continue;
1411 }
1412
1413 /* Walk back through the delay slots to find the branch
1414 * instr.
1415 */
1416 struct list_head *entry = block->instructions.prev;
1417 for (int i = 0; i < 3; i++)
1418 entry = entry->prev;
1419 struct qinst *branch = container_of(entry, branch, link);
1420 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1421
1422 /* Make sure that the if-we-don't-jump
1423 * successor was scheduled just after the
1424 * delay slots.
1425 */
1426 assert(!block->successors[1] ||
1427 block->successors[1]->start_qpu_ip ==
1428 block->branch_qpu_ip + 4);
1429
1430 branch->qpu.branch.offset =
1431 ((block->successors[0]->start_qpu_ip -
1432 (block->branch_qpu_ip + 4)) *
1433 sizeof(uint64_t));
1434
1435 /* Set up the relative offset to jump in the
1436 * uniform stream.
1437 *
1438 * Use a temporary here, because
1439 * uniform_data[inst->uniform] may be shared
1440 * between multiple instructions.
1441 */
1442 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1443 c->uniform_data[branch->uniform] =
1444 (block->successors[0]->start_uniform -
1445 (block->branch_uniform + 1)) * 4;
1446 }
1447 }
1448
1449 uint32_t
1450 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1451 {
1452 const struct v3d_device_info *devinfo = c->devinfo;
1453 struct qblock *end_block = list_last_entry(&c->blocks,
1454 struct qblock, link);
1455
1456 /* We reorder the uniforms as we schedule instructions, so save the
1457 * old data off and replace it.
1458 */
1459 uint32_t *uniform_data = c->uniform_data;
1460 enum quniform_contents *uniform_contents = c->uniform_contents;
1461 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1462 c->num_uniforms);
1463 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1464 c->uniform_array_size = c->num_uniforms;
1465 uint32_t next_uniform = 0;
1466
1467 struct choose_scoreboard scoreboard;
1468 memset(&scoreboard, 0, sizeof(scoreboard));
1469 scoreboard.last_ldvary_tick = -10;
1470 scoreboard.last_sfu_write_tick = -10;
1471 scoreboard.last_uniforms_reset_tick = -10;
1472
1473 if (debug) {
1474 fprintf(stderr, "Pre-schedule instructions\n");
1475 vir_for_each_block(block, c) {
1476 fprintf(stderr, "BLOCK %d\n", block->index);
1477 list_for_each_entry(struct qinst, qinst,
1478 &block->instructions, link) {
1479 v3d_qpu_dump(devinfo, &qinst->qpu);
1480 fprintf(stderr, "\n");
1481 }
1482 }
1483 fprintf(stderr, "\n");
1484 }
1485
1486 uint32_t cycles = 0;
1487 vir_for_each_block(block, c) {
1488 block->start_qpu_ip = c->qpu_inst_count;
1489 block->branch_qpu_ip = ~0;
1490 block->start_uniform = next_uniform;
1491
1492 cycles += qpu_schedule_instructions_block(c,
1493 &scoreboard,
1494 block,
1495 uniform_contents,
1496 uniform_data,
1497 &next_uniform);
1498
1499 block->end_qpu_ip = c->qpu_inst_count - 1;
1500 }
1501
1502 /* Emit the program-end THRSW instruction. */;
1503 struct qinst *thrsw = vir_nop();
1504 thrsw->qpu.sig.thrsw = true;
1505 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1506
1507 qpu_set_branch_targets(c);
1508
1509 assert(next_uniform == c->num_uniforms);
1510
1511 return cycles;
1512 }