projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
broadcom/vc5: Extract v3d_qpu_writes_tmu() helper.
[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct qinst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68 };
69
70 struct schedule_node_child {
71 struct schedule_node *node;
72 bool write_after_read;
73 };
74
75 /* When walking the instructions in reverse, we need to swap before/after in
76 * add_dep().
77 */
78 enum direction { F, R };
79
80 struct schedule_state {
81 const struct v3d_device_info *devinfo;
82 struct schedule_node *last_r[6];
83 struct schedule_node *last_rf[64];
84 struct schedule_node *last_sf;
85 struct schedule_node *last_vpm_read;
86 struct schedule_node *last_tmu_write;
87 struct schedule_node *last_tmu_config;
88 struct schedule_node *last_tlb;
89 struct schedule_node *last_vpm;
90 struct schedule_node *last_unif;
91 struct schedule_node *last_rtop;
92 enum direction dir;
93 /* Estimated cycle when the current instruction would start. */
94 uint32_t time;
95 };
96
97 static void
98 add_dep(struct schedule_state *state,
99 struct schedule_node *before,
100 struct schedule_node *after,
101 bool write)
102 {
103 bool write_after_read = !write && state->dir == R;
104
105 if (!before || !after)
106 return;
107
108 assert(before != after);
109
110 if (state->dir == R) {
111 struct schedule_node *t = before;
112 before = after;
113 after = t;
114 }
115
116 for (int i = 0; i < before->child_count; i++) {
117 if (before->children[i].node == after &&
118 (before->children[i].write_after_read == write_after_read)) {
119 return;
120 }
121 }
122
123 if (before->child_array_size <= before->child_count) {
124 before->child_array_size = MAX2(before->child_array_size * 2, 16);
125 before->children = reralloc(before, before->children,
126 struct schedule_node_child,
127 before->child_array_size);
128 }
129
130 before->children[before->child_count].node = after;
131 before->children[before->child_count].write_after_read =
132 write_after_read;
133 before->child_count++;
134 after->parent_count++;
135 }
136
137 static void
138 add_read_dep(struct schedule_state *state,
139 struct schedule_node *before,
140 struct schedule_node *after)
141 {
142 add_dep(state, before, after, false);
143 }
144
145 static void
146 add_write_dep(struct schedule_state *state,
147 struct schedule_node **before,
148 struct schedule_node *after)
149 {
150 add_dep(state, *before, after, true);
151 *before = after;
152 }
153
154 static bool
155 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
156 {
157 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
158 return false;
159
160 if (inst->alu.add.magic_write &&
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
163 return true;
164
165 if (inst->alu.mul.magic_write &&
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
168 return true;
169
170 return false;
171 }
172
173 static void
174 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
175 enum v3d_qpu_mux mux)
176 {
177 switch (mux) {
178 case V3D_QPU_MUX_A:
179 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
180 break;
181 case V3D_QPU_MUX_B:
182 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
183 break;
184 default:
185 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
186 break;
187 }
188 }
189
190
191 static void
192 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
193 uint32_t waddr, bool magic)
194 {
195 if (!magic) {
196 add_write_dep(state, &state->last_rf[waddr], n);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
198 add_write_dep(state, &state->last_tmu_write, n);
199 switch (waddr) {
200 case V3D_QPU_WADDR_TMUS:
201 case V3D_QPU_WADDR_TMUSCM:
202 case V3D_QPU_WADDR_TMUSF:
203 case V3D_QPU_WADDR_TMUSLOD:
204 add_write_dep(state, &state->last_tmu_config, n);
205 break;
206 default:
207 break;
208 }
209 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
210 /* Handled by v3d_qpu_writes_r4() check. */
211 } else {
212 switch (waddr) {
213 case V3D_QPU_WADDR_R0:
214 case V3D_QPU_WADDR_R1:
215 case V3D_QPU_WADDR_R2:
216 add_write_dep(state,
217 &state->last_r[waddr - V3D_QPU_WADDR_R0],
218 n);
219 break;
220 case V3D_QPU_WADDR_R3:
221 case V3D_QPU_WADDR_R4:
222 case V3D_QPU_WADDR_R5:
223 /* Handled by v3d_qpu_writes_r*() checks below. */
224 break;
225
226 case V3D_QPU_WADDR_VPM:
227 case V3D_QPU_WADDR_VPMU:
228 add_write_dep(state, &state->last_vpm, n);
229 break;
230
231 case V3D_QPU_WADDR_TLB:
232 case V3D_QPU_WADDR_TLBU:
233 add_write_dep(state, &state->last_tlb, n);
234 break;
235
236 case V3D_QPU_WADDR_NOP:
237 break;
238
239 default:
240 fprintf(stderr, "Unknown waddr %d\n", waddr);
241 abort();
242 }
243 }
244 }
245
246 static void
247 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
248 enum v3d_qpu_cond cond)
249 {
250 if (cond != V3D_QPU_COND_NONE)
251 add_read_dep(state, state->last_sf, n);
252 }
253
254 static void
255 process_pf_deps(struct schedule_state *state, struct schedule_node *n,
256 enum v3d_qpu_pf pf)
257 {
258 if (pf != V3D_QPU_PF_NONE)
259 add_write_dep(state, &state->last_sf, n);
260 }
261
262 static void
263 process_uf_deps(struct schedule_state *state, struct schedule_node *n,
264 enum v3d_qpu_uf uf)
265 {
266 if (uf != V3D_QPU_UF_NONE)
267 add_write_dep(state, &state->last_sf, n);
268 }
269
270 /**
271 * Common code for dependencies that need to be tracked both forward and
272 * backward.
273 *
274 * This is for things like "all reads of r4 have to happen between the r4
275 * writes that surround them".
276 */
277 static void
278 calculate_deps(struct schedule_state *state, struct schedule_node *n)
279 {
280 const struct v3d_device_info *devinfo = state->devinfo;
281 struct qinst *qinst = n->inst;
282 struct v3d_qpu_instr *inst = &qinst->qpu;
283
284 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
285 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
286 add_read_dep(state, state->last_sf, n);
287
288 /* XXX: BDI */
289 /* XXX: BDU */
290 /* XXX: ub */
291 /* XXX: raddr_a */
292
293 add_write_dep(state, &state->last_unif, n);
294 return;
295 }
296
297 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
298
299 /* XXX: LOAD_IMM */
300
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
302 process_mux_deps(state, n, inst->alu.add.a);
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
304 process_mux_deps(state, n, inst->alu.add.b);
305
306 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
307 process_mux_deps(state, n, inst->alu.mul.a);
308 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
309 process_mux_deps(state, n, inst->alu.mul.b);
310
311 switch (inst->alu.add.op) {
312 case V3D_QPU_A_VPMSETUP:
313 /* Could distinguish read/write by unpacking the uniform. */
314 add_write_dep(state, &state->last_vpm, n);
315 add_write_dep(state, &state->last_vpm_read, n);
316 break;
317
318 case V3D_QPU_A_STVPMV:
319 case V3D_QPU_A_STVPMD:
320 case V3D_QPU_A_STVPMP:
321 add_write_dep(state, &state->last_vpm, n);
322 break;
323
324 case V3D_QPU_A_VPMWT:
325 add_read_dep(state, state->last_vpm, n);
326 break;
327
328 case V3D_QPU_A_MSF:
329 add_read_dep(state, state->last_tlb, n);
330 break;
331
332 case V3D_QPU_A_SETMSF:
333 case V3D_QPU_A_SETREVF:
334 add_write_dep(state, &state->last_tlb, n);
335 break;
336
337 case V3D_QPU_A_FLAPUSH:
338 case V3D_QPU_A_FLBPUSH:
339 case V3D_QPU_A_VFLA:
340 case V3D_QPU_A_VFLNA:
341 case V3D_QPU_A_VFLB:
342 case V3D_QPU_A_VFLNB:
343 add_read_dep(state, state->last_sf, n);
344 break;
345
346 case V3D_QPU_A_FLBPOP:
347 add_write_dep(state, &state->last_sf, n);
348 break;
349
350 default:
351 break;
352 }
353
354 switch (inst->alu.mul.op) {
355 case V3D_QPU_M_MULTOP:
356 case V3D_QPU_M_UMUL24:
357 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
358 * resets it to 0. We could possibly reorder umul24s relative
359 * to each other, but for now just keep all the MUL parts in
360 * order.
361 */
362 add_write_dep(state, &state->last_rtop, n);
363 break;
364 default:
365 break;
366 }
367
368 if (inst->alu.add.op != V3D_QPU_A_NOP) {
369 process_waddr_deps(state, n, inst->alu.add.waddr,
370 inst->alu.add.magic_write);
371 }
372 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
374 inst->alu.mul.magic_write);
375 }
376 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
377 process_waddr_deps(state, n, inst->sig_addr,
378 inst->sig_magic);
379 }
380
381 if (v3d_qpu_writes_r3(devinfo, inst))
382 add_write_dep(state, &state->last_r[3], n);
383 if (v3d_qpu_writes_r4(devinfo, inst))
384 add_write_dep(state, &state->last_r[4], n);
385 if (v3d_qpu_writes_r5(devinfo, inst))
386 add_write_dep(state, &state->last_r[5], n);
387
388 if (inst->sig.thrsw) {
389 /* All accumulator contents and flags are undefined after the
390 * switch.
391 */
392 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
393 add_write_dep(state, &state->last_r[i], n);
394 add_write_dep(state, &state->last_sf, n);
395
396 /* Scoreboard-locking operations have to stay after the last
397 * thread switch.
398 */
399 add_write_dep(state, &state->last_tlb, n);
400
401 add_write_dep(state, &state->last_tmu_write, n);
402 add_write_dep(state, &state->last_tmu_config, n);
403 }
404
405 if (inst->sig.ldtmu) {
406 /* TMU loads are coming from a FIFO, so ordering is important.
407 */
408 add_write_dep(state, &state->last_tmu_write, n);
409 }
410
411 if (inst->sig.wrtmuc)
412 add_write_dep(state, &state->last_tmu_config, n);
413
414 if (inst->sig.ldtlb | inst->sig.ldtlbu)
415 add_read_dep(state, state->last_tlb, n);
416
417 if (inst->sig.ldvpm)
418 add_write_dep(state, &state->last_vpm_read, n);
419
420 /* inst->sig.ldunif or sideband uniform read */
421 if (qinst->uniform != ~0)
422 add_write_dep(state, &state->last_unif, n);
423
424 process_cond_deps(state, n, inst->flags.ac);
425 process_cond_deps(state, n, inst->flags.mc);
426 process_pf_deps(state, n, inst->flags.apf);
427 process_pf_deps(state, n, inst->flags.mpf);
428 process_uf_deps(state, n, inst->flags.auf);
429 process_uf_deps(state, n, inst->flags.muf);
430 }
431
432 static void
433 calculate_forward_deps(struct v3d_compile *c, struct list_head *schedule_list)
434 {
435 struct schedule_state state;
436
437 memset(&state, 0, sizeof(state));
438 state.devinfo = c->devinfo;
439 state.dir = F;
440
441 list_for_each_entry(struct schedule_node, node, schedule_list, link)
442 calculate_deps(&state, node);
443 }
444
445 static void
446 calculate_reverse_deps(struct v3d_compile *c, struct list_head *schedule_list)
447 {
448 struct list_head *node;
449 struct schedule_state state;
450
451 memset(&state, 0, sizeof(state));
452 state.devinfo = c->devinfo;
453 state.dir = R;
454
455 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
456 calculate_deps(&state, (struct schedule_node *)node);
457 }
458 }
459
460 struct choose_scoreboard {
461 int tick;
462 int last_sfu_write_tick;
463 int last_ldvary_tick;
464 int last_uniforms_reset_tick;
465 uint32_t last_waddr_add, last_waddr_mul;
466 bool tlb_locked;
467 };
468
469 static bool
470 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
471 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
472 {
473 switch (mux) {
474 case V3D_QPU_MUX_A:
475 if (scoreboard->last_waddr_add == inst->raddr_a ||
476 scoreboard->last_waddr_mul == inst->raddr_a) {
477 return true;
478 }
479 break;
480
481 case V3D_QPU_MUX_B:
482 if (scoreboard->last_waddr_add == inst->raddr_b ||
483 scoreboard->last_waddr_mul == inst->raddr_b) {
484 return true;
485 }
486 break;
487
488 case V3D_QPU_MUX_R4:
489 if (scoreboard->tick - scoreboard->last_sfu_write_tick <= 2)
490 return true;
491 break;
492
493 case V3D_QPU_MUX_R5:
494 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
495 return true;
496 break;
497 default:
498 break;
499 }
500
501 return false;
502 }
503
504 static bool
505 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
506 struct qinst *qinst)
507 {
508 const struct v3d_qpu_instr *inst = &qinst->qpu;
509
510 /* XXX: Branching off of raddr. */
511 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
512 return false;
513
514 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
515
516 if (inst->alu.add.op != V3D_QPU_A_NOP) {
517 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
518 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
519 return true;
520 }
521 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
522 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
523 return true;
524 }
525 }
526
527 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
528 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
529 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
530 return true;
531 }
532 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
533 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
534 return true;
535 }
536 }
537
538 /* XXX: imm */
539
540 return false;
541 }
542
543 static bool
544 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
545 struct choose_scoreboard *scoreboard,
546 struct qinst *qinst)
547 {
548 const struct v3d_qpu_instr *inst = &qinst->qpu;
549
550 /* Don't schedule any other r4 write too soon after an SFU write.
551 * This would normally be prevented by dependency tracking, but might
552 * occur if a dead SFU computation makes it to scheduling.
553 */
554 if (scoreboard->tick - scoreboard->last_sfu_write_tick < 2 &&
555 v3d_qpu_writes_r4(devinfo, inst))
556 return true;
557
558 return false;
559 }
560
561 static bool
562 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
563 const struct v3d_qpu_instr *inst)
564 {
565 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
566 }
567
568 static int
569 get_instruction_priority(const struct v3d_qpu_instr *inst)
570 {
571 uint32_t baseline_score;
572 uint32_t next_score = 0;
573
574 /* Schedule TLB operations as late as possible, to get more
575 * parallelism between shaders.
576 */
577 if (qpu_inst_is_tlb(inst))
578 return next_score;
579 next_score++;
580
581 /* Schedule texture read results collection late to hide latency. */
582 if (inst->sig.ldtmu)
583 return next_score;
584 next_score++;
585
586 /* Default score for things that aren't otherwise special. */
587 baseline_score = next_score;
588 next_score++;
589
590 /* Schedule texture read setup early to hide their latency better. */
591 if (v3d_qpu_writes_tmu(inst))
592 return next_score;
593 next_score++;
594
595 return baseline_score;
596 }
597
598 static bool
599 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
600 {
601 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
602 v3d_qpu_magic_waddr_is_sfu(waddr) ||
603 v3d_qpu_magic_waddr_is_tlb(waddr) ||
604 v3d_qpu_magic_waddr_is_vpm(waddr) ||
605 v3d_qpu_magic_waddr_is_tsy(waddr));
606 }
607
608 static bool
609 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
610 {
611 if (v3d_qpu_uses_vpm(inst))
612 return true;
613
614 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
615 if (inst->alu.add.op != V3D_QPU_A_NOP &&
616 inst->alu.add.magic_write &&
617 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
618 return true;
619 }
620
621 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
622 inst->alu.mul.magic_write &&
623 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
624 return true;
625 }
626 }
627
628 return (inst->sig.ldvpm ||
629 inst->sig.ldtmu ||
630 inst->sig.ldtlb ||
631 inst->sig.ldtlbu ||
632 inst->sig.wrtmuc);
633 }
634
635 static bool
636 qpu_merge_inst(const struct v3d_device_info *devinfo,
637 struct v3d_qpu_instr *result,
638 const struct v3d_qpu_instr *a,
639 const struct v3d_qpu_instr *b)
640 {
641 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
642 b->type != V3D_QPU_INSTR_TYPE_ALU) {
643 return false;
644 }
645
646 /* Can't do more than one peripheral access in an instruction.
647 *
648 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
649 * WRTMUC with a TMU magic register write (other than tmuc).
650 */
651 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
652 return false;
653
654 struct v3d_qpu_instr merge = *a;
655
656 if (b->alu.add.op != V3D_QPU_A_NOP) {
657 if (a->alu.add.op != V3D_QPU_A_NOP)
658 return false;
659 merge.alu.add = b->alu.add;
660
661 merge.flags.ac = b->flags.ac;
662 merge.flags.apf = b->flags.apf;
663 merge.flags.auf = b->flags.auf;
664 }
665
666 if (b->alu.mul.op != V3D_QPU_M_NOP) {
667 if (a->alu.mul.op != V3D_QPU_M_NOP)
668 return false;
669 merge.alu.mul = b->alu.mul;
670
671 merge.flags.mc = b->flags.mc;
672 merge.flags.mpf = b->flags.mpf;
673 merge.flags.muf = b->flags.muf;
674 }
675
676 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
677 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
678 a->raddr_a != b->raddr_a) {
679 return false;
680 }
681 merge.raddr_a = b->raddr_a;
682 }
683
684 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
685 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
686 a->raddr_b != b->raddr_b) {
687 return false;
688 }
689 merge.raddr_b = b->raddr_b;
690 }
691
692 merge.sig.thrsw |= b->sig.thrsw;
693 merge.sig.ldunif |= b->sig.ldunif;
694 merge.sig.ldunifrf |= b->sig.ldunifrf;
695 merge.sig.ldunifa |= b->sig.ldunifa;
696 merge.sig.ldunifarf |= b->sig.ldunifarf;
697 merge.sig.ldtmu |= b->sig.ldtmu;
698 merge.sig.ldvary |= b->sig.ldvary;
699 merge.sig.ldvpm |= b->sig.ldvpm;
700 merge.sig.small_imm |= b->sig.small_imm;
701 merge.sig.ldtlb |= b->sig.ldtlb;
702 merge.sig.ldtlbu |= b->sig.ldtlbu;
703 merge.sig.ucb |= b->sig.ucb;
704 merge.sig.rotate |= b->sig.rotate;
705 merge.sig.wrtmuc |= b->sig.wrtmuc;
706
707 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
708 v3d_qpu_sig_writes_address(devinfo, &b->sig))
709 return false;
710 merge.sig_addr |= b->sig_addr;
711 merge.sig_magic |= b->sig_magic;
712
713 uint64_t packed;
714 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
715
716 *result = merge;
717 /* No modifying the real instructions on failure. */
718 assert(ok || (a != result && b != result));
719
720 return ok;
721 }
722
723 static struct schedule_node *
724 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
725 struct choose_scoreboard *scoreboard,
726 struct list_head *schedule_list,
727 struct schedule_node *prev_inst)
728 {
729 struct schedule_node *chosen = NULL;
730 int chosen_prio = 0;
731
732 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
733 * will handle pairing it along with filling the delay slots.
734 */
735 if (prev_inst) {
736 if (prev_inst->inst->qpu.sig.thrsw)
737 return NULL;
738 }
739
740 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
741 const struct v3d_qpu_instr *inst = &n->inst->qpu;
742
743 /* Don't choose the branch instruction until it's the last one
744 * left. We'll move it up to fit its delay slots after we
745 * choose it.
746 */
747 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
748 !list_is_singular(schedule_list)) {
749 continue;
750 }
751
752 /* "An instruction must not read from a location in physical
753 * regfile A or B that was written to by the previous
754 * instruction."
755 */
756 if (reads_too_soon_after_write(scoreboard, n->inst))
757 continue;
758
759 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
760 continue;
761
762 /* "A scoreboard wait must not occur in the first two
763 * instructions of a fragment shader. This is either the
764 * explicit Wait for Scoreboard signal or an implicit wait
765 * with the first tile-buffer read or write instruction."
766 */
767 if (pixel_scoreboard_too_soon(scoreboard, inst))
768 continue;
769
770 /* ldunif and ldvary both write r5, but ldunif does so a tick
771 * sooner. If the ldvary's r5 wasn't used, then ldunif might
772 * otherwise get scheduled so ldunif and ldvary try to update
773 * r5 in the same tick.
774 */
775 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
776 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
777 continue;
778 }
779
780 /* If we're trying to pair with another instruction, check
781 * that they're compatible.
782 */
783 if (prev_inst) {
784 /* Don't pair up a thread switch signal -- we'll
785 * handle pairing it when we pick it on its own.
786 */
787 if (inst->sig.thrsw)
788 continue;
789
790 if (prev_inst->inst->uniform != -1 &&
791 n->inst->uniform != -1)
792 continue;
793
794 /* Don't merge in something that will lock the TLB.
795 * Hopwefully what we have in inst will release some
796 * other instructions, allowing us to delay the
797 * TLB-locking instruction until later.
798 */
799 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
800 continue;
801
802 struct v3d_qpu_instr merged_inst;
803 if (!qpu_merge_inst(devinfo, &merged_inst,
804 &prev_inst->inst->qpu, inst)) {
805 continue;
806 }
807 }
808
809 int prio = get_instruction_priority(inst);
810
811 /* Found a valid instruction. If nothing better comes along,
812 * this one works.
813 */
814 if (!chosen) {
815 chosen = n;
816 chosen_prio = prio;
817 continue;
818 }
819
820 if (prio > chosen_prio) {
821 chosen = n;
822 chosen_prio = prio;
823 } else if (prio < chosen_prio) {
824 continue;
825 }
826
827 if (n->delay > chosen->delay) {
828 chosen = n;
829 chosen_prio = prio;
830 } else if (n->delay < chosen->delay) {
831 continue;
832 }
833 }
834
835 return chosen;
836 }
837
838 static void
839 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
840 enum v3d_qpu_waddr waddr)
841 {
842 if (v3d_qpu_magic_waddr_is_sfu(waddr))
843 scoreboard->last_sfu_write_tick = scoreboard->tick;
844 }
845
846 static void
847 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
848 const struct v3d_qpu_instr *inst)
849 {
850 scoreboard->last_waddr_add = ~0;
851 scoreboard->last_waddr_mul = ~0;
852
853 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
854 return;
855
856 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
857
858 if (inst->alu.add.op != V3D_QPU_A_NOP) {
859 if (inst->alu.add.magic_write) {
860 update_scoreboard_for_magic_waddr(scoreboard,
861 inst->alu.add.waddr);
862 } else {
863 scoreboard->last_waddr_add = inst->alu.add.waddr;
864 }
865 }
866
867 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
868 if (inst->alu.mul.magic_write) {
869 update_scoreboard_for_magic_waddr(scoreboard,
870 inst->alu.mul.waddr);
871 } else {
872 scoreboard->last_waddr_mul = inst->alu.mul.waddr;
873 }
874 }
875
876 if (inst->sig.ldvary)
877 scoreboard->last_ldvary_tick = scoreboard->tick;
878
879 if (qpu_inst_is_tlb(inst))
880 scoreboard->tlb_locked = true;
881 }
882
883 static void
884 dump_state(const struct v3d_device_info *devinfo,
885 struct list_head *schedule_list)
886 {
887 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
888 fprintf(stderr, " t=%4d: ", n->unblocked_time);
889 v3d_qpu_dump(devinfo, &n->inst->qpu);
890 fprintf(stderr, "\n");
891
892 for (int i = 0; i < n->child_count; i++) {
893 struct schedule_node *child = n->children[i].node;
894 if (!child)
895 continue;
896
897 fprintf(stderr, " - ");
898 v3d_qpu_dump(devinfo, &child->inst->qpu);
899 fprintf(stderr, " (%d parents, %c)\n",
900 child->parent_count,
901 n->children[i].write_after_read ? 'w' : 'r');
902 }
903 }
904 }
905
906 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
907 const struct v3d_qpu_instr *after)
908 {
909 /* Apply some huge latency between texture fetch requests and getting
910 * their results back.
911 *
912 * FIXME: This is actually pretty bogus. If we do:
913 *
914 * mov tmu0_s, a
915 * <a bit of math>
916 * mov tmu0_s, b
917 * load_tmu0
918 * <more math>
919 * load_tmu0
920 *
921 * we count that as worse than
922 *
923 * mov tmu0_s, a
924 * mov tmu0_s, b
925 * <lots of math>
926 * load_tmu0
927 * <more math>
928 * load_tmu0
929 *
930 * because we associate the first load_tmu0 with the *second* tmu0_s.
931 */
932 if (v3d_qpu_magic_waddr_is_tmu(waddr) && after->sig.ldtmu)
933 return 100;
934
935 /* Assume that anything depending on us is consuming the SFU result. */
936 if (v3d_qpu_magic_waddr_is_sfu(waddr))
937 return 3;
938
939 return 1;
940 }
941
942 static uint32_t
943 instruction_latency(struct schedule_node *before, struct schedule_node *after)
944 {
945 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
946 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
947 uint32_t latency = 1;
948
949 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
950 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
951 return latency;
952
953 if (before_inst->alu.add.magic_write) {
954 latency = MAX2(latency,
955 magic_waddr_latency(before_inst->alu.add.waddr,
956 after_inst));
957 }
958
959 if (before_inst->alu.mul.magic_write) {
960 latency = MAX2(latency,
961 magic_waddr_latency(before_inst->alu.mul.waddr,
962 after_inst));
963 }
964
965 return latency;
966 }
967
968 /** Recursive computation of the delay member of a node. */
969 static void
970 compute_delay(struct schedule_node *n)
971 {
972 if (!n->child_count) {
973 n->delay = 1;
974 } else {
975 for (int i = 0; i < n->child_count; i++) {
976 if (!n->children[i].node->delay)
977 compute_delay(n->children[i].node);
978 n->delay = MAX2(n->delay,
979 n->children[i].node->delay +
980 instruction_latency(n, n->children[i].node));
981 }
982 }
983 }
984
985 static void
986 mark_instruction_scheduled(struct list_head *schedule_list,
987 uint32_t time,
988 struct schedule_node *node,
989 bool war_only)
990 {
991 if (!node)
992 return;
993
994 for (int i = node->child_count - 1; i >= 0; i--) {
995 struct schedule_node *child =
996 node->children[i].node;
997
998 if (!child)
999 continue;
1000
1001 if (war_only && !node->children[i].write_after_read)
1002 continue;
1003
1004 /* If the requirement is only that the node not appear before
1005 * the last read of its destination, then it can be scheduled
1006 * immediately after (or paired with!) the thing reading the
1007 * destination.
1008 */
1009 uint32_t latency = 0;
1010 if (!war_only) {
1011 latency = instruction_latency(node,
1012 node->children[i].node);
1013 }
1014
1015 child->unblocked_time = MAX2(child->unblocked_time,
1016 time + latency);
1017 child->parent_count--;
1018 if (child->parent_count == 0)
1019 list_add(&child->link, schedule_list);
1020
1021 node->children[i].node = NULL;
1022 }
1023 }
1024
1025 static void
1026 insert_scheduled_instruction(struct v3d_compile *c,
1027 struct qblock *block,
1028 struct choose_scoreboard *scoreboard,
1029 struct qinst *inst)
1030 {
1031 list_addtail(&inst->link, &block->instructions);
1032
1033 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1034 c->qpu_inst_count++;
1035 scoreboard->tick++;
1036 }
1037
1038 static struct qinst *
1039 vir_nop()
1040 {
1041 struct qreg undef = { QFILE_NULL, 0 };
1042 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1043
1044 return qinst;
1045 }
1046
1047 static void
1048 emit_nop(struct v3d_compile *c, struct qblock *block,
1049 struct choose_scoreboard *scoreboard)
1050 {
1051 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1052 }
1053
1054 static bool
1055 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1056 const struct qinst *qinst, int slot)
1057 {
1058 const struct v3d_qpu_instr *inst = &qinst->qpu;
1059
1060 /* Only TLB Z writes are prohibited in the last slot, but we don't
1061 * have those flagged so prohibit all TLB ops for now.
1062 */
1063 if (slot == 2 && qpu_inst_is_tlb(inst))
1064 return false;
1065
1066 if (slot > 0 && qinst->uniform != ~0)
1067 return false;
1068
1069 if (v3d_qpu_uses_vpm(inst))
1070 return false;
1071
1072 if (inst->sig.ldvary)
1073 return false;
1074
1075 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1076 /* No writing physical registers at the end. */
1077 if (!inst->alu.add.magic_write ||
1078 !inst->alu.mul.magic_write) {
1079 return false;
1080 }
1081
1082 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1083 return false;
1084
1085 /* RF0-2 might be overwritten during the delay slots by
1086 * fragment shader setup.
1087 */
1088 if (inst->raddr_a < 3 &&
1089 (inst->alu.add.a == V3D_QPU_MUX_A ||
1090 inst->alu.add.b == V3D_QPU_MUX_A ||
1091 inst->alu.mul.a == V3D_QPU_MUX_A ||
1092 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1093 return false;
1094 }
1095
1096 if (inst->raddr_b < 3 &&
1097 !inst->sig.small_imm &&
1098 (inst->alu.add.a == V3D_QPU_MUX_B ||
1099 inst->alu.add.b == V3D_QPU_MUX_B ||
1100 inst->alu.mul.a == V3D_QPU_MUX_B ||
1101 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1102 return false;
1103 }
1104 }
1105
1106 return true;
1107 }
1108
1109 static bool
1110 valid_thrsw_sequence(struct v3d_compile *c,
1111 struct qinst *qinst, int instructions_in_sequence,
1112 bool is_thrend)
1113 {
1114 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1115 /* No scheduling SFU when the result would land in the other
1116 * thread. The simulator complains for safety, though it
1117 * would only occur for dead code in our case.
1118 */
1119 if (slot > 0 &&
1120 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1121 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1122 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1123 return false;
1124 }
1125
1126 if (slot > 0 && qinst->qpu.sig.ldvary)
1127 return false;
1128
1129 if (is_thrend &&
1130 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1131 return false;
1132 }
1133
1134 /* Note that the list is circular, so we can only do this up
1135 * to instructions_in_sequence.
1136 */
1137 qinst = (struct qinst *)qinst->link.next;
1138 }
1139
1140 return true;
1141 }
1142
1143 /**
1144 * Emits a THRSW signal in the stream, trying to move it up to pair with
1145 * another instruction.
1146 */
1147 static int
1148 emit_thrsw(struct v3d_compile *c,
1149 struct qblock *block,
1150 struct choose_scoreboard *scoreboard,
1151 struct qinst *inst,
1152 bool is_thrend)
1153 {
1154 int time = 0;
1155
1156 /* There should be nothing in a thrsw inst being scheduled other than
1157 * the signal bits.
1158 */
1159 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1160 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1161 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1162
1163 /* Find how far back into previous instructions we can put the THRSW. */
1164 int slots_filled = 0;
1165 struct qinst *merge_inst = NULL;
1166 vir_for_each_inst_rev(prev_inst, block) {
1167 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1168 sig.thrsw = true;
1169 uint32_t packed_sig;
1170
1171 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1172 break;
1173
1174 if (!valid_thrsw_sequence(c, prev_inst, slots_filled + 1,
1175 is_thrend)) {
1176 break;
1177 }
1178
1179 merge_inst = prev_inst;
1180 if (++slots_filled == 3)
1181 break;
1182 }
1183
1184 bool needs_free = false;
1185 if (merge_inst) {
1186 merge_inst->qpu.sig.thrsw = true;
1187 needs_free = true;
1188 } else {
1189 insert_scheduled_instruction(c, block, scoreboard, inst);
1190 time++;
1191 slots_filled++;
1192 merge_inst = inst;
1193 }
1194
1195 /* Insert any extra delay slot NOPs we need. */
1196 for (int i = 0; i < 3 - slots_filled; i++) {
1197 emit_nop(c, block, scoreboard);
1198 time++;
1199 }
1200
1201 /* If we're emitting the last THRSW (other than program end), then
1202 * signal that to the HW by emitting two THRSWs in a row.
1203 */
1204 if (inst->is_last_thrsw) {
1205 struct qinst *second_inst =
1206 (struct qinst *)merge_inst->link.next;
1207 second_inst->qpu.sig.thrsw = true;
1208 }
1209
1210 /* If we put our THRSW into another instruction, free up the
1211 * instruction that didn't end up scheduled into the list.
1212 */
1213 if (needs_free)
1214 free(inst);
1215
1216 return time;
1217 }
1218
1219 static uint32_t
1220 schedule_instructions(struct v3d_compile *c,
1221 struct choose_scoreboard *scoreboard,
1222 struct qblock *block,
1223 struct list_head *schedule_list,
1224 enum quniform_contents *orig_uniform_contents,
1225 uint32_t *orig_uniform_data,
1226 uint32_t *next_uniform)
1227 {
1228 const struct v3d_device_info *devinfo = c->devinfo;
1229 uint32_t time = 0;
1230
1231 if (debug) {
1232 fprintf(stderr, "initial deps:\n");
1233 dump_state(devinfo, schedule_list);
1234 fprintf(stderr, "\n");
1235 }
1236
1237 /* Remove non-DAG heads from the list. */
1238 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
1239 if (n->parent_count != 0)
1240 list_del(&n->link);
1241 }
1242
1243 while (!list_empty(schedule_list)) {
1244 struct schedule_node *chosen =
1245 choose_instruction_to_schedule(devinfo,
1246 scoreboard,
1247 schedule_list,
1248 NULL);
1249 struct schedule_node *merge = NULL;
1250
1251 /* If there are no valid instructions to schedule, drop a NOP
1252 * in.
1253 */
1254 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1255 struct v3d_qpu_instr *inst = &qinst->qpu;
1256
1257 if (debug) {
1258 fprintf(stderr, "t=%4d: current list:\n",
1259 time);
1260 dump_state(devinfo, schedule_list);
1261 fprintf(stderr, "t=%4d: chose: ", time);
1262 v3d_qpu_dump(devinfo, inst);
1263 fprintf(stderr, "\n");
1264 }
1265
1266 /* We can't mark_instruction_scheduled() the chosen inst until
1267 * we're done identifying instructions to merge, so put the
1268 * merged instructions on a list for a moment.
1269 */
1270 struct list_head merged_list;
1271 list_inithead(&merged_list);
1272
1273 /* Schedule this instruction onto the QPU list. Also try to
1274 * find an instruction to pair with it.
1275 */
1276 if (chosen) {
1277 time = MAX2(chosen->unblocked_time, time);
1278 list_del(&chosen->link);
1279 mark_instruction_scheduled(schedule_list, time,
1280 chosen, true);
1281
1282 while ((merge =
1283 choose_instruction_to_schedule(devinfo,
1284 scoreboard,
1285 schedule_list,
1286 chosen))) {
1287 time = MAX2(merge->unblocked_time, time);
1288 list_del(&merge->link);
1289 list_addtail(&merge->link, &merged_list);
1290 (void)qpu_merge_inst(devinfo, inst,
1291 inst, &merge->inst->qpu);
1292 if (merge->inst->uniform != -1) {
1293 chosen->inst->uniform =
1294 merge->inst->uniform;
1295 }
1296
1297 if (debug) {
1298 fprintf(stderr, "t=%4d: merging: ",
1299 time);
1300 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1301 fprintf(stderr, "\n");
1302 fprintf(stderr, " result: ");
1303 v3d_qpu_dump(devinfo, inst);
1304 fprintf(stderr, "\n");
1305 }
1306 }
1307 }
1308
1309 /* Update the uniform index for the rewritten location --
1310 * branch target updating will still need to change
1311 * c->uniform_data[] using this index.
1312 */
1313 if (qinst->uniform != -1) {
1314 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1315 block->branch_uniform = *next_uniform;
1316
1317 c->uniform_data[*next_uniform] =
1318 orig_uniform_data[qinst->uniform];
1319 c->uniform_contents[*next_uniform] =
1320 orig_uniform_contents[qinst->uniform];
1321 qinst->uniform = *next_uniform;
1322 (*next_uniform)++;
1323 }
1324
1325 if (debug) {
1326 fprintf(stderr, "\n");
1327 }
1328
1329 /* Now that we've scheduled a new instruction, some of its
1330 * children can be promoted to the list of instructions ready to
1331 * be scheduled. Update the children's unblocked time for this
1332 * DAG edge as we do so.
1333 */
1334 mark_instruction_scheduled(schedule_list, time, chosen, false);
1335 list_for_each_entry(struct schedule_node, merge, &merged_list,
1336 link) {
1337 mark_instruction_scheduled(schedule_list, time, merge,
1338 false);
1339
1340 /* The merged VIR instruction doesn't get re-added to the
1341 * block, so free it now.
1342 */
1343 free(merge->inst);
1344 }
1345
1346 if (inst->sig.thrsw) {
1347 time += emit_thrsw(c, block, scoreboard, qinst, false);
1348 } else {
1349 insert_scheduled_instruction(c, block,
1350 scoreboard, qinst);
1351
1352 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1353 block->branch_qpu_ip = c->qpu_inst_count - 1;
1354 /* Fill the delay slots.
1355 *
1356 * We should fill these with actual instructions,
1357 * instead, but that will probably need to be done
1358 * after this, once we know what the leading
1359 * instructions of the successors are (so we can
1360 * handle A/B register file write latency)
1361 */
1362 for (int i = 0; i < 3; i++)
1363 emit_nop(c, block, scoreboard);
1364 }
1365 }
1366 }
1367
1368 return time;
1369 }
1370
1371 static uint32_t
1372 qpu_schedule_instructions_block(struct v3d_compile *c,
1373 struct choose_scoreboard *scoreboard,
1374 struct qblock *block,
1375 enum quniform_contents *orig_uniform_contents,
1376 uint32_t *orig_uniform_data,
1377 uint32_t *next_uniform)
1378 {
1379 void *mem_ctx = ralloc_context(NULL);
1380 struct list_head schedule_list;
1381
1382 list_inithead(&schedule_list);
1383
1384 /* Wrap each instruction in a scheduler structure. */
1385 while (!list_empty(&block->instructions)) {
1386 struct qinst *qinst = (struct qinst *)block->instructions.next;
1387 struct schedule_node *n =
1388 rzalloc(mem_ctx, struct schedule_node);
1389
1390 n->inst = qinst;
1391
1392 list_del(&qinst->link);
1393 list_addtail(&n->link, &schedule_list);
1394 }
1395
1396 calculate_forward_deps(c, &schedule_list);
1397 calculate_reverse_deps(c, &schedule_list);
1398
1399 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
1400 compute_delay(n);
1401 }
1402
1403 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1404 &schedule_list,
1405 orig_uniform_contents,
1406 orig_uniform_data,
1407 next_uniform);
1408
1409 ralloc_free(mem_ctx);
1410
1411 return cycles;
1412 }
1413
1414 static void
1415 qpu_set_branch_targets(struct v3d_compile *c)
1416 {
1417 vir_for_each_block(block, c) {
1418 /* The end block of the program has no branch. */
1419 if (!block->successors[0])
1420 continue;
1421
1422 /* If there was no branch instruction, then the successor
1423 * block must follow immediately after this one.
1424 */
1425 if (block->branch_qpu_ip == ~0) {
1426 assert(block->end_qpu_ip + 1 ==
1427 block->successors[0]->start_qpu_ip);
1428 continue;
1429 }
1430
1431 /* Walk back through the delay slots to find the branch
1432 * instr.
1433 */
1434 struct list_head *entry = block->instructions.prev;
1435 for (int i = 0; i < 3; i++)
1436 entry = entry->prev;
1437 struct qinst *branch = container_of(entry, branch, link);
1438 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1439
1440 /* Make sure that the if-we-don't-jump
1441 * successor was scheduled just after the
1442 * delay slots.
1443 */
1444 assert(!block->successors[1] ||
1445 block->successors[1]->start_qpu_ip ==
1446 block->branch_qpu_ip + 4);
1447
1448 branch->qpu.branch.offset =
1449 ((block->successors[0]->start_qpu_ip -
1450 (block->branch_qpu_ip + 4)) *
1451 sizeof(uint64_t));
1452
1453 /* Set up the relative offset to jump in the
1454 * uniform stream.
1455 *
1456 * Use a temporary here, because
1457 * uniform_data[inst->uniform] may be shared
1458 * between multiple instructions.
1459 */
1460 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1461 c->uniform_data[branch->uniform] =
1462 (block->successors[0]->start_uniform -
1463 (block->branch_uniform + 1)) * 4;
1464 }
1465 }
1466
1467 uint32_t
1468 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1469 {
1470 const struct v3d_device_info *devinfo = c->devinfo;
1471 struct qblock *end_block = list_last_entry(&c->blocks,
1472 struct qblock, link);
1473
1474 /* We reorder the uniforms as we schedule instructions, so save the
1475 * old data off and replace it.
1476 */
1477 uint32_t *uniform_data = c->uniform_data;
1478 enum quniform_contents *uniform_contents = c->uniform_contents;
1479 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1480 c->num_uniforms);
1481 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1482 c->uniform_array_size = c->num_uniforms;
1483 uint32_t next_uniform = 0;
1484
1485 struct choose_scoreboard scoreboard;
1486 memset(&scoreboard, 0, sizeof(scoreboard));
1487 scoreboard.last_waddr_add = ~0;
1488 scoreboard.last_waddr_mul = ~0;
1489 scoreboard.last_ldvary_tick = -10;
1490 scoreboard.last_sfu_write_tick = -10;
1491 scoreboard.last_uniforms_reset_tick = -10;
1492
1493 if (debug) {
1494 fprintf(stderr, "Pre-schedule instructions\n");
1495 vir_for_each_block(block, c) {
1496 fprintf(stderr, "BLOCK %d\n", block->index);
1497 list_for_each_entry(struct qinst, qinst,
1498 &block->instructions, link) {
1499 v3d_qpu_dump(devinfo, &qinst->qpu);
1500 fprintf(stderr, "\n");
1501 }
1502 }
1503 fprintf(stderr, "\n");
1504 }
1505
1506 uint32_t cycles = 0;
1507 vir_for_each_block(block, c) {
1508 block->start_qpu_ip = c->qpu_inst_count;
1509 block->branch_qpu_ip = ~0;
1510 block->start_uniform = next_uniform;
1511
1512 cycles += qpu_schedule_instructions_block(c,
1513 &scoreboard,
1514 block,
1515 uniform_contents,
1516 uniform_data,
1517 &next_uniform);
1518
1519 block->end_qpu_ip = c->qpu_inst_count - 1;
1520 }
1521
1522 /* Emit the program-end THRSW instruction. */;
1523 struct qinst *thrsw = vir_nop();
1524 thrsw->qpu.sig.thrsw = true;
1525 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1526
1527 qpu_set_branch_targets(c);
1528
1529 assert(next_uniform == c->num_uniforms);
1530
1531 return cycles;
1532 }