src/broadcom/compiler/qpu_validate.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file
  26  *
  27  * Validates the QPU instruction sequence after register allocation and
  28  * scheduling.
  29  */
  30
  31 #include <assert.h>
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include "v3d_compiler.h"
  35 #include "qpu/qpu_disasm.h"
  36
  37 struct v3d_qpu_validate_state {
  38         struct v3d_compile *c;
  39         const struct v3d_qpu_instr *last;
  40         int ip;
  41         int last_sfu_write;
  42 };
  43
  44 static void
  45 fail_instr(struct v3d_qpu_validate_state *state, const char *msg)
  46 {
  47         struct v3d_compile *c = state->c;
  48
  49         fprintf(stderr, "v3d_qpu_validate at ip %d: %s:\n", state->ip, msg);
  50
  51         int dump_ip = 0;
  52         vir_for_each_inst_inorder(inst, c) {
  53                 v3d_qpu_dump(c->devinfo, &inst->qpu);
  54
  55                 if (dump_ip++ == state->ip)
  56                         fprintf(stderr, " *** ERROR ***");
  57
  58                 fprintf(stderr, "\n");
  59         }
  60
  61         fprintf(stderr, "\n");
  62         abort();
  63 }
  64
  65 static bool
  66 qpu_magic_waddr_matches(const struct v3d_qpu_instr *inst,
  67                         bool (*predicate)(enum v3d_qpu_waddr waddr))
  68 {
  69         if (inst->type == V3D_QPU_INSTR_TYPE_ALU)
  70                 return false;
  71
  72         if (inst->alu.add.op != V3D_QPU_A_NOP &&
  73             inst->alu.add.magic_write &&
  74             predicate(inst->alu.add.waddr))
  75                 return true;
  76
  77         if (inst->alu.mul.op != V3D_QPU_M_NOP &&
  78             inst->alu.mul.magic_write &&
  79             predicate(inst->alu.mul.waddr))
  80                 return true;
  81
  82         return false;
  83 }
  84
  85 static void
  86 qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst)
  87 {
  88         const struct v3d_qpu_instr *inst = &qinst->qpu;
  89
  90         if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
  91                 return;
  92
  93         /* LDVARY writes r5 two instructions later and LDUNIF writes
  94          * r5 one instruction later, which is illegal to have
  95          * together.
  96          */
  97         if (state->last && state->last->sig.ldvary && inst->sig.ldunif) {
  98                 fail_instr(state, "LDUNIF after a LDVARY");
  99         }
 100
 101         int tmu_writes = 0;
 102         int sfu_writes = 0;
 103         int vpm_writes = 0;
 104         int tlb_writes = 0;
 105         int tsy_writes = 0;
 106
 107         if (inst->alu.add.op != V3D_QPU_A_NOP) {
 108                 if (inst->alu.add.magic_write) {
 109                         if (v3d_qpu_magic_waddr_is_tmu(inst->alu.add.waddr))
 110                                 tmu_writes++;
 111                         if (v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))
 112                                 sfu_writes++;
 113                         if (v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr))
 114                                 vpm_writes++;
 115                         if (v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr))
 116                                 tlb_writes++;
 117                         if (v3d_qpu_magic_waddr_is_tsy(inst->alu.add.waddr))
 118                                 tsy_writes++;
 119                 }
 120         }
 121
 122         if (inst->alu.mul.op != V3D_QPU_M_NOP) {
 123                 if (inst->alu.mul.magic_write) {
 124                         if (v3d_qpu_magic_waddr_is_tmu(inst->alu.mul.waddr))
 125                                 tmu_writes++;
 126                         if (v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))
 127                                 sfu_writes++;
 128                         if (v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr))
 129                                 vpm_writes++;
 130                         if (v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr))
 131                                 tlb_writes++;
 132                         if (v3d_qpu_magic_waddr_is_tsy(inst->alu.mul.waddr))
 133                                 tsy_writes++;
 134                 }
 135         }
 136
 137         (void)qpu_magic_waddr_matches; /* XXX */
 138
 139         /* SFU r4 results come back two instructions later.  No doing
 140          * r4 read/writes or other SFU lookups until it's done.
 141          */
 142         if (state->ip - state->last_sfu_write < 2) {
 143                 if (v3d_qpu_uses_mux(inst, V3D_QPU_MUX_R4))
 144                         fail_instr(state, "R4 read too soon after SFU");
 145
 146                 if (v3d_qpu_writes_r4(inst))
 147                         fail_instr(state, "R4 write too soon after SFU");
 148
 149                 if (sfu_writes)
 150                         fail_instr(state, "SFU write too soon after SFU");
 151         }
 152
 153         /* XXX: The docs say VPM can happen with the others, but the simulator
 154          * disagrees.
 155          */
 156         if (tmu_writes +
 157             sfu_writes +
 158             vpm_writes +
 159             tlb_writes +
 160             tsy_writes +
 161             inst->sig.ldtmu +
 162             inst->sig.ldtlb +
 163             inst->sig.ldvpm +
 164             inst->sig.ldtlbu > 1) {
 165                 fail_instr(state,
 166                            "Only one of [TMU, SFU, TSY, TLB read, VPM] allowed");
 167         }
 168
 169         if (sfu_writes)
 170                 state->last_sfu_write = state->ip;
 171 }
 172
 173 static void
 174 qpu_validate_block(struct v3d_qpu_validate_state *state, struct qblock *block)
 175 {
 176         vir_for_each_inst(qinst, block) {
 177                 qpu_validate_inst(state, qinst);
 178
 179                 state->last = &qinst->qpu;
 180                 state->ip++;
 181         }
 182 }
 183
 184 /**
 185  * Checks for the instruction restrictions from page 37 ("Summary of
 186  * Instruction Restrictions").
 187  */
 188 void
 189 qpu_validate(struct v3d_compile *c)
 190 {
 191         /* We don't want to do validation in release builds, but we want to
 192          * keep compiling the validation code to make sure it doesn't get
 193          * broken.
 194          */
 195 #ifndef DEBUG
 196         return;
 197 #endif
 198
 199         struct v3d_qpu_validate_state state = {
 200                 .c = c,
 201                 .last_sfu_write = -10,
 202                 .ip = 0,
 203         };
 204
 205         vir_for_each_block(block, c) {
 206                 qpu_validate_block(&state, block);
 207         }
 208 }