src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "compiler/nir/nir.h"
  38 #include "util/list.h"
  39 #include "util/u_math.h"
  40
  41 #include "qpu/qpu_instr.h"
  42 #include "pipe/p_state.h"
  43
  44 #define V3D_MAX_TEXTURE_SAMPLERS 32
  45 #define V3D_MAX_SAMPLES 4
  46 #define V3D_MAX_FS_INPUTS 64
  47 #define V3D_MAX_VS_INPUTS 64
  48
  49 struct nir_builder;
  50
  51 struct v3d_fs_inputs {
  52         /**
  53          * Array of the meanings of the VPM inputs this shader needs.
  54          *
  55          * It doesn't include those that aren't part of the VPM, like
  56          * point/line coordinates.
  57          */
  58         struct v3d_varying_slot *input_slots;
  59         uint32_t num_inputs;
  60 };
  61
  62 enum qfile {
  63         /** An unused source or destination register. */
  64         QFILE_NULL,
  65
  66         /** A physical register, such as the W coordinate payload. */
  67         QFILE_REG,
  68         /** One of the regsiters for fixed function interactions. */
  69         QFILE_MAGIC,
  70
  71         /**
  72          *  A virtual register, that will be allocated to actual accumulator
  73          * or physical registers later.
  74          */
  75         QFILE_TEMP,
  76         QFILE_VARY,
  77         QFILE_UNIF,
  78         QFILE_TLB,
  79         QFILE_TLBU,
  80
  81         /**
  82          * VPM reads use this with an index value to say what part of the VPM
  83          * is being read.
  84          */
  85         QFILE_VPM,
  86
  87         /**
  88          * Stores an immediate value in the index field that will be used
  89          * directly by qpu_load_imm().
  90          */
  91         QFILE_LOAD_IMM,
  92
  93         /**
  94          * Stores an immediate value in the index field that can be turned
  95          * into a small immediate field by qpu_encode_small_immediate().
  96          */
  97         QFILE_SMALL_IMM,
  98 };
  99
 100 /**
 101  * A reference to a QPU register or a virtual temp register.
 102  */
 103 struct qreg {
 104         enum qfile file;
 105         uint32_t index;
 106 };
 107
 108 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 109 {
 110         return (struct qreg){file, index};
 111 }
 112
 113 /**
 114  * A reference to an actual register at the QPU level, for register
 115  * allocation.
 116  */
 117 struct qpu_reg {
 118         bool magic;
 119         int index;
 120 };
 121
 122 struct qinst {
 123         /** Entry in qblock->instructions */
 124         struct list_head link;
 125
 126         /**
 127          * The instruction being wrapped.  Its condition codes, pack flags,
 128          * signals, etc. will all be used, with just the register references
 129          * being replaced by the contents of qinst->dst and qinst->src[].
 130          */
 131         struct v3d_qpu_instr qpu;
 132
 133         /* Pre-register-allocation references to src/dst registers */
 134         struct qreg dst;
 135         struct qreg src[3];
 136         bool cond_is_exec_mask;
 137         bool has_implicit_uniform;
 138         bool is_last_thrsw;
 139
 140         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 141          * the uncompiled stream it is.
 142          */
 143         int uniform;
 144 };
 145
 146 enum quniform_contents {
 147         /**
 148          * Indicates that a constant 32-bit value is copied from the program's
 149          * uniform contents.
 150          */
 151         QUNIFORM_CONSTANT,
 152         /**
 153          * Indicates that the program's uniform contents are used as an index
 154          * into the GL uniform storage.
 155          */
 156         QUNIFORM_UNIFORM,
 157
 158         /** @{
 159          * Scaling factors from clip coordinates to relative to the viewport
 160          * center.
 161          *
 162          * This is used by the coordinate and vertex shaders to produce the
 163          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 164          * point offsets from the viewport ccenter.
 165          */
 166         QUNIFORM_VIEWPORT_X_SCALE,
 167         QUNIFORM_VIEWPORT_Y_SCALE,
 168         /** @} */
 169
 170         QUNIFORM_VIEWPORT_Z_OFFSET,
 171         QUNIFORM_VIEWPORT_Z_SCALE,
 172
 173         QUNIFORM_USER_CLIP_PLANE,
 174
 175         /**
 176          * A reference to a V3D 3.x texture config parameter 0 uniform.
 177          *
 178          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 179          * defines texture type, miplevels, and such.  It will be found as a
 180          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 181          */
 182         QUNIFORM_TEXTURE_CONFIG_P0_0,
 183         QUNIFORM_TEXTURE_CONFIG_P0_1,
 184         QUNIFORM_TEXTURE_CONFIG_P0_2,
 185         QUNIFORM_TEXTURE_CONFIG_P0_3,
 186         QUNIFORM_TEXTURE_CONFIG_P0_4,
 187         QUNIFORM_TEXTURE_CONFIG_P0_5,
 188         QUNIFORM_TEXTURE_CONFIG_P0_6,
 189         QUNIFORM_TEXTURE_CONFIG_P0_7,
 190         QUNIFORM_TEXTURE_CONFIG_P0_8,
 191         QUNIFORM_TEXTURE_CONFIG_P0_9,
 192         QUNIFORM_TEXTURE_CONFIG_P0_10,
 193         QUNIFORM_TEXTURE_CONFIG_P0_11,
 194         QUNIFORM_TEXTURE_CONFIG_P0_12,
 195         QUNIFORM_TEXTURE_CONFIG_P0_13,
 196         QUNIFORM_TEXTURE_CONFIG_P0_14,
 197         QUNIFORM_TEXTURE_CONFIG_P0_15,
 198         QUNIFORM_TEXTURE_CONFIG_P0_16,
 199         QUNIFORM_TEXTURE_CONFIG_P0_17,
 200         QUNIFORM_TEXTURE_CONFIG_P0_18,
 201         QUNIFORM_TEXTURE_CONFIG_P0_19,
 202         QUNIFORM_TEXTURE_CONFIG_P0_20,
 203         QUNIFORM_TEXTURE_CONFIG_P0_21,
 204         QUNIFORM_TEXTURE_CONFIG_P0_22,
 205         QUNIFORM_TEXTURE_CONFIG_P0_23,
 206         QUNIFORM_TEXTURE_CONFIG_P0_24,
 207         QUNIFORM_TEXTURE_CONFIG_P0_25,
 208         QUNIFORM_TEXTURE_CONFIG_P0_26,
 209         QUNIFORM_TEXTURE_CONFIG_P0_27,
 210         QUNIFORM_TEXTURE_CONFIG_P0_28,
 211         QUNIFORM_TEXTURE_CONFIG_P0_29,
 212         QUNIFORM_TEXTURE_CONFIG_P0_30,
 213         QUNIFORM_TEXTURE_CONFIG_P0_31,
 214         QUNIFORM_TEXTURE_CONFIG_P0_32,
 215
 216         /**
 217          * A reference to a V3D 3.x texture config parameter 1 uniform.
 218          *
 219          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 220          * has the pointer to the indirect texture state.  Our data[] field
 221          * will have a packed p1 value, but the address field will be just
 222          * which texture unit's texture should be referenced.
 223          */
 224         QUNIFORM_TEXTURE_CONFIG_P1,
 225
 226         /* A a V3D 4.x texture config parameter.  The high 8 bits will be
 227          * which texture or sampler is being sampled, and the driver must
 228          * replace the address field with the appropriate address.
 229          */
 230         QUNIFORM_TMU_CONFIG_P0,
 231         QUNIFORM_TMU_CONFIG_P1,
 232
 233         QUNIFORM_TEXTURE_FIRST_LEVEL,
 234
 235         QUNIFORM_TEXTURE_WIDTH,
 236         QUNIFORM_TEXTURE_HEIGHT,
 237         QUNIFORM_TEXTURE_DEPTH,
 238         QUNIFORM_TEXTURE_ARRAY_SIZE,
 239         QUNIFORM_TEXTURE_LEVELS,
 240
 241         QUNIFORM_UBO_ADDR,
 242
 243         QUNIFORM_TEXRECT_SCALE_X,
 244         QUNIFORM_TEXRECT_SCALE_Y,
 245
 246         QUNIFORM_TEXTURE_BORDER_COLOR,
 247
 248         QUNIFORM_STENCIL,
 249
 250         QUNIFORM_ALPHA_REF,
 251         QUNIFORM_SAMPLE_MASK,
 252 };
 253
 254 struct v3d_varying_slot {
 255         uint8_t slot_and_component;
 256 };
 257
 258 static inline struct v3d_varying_slot
 259 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 260 {
 261         assert(slot < 255 / 4);
 262         return (struct v3d_varying_slot){ (slot << 2) + component };
 263 }
 264
 265 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 266 {
 267         return slot.slot_and_component >> 2;
 268 }
 269
 270 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 271 {
 272         return slot.slot_and_component & 3;
 273 }
 274
 275 struct v3d_ubo_range {
 276         /**
 277          * offset in bytes from the start of the ubo where this range is
 278          * uploaded.
 279          *
 280          * Only set once used is set.
 281          */
 282         uint32_t dst_offset;
 283
 284         /**
 285          * offset in bytes from the start of the gallium uniforms where the
 286          * data comes from.
 287          */
 288         uint32_t src_offset;
 289
 290         /** size in bytes of this ubo range */
 291         uint32_t size;
 292 };
 293
 294 struct v3d_key {
 295         void *shader_state;
 296         struct {
 297                 uint8_t swizzle[4];
 298                 uint8_t return_size;
 299                 uint8_t return_channels;
 300                 union {
 301                         struct {
 302                                 unsigned compare_mode:1;
 303                                 unsigned compare_func:3;
 304                                 bool clamp_s:1;
 305                                 bool clamp_t:1;
 306                                 bool clamp_r:1;
 307                         };
 308                         struct {
 309                                 uint16_t msaa_width, msaa_height;
 310                         };
 311                 };
 312         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 313         uint8_t ucp_enables;
 314 };
 315
 316 struct v3d_fs_key {
 317         struct v3d_key base;
 318         bool depth_enabled;
 319         bool is_points;
 320         bool is_lines;
 321         bool alpha_test;
 322         bool point_coord_upper_left;
 323         bool light_twoside;
 324         bool msaa;
 325         bool sample_coverage;
 326         bool sample_alpha_to_coverage;
 327         bool sample_alpha_to_one;
 328         bool clamp_color;
 329         bool shade_model_flat;
 330         uint8_t nr_cbufs;
 331         uint8_t swap_color_rb;
 332         /* Mask of which render targets need to be written as 32-bit floats */
 333         uint8_t f32_color_rb;
 334         uint8_t alpha_test_func;
 335         uint8_t logicop_func;
 336         uint32_t point_sprite_mask;
 337
 338         struct pipe_rt_blend_state blend;
 339 };
 340
 341 struct v3d_vs_key {
 342         struct v3d_key base;
 343
 344         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 345         uint8_t num_fs_inputs;
 346
 347         bool is_coord;
 348         bool per_vertex_point_size;
 349         bool clamp_color;
 350 };
 351
 352 /** A basic block of VIR intructions. */
 353 struct qblock {
 354         struct list_head link;
 355
 356         struct list_head instructions;
 357
 358         struct set *predecessors;
 359         struct qblock *successors[2];
 360
 361         int index;
 362
 363         /* Instruction IPs for the first and last instruction of the block.
 364          * Set by qpu_schedule.c.
 365          */
 366         uint32_t start_qpu_ip;
 367         uint32_t end_qpu_ip;
 368
 369         /* Instruction IP for the branch instruction of the block.  Set by
 370          * qpu_schedule.c.
 371          */
 372         uint32_t branch_qpu_ip;
 373
 374         /** Offset within the uniform stream at the start of the block. */
 375         uint32_t start_uniform;
 376         /** Offset within the uniform stream of the branch instruction */
 377         uint32_t branch_uniform;
 378
 379         /** @{ used by v3d_vir_live_variables.c */
 380         BITSET_WORD *def;
 381         BITSET_WORD *use;
 382         BITSET_WORD *live_in;
 383         BITSET_WORD *live_out;
 384         int start_ip, end_ip;
 385         /** @} */
 386 };
 387
 388 /**
 389  * Compiler state saved across compiler invocations, for any expensive global
 390  * setup.
 391  */
 392 struct v3d_compiler {
 393         const struct v3d_device_info *devinfo;
 394         struct ra_regs *regs;
 395         unsigned int reg_class_phys[3];
 396         unsigned int reg_class_phys_or_acc[3];
 397 };
 398
 399 struct v3d_compile {
 400         const struct v3d_device_info *devinfo;
 401         nir_shader *s;
 402         nir_function_impl *impl;
 403         struct exec_list *cf_node_list;
 404         const struct v3d_compiler *compiler;
 405
 406         /**
 407          * Mapping from nir_register * or nir_ssa_def * to array of struct
 408          * qreg for the values.
 409          */
 410         struct hash_table *def_ht;
 411
 412         /* For each temp, the instruction generating its value. */
 413         struct qinst **defs;
 414         uint32_t defs_array_size;
 415
 416         /**
 417          * Inputs to the shader, arranged by TGSI declaration order.
 418          *
 419          * Not all fragment shader QFILE_VARY reads are present in this array.
 420          */
 421         struct qreg *inputs;
 422         struct qreg *outputs;
 423         bool msaa_per_sample_output;
 424         struct qreg color_reads[V3D_MAX_SAMPLES];
 425         struct qreg sample_colors[V3D_MAX_SAMPLES];
 426         uint32_t inputs_array_size;
 427         uint32_t outputs_array_size;
 428         uint32_t uniforms_array_size;
 429
 430         /* Booleans for whether the corresponding QFILE_VARY[i] is
 431          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 432          * customized based on the shademodel_flat shader key.
 433          */
 434         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 435
 436         struct v3d_ubo_range *ubo_ranges;
 437         bool *ubo_range_used;
 438         uint32_t ubo_ranges_array_size;
 439         /** Number of uniform areas tracked in ubo_ranges. */
 440         uint32_t num_ubo_ranges;
 441         uint32_t next_ubo_dst_offset;
 442
 443         /* State for whether we're executing on each channel currently.  0 if
 444          * yes, otherwise a block number + 1 that the channel jumped to.
 445          */
 446         struct qreg execute;
 447
 448         struct qreg line_x, point_x, point_y;
 449
 450         /**
 451          * Instance ID, which comes in before the vertex attribute payload if
 452          * the shader record requests it.
 453          */
 454         struct qreg iid;
 455
 456         /**
 457          * Vertex ID, which comes in before the vertex attribute payload
 458          * (after Instance ID) if the shader record requests it.
 459          */
 460         struct qreg vid;
 461
 462         /* Fragment shader payload regs. */
 463         struct qreg payload_w, payload_w_centroid, payload_z;
 464
 465         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 466         uint32_t num_vpm_writes;
 467
 468         /**
 469          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 470          *
 471          * This includes those that aren't part of the VPM varyings, like
 472          * point/line coordinates.
 473          */
 474         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 475
 476         /**
 477          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 478          * of the output is.  Used to emit from the VS in the order that the
 479          * FS needs.
 480          */
 481         struct v3d_varying_slot *output_slots;
 482
 483         struct pipe_shader_state *shader_state;
 484         struct v3d_key *key;
 485         struct v3d_fs_key *fs_key;
 486         struct v3d_vs_key *vs_key;
 487
 488         /* Live ranges of temps. */
 489         int *temp_start, *temp_end;
 490
 491         uint32_t *uniform_data;
 492         enum quniform_contents *uniform_contents;
 493         uint32_t uniform_array_size;
 494         uint32_t num_uniforms;
 495         uint32_t num_outputs;
 496         uint32_t output_position_index;
 497         nir_variable *output_color_var[4];
 498         uint32_t output_point_size_index;
 499         uint32_t output_sample_mask_index;
 500
 501         struct qreg undef;
 502         uint32_t num_temps;
 503
 504         struct list_head blocks;
 505         int next_block_index;
 506         struct qblock *cur_block;
 507         struct qblock *loop_cont_block;
 508         struct qblock *loop_break_block;
 509
 510         uint64_t *qpu_insts;
 511         uint32_t qpu_inst_count;
 512         uint32_t qpu_inst_size;
 513
 514         /* For the FS, the number of varying inputs not counting the
 515          * point/line varyings payload
 516          */
 517         uint32_t num_inputs;
 518
 519         /**
 520          * Number of inputs from num_inputs remaining to be queued to the read
 521          * FIFO in the VS/CS.
 522          */
 523         uint32_t num_inputs_remaining;
 524
 525         /* Number of inputs currently in the read FIFO for the VS/CS */
 526         uint32_t num_inputs_in_fifo;
 527
 528         /** Next offset in the VPM to read from in the VS/CS */
 529         uint32_t vpm_read_offset;
 530
 531         uint32_t program_id;
 532         uint32_t variant_id;
 533
 534         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 535          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 536          * limiting ourselves to the part of the physical reg space.
 537          *
 538          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 539          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 540          * physical reg space in half.
 541          */
 542         uint8_t threads;
 543         struct qinst *last_thrsw;
 544         bool last_thrsw_at_top_level;
 545
 546         bool failed;
 547 };
 548
 549 struct v3d_uniform_list {
 550         enum quniform_contents *contents;
 551         uint32_t *data;
 552         uint32_t count;
 553 };
 554
 555 struct v3d_prog_data {
 556         struct v3d_uniform_list uniforms;
 557
 558         struct v3d_ubo_range *ubo_ranges;
 559         uint32_t num_ubo_ranges;
 560         uint32_t ubo_size;
 561
 562         uint8_t num_inputs;
 563         uint8_t threads;
 564
 565         /* For threads > 1, whether the program should be dispatched in the
 566          * after-final-THRSW state.
 567          */
 568         bool single_seg;
 569 };
 570
 571 struct v3d_vs_prog_data {
 572         struct v3d_prog_data base;
 573
 574         bool uses_iid, uses_vid;
 575
 576         /* Number of components read from each vertex attribute. */
 577         uint8_t vattr_sizes[32];
 578
 579         /* Total number of components read, for the shader state record. */
 580         uint32_t vpm_input_size;
 581
 582         /* Total number of components written, for the shader state record. */
 583         uint32_t vpm_output_size;
 584 };
 585
 586 struct v3d_fs_prog_data {
 587         struct v3d_prog_data base;
 588
 589         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 590
 591         /* Array of flat shade flags.
 592          *
 593          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 594          * packet layout.
 595          */
 596         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 597
 598         bool writes_z;
 599         bool discard;
 600 };
 601
 602 /* Special nir_load_input intrinsic index for loading the current TLB
 603  * destination color.
 604  */
 605 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 606
 607 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 608
 609 extern const nir_shader_compiler_options v3d_nir_options;
 610
 611 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 612 void v3d_compiler_free(const struct v3d_compiler *compiler);
 613 void v3d_optimize_nir(struct nir_shader *s);
 614
 615 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 616                          struct v3d_vs_key *key,
 617                          struct v3d_vs_prog_data *prog_data,
 618                          nir_shader *s,
 619                          int program_id, int variant_id,
 620                          uint32_t *final_assembly_size);
 621
 622 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 623                          struct v3d_fs_key *key,
 624                          struct v3d_fs_prog_data *prog_data,
 625                          nir_shader *s,
 626                          int program_id, int variant_id,
 627                          uint32_t *final_assembly_size);
 628
 629 void v3d_nir_to_vir(struct v3d_compile *c);
 630
 631 void vir_compile_destroy(struct v3d_compile *c);
 632 const char *vir_get_stage_name(struct v3d_compile *c);
 633 struct qblock *vir_new_block(struct v3d_compile *c);
 634 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 635 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 636 struct qblock *vir_entry_block(struct v3d_compile *c);
 637 struct qblock *vir_exit_block(struct v3d_compile *c);
 638 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 639                            struct qreg src0, struct qreg src1);
 640 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 641                            struct qreg src0, struct qreg src1);
 642 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 643 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 644 struct qreg vir_uniform(struct v3d_compile *c,
 645                         enum quniform_contents contents,
 646                         uint32_t data);
 647 void vir_schedule_instructions(struct v3d_compile *c);
 648 struct v3d_qpu_instr v3d_qpu_nop(void);
 649
 650 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 651 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 652 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 653 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 654 void vir_set_unpack(struct qinst *inst, int src,
 655                     enum v3d_qpu_input_unpack unpack);
 656
 657 struct qreg vir_get_temp(struct v3d_compile *c);
 658 void vir_calculate_live_intervals(struct v3d_compile *c);
 659 bool vir_has_implicit_uniform(struct qinst *inst);
 660 int vir_get_implicit_uniform_src(struct qinst *inst);
 661 int vir_get_non_sideband_nsrc(struct qinst *inst);
 662 int vir_get_nsrc(struct qinst *inst);
 663 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 664 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 665 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 666 bool vir_is_raw_mov(struct qinst *inst);
 667 bool vir_is_tex(struct qinst *inst);
 668 bool vir_is_add(struct qinst *inst);
 669 bool vir_is_mul(struct qinst *inst);
 670 bool vir_is_float_input(struct qinst *inst);
 671 bool vir_depends_on_flags(struct qinst *inst);
 672 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 673 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 674 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 675 uint8_t vir_channels_written(struct qinst *inst);
 676 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 677 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 678                     struct qreg result);
 679 void vir_emit_thrsw(struct v3d_compile *c);
 680
 681 void vir_dump(struct v3d_compile *c);
 682 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 683
 684 void vir_validate(struct v3d_compile *c);
 685
 686 void vir_optimize(struct v3d_compile *c);
 687 bool vir_opt_algebraic(struct v3d_compile *c);
 688 bool vir_opt_constant_folding(struct v3d_compile *c);
 689 bool vir_opt_copy_propagate(struct v3d_compile *c);
 690 bool vir_opt_dead_code(struct v3d_compile *c);
 691 bool vir_opt_peephole_sf(struct v3d_compile *c);
 692 bool vir_opt_small_immediates(struct v3d_compile *c);
 693 bool vir_opt_vpm(struct v3d_compile *c);
 694 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 695 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 696 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 697 void vir_lower_uniforms(struct v3d_compile *c);
 698
 699 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 700 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 701 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 702 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 703
 704 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 705 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 706 void qpu_validate(struct v3d_compile *c);
 707 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
 708 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 709
 710 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 711
 712 static inline bool
 713 quniform_contents_is_texture_p0(enum quniform_contents contents)
 714 {
 715         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 716                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 717                             V3D_MAX_TEXTURE_SAMPLERS));
 718 }
 719
 720 static inline struct qreg
 721 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 722 {
 723         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 724 }
 725
 726 static inline struct qreg
 727 vir_uniform_f(struct v3d_compile *c, float f)
 728 {
 729         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 730 }
 731
 732 #define VIR_ALU0(name, vir_inst, op)                                     \
 733 static inline struct qreg                                                \
 734 vir_##name(struct v3d_compile *c)                                        \
 735 {                                                                        \
 736         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 737                                         c->undef, c->undef));            \
 738 }                                                                        \
 739 static inline struct qinst *                                             \
 740 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 741 {                                                                        \
 742         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 743                                            c->undef, c->undef));         \
 744 }
 745
 746 #define VIR_ALU1(name, vir_inst, op)                                     \
 747 static inline struct qreg                                                \
 748 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 749 {                                                                        \
 750         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 751                                         a, c->undef));                   \
 752 }                                                                        \
 753 static inline struct qinst *                                             \
 754 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 755                   struct qreg a)                                         \
 756 {                                                                        \
 757         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 758                                            c->undef));                   \
 759 }
 760
 761 #define VIR_ALU2(name, vir_inst, op)                                       \
 762 static inline struct qreg                                                \
 763 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 764 {                                                                        \
 765         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 766 }                                                                        \
 767 static inline struct qinst *                                             \
 768 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 769                   struct qreg a, struct qreg b)                          \
 770 {                                                                        \
 771         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 772 }
 773
 774 #define VIR_NODST_0(name, vir_inst, op)                                 \
 775 static inline struct qinst *                                            \
 776 vir_##name(struct v3d_compile *c)                                       \
 777 {                                                                       \
 778         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 779                                            c->undef, c->undef));        \
 780 }
 781
 782 #define VIR_NODST_1(name, vir_inst, op)                                               \
 783 static inline struct qinst *                                            \
 784 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 785 {                                                                       \
 786         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 787                                            a, c->undef));               \
 788 }
 789
 790 #define VIR_NODST_2(name, vir_inst, op)                                               \
 791 static inline struct qinst *                                            \
 792 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 793 {                                                                       \
 794         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 795                                            a, b));                      \
 796 }
 797
 798 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 799 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 800 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 801 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 802 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 803 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 804 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 805 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 806 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 807 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 808 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 809
 810 VIR_A_ALU2(FADD)
 811 VIR_A_ALU2(VFPACK)
 812 VIR_A_ALU2(FSUB)
 813 VIR_A_ALU2(FMIN)
 814 VIR_A_ALU2(FMAX)
 815
 816 VIR_A_ALU2(ADD)
 817 VIR_A_ALU2(SUB)
 818 VIR_A_ALU2(SHL)
 819 VIR_A_ALU2(SHR)
 820 VIR_A_ALU2(ASR)
 821 VIR_A_ALU2(ROR)
 822 VIR_A_ALU2(MIN)
 823 VIR_A_ALU2(MAX)
 824 VIR_A_ALU2(UMIN)
 825 VIR_A_ALU2(UMAX)
 826 VIR_A_ALU2(AND)
 827 VIR_A_ALU2(OR)
 828 VIR_A_ALU2(XOR)
 829 VIR_A_ALU2(VADD)
 830 VIR_A_ALU2(VSUB)
 831 VIR_A_ALU2(STVPMV)
 832 VIR_A_ALU1(NOT)
 833 VIR_A_ALU1(NEG)
 834 VIR_A_ALU1(FLAPUSH)
 835 VIR_A_ALU1(FLBPUSH)
 836 VIR_A_ALU1(FLBPOP)
 837 VIR_A_ALU1(SETMSF)
 838 VIR_A_ALU1(SETREVF)
 839 VIR_A_ALU1(TIDX)
 840 VIR_A_ALU1(EIDX)
 841 VIR_A_ALU1(LDVPMV_IN)
 842 VIR_A_ALU1(LDVPMV_OUT)
 843
 844 VIR_A_ALU0(FXCD)
 845 VIR_A_ALU0(XCD)
 846 VIR_A_ALU0(FYCD)
 847 VIR_A_ALU0(YCD)
 848 VIR_A_ALU0(MSF)
 849 VIR_A_ALU0(REVF)
 850 VIR_A_NODST_1(VPMSETUP)
 851 VIR_A_NODST_0(VPMWT)
 852 VIR_A_ALU2(FCMP)
 853 VIR_A_ALU2(VFMAX)
 854
 855 VIR_A_ALU1(FROUND)
 856 VIR_A_ALU1(FTOIN)
 857 VIR_A_ALU1(FTRUNC)
 858 VIR_A_ALU1(FTOIZ)
 859 VIR_A_ALU1(FFLOOR)
 860 VIR_A_ALU1(FTOUZ)
 861 VIR_A_ALU1(FCEIL)
 862 VIR_A_ALU1(FTOC)
 863
 864 VIR_A_ALU1(FDX)
 865 VIR_A_ALU1(FDY)
 866
 867 VIR_A_ALU1(ITOF)
 868 VIR_A_ALU1(CLZ)
 869 VIR_A_ALU1(UTOF)
 870
 871 VIR_M_ALU2(UMUL24)
 872 VIR_M_ALU2(FMUL)
 873 VIR_M_ALU2(SMUL24)
 874 VIR_M_NODST_2(MULTOP)
 875
 876 VIR_M_ALU1(MOV)
 877 VIR_M_ALU1(FMOV)
 878
 879 static inline struct qinst *
 880 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
 881              struct qreg dest, struct qreg src)
 882 {
 883         struct qinst *mov = vir_MOV_dest(c, dest, src);
 884         vir_set_cond(mov, cond);
 885         return mov;
 886 }
 887
 888 static inline struct qreg
 889 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
 890         struct qreg src0, struct qreg src1)
 891 {
 892         struct qreg t = vir_get_temp(c);
 893         vir_MOV_dest(c, t, src1);
 894         vir_MOV_cond(c, cond, t, src0);
 895         return t;
 896 }
 897
 898 static inline struct qinst *
 899 vir_NOP(struct v3d_compile *c)
 900 {
 901         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
 902                                                c->undef, c->undef, c->undef));
 903 }
 904
 905 static inline struct qreg
 906 vir_LDTMU(struct v3d_compile *c)
 907 {
 908         if (c->devinfo->ver >= 41) {
 909                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
 910                                                    c->undef, c->undef);
 911                 ldtmu->qpu.sig.ldtmu = true;
 912
 913                 return vir_emit_def(c, ldtmu);
 914         } else {
 915                 vir_NOP(c)->qpu.sig.ldtmu = true;
 916                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
 917         }
 918 }
 919
 920 /*
 921 static inline struct qreg
 922 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
 923 {
 924         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
 925                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
 926 }
 927
 928 static inline struct qreg
 929 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
 930 {
 931         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
 932                                         vir_reg(QFILE_LOAD_IMM, val),
 933                                         c->undef));
 934 }
 935 static inline struct qreg
 936 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
 937 {
 938         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
 939                                         vir_reg(QFILE_LOAD_IMM, val),
 940                                         c->undef));
 941 }
 942 */
 943
 944 static inline struct qinst *
 945 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
 946 {
 947         /* The actual uniform_data value will be set at scheduling time */
 948         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
 949 }
 950
 951 #define vir_for_each_block(block, c)                                    \
 952         list_for_each_entry(struct qblock, block, &c->blocks, link)
 953
 954 #define vir_for_each_block_rev(block, c)                                \
 955         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
 956
 957 /* Loop over the non-NULL members of the successors array. */
 958 #define vir_for_each_successor(succ, block)                             \
 959         for (struct qblock *succ = block->successors[0];                \
 960              succ != NULL;                                              \
 961              succ = (succ == block->successors[1] ? NULL :              \
 962                      block->successors[1]))
 963
 964 #define vir_for_each_inst(inst, block)                                  \
 965         list_for_each_entry(struct qinst, inst, &block->instructions, link)
 966
 967 #define vir_for_each_inst_rev(inst, block)                                  \
 968         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
 969
 970 #define vir_for_each_inst_safe(inst, block)                             \
 971         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
 972
 973 #define vir_for_each_inst_inorder(inst, c)                              \
 974         vir_for_each_block(_block, c)                                   \
 975                 vir_for_each_inst(inst, _block)
 976
 977 #endif /* V3D_COMPILER_H */