src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "compiler/nir/nir.h"
  38 #include "util/list.h"
  39 #include "util/u_math.h"
  40
  41 #include "qpu/qpu_instr.h"
  42 #include "pipe/p_state.h"
  43
  44 #define V3D_MAX_TEXTURE_SAMPLERS 32
  45 #define V3D_MAX_SAMPLES 4
  46 #define V3D_MAX_FS_INPUTS 64
  47 #define V3D_MAX_VS_INPUTS 64
  48
  49 struct nir_builder;
  50
  51 struct v3d_fs_inputs {
  52         /**
  53          * Array of the meanings of the VPM inputs this shader needs.
  54          *
  55          * It doesn't include those that aren't part of the VPM, like
  56          * point/line coordinates.
  57          */
  58         struct v3d_varying_slot *input_slots;
  59         uint32_t num_inputs;
  60 };
  61
  62 enum qfile {
  63         /** An unused source or destination register. */
  64         QFILE_NULL,
  65
  66         /** A physical register, such as the W coordinate payload. */
  67         QFILE_REG,
  68         /** One of the regsiters for fixed function interactions. */
  69         QFILE_MAGIC,
  70
  71         /**
  72          *  A virtual register, that will be allocated to actual accumulator
  73          * or physical registers later.
  74          */
  75         QFILE_TEMP,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         bool smimm;
 119         int index;
 120 };
 121
 122 struct qinst {
 123         /** Entry in qblock->instructions */
 124         struct list_head link;
 125
 126         /**
 127          * The instruction being wrapped.  Its condition codes, pack flags,
 128          * signals, etc. will all be used, with just the register references
 129          * being replaced by the contents of qinst->dst and qinst->src[].
 130          */
 131         struct v3d_qpu_instr qpu;
 132
 133         /* Pre-register-allocation references to src/dst registers */
 134         struct qreg dst;
 135         struct qreg src[3];
 136         bool cond_is_exec_mask;
 137         bool has_implicit_uniform;
 138         bool is_last_thrsw;
 139
 140         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 141          * the uncompiled stream it is.
 142          */
 143         int uniform;
 144 };
 145
 146 enum quniform_contents {
 147         /**
 148          * Indicates that a constant 32-bit value is copied from the program's
 149          * uniform contents.
 150          */
 151         QUNIFORM_CONSTANT,
 152         /**
 153          * Indicates that the program's uniform contents are used as an index
 154          * into the GL uniform storage.
 155          */
 156         QUNIFORM_UNIFORM,
 157
 158         /** @{
 159          * Scaling factors from clip coordinates to relative to the viewport
 160          * center.
 161          *
 162          * This is used by the coordinate and vertex shaders to produce the
 163          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 164          * point offsets from the viewport ccenter.
 165          */
 166         QUNIFORM_VIEWPORT_X_SCALE,
 167         QUNIFORM_VIEWPORT_Y_SCALE,
 168         /** @} */
 169
 170         QUNIFORM_VIEWPORT_Z_OFFSET,
 171         QUNIFORM_VIEWPORT_Z_SCALE,
 172
 173         QUNIFORM_USER_CLIP_PLANE,
 174
 175         /**
 176          * A reference to a V3D 3.x texture config parameter 0 uniform.
 177          *
 178          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 179          * defines texture type, miplevels, and such.  It will be found as a
 180          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 181          */
 182         QUNIFORM_TEXTURE_CONFIG_P0_0,
 183         QUNIFORM_TEXTURE_CONFIG_P0_1,
 184         QUNIFORM_TEXTURE_CONFIG_P0_2,
 185         QUNIFORM_TEXTURE_CONFIG_P0_3,
 186         QUNIFORM_TEXTURE_CONFIG_P0_4,
 187         QUNIFORM_TEXTURE_CONFIG_P0_5,
 188         QUNIFORM_TEXTURE_CONFIG_P0_6,
 189         QUNIFORM_TEXTURE_CONFIG_P0_7,
 190         QUNIFORM_TEXTURE_CONFIG_P0_8,
 191         QUNIFORM_TEXTURE_CONFIG_P0_9,
 192         QUNIFORM_TEXTURE_CONFIG_P0_10,
 193         QUNIFORM_TEXTURE_CONFIG_P0_11,
 194         QUNIFORM_TEXTURE_CONFIG_P0_12,
 195         QUNIFORM_TEXTURE_CONFIG_P0_13,
 196         QUNIFORM_TEXTURE_CONFIG_P0_14,
 197         QUNIFORM_TEXTURE_CONFIG_P0_15,
 198         QUNIFORM_TEXTURE_CONFIG_P0_16,
 199         QUNIFORM_TEXTURE_CONFIG_P0_17,
 200         QUNIFORM_TEXTURE_CONFIG_P0_18,
 201         QUNIFORM_TEXTURE_CONFIG_P0_19,
 202         QUNIFORM_TEXTURE_CONFIG_P0_20,
 203         QUNIFORM_TEXTURE_CONFIG_P0_21,
 204         QUNIFORM_TEXTURE_CONFIG_P0_22,
 205         QUNIFORM_TEXTURE_CONFIG_P0_23,
 206         QUNIFORM_TEXTURE_CONFIG_P0_24,
 207         QUNIFORM_TEXTURE_CONFIG_P0_25,
 208         QUNIFORM_TEXTURE_CONFIG_P0_26,
 209         QUNIFORM_TEXTURE_CONFIG_P0_27,
 210         QUNIFORM_TEXTURE_CONFIG_P0_28,
 211         QUNIFORM_TEXTURE_CONFIG_P0_29,
 212         QUNIFORM_TEXTURE_CONFIG_P0_30,
 213         QUNIFORM_TEXTURE_CONFIG_P0_31,
 214         QUNIFORM_TEXTURE_CONFIG_P0_32,
 215
 216         /**
 217          * A reference to a V3D 3.x texture config parameter 1 uniform.
 218          *
 219          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 220          * has the pointer to the indirect texture state.  Our data[] field
 221          * will have a packed p1 value, but the address field will be just
 222          * which texture unit's texture should be referenced.
 223          */
 224         QUNIFORM_TEXTURE_CONFIG_P1,
 225
 226         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 227          * which texture or sampler is being sampled, and the driver must
 228          * replace the address field with the appropriate address.
 229          */
 230         QUNIFORM_TMU_CONFIG_P0,
 231         QUNIFORM_TMU_CONFIG_P1,
 232
 233         QUNIFORM_TEXTURE_FIRST_LEVEL,
 234
 235         QUNIFORM_TEXTURE_WIDTH,
 236         QUNIFORM_TEXTURE_HEIGHT,
 237         QUNIFORM_TEXTURE_DEPTH,
 238         QUNIFORM_TEXTURE_ARRAY_SIZE,
 239         QUNIFORM_TEXTURE_LEVELS,
 240
 241         QUNIFORM_UBO_ADDR,
 242
 243         QUNIFORM_TEXRECT_SCALE_X,
 244         QUNIFORM_TEXRECT_SCALE_Y,
 245
 246         QUNIFORM_ALPHA_REF,
 247
 248         /**
 249          * Returns the the offset of the scratch buffer for register spilling.
 250          */
 251         QUNIFORM_SPILL_OFFSET,
 252         QUNIFORM_SPILL_SIZE_PER_THREAD,
 253 };
 254
 255 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
 256 {
 257         return unit << 24 | value;
 258 }
 259
 260 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
 261 {
 262         return data >> 24;
 263 }
 264
 265 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
 266 {
 267         return data & 0xffffff;
 268 }
 269
 270 struct v3d_varying_slot {
 271         uint8_t slot_and_component;
 272 };
 273
 274 static inline struct v3d_varying_slot
 275 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 276 {
 277         assert(slot < 255 / 4);
 278         return (struct v3d_varying_slot){ (slot << 2) + component };
 279 }
 280
 281 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 282 {
 283         return slot.slot_and_component >> 2;
 284 }
 285
 286 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 287 {
 288         return slot.slot_and_component & 3;
 289 }
 290
 291 struct v3d_ubo_range {
 292         /**
 293          * offset in bytes from the start of the ubo where this range is
 294          * uploaded.
 295          *
 296          * Only set once used is set.
 297          */
 298         uint32_t dst_offset;
 299
 300         /**
 301          * offset in bytes from the start of the gallium uniforms where the
 302          * data comes from.
 303          */
 304         uint32_t src_offset;
 305
 306         /** size in bytes of this ubo range */
 307         uint32_t size;
 308 };
 309
 310 struct v3d_key {
 311         void *shader_state;
 312         struct {
 313                 uint8_t swizzle[4];
 314                 uint8_t return_size;
 315                 uint8_t return_channels;
 316                 bool clamp_s:1;
 317                 bool clamp_t:1;
 318                 bool clamp_r:1;
 319         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 320         uint8_t ucp_enables;
 321 };
 322
 323 struct v3d_fs_key {
 324         struct v3d_key base;
 325         bool depth_enabled;
 326         bool is_points;
 327         bool is_lines;
 328         bool alpha_test;
 329         bool point_coord_upper_left;
 330         bool light_twoside;
 331         bool msaa;
 332         bool sample_coverage;
 333         bool sample_alpha_to_coverage;
 334         bool sample_alpha_to_one;
 335         bool clamp_color;
 336         bool shade_model_flat;
 337         uint8_t nr_cbufs;
 338         uint8_t swap_color_rb;
 339         /* Mask of which render targets need to be written as 32-bit floats */
 340         uint8_t f32_color_rb;
 341         /* Masks of which render targets need to be written as ints/uints.
 342          * Used by gallium to work around lost information in TGSI.
 343          */
 344         uint8_t int_color_rb;
 345         uint8_t uint_color_rb;
 346         uint8_t alpha_test_func;
 347         uint8_t logicop_func;
 348         uint32_t point_sprite_mask;
 349
 350         struct pipe_rt_blend_state blend;
 351 };
 352
 353 struct v3d_vs_key {
 354         struct v3d_key base;
 355
 356         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 357         uint8_t num_fs_inputs;
 358
 359         bool is_coord;
 360         bool per_vertex_point_size;
 361         bool clamp_color;
 362 };
 363
 364 /** A basic block of VIR intructions. */
 365 struct qblock {
 366         struct list_head link;
 367
 368         struct list_head instructions;
 369
 370         struct set *predecessors;
 371         struct qblock *successors[2];
 372
 373         int index;
 374
 375         /* Instruction IPs for the first and last instruction of the block.
 376          * Set by qpu_schedule.c.
 377          */
 378         uint32_t start_qpu_ip;
 379         uint32_t end_qpu_ip;
 380
 381         /* Instruction IP for the branch instruction of the block.  Set by
 382          * qpu_schedule.c.
 383          */
 384         uint32_t branch_qpu_ip;
 385
 386         /** Offset within the uniform stream at the start of the block. */
 387         uint32_t start_uniform;
 388         /** Offset within the uniform stream of the branch instruction */
 389         uint32_t branch_uniform;
 390
 391         /** @{ used by v3d_vir_live_variables.c */
 392         BITSET_WORD *def;
 393         BITSET_WORD *use;
 394         BITSET_WORD *live_in;
 395         BITSET_WORD *live_out;
 396         int start_ip, end_ip;
 397         /** @} */
 398 };
 399
 400 /** Which util/list.h add mode we should use when inserting an instruction. */
 401 enum vir_cursor_mode {
 402         vir_cursor_add,
 403         vir_cursor_addtail,
 404 };
 405
 406 /**
 407  * Tracking structure for where new instructions should be inserted.  Create
 408  * with one of the vir_after_inst()-style helper functions.
 409  *
 410  * This does not protect against removal of the block or instruction, so we
 411  * have an assert in instruction removal to try to catch it.
 412  */
 413 struct vir_cursor {
 414         enum vir_cursor_mode mode;
 415         struct list_head *link;
 416 };
 417
 418 static inline struct vir_cursor
 419 vir_before_inst(struct qinst *inst)
 420 {
 421         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 422 }
 423
 424 static inline struct vir_cursor
 425 vir_after_inst(struct qinst *inst)
 426 {
 427         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 428 }
 429
 430 static inline struct vir_cursor
 431 vir_before_block(struct qblock *block)
 432 {
 433         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 434 }
 435
 436 static inline struct vir_cursor
 437 vir_after_block(struct qblock *block)
 438 {
 439         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 440 }
 441
 442 /**
 443  * Compiler state saved across compiler invocations, for any expensive global
 444  * setup.
 445  */
 446 struct v3d_compiler {
 447         const struct v3d_device_info *devinfo;
 448         struct ra_regs *regs;
 449         unsigned int reg_class_phys[3];
 450         unsigned int reg_class_phys_or_acc[3];
 451 };
 452
 453 struct v3d_compile {
 454         const struct v3d_device_info *devinfo;
 455         nir_shader *s;
 456         nir_function_impl *impl;
 457         struct exec_list *cf_node_list;
 458         const struct v3d_compiler *compiler;
 459
 460         /**
 461          * Mapping from nir_register * or nir_ssa_def * to array of struct
 462          * qreg for the values.
 463          */
 464         struct hash_table *def_ht;
 465
 466         /* For each temp, the instruction generating its value. */
 467         struct qinst **defs;
 468         uint32_t defs_array_size;
 469
 470         /**
 471          * Inputs to the shader, arranged by TGSI declaration order.
 472          *
 473          * Not all fragment shader QFILE_VARY reads are present in this array.
 474          */
 475         struct qreg *inputs;
 476         struct qreg *outputs;
 477         bool msaa_per_sample_output;
 478         struct qreg color_reads[V3D_MAX_SAMPLES];
 479         struct qreg sample_colors[V3D_MAX_SAMPLES];
 480         uint32_t inputs_array_size;
 481         uint32_t outputs_array_size;
 482         uint32_t uniforms_array_size;
 483
 484         /* Booleans for whether the corresponding QFILE_VARY[i] is
 485          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 486          * customized based on the shademodel_flat shader key.
 487          */
 488         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 489
 490         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 491
 492         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 493
 494         bool uses_center_w;
 495
 496         struct v3d_ubo_range *ubo_ranges;
 497         bool *ubo_range_used;
 498         uint32_t ubo_ranges_array_size;
 499         /** Number of uniform areas tracked in ubo_ranges. */
 500         uint32_t num_ubo_ranges;
 501         uint32_t next_ubo_dst_offset;
 502
 503         /* State for whether we're executing on each channel currently.  0 if
 504          * yes, otherwise a block number + 1 that the channel jumped to.
 505          */
 506         struct qreg execute;
 507
 508         struct qreg line_x, point_x, point_y;
 509
 510         /**
 511          * Instance ID, which comes in before the vertex attribute payload if
 512          * the shader record requests it.
 513          */
 514         struct qreg iid;
 515
 516         /**
 517          * Vertex ID, which comes in before the vertex attribute payload
 518          * (after Instance ID) if the shader record requests it.
 519          */
 520         struct qreg vid;
 521
 522         /* Fragment shader payload regs. */
 523         struct qreg payload_w, payload_w_centroid, payload_z;
 524
 525         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 526         uint32_t num_vpm_writes;
 527
 528         /* Size in bytes of registers that have been spilled. This is how much
 529          * space needs to be available in the spill BO per thread per QPU.
 530          */
 531         uint32_t spill_size;
 532         /* Shader-db stats for register spilling. */
 533         uint32_t spills, fills;
 534         /**
 535          * Register spilling's per-thread base address, shared between each
 536          * spill/fill's addressing calculations.
 537          */
 538         struct qreg spill_base;
 539         /* Bit vector of which temps may be spilled */
 540         BITSET_WORD *spillable;
 541
 542         /**
 543          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 544          *
 545          * This includes those that aren't part of the VPM varyings, like
 546          * point/line coordinates.
 547          */
 548         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 549
 550         /**
 551          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 552          * of the output is.  Used to emit from the VS in the order that the
 553          * FS needs.
 554          */
 555         struct v3d_varying_slot *output_slots;
 556
 557         struct pipe_shader_state *shader_state;
 558         struct v3d_key *key;
 559         struct v3d_fs_key *fs_key;
 560         struct v3d_vs_key *vs_key;
 561
 562         /* Live ranges of temps. */
 563         int *temp_start, *temp_end;
 564         bool live_intervals_valid;
 565
 566         uint32_t *uniform_data;
 567         enum quniform_contents *uniform_contents;
 568         uint32_t uniform_array_size;
 569         uint32_t num_uniforms;
 570         uint32_t num_outputs;
 571         uint32_t output_position_index;
 572         nir_variable *output_color_var[4];
 573         uint32_t output_point_size_index;
 574         uint32_t output_sample_mask_index;
 575
 576         struct qreg undef;
 577         uint32_t num_temps;
 578
 579         struct vir_cursor cursor;
 580         struct list_head blocks;
 581         int next_block_index;
 582         struct qblock *cur_block;
 583         struct qblock *loop_cont_block;
 584         struct qblock *loop_break_block;
 585
 586         uint64_t *qpu_insts;
 587         uint32_t qpu_inst_count;
 588         uint32_t qpu_inst_size;
 589
 590         /* For the FS, the number of varying inputs not counting the
 591          * point/line varyings payload
 592          */
 593         uint32_t num_inputs;
 594
 595         /**
 596          * Number of inputs from num_inputs remaining to be queued to the read
 597          * FIFO in the VS/CS.
 598          */
 599         uint32_t num_inputs_remaining;
 600
 601         /* Number of inputs currently in the read FIFO for the VS/CS */
 602         uint32_t num_inputs_in_fifo;
 603
 604         /** Next offset in the VPM to read from in the VS/CS */
 605         uint32_t vpm_read_offset;
 606
 607         uint32_t program_id;
 608         uint32_t variant_id;
 609
 610         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 611          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 612          * limiting ourselves to the part of the physical reg space.
 613          *
 614          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 615          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 616          * physical reg space in half.
 617          */
 618         uint8_t threads;
 619         struct qinst *last_thrsw;
 620         bool last_thrsw_at_top_level;
 621
 622         bool failed;
 623 };
 624
 625 struct v3d_uniform_list {
 626         enum quniform_contents *contents;
 627         uint32_t *data;
 628         uint32_t count;
 629 };
 630
 631 struct v3d_prog_data {
 632         struct v3d_uniform_list uniforms;
 633
 634         struct v3d_ubo_range *ubo_ranges;
 635         uint32_t num_ubo_ranges;
 636         uint32_t ubo_size;
 637         uint32_t spill_size;
 638
 639         uint8_t num_inputs;
 640         uint8_t threads;
 641
 642         /* For threads > 1, whether the program should be dispatched in the
 643          * after-final-THRSW state.
 644          */
 645         bool single_seg;
 646 };
 647
 648 struct v3d_vs_prog_data {
 649         struct v3d_prog_data base;
 650
 651         bool uses_iid, uses_vid;
 652
 653         /* Number of components read from each vertex attribute. */
 654         uint8_t vattr_sizes[32];
 655
 656         /* Total number of components read, for the shader state record. */
 657         uint32_t vpm_input_size;
 658
 659         /* Total number of components written, for the shader state record. */
 660         uint32_t vpm_output_size;
 661
 662         /* Set if there should be separate VPM segments for input and output.
 663          * If unset, vpm_input_size will be 0.
 664          */
 665         bool separate_segments;
 666
 667         /* Value to be programmed in VCM_CACHE_SIZE. */
 668         uint8_t vcm_cache_size;
 669 };
 670
 671 struct v3d_fs_prog_data {
 672         struct v3d_prog_data base;
 673
 674         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 675
 676         /* Array of flat shade flags.
 677          *
 678          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 679          * packet layout.
 680          */
 681         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 682
 683         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 684
 685         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 686
 687         bool writes_z;
 688         bool discard;
 689         bool uses_center_w;
 690 };
 691
 692 /* Special nir_load_input intrinsic index for loading the current TLB
 693  * destination color.
 694  */
 695 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 696
 697 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 698
 699 extern const nir_shader_compiler_options v3d_nir_options;
 700
 701 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 702 void v3d_compiler_free(const struct v3d_compiler *compiler);
 703 void v3d_optimize_nir(struct nir_shader *s);
 704
 705 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 706                          struct v3d_vs_key *key,
 707                          struct v3d_vs_prog_data *prog_data,
 708                          nir_shader *s,
 709                          int program_id, int variant_id,
 710                          uint32_t *final_assembly_size);
 711
 712 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 713                          struct v3d_fs_key *key,
 714                          struct v3d_fs_prog_data *prog_data,
 715                          nir_shader *s,
 716                          int program_id, int variant_id,
 717                          uint32_t *final_assembly_size);
 718
 719 void v3d_nir_to_vir(struct v3d_compile *c);
 720
 721 void vir_compile_destroy(struct v3d_compile *c);
 722 const char *vir_get_stage_name(struct v3d_compile *c);
 723 struct qblock *vir_new_block(struct v3d_compile *c);
 724 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 725 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 726 struct qblock *vir_entry_block(struct v3d_compile *c);
 727 struct qblock *vir_exit_block(struct v3d_compile *c);
 728 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 729                            struct qreg src0, struct qreg src1);
 730 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 731                            struct qreg src0, struct qreg src1);
 732 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 733 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 734 struct qreg vir_uniform(struct v3d_compile *c,
 735                         enum quniform_contents contents,
 736                         uint32_t data);
 737 void vir_schedule_instructions(struct v3d_compile *c);
 738 struct v3d_qpu_instr v3d_qpu_nop(void);
 739
 740 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 741 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 742 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 743 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 744 void vir_set_unpack(struct qinst *inst, int src,
 745                     enum v3d_qpu_input_unpack unpack);
 746
 747 struct qreg vir_get_temp(struct v3d_compile *c);
 748 void vir_emit_last_thrsw(struct v3d_compile *c);
 749 void vir_calculate_live_intervals(struct v3d_compile *c);
 750 bool vir_has_implicit_uniform(struct qinst *inst);
 751 int vir_get_implicit_uniform_src(struct qinst *inst);
 752 int vir_get_non_sideband_nsrc(struct qinst *inst);
 753 int vir_get_nsrc(struct qinst *inst);
 754 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 755 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 756 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 757 bool vir_is_raw_mov(struct qinst *inst);
 758 bool vir_is_tex(struct qinst *inst);
 759 bool vir_is_add(struct qinst *inst);
 760 bool vir_is_mul(struct qinst *inst);
 761 bool vir_is_float_input(struct qinst *inst);
 762 bool vir_depends_on_flags(struct qinst *inst);
 763 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 764 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 765 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 766 uint8_t vir_channels_written(struct qinst *inst);
 767 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 768 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 769                     struct qreg result);
 770 void vir_emit_thrsw(struct v3d_compile *c);
 771
 772 void vir_dump(struct v3d_compile *c);
 773 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 774 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 775
 776 void vir_validate(struct v3d_compile *c);
 777
 778 void vir_optimize(struct v3d_compile *c);
 779 bool vir_opt_algebraic(struct v3d_compile *c);
 780 bool vir_opt_constant_folding(struct v3d_compile *c);
 781 bool vir_opt_copy_propagate(struct v3d_compile *c);
 782 bool vir_opt_dead_code(struct v3d_compile *c);
 783 bool vir_opt_peephole_sf(struct v3d_compile *c);
 784 bool vir_opt_small_immediates(struct v3d_compile *c);
 785 bool vir_opt_vpm(struct v3d_compile *c);
 786 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 787 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 788 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 789 void vir_lower_uniforms(struct v3d_compile *c);
 790
 791 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 792 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 793 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 794 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 795
 796 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 797 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 798 void qpu_validate(struct v3d_compile *c);
 799 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 800 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 801
 802 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 803
 804 static inline bool
 805 quniform_contents_is_texture_p0(enum quniform_contents contents)
 806 {
 807         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 808                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 809                             V3D_MAX_TEXTURE_SAMPLERS));
 810 }
 811
 812 static inline struct qreg
 813 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 814 {
 815         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 816 }
 817
 818 static inline struct qreg
 819 vir_uniform_f(struct v3d_compile *c, float f)
 820 {
 821         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 822 }
 823
 824 #define VIR_ALU0(name, vir_inst, op)                                     \
 825 static inline struct qreg                                                \
 826 vir_##name(struct v3d_compile *c)                                        \
 827 {                                                                        \
 828         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 829                                         c->undef, c->undef));            \
 830 }                                                                        \
 831 static inline struct qinst *                                             \
 832 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 833 {                                                                        \
 834         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 835                                            c->undef, c->undef));         \
 836 }
 837
 838 #define VIR_ALU1(name, vir_inst, op)                                     \
 839 static inline struct qreg                                                \
 840 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 841 {                                                                        \
 842         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 843                                         a, c->undef));                   \
 844 }                                                                        \
 845 static inline struct qinst *                                             \
 846 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 847                   struct qreg a)                                         \
 848 {                                                                        \
 849         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 850                                            c->undef));                   \
 851 }
 852
 853 #define VIR_ALU2(name, vir_inst, op)                                       \
 854 static inline struct qreg                                                \
 855 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 856 {                                                                        \
 857         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 858 }                                                                        \
 859 static inline struct qinst *                                             \
 860 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 861                   struct qreg a, struct qreg b)                          \
 862 {                                                                        \
 863         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 864 }
 865
 866 #define VIR_NODST_0(name, vir_inst, op)                                 \
 867 static inline struct qinst *                                            \
 868 vir_##name(struct v3d_compile *c)                                       \
 869 {                                                                       \
 870         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 871                                            c->undef, c->undef));        \
 872 }
 873
 874 #define VIR_NODST_1(name, vir_inst, op)                                               \
 875 static inline struct qinst *                                            \
 876 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 877 {                                                                       \
 878         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 879                                            a, c->undef));               \
 880 }
 881
 882 #define VIR_NODST_2(name, vir_inst, op)                                               \
 883 static inline struct qinst *                                            \
 884 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 885 {                                                                       \
 886         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 887                                            a, b));                      \
 888 }
 889
 890 #define VIR_SFU(name)                                                      \
 891 static inline struct qreg                                                \
 892 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 893 {                                                                        \
 894         if (c->devinfo->ver >= 41) {                                     \
 895                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 896                                                     c->undef,            \
 897                                                     a, c->undef));       \
 898         } else {                                                         \
 899                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 900                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 901         }                                                                \
 902 }                                                                        \
 903 static inline struct qinst *                                             \
 904 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 905                   struct qreg a)                                         \
 906 {                                                                        \
 907         if (c->devinfo->ver >= 41) {                                     \
 908                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 909                                                        dest,             \
 910                                                        a, c->undef));    \
 911         } else {                                                         \
 912                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 913                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 914         }                                                                \
 915 }
 916
 917 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 918 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 919 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 920 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 921 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 922 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 923 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 924 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 925 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 926 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 927 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 928
 929 VIR_A_ALU2(FADD)
 930 VIR_A_ALU2(VFPACK)
 931 VIR_A_ALU2(FSUB)
 932 VIR_A_ALU2(FMIN)
 933 VIR_A_ALU2(FMAX)
 934
 935 VIR_A_ALU2(ADD)
 936 VIR_A_ALU2(SUB)
 937 VIR_A_ALU2(SHL)
 938 VIR_A_ALU2(SHR)
 939 VIR_A_ALU2(ASR)
 940 VIR_A_ALU2(ROR)
 941 VIR_A_ALU2(MIN)
 942 VIR_A_ALU2(MAX)
 943 VIR_A_ALU2(UMIN)
 944 VIR_A_ALU2(UMAX)
 945 VIR_A_ALU2(AND)
 946 VIR_A_ALU2(OR)
 947 VIR_A_ALU2(XOR)
 948 VIR_A_ALU2(VADD)
 949 VIR_A_ALU2(VSUB)
 950 VIR_A_NODST_2(STVPMV)
 951 VIR_A_ALU1(NOT)
 952 VIR_A_ALU1(NEG)
 953 VIR_A_ALU1(FLAPUSH)
 954 VIR_A_ALU1(FLBPUSH)
 955 VIR_A_ALU1(FLPOP)
 956 VIR_A_ALU1(SETMSF)
 957 VIR_A_ALU1(SETREVF)
 958 VIR_A_ALU0(TIDX)
 959 VIR_A_ALU0(EIDX)
 960 VIR_A_ALU1(LDVPMV_IN)
 961 VIR_A_ALU1(LDVPMV_OUT)
 962 VIR_A_ALU0(TMUWT)
 963
 964 VIR_A_ALU0(FXCD)
 965 VIR_A_ALU0(XCD)
 966 VIR_A_ALU0(FYCD)
 967 VIR_A_ALU0(YCD)
 968 VIR_A_ALU0(MSF)
 969 VIR_A_ALU0(REVF)
 970 VIR_A_NODST_1(VPMSETUP)
 971 VIR_A_NODST_0(VPMWT)
 972 VIR_A_ALU2(FCMP)
 973 VIR_A_ALU2(VFMAX)
 974
 975 VIR_A_ALU1(FROUND)
 976 VIR_A_ALU1(FTOIN)
 977 VIR_A_ALU1(FTRUNC)
 978 VIR_A_ALU1(FTOIZ)
 979 VIR_A_ALU1(FFLOOR)
 980 VIR_A_ALU1(FTOUZ)
 981 VIR_A_ALU1(FCEIL)
 982 VIR_A_ALU1(FTOC)
 983
 984 VIR_A_ALU1(FDX)
 985 VIR_A_ALU1(FDY)
 986
 987 VIR_A_ALU1(ITOF)
 988 VIR_A_ALU1(CLZ)
 989 VIR_A_ALU1(UTOF)
 990
 991 VIR_M_ALU2(UMUL24)
 992 VIR_M_ALU2(FMUL)
 993 VIR_M_ALU2(SMUL24)
 994 VIR_M_NODST_2(MULTOP)
 995
 996 VIR_M_ALU1(MOV)
 997 VIR_M_ALU1(FMOV)
 998
 999 VIR_SFU(RECIP)
1000 VIR_SFU(RSQRT)
1001 VIR_SFU(EXP)
1002 VIR_SFU(LOG)
1003 VIR_SFU(SIN)
1004 VIR_SFU(RSQRT2)
1005
1006 static inline struct qinst *
1007 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1008              struct qreg dest, struct qreg src)
1009 {
1010         struct qinst *mov = vir_MOV_dest(c, dest, src);
1011         vir_set_cond(mov, cond);
1012         return mov;
1013 }
1014
1015 static inline struct qreg
1016 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1017         struct qreg src0, struct qreg src1)
1018 {
1019         struct qreg t = vir_get_temp(c);
1020         vir_MOV_dest(c, t, src1);
1021         vir_MOV_cond(c, cond, t, src0);
1022         return t;
1023 }
1024
1025 static inline struct qinst *
1026 vir_NOP(struct v3d_compile *c)
1027 {
1028         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1029                                                c->undef, c->undef, c->undef));
1030 }
1031
1032 static inline struct qreg
1033 vir_LDTMU(struct v3d_compile *c)
1034 {
1035         if (c->devinfo->ver >= 41) {
1036                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1037                                                    c->undef, c->undef);
1038                 ldtmu->qpu.sig.ldtmu = true;
1039
1040                 return vir_emit_def(c, ldtmu);
1041         } else {
1042                 vir_NOP(c)->qpu.sig.ldtmu = true;
1043                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1044         }
1045 }
1046
1047 static inline struct qreg
1048 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1049 {
1050         vir_MULTOP(c, src0, src1);
1051         return vir_UMUL24(c, src0, src1);
1052 }
1053
1054 /*
1055 static inline struct qreg
1056 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1057 {
1058         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1059                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1060 }
1061
1062 static inline struct qreg
1063 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1064 {
1065         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1066                                         vir_reg(QFILE_LOAD_IMM, val),
1067                                         c->undef));
1068 }
1069 static inline struct qreg
1070 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1071 {
1072         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1073                                         vir_reg(QFILE_LOAD_IMM, val),
1074                                         c->undef));
1075 }
1076 */
1077
1078 static inline struct qinst *
1079 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1080 {
1081         /* The actual uniform_data value will be set at scheduling time */
1082         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1083 }
1084
1085 #define vir_for_each_block(block, c)                                    \
1086         list_for_each_entry(struct qblock, block, &c->blocks, link)
1087
1088 #define vir_for_each_block_rev(block, c)                                \
1089         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1090
1091 /* Loop over the non-NULL members of the successors array. */
1092 #define vir_for_each_successor(succ, block)                             \
1093         for (struct qblock *succ = block->successors[0];                \
1094              succ != NULL;                                              \
1095              succ = (succ == block->successors[1] ? NULL :              \
1096                      block->successors[1]))
1097
1098 #define vir_for_each_inst(inst, block)                                  \
1099         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1100
1101 #define vir_for_each_inst_rev(inst, block)                                  \
1102         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1103
1104 #define vir_for_each_inst_safe(inst, block)                             \
1105         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1106
1107 #define vir_for_each_inst_inorder(inst, c)                              \
1108         vir_for_each_block(_block, c)                                   \
1109                 vir_for_each_inst(inst, _block)
1110
1111 #endif /* V3D_COMPILER_H */