2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
28 vir_get_non_sideband_nsrc(struct qinst
*inst
)
30 switch (inst
->qpu
.type
) {
31 case V3D_QPU_INSTR_TYPE_BRANCH
:
33 case V3D_QPU_INSTR_TYPE_ALU
:
34 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
)
35 return v3d_qpu_add_op_num_src(inst
->qpu
.alu
.add
.op
);
37 return v3d_qpu_mul_op_num_src(inst
->qpu
.alu
.mul
.op
);
44 vir_get_nsrc(struct qinst
*inst
)
46 int nsrc
= vir_get_non_sideband_nsrc(inst
);
48 if (vir_has_implicit_uniform(inst
))
55 vir_has_implicit_uniform(struct qinst
*inst
)
57 switch (inst
->qpu
.type
) {
58 case V3D_QPU_INSTR_TYPE_BRANCH
:
60 case V3D_QPU_INSTR_TYPE_ALU
:
61 switch (inst
->dst
.file
) {
65 return inst
->has_implicit_uniform
;
71 /* The sideband uniform for textures gets stored after the normal ALU
75 vir_get_implicit_uniform_src(struct qinst
*inst
)
77 if (!vir_has_implicit_uniform(inst
))
79 return vir_get_nsrc(inst
) - 1;
83 * Returns whether the instruction has any side effects that must be
87 vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
)
89 switch (inst
->qpu
.type
) {
90 case V3D_QPU_INSTR_TYPE_BRANCH
:
92 case V3D_QPU_INSTR_TYPE_ALU
:
93 switch (inst
->qpu
.alu
.add
.op
) {
94 case V3D_QPU_A_SETREVF
:
95 case V3D_QPU_A_SETMSF
:
96 case V3D_QPU_A_VPMSETUP
:
97 case V3D_QPU_A_STVPMV
:
98 case V3D_QPU_A_STVPMD
:
99 case V3D_QPU_A_STVPMP
:
100 case V3D_QPU_A_VPMWT
:
101 case V3D_QPU_A_TMUWT
:
107 switch (inst
->qpu
.alu
.mul
.op
) {
108 case V3D_QPU_M_MULTOP
:
115 if (inst
->qpu
.sig
.ldtmu
||
116 inst
->qpu
.sig
.ldvary
||
117 inst
->qpu
.sig
.wrtmuc
||
118 inst
->qpu
.sig
.thrsw
) {
126 vir_is_float_input(struct qinst
*inst
)
128 /* XXX: More instrs */
129 switch (inst
->qpu
.type
) {
130 case V3D_QPU_INSTR_TYPE_BRANCH
:
132 case V3D_QPU_INSTR_TYPE_ALU
:
133 switch (inst
->qpu
.alu
.add
.op
) {
138 case V3D_QPU_A_FTOIN
:
144 switch (inst
->qpu
.alu
.mul
.op
) {
146 case V3D_QPU_M_VFMUL
:
158 vir_is_raw_mov(struct qinst
*inst
)
160 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
161 (inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_FMOV
&&
162 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_MOV
)) {
166 if (inst
->qpu
.alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
167 inst
->qpu
.alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
) {
171 if (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
||
172 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
)
179 vir_is_add(struct qinst
*inst
)
181 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
182 inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
);
186 vir_is_mul(struct qinst
*inst
)
188 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
189 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_NOP
);
193 vir_is_tex(struct qinst
*inst
)
195 if (inst
->dst
.file
== QFILE_MAGIC
)
196 return v3d_qpu_magic_waddr_is_tmu(inst
->dst
.index
);
198 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
199 inst
->qpu
.alu
.add
.op
== V3D_QPU_A_TMUWT
) {
207 vir_depends_on_flags(struct qinst
*inst
)
209 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
210 return (inst
->qpu
.branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
);
212 return (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
&&
213 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
);
218 vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
220 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
221 switch (inst
->src
[i
].file
) {
229 if (devinfo
->ver
< 41 && (inst
->qpu
.sig
.ldvary
||
230 inst
->qpu
.sig
.ldtlb
||
231 inst
->qpu
.sig
.ldtlbu
||
232 inst
->qpu
.sig
.ldvpm
)) {
240 vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
242 switch (inst
->dst
.file
) {
244 switch (inst
->dst
.index
) {
245 case V3D_QPU_WADDR_RECIP
:
246 case V3D_QPU_WADDR_RSQRT
:
247 case V3D_QPU_WADDR_EXP
:
248 case V3D_QPU_WADDR_LOG
:
249 case V3D_QPU_WADDR_SIN
:
257 if (devinfo
->ver
< 41 && inst
->qpu
.sig
.ldtmu
)
264 vir_set_unpack(struct qinst
*inst
, int src
,
265 enum v3d_qpu_input_unpack unpack
)
267 assert(src
== 0 || src
== 1);
269 if (vir_is_add(inst
)) {
271 inst
->qpu
.alu
.add
.a_unpack
= unpack
;
273 inst
->qpu
.alu
.add
.b_unpack
= unpack
;
275 assert(vir_is_mul(inst
));
277 inst
->qpu
.alu
.mul
.a_unpack
= unpack
;
279 inst
->qpu
.alu
.mul
.b_unpack
= unpack
;
284 vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
)
286 if (vir_is_add(inst
)) {
287 inst
->qpu
.flags
.ac
= cond
;
289 assert(vir_is_mul(inst
));
290 inst
->qpu
.flags
.mc
= cond
;
295 vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
)
297 if (vir_is_add(inst
)) {
298 inst
->qpu
.flags
.apf
= pf
;
300 assert(vir_is_mul(inst
));
301 inst
->qpu
.flags
.mpf
= pf
;
307 vir_channels_written(struct qinst
*inst
)
309 if (vir_is_mul(inst
)) {
310 switch (inst
->dst
.pack
) {
311 case QPU_PACK_MUL_NOP
:
312 case QPU_PACK_MUL_8888
:
314 case QPU_PACK_MUL_8A
:
316 case QPU_PACK_MUL_8B
:
318 case QPU_PACK_MUL_8C
:
320 case QPU_PACK_MUL_8D
:
324 switch (inst
->dst
.pack
) {
326 case QPU_PACK_A_8888
:
327 case QPU_PACK_A_8888_SAT
:
328 case QPU_PACK_A_32_SAT
:
331 case QPU_PACK_A_8A_SAT
:
334 case QPU_PACK_A_8B_SAT
:
337 case QPU_PACK_A_8C_SAT
:
340 case QPU_PACK_A_8D_SAT
:
343 case QPU_PACK_A_16A_SAT
:
346 case QPU_PACK_A_16B_SAT
:
350 unreachable("Bad pack field");
355 vir_get_temp(struct v3d_compile
*c
)
359 reg
.file
= QFILE_TEMP
;
360 reg
.index
= c
->num_temps
++;
362 if (c
->num_temps
> c
->defs_array_size
) {
363 uint32_t old_size
= c
->defs_array_size
;
364 c
->defs_array_size
= MAX2(old_size
* 2, 16);
366 c
->defs
= reralloc(c
, c
->defs
, struct qinst
*,
368 memset(&c
->defs
[old_size
], 0,
369 sizeof(c
->defs
[0]) * (c
->defs_array_size
- old_size
));
371 c
->spillable
= reralloc(c
, c
->spillable
,
373 BITSET_WORDS(c
->defs_array_size
));
374 for (int i
= old_size
; i
< c
->defs_array_size
; i
++)
375 BITSET_SET(c
->spillable
, i
);
382 vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
384 struct qinst
*inst
= calloc(1, sizeof(*inst
));
386 inst
->qpu
= v3d_qpu_nop();
387 inst
->qpu
.alu
.add
.op
= op
;
398 vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
400 struct qinst
*inst
= calloc(1, sizeof(*inst
));
402 inst
->qpu
= v3d_qpu_nop();
403 inst
->qpu
.alu
.mul
.op
= op
;
414 vir_branch_inst(enum v3d_qpu_branch_cond cond
, struct qreg src
)
416 struct qinst
*inst
= calloc(1, sizeof(*inst
));
418 inst
->qpu
= v3d_qpu_nop();
419 inst
->qpu
.type
= V3D_QPU_INSTR_TYPE_BRANCH
;
420 inst
->qpu
.branch
.cond
= cond
;
421 inst
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_NONE
;
422 inst
->qpu
.branch
.bdi
= V3D_QPU_BRANCH_DEST_REL
;
423 inst
->qpu
.branch
.ub
= true;
424 inst
->qpu
.branch
.bdu
= V3D_QPU_BRANCH_DEST_REL
;
426 inst
->dst
= vir_reg(QFILE_NULL
, 0);
434 vir_emit(struct v3d_compile
*c
, struct qinst
*inst
)
436 switch (c
->cursor
.mode
) {
438 list_add(&inst
->link
, c
->cursor
.link
);
440 case vir_cursor_addtail
:
441 list_addtail(&inst
->link
, c
->cursor
.link
);
445 c
->cursor
= vir_after_inst(inst
);
446 c
->live_intervals_valid
= false;
449 /* Updates inst to write to a new temporary, emits it, and notes the def. */
451 vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
)
453 assert(inst
->dst
.file
== QFILE_NULL
);
455 /* If we're emitting an instruction that's a def, it had better be
456 * writing a register.
458 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
459 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
||
460 v3d_qpu_add_op_has_dst(inst
->qpu
.alu
.add
.op
));
461 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
||
462 v3d_qpu_mul_op_has_dst(inst
->qpu
.alu
.mul
.op
));
465 inst
->dst
= vir_get_temp(c
);
467 if (inst
->dst
.file
== QFILE_TEMP
)
468 c
->defs
[inst
->dst
.index
] = inst
;
476 vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
)
478 if (inst
->dst
.file
== QFILE_TEMP
)
479 c
->defs
[inst
->dst
.index
] = NULL
;
487 vir_new_block(struct v3d_compile
*c
)
489 struct qblock
*block
= rzalloc(c
, struct qblock
);
491 list_inithead(&block
->instructions
);
493 block
->predecessors
= _mesa_set_create(block
,
495 _mesa_key_pointer_equal
);
497 block
->index
= c
->next_block_index
++;
503 vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
)
505 c
->cur_block
= block
;
506 c
->cursor
= vir_after_block(block
);
507 list_addtail(&block
->link
, &c
->blocks
);
511 vir_entry_block(struct v3d_compile
*c
)
513 return list_first_entry(&c
->blocks
, struct qblock
, link
);
517 vir_exit_block(struct v3d_compile
*c
)
519 return list_last_entry(&c
->blocks
, struct qblock
, link
);
523 vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
)
525 _mesa_set_add(successor
->predecessors
, predecessor
);
526 if (predecessor
->successors
[0]) {
527 assert(!predecessor
->successors
[1]);
528 predecessor
->successors
[1] = successor
;
530 predecessor
->successors
[0] = successor
;
534 const struct v3d_compiler
*
535 v3d_compiler_init(const struct v3d_device_info
*devinfo
)
537 struct v3d_compiler
*compiler
= rzalloc(NULL
, struct v3d_compiler
);
541 compiler
->devinfo
= devinfo
;
543 if (!vir_init_reg_sets(compiler
)) {
544 ralloc_free(compiler
);
552 v3d_compiler_free(const struct v3d_compiler
*compiler
)
554 ralloc_free((void *)compiler
);
557 static struct v3d_compile
*
558 vir_compile_init(const struct v3d_compiler
*compiler
,
561 int program_id
, int variant_id
)
563 struct v3d_compile
*c
= rzalloc(NULL
, struct v3d_compile
);
565 c
->compiler
= compiler
;
566 c
->devinfo
= compiler
->devinfo
;
568 c
->program_id
= program_id
;
569 c
->variant_id
= variant_id
;
572 s
= nir_shader_clone(c
, s
);
575 list_inithead(&c
->blocks
);
576 vir_set_emit_block(c
, vir_new_block(c
));
578 c
->output_position_index
= -1;
579 c
->output_point_size_index
= -1;
580 c
->output_sample_mask_index
= -1;
582 c
->def_ht
= _mesa_hash_table_create(c
, _mesa_hash_pointer
,
583 _mesa_key_pointer_equal
);
589 type_size_vec4(const struct glsl_type
*type
)
591 return glsl_count_attribute_slots(type
, false);
595 v3d_lower_nir(struct v3d_compile
*c
)
597 struct nir_lower_tex_options tex_options
= {
599 .lower_rect
= false, /* XXX: Use this on V3D 3.x */
601 /* Apply swizzles to all samplers. */
602 .swizzle_result
= ~0,
605 /* Lower the format swizzle and (for 32-bit returns)
606 * ARB_texture_swizzle-style swizzle.
608 for (int i
= 0; i
< ARRAY_SIZE(c
->key
->tex
); i
++) {
609 for (int j
= 0; j
< 4; j
++)
610 tex_options
.swizzles
[i
][j
] = c
->key
->tex
[i
].swizzle
[j
];
612 if (c
->key
->tex
[i
].clamp_s
)
613 tex_options
.saturate_s
|= 1 << i
;
614 if (c
->key
->tex
[i
].clamp_t
)
615 tex_options
.saturate_t
|= 1 << i
;
616 if (c
->key
->tex
[i
].clamp_r
)
617 tex_options
.saturate_r
|= 1 << i
;
620 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
624 v3d_lower_nir_late(struct v3d_compile
*c
)
626 NIR_PASS_V(c
->s
, v3d_nir_lower_io
, c
);
627 NIR_PASS_V(c
->s
, v3d_nir_lower_txf_ms
, c
);
628 NIR_PASS_V(c
->s
, nir_lower_idiv
);
632 v3d_set_prog_data_uniforms(struct v3d_compile
*c
,
633 struct v3d_prog_data
*prog_data
)
635 int count
= c
->num_uniforms
;
636 struct v3d_uniform_list
*ulist
= &prog_data
->uniforms
;
638 ulist
->count
= count
;
639 ulist
->data
= ralloc_array(prog_data
, uint32_t, count
);
640 memcpy(ulist
->data
, c
->uniform_data
,
641 count
* sizeof(*ulist
->data
));
642 ulist
->contents
= ralloc_array(prog_data
, enum quniform_contents
, count
);
643 memcpy(ulist
->contents
, c
->uniform_contents
,
644 count
* sizeof(*ulist
->contents
));
647 /* Copy the compiler UBO range state to the compiled shader, dropping out
648 * arrays that were never referenced by an indirect load.
650 * (Note that QIR dead code elimination of an array access still leaves that
651 * array alive, though)
654 v3d_set_prog_data_ubo(struct v3d_compile
*c
,
655 struct v3d_prog_data
*prog_data
)
657 if (!c
->num_ubo_ranges
)
660 prog_data
->num_ubo_ranges
= 0;
661 prog_data
->ubo_ranges
= ralloc_array(prog_data
, struct v3d_ubo_range
,
663 for (int i
= 0; i
< c
->num_ubo_ranges
; i
++) {
664 if (!c
->ubo_range_used
[i
])
667 struct v3d_ubo_range
*range
= &c
->ubo_ranges
[i
];
668 prog_data
->ubo_ranges
[prog_data
->num_ubo_ranges
++] = *range
;
669 prog_data
->ubo_size
+= range
->size
;
672 if (prog_data
->ubo_size
) {
673 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
) {
674 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
675 vir_get_stage_name(c
),
676 c
->program_id
, c
->variant_id
,
677 prog_data
->ubo_size
/ 4);
683 v3d_set_prog_data(struct v3d_compile
*c
,
684 struct v3d_prog_data
*prog_data
)
686 prog_data
->threads
= c
->threads
;
687 prog_data
->single_seg
= !c
->last_thrsw
;
688 prog_data
->spill_size
= c
->spill_size
;
690 v3d_set_prog_data_uniforms(c
, prog_data
);
691 v3d_set_prog_data_ubo(c
, prog_data
);
695 v3d_return_qpu_insts(struct v3d_compile
*c
, uint32_t *final_assembly_size
)
697 *final_assembly_size
= c
->qpu_inst_count
* sizeof(uint64_t);
699 uint64_t *qpu_insts
= malloc(*final_assembly_size
);
703 memcpy(qpu_insts
, c
->qpu_insts
, *final_assembly_size
);
705 vir_compile_destroy(c
);
710 uint64_t *v3d_compile_vs(const struct v3d_compiler
*compiler
,
711 struct v3d_vs_key
*key
,
712 struct v3d_vs_prog_data
*prog_data
,
714 int program_id
, int variant_id
,
715 uint32_t *final_assembly_size
)
717 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
718 program_id
, variant_id
);
722 /* Split our I/O vars and dead code eliminate the unused
725 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar_early
,
726 nir_var_shader_in
| nir_var_shader_out
);
727 uint64_t used_outputs
[4] = {0};
728 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
729 int slot
= v3d_slot_get_slot(c
->vs_key
->fs_inputs
[i
]);
730 int comp
= v3d_slot_get_component(c
->vs_key
->fs_inputs
[i
]);
731 used_outputs
[comp
] |= 1ull << slot
;
733 NIR_PASS_V(c
->s
, nir_remove_unused_io_vars
,
734 &c
->s
->outputs
, used_outputs
, NULL
); /* demotes to globals */
735 NIR_PASS_V(c
->s
, nir_lower_global_vars_to_local
);
736 v3d_optimize_nir(c
->s
);
737 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_shader_in
);
738 NIR_PASS_V(c
->s
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
740 (nir_lower_io_options
)0);
744 if (key
->clamp_color
)
745 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
747 if (key
->base
.ucp_enables
) {
748 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, key
->base
.ucp_enables
,
750 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
754 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
755 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
757 v3d_lower_nir_late(c
);
758 v3d_optimize_nir(c
->s
);
759 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
763 v3d_set_prog_data(c
, &prog_data
->base
);
765 prog_data
->base
.num_inputs
= c
->num_inputs
;
767 /* The vertex data gets format converted by the VPM so that
768 * each attribute channel takes up a VPM column. Precompute
769 * the sizes for the shader record.
771 for (int i
= 0; i
< ARRAY_SIZE(prog_data
->vattr_sizes
); i
++) {
772 prog_data
->vattr_sizes
[i
] = c
->vattr_sizes
[i
];
773 prog_data
->vpm_input_size
+= c
->vattr_sizes
[i
];
776 prog_data
->uses_vid
= (s
->info
.system_values_read
&
777 (1ull << SYSTEM_VALUE_VERTEX_ID
));
778 prog_data
->uses_iid
= (s
->info
.system_values_read
&
779 (1ull << SYSTEM_VALUE_INSTANCE_ID
));
781 if (prog_data
->uses_vid
)
782 prog_data
->vpm_input_size
++;
783 if (prog_data
->uses_iid
)
784 prog_data
->vpm_input_size
++;
786 /* Input/output segment size are in sectors (8 rows of 32 bits per
789 prog_data
->vpm_input_size
= align(prog_data
->vpm_input_size
, 8) / 8;
790 prog_data
->vpm_output_size
= align(c
->num_vpm_writes
, 8) / 8;
792 /* Set us up for shared input/output segments. This is apparently
793 * necessary for our VCM setup to avoid varying corruption.
795 prog_data
->separate_segments
= false;
796 prog_data
->vpm_output_size
= MAX2(prog_data
->vpm_output_size
,
797 prog_data
->vpm_input_size
);
798 prog_data
->vpm_input_size
= 0;
800 /* Compute VCM cache size. We set up our program to take up less than
801 * half of the VPM, so that any set of bin and render programs won't
802 * run out of space. We need space for at least one input segment,
803 * and then allocate the rest to output segments (one for the current
804 * program, the rest to VCM). The valid range of the VCM cache size
805 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
808 assert(c
->devinfo
->vpm_size
);
809 int sector_size
= 16 * sizeof(uint32_t) * 8;
810 int vpm_size_in_sectors
= c
->devinfo
->vpm_size
/ sector_size
;
811 int half_vpm
= vpm_size_in_sectors
/ 2;
812 int vpm_output_sectors
= half_vpm
- prog_data
->vpm_input_size
;
813 int vpm_output_batches
= vpm_output_sectors
/ prog_data
->vpm_output_size
;
814 assert(vpm_output_batches
>= 2);
815 prog_data
->vcm_cache_size
= CLAMP(vpm_output_batches
- 1, 2, 4);
817 return v3d_return_qpu_insts(c
, final_assembly_size
);
821 v3d_set_fs_prog_data_inputs(struct v3d_compile
*c
,
822 struct v3d_fs_prog_data
*prog_data
)
824 prog_data
->base
.num_inputs
= c
->num_inputs
;
825 memcpy(prog_data
->input_slots
, c
->input_slots
,
826 c
->num_inputs
* sizeof(*c
->input_slots
));
828 STATIC_ASSERT(ARRAY_SIZE(prog_data
->flat_shade_flags
) >
829 (V3D_MAX_FS_INPUTS
- 1) / 24);
830 for (int i
= 0; i
< V3D_MAX_FS_INPUTS
; i
++) {
831 if (BITSET_TEST(c
->flat_shade_flags
, i
))
832 prog_data
->flat_shade_flags
[i
/ 24] |= 1 << (i
% 24);
834 if (BITSET_TEST(c
->noperspective_flags
, i
))
835 prog_data
->noperspective_flags
[i
/ 24] |= 1 << (i
% 24);
837 if (BITSET_TEST(c
->centroid_flags
, i
))
838 prog_data
->centroid_flags
[i
/ 24] |= 1 << (i
% 24);
843 v3d_fixup_fs_output_types(struct v3d_compile
*c
)
845 nir_foreach_variable(var
, &c
->s
->outputs
) {
848 switch (var
->data
.location
) {
849 case FRAG_RESULT_COLOR
:
852 case FRAG_RESULT_DATA0
:
853 case FRAG_RESULT_DATA1
:
854 case FRAG_RESULT_DATA2
:
855 case FRAG_RESULT_DATA3
:
856 mask
= 1 << (var
->data
.location
- FRAG_RESULT_DATA0
);
860 if (c
->fs_key
->int_color_rb
& mask
) {
862 glsl_vector_type(GLSL_TYPE_INT
,
863 glsl_get_components(var
->type
));
864 } else if (c
->fs_key
->uint_color_rb
& mask
) {
866 glsl_vector_type(GLSL_TYPE_UINT
,
867 glsl_get_components(var
->type
));
872 uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler
,
873 struct v3d_fs_key
*key
,
874 struct v3d_fs_prog_data
*prog_data
,
876 int program_id
, int variant_id
,
877 uint32_t *final_assembly_size
)
879 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
880 program_id
, variant_id
);
884 if (key
->int_color_rb
|| key
->uint_color_rb
)
885 v3d_fixup_fs_output_types(c
);
889 if (key
->light_twoside
)
890 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
892 if (key
->clamp_color
)
893 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
895 if (key
->alpha_test
) {
896 NIR_PASS_V(c
->s
, nir_lower_alpha_test
, key
->alpha_test_func
,
900 if (key
->base
.ucp_enables
)
901 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, key
->base
.ucp_enables
);
903 /* Note: FS input scalarizing must happen after
904 * nir_lower_two_sided_color, which only handles a vec4 at a time.
906 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
908 v3d_lower_nir_late(c
);
909 v3d_optimize_nir(c
->s
);
910 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
914 v3d_set_prog_data(c
, &prog_data
->base
);
915 v3d_set_fs_prog_data_inputs(c
, prog_data
);
916 prog_data
->writes_z
= (c
->s
->info
.outputs_written
&
917 (1 << FRAG_RESULT_DEPTH
));
918 prog_data
->discard
= (c
->s
->info
.fs
.uses_discard
||
919 c
->fs_key
->sample_alpha_to_coverage
);
920 prog_data
->uses_center_w
= c
->uses_center_w
;
922 return v3d_return_qpu_insts(c
, final_assembly_size
);
926 vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
)
928 if (qinst
->dst
.file
== QFILE_TEMP
)
929 c
->defs
[qinst
->dst
.index
] = NULL
;
931 assert(&qinst
->link
!= c
->cursor
.link
);
933 list_del(&qinst
->link
);
936 c
->live_intervals_valid
= false;
940 vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
)
945 while (reg.file == QFILE_TEMP &&
946 c->defs[reg.index] &&
947 (c->defs[reg.index]->op == QOP_MOV ||
948 c->defs[reg.index]->op == QOP_FMOV) &&
949 !c->defs[reg.index]->dst.pack &&
950 !c->defs[reg.index]->src[0].pack) {
951 reg = c->defs[reg.index]->src[0];
960 vir_compile_destroy(struct v3d_compile
*c
)
962 /* Defuse the assert that we aren't removing the cursor's instruction.
964 c
->cursor
.link
= NULL
;
966 vir_for_each_block(block
, c
) {
967 while (!list_empty(&block
->instructions
)) {
968 struct qinst
*qinst
=
969 list_first_entry(&block
->instructions
,
971 vir_remove_instruction(c
, qinst
);
979 vir_uniform(struct v3d_compile
*c
,
980 enum quniform_contents contents
,
983 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
984 if (c
->uniform_contents
[i
] == contents
&&
985 c
->uniform_data
[i
] == data
) {
986 return vir_reg(QFILE_UNIF
, i
);
990 uint32_t uniform
= c
->num_uniforms
++;
992 if (uniform
>= c
->uniform_array_size
) {
993 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
994 c
->uniform_array_size
* 2);
996 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
998 c
->uniform_array_size
);
999 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
1000 enum quniform_contents
,
1001 c
->uniform_array_size
);
1004 c
->uniform_contents
[uniform
] = contents
;
1005 c
->uniform_data
[uniform
] = data
;
1007 return vir_reg(QFILE_UNIF
, uniform
);
1011 vir_can_set_flags(struct v3d_compile
*c
, struct qinst
*inst
)
1013 if (c
->devinfo
->ver
>= 40 && (v3d_qpu_reads_vpm(&inst
->qpu
) ||
1014 v3d_qpu_uses_sfu(&inst
->qpu
))) {
1018 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
1019 (inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
&&
1020 inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
)) {
1028 vir_PF(struct v3d_compile
*c
, struct qreg src
, enum v3d_qpu_pf pf
)
1030 struct qinst
*last_inst
= NULL
;
1032 if (!list_empty(&c
->cur_block
->instructions
)) {
1033 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
1035 /* Can't stuff the PF into the last last inst if our cursor
1036 * isn't pointing after it.
1038 struct vir_cursor after_inst
= vir_after_inst(last_inst
);
1039 if (c
->cursor
.mode
!= after_inst
.mode
||
1040 c
->cursor
.link
!= after_inst
.link
)
1044 if (src
.file
!= QFILE_TEMP
||
1045 !c
->defs
[src
.index
] ||
1046 last_inst
!= c
->defs
[src
.index
] ||
1047 !vir_can_set_flags(c
, last_inst
)) {
1048 /* XXX: Make the MOV be the appropriate type */
1049 last_inst
= vir_MOV_dest(c
, vir_reg(QFILE_NULL
, 0), src
);
1052 vir_set_pf(last_inst
, pf
);
1055 #define OPTPASS(func) \
1057 bool stage_progress = func(c); \
1058 if (stage_progress) { \
1060 if (print_opt_debug) { \
1062 "VIR opt pass %2d: %s progress\n", \
1065 /*XXX vir_validate(c);*/ \
1070 vir_optimize(struct v3d_compile
*c
)
1072 bool print_opt_debug
= false;
1076 bool progress
= false;
1078 OPTPASS(vir_opt_copy_propagate
);
1079 OPTPASS(vir_opt_dead_code
);
1080 OPTPASS(vir_opt_small_immediates
);
1090 vir_get_stage_name(struct v3d_compile
*c
)
1092 if (c
->vs_key
&& c
->vs_key
->is_coord
)
1093 return "MESA_SHADER_COORD";
1095 return gl_shader_stage_name(c
->s
->info
.stage
);