2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/macros.h"
27 #include "broadcom/common/v3d_device_info.h"
28 #include "qpu_instr.h"
31 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
32 /* Using the GNU statement expression extension */
33 #define QPU_SET_FIELD(value, field) \
35 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
36 assert((fieldval & ~ field ## _MASK) == 0); \
37 fieldval & field ## _MASK; \
40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
42 #define QPU_UPDATE_FIELD(inst, value, field) \
43 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
46 #define VC5_QPU_OP_MUL_SHIFT 58
47 #define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58)
49 #define VC5_QPU_SIG_SHIFT 53
50 #define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
52 #define VC5_QPU_COND_SHIFT 46
53 #define VC5_QPU_COND_MASK QPU_MASK(52, 46)
54 #define VC5_QPU_COND_SIG_MAGIC_ADDR (1 << 6)
56 #define VC5_QPU_MM QPU_MASK(45, 45)
57 #define VC5_QPU_MA QPU_MASK(44, 44)
59 #define V3D_QPU_WADDR_M_SHIFT 38
60 #define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38)
62 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35
63 #define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35)
65 #define V3D_QPU_WADDR_A_SHIFT 32
66 #define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32)
68 #define VC5_QPU_BRANCH_COND_SHIFT 32
69 #define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32)
71 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24
72 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24)
74 #define VC5_QPU_OP_ADD_SHIFT 24
75 #define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24)
77 #define VC5_QPU_MUL_B_SHIFT 21
78 #define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21)
80 #define VC5_QPU_BRANCH_MSFIGN_SHIFT 21
81 #define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21)
83 #define VC5_QPU_MUL_A_SHIFT 18
84 #define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18)
86 #define VC5_QPU_ADD_B_SHIFT 15
87 #define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15)
89 #define VC5_QPU_BRANCH_BDU_SHIFT 15
90 #define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15)
92 #define VC5_QPU_BRANCH_UB QPU_MASK(14, 14)
94 #define VC5_QPU_ADD_A_SHIFT 12
95 #define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12)
97 #define VC5_QPU_BRANCH_BDI_SHIFT 12
98 #define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12)
100 #define VC5_QPU_RADDR_A_SHIFT 6
101 #define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6)
103 #define VC5_QPU_RADDR_B_SHIFT 0
104 #define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0)
106 #define THRSW .thrsw = true
107 #define LDUNIF .ldunif = true
108 #define LDUNIFRF .ldunifrf = true
109 #define LDUNIFA .ldunifa = true
110 #define LDUNIFARF .ldunifarf = true
111 #define LDTMU .ldtmu = true
112 #define LDVARY .ldvary = true
113 #define LDVPM .ldvpm = true
114 #define SMIMM .small_imm = true
115 #define LDTLB .ldtlb = true
116 #define LDTLBU .ldtlbu = true
117 #define UCB .ucb = true
118 #define ROT .rotate = true
119 #define WRTMUC .wrtmuc = true
121 static const struct v3d_qpu_sig v33_sig_map
[] = {
126 [3] = { THRSW
, LDUNIF
},
128 [5] = { THRSW
, LDTMU
, },
129 [6] = { LDTMU
, LDUNIF
},
130 [7] = { THRSW
, LDTMU
, LDUNIF
},
132 [9] = { THRSW
, LDVARY
, },
133 [10] = { LDVARY
, LDUNIF
},
134 [11] = { THRSW
, LDVARY
, LDUNIF
},
135 [12] = { LDVARY
, LDTMU
, },
136 [13] = { THRSW
, LDVARY
, LDTMU
, },
137 [14] = { SMIMM
, LDVARY
, },
145 [25] = { THRSW
, LDVPM
, },
146 [26] = { LDVPM
, LDUNIF
},
147 [27] = { THRSW
, LDVPM
, LDUNIF
},
148 [28] = { LDVPM
, LDTMU
, },
149 [29] = { THRSW
, LDVPM
, LDTMU
, },
150 [30] = { SMIMM
, LDVPM
, },
154 static const struct v3d_qpu_sig v40_sig_map
[] = {
159 [3] = { THRSW
, LDUNIF
},
161 [5] = { THRSW
, LDTMU
, },
162 [6] = { LDTMU
, LDUNIF
},
163 [7] = { THRSW
, LDTMU
, LDUNIF
},
165 [9] = { THRSW
, LDVARY
, },
166 [10] = { LDVARY
, LDUNIF
},
167 [11] = { THRSW
, LDVARY
, LDUNIF
},
169 [14] = { SMIMM
, LDVARY
, },
174 [19] = { THRSW
, WRTMUC
},
175 [20] = { LDVARY
, WRTMUC
},
176 [21] = { THRSW
, LDVARY
, WRTMUC
},
180 [31] = { SMIMM
, LDTMU
, },
183 static const struct v3d_qpu_sig v41_sig_map
[] = {
188 [3] = { THRSW
, LDUNIF
},
190 [5] = { THRSW
, LDTMU
, },
191 [6] = { LDTMU
, LDUNIF
},
192 [7] = { THRSW
, LDTMU
, LDUNIF
},
194 [9] = { THRSW
, LDVARY
, },
195 [10] = { LDVARY
, LDUNIF
},
196 [11] = { THRSW
, LDVARY
, LDUNIF
},
198 [13] = { THRSW
, LDUNIFRF
},
199 [14] = { SMIMM
, LDVARY
, },
204 [19] = { THRSW
, WRTMUC
},
205 [20] = { LDVARY
, WRTMUC
},
206 [21] = { THRSW
, LDVARY
, WRTMUC
},
211 [25] = { LDUNIFARF
},
212 [31] = { SMIMM
, LDTMU
, },
216 v3d_qpu_sig_unpack(const struct v3d_device_info
*devinfo
,
218 struct v3d_qpu_sig
*sig
)
220 if (packed_sig
>= ARRAY_SIZE(v33_sig_map
))
223 if (devinfo
->ver
>= 41)
224 *sig
= v41_sig_map
[packed_sig
];
225 else if (devinfo
->ver
== 40)
226 *sig
= v40_sig_map
[packed_sig
];
228 *sig
= v33_sig_map
[packed_sig
];
230 /* Signals with zeroed unpacked contents after element 0 are reserved. */
231 return (packed_sig
== 0 ||
232 memcmp(sig
, &v33_sig_map
[0], sizeof(*sig
)) != 0);
236 v3d_qpu_sig_pack(const struct v3d_device_info
*devinfo
,
237 const struct v3d_qpu_sig
*sig
,
238 uint32_t *packed_sig
)
240 static const struct v3d_qpu_sig
*map
;
242 if (devinfo
->ver
>= 41)
244 else if (devinfo
->ver
== 40)
249 for (int i
= 0; i
< ARRAY_SIZE(v33_sig_map
); i
++) {
250 if (memcmp(&map
[i
], sig
, sizeof(*sig
)) == 0) {
260 v3d_qpu_flags_unpack(const struct v3d_device_info
*devinfo
,
261 uint32_t packed_cond
,
262 struct v3d_qpu_flags
*cond
)
264 static const enum v3d_qpu_cond cond_map
[4] = {
265 [0] = V3D_QPU_COND_IFA
,
266 [1] = V3D_QPU_COND_IFB
,
267 [2] = V3D_QPU_COND_IFNA
,
268 [3] = V3D_QPU_COND_IFNB
,
271 cond
->ac
= V3D_QPU_COND_NONE
;
272 cond
->mc
= V3D_QPU_COND_NONE
;
273 cond
->apf
= V3D_QPU_PF_NONE
;
274 cond
->mpf
= V3D_QPU_PF_NONE
;
275 cond
->auf
= V3D_QPU_UF_NONE
;
276 cond
->muf
= V3D_QPU_UF_NONE
;
278 if (packed_cond
== 0) {
280 } else if (packed_cond
>> 2 == 0) {
281 cond
->apf
= packed_cond
& 0x3;
282 } else if (packed_cond
>> 4 == 0) {
283 cond
->auf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
284 } else if (packed_cond
== 0x10) {
286 } else if (packed_cond
>> 2 == 0x4) {
287 cond
->mpf
= packed_cond
& 0x3;
288 } else if (packed_cond
>> 4 == 0x1) {
289 cond
->muf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
290 } else if (packed_cond
>> 4 == 0x2) {
291 cond
->ac
= ((packed_cond
>> 2) & 0x3) + V3D_QPU_COND_IFA
;
292 cond
->mpf
= packed_cond
& 0x3;
293 } else if (packed_cond
>> 4 == 0x3) {
294 cond
->mc
= ((packed_cond
>> 2) & 0x3) + V3D_QPU_COND_IFA
;
295 cond
->apf
= packed_cond
& 0x3;
296 } else if (packed_cond
>> 6) {
297 cond
->mc
= cond_map
[(packed_cond
>> 4) & 0x3];
298 if (((packed_cond
>> 2) & 0x3) == 0) {
299 cond
->ac
= cond_map
[packed_cond
& 0x3];
301 cond
->auf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
309 v3d_qpu_flags_pack(const struct v3d_device_info
*devinfo
,
310 const struct v3d_qpu_flags
*cond
,
311 uint32_t *packed_cond
)
319 static const struct {
320 uint8_t flags_present
;
329 { AC
| MPF
, (1 << 5) },
330 { MC
, (1 << 5) | (1 << 4) },
331 { MC
| APF
, (1 << 5) | (1 << 4) },
332 { MC
| AC
, (1 << 6) },
333 { MC
| AUF
, (1 << 6) },
336 uint8_t flags_present
= 0;
337 if (cond
->ac
!= V3D_QPU_COND_NONE
)
339 if (cond
->mc
!= V3D_QPU_COND_NONE
)
341 if (cond
->apf
!= V3D_QPU_PF_NONE
)
342 flags_present
|= APF
;
343 if (cond
->mpf
!= V3D_QPU_PF_NONE
)
344 flags_present
|= MPF
;
345 if (cond
->auf
!= V3D_QPU_UF_NONE
)
346 flags_present
|= AUF
;
347 if (cond
->muf
!= V3D_QPU_UF_NONE
)
348 flags_present
|= MUF
;
350 for (int i
= 0; i
< ARRAY_SIZE(flags_table
); i
++) {
351 if (flags_table
[i
].flags_present
!= flags_present
)
354 *packed_cond
= flags_table
[i
].bits
;
356 *packed_cond
|= cond
->apf
;
357 *packed_cond
|= cond
->mpf
;
359 if (flags_present
& AUF
)
360 *packed_cond
|= cond
->auf
- V3D_QPU_UF_ANDZ
+ 4;
361 if (flags_present
& MUF
)
362 *packed_cond
|= cond
->muf
- V3D_QPU_UF_ANDZ
+ 4;
364 if (flags_present
& AC
)
365 *packed_cond
|= (cond
->ac
- V3D_QPU_COND_IFA
) << 2;
367 if (flags_present
& MC
) {
368 if (*packed_cond
& (1 << 6))
369 *packed_cond
|= (cond
->mc
-
370 V3D_QPU_COND_IFA
) << 4;
372 *packed_cond
|= (cond
->mc
-
373 V3D_QPU_COND_IFA
) << 2;
382 /* Make a mapping of the table of opcodes in the spec. The opcode is
383 * determined by a combination of the opcode field, and in the case of 0 or
384 * 1-arg opcodes, the mux_b field as well.
386 #define MUX_MASK(bot, top) (((1 << (top + 1)) - 1) - ((1 << (bot)) - 1))
387 #define ANYMUX MUX_MASK(0, 7)
390 uint8_t opcode_first
;
395 /* 0 if it's the same across V3D versions, or a specific V3D version. */
399 static const struct opcode_desc add_ops
[] = {
400 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
401 { 0, 47, ANYMUX
, ANYMUX
, V3D_QPU_A_FADD
},
402 { 0, 47, ANYMUX
, ANYMUX
, V3D_QPU_A_FADDNF
},
403 { 53, 55, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
404 { 56, 56, ANYMUX
, ANYMUX
, V3D_QPU_A_ADD
},
405 { 57, 59, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
406 { 60, 60, ANYMUX
, ANYMUX
, V3D_QPU_A_SUB
},
407 { 61, 63, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
408 { 64, 111, ANYMUX
, ANYMUX
, V3D_QPU_A_FSUB
},
409 { 120, 120, ANYMUX
, ANYMUX
, V3D_QPU_A_MIN
},
410 { 121, 121, ANYMUX
, ANYMUX
, V3D_QPU_A_MAX
},
411 { 122, 122, ANYMUX
, ANYMUX
, V3D_QPU_A_UMIN
},
412 { 123, 123, ANYMUX
, ANYMUX
, V3D_QPU_A_UMAX
},
413 { 124, 124, ANYMUX
, ANYMUX
, V3D_QPU_A_SHL
},
414 { 125, 125, ANYMUX
, ANYMUX
, V3D_QPU_A_SHR
},
415 { 126, 126, ANYMUX
, ANYMUX
, V3D_QPU_A_ASR
},
416 { 127, 127, ANYMUX
, ANYMUX
, V3D_QPU_A_ROR
},
417 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
418 { 128, 175, ANYMUX
, ANYMUX
, V3D_QPU_A_FMIN
},
419 { 128, 175, ANYMUX
, ANYMUX
, V3D_QPU_A_FMAX
},
420 { 176, 180, ANYMUX
, ANYMUX
, V3D_QPU_A_VFMIN
},
422 { 181, 181, ANYMUX
, ANYMUX
, V3D_QPU_A_AND
},
423 { 182, 182, ANYMUX
, ANYMUX
, V3D_QPU_A_OR
},
424 { 183, 183, ANYMUX
, ANYMUX
, V3D_QPU_A_XOR
},
426 { 184, 184, ANYMUX
, ANYMUX
, V3D_QPU_A_VADD
},
427 { 185, 185, ANYMUX
, ANYMUX
, V3D_QPU_A_VSUB
},
428 { 186, 186, 1 << 0, ANYMUX
, V3D_QPU_A_NOT
},
429 { 186, 186, 1 << 1, ANYMUX
, V3D_QPU_A_NEG
},
430 { 186, 186, 1 << 2, ANYMUX
, V3D_QPU_A_FLAPUSH
},
431 { 186, 186, 1 << 3, ANYMUX
, V3D_QPU_A_FLBPUSH
},
432 { 186, 186, 1 << 4, ANYMUX
, V3D_QPU_A_FLBPOP
},
433 { 186, 186, 1 << 6, ANYMUX
, V3D_QPU_A_SETMSF
},
434 { 186, 186, 1 << 7, ANYMUX
, V3D_QPU_A_SETREVF
},
435 { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP
, 0 },
436 { 187, 187, 1 << 0, 1 << 1, V3D_QPU_A_TIDX
},
437 { 187, 187, 1 << 0, 1 << 2, V3D_QPU_A_EIDX
},
438 { 187, 187, 1 << 0, 1 << 3, V3D_QPU_A_LR
},
439 { 187, 187, 1 << 0, 1 << 4, V3D_QPU_A_VFLA
},
440 { 187, 187, 1 << 0, 1 << 5, V3D_QPU_A_VFLNA
},
441 { 187, 187, 1 << 0, 1 << 6, V3D_QPU_A_VFLB
},
442 { 187, 187, 1 << 0, 1 << 7, V3D_QPU_A_VFLNB
},
444 { 187, 187, 1 << 1, MUX_MASK(0, 2), V3D_QPU_A_FXCD
},
445 { 187, 187, 1 << 1, 1 << 3, V3D_QPU_A_XCD
},
446 { 187, 187, 1 << 1, MUX_MASK(4, 6), V3D_QPU_A_FYCD
},
447 { 187, 187, 1 << 1, 1 << 7, V3D_QPU_A_YCD
},
449 { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF
},
450 { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF
},
451 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT
},
452 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT
},
453 { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT
},
455 { 187, 187, 1 << 3, ANYMUX
, V3D_QPU_A_VPMSETUP
},
457 /* FIXME: MORE COMPLICATED */
458 /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
460 { 192, 239, ANYMUX
, ANYMUX
, V3D_QPU_A_FCMP
},
461 { 240, 244, ANYMUX
, ANYMUX
, V3D_QPU_A_VFMAX
},
463 { 245, 245, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FROUND
},
464 { 245, 245, 1 << 3, ANYMUX
, V3D_QPU_A_FTOIN
},
465 { 245, 245, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FTRUNC
},
466 { 245, 245, 1 << 7, ANYMUX
, V3D_QPU_A_FTOIZ
},
467 { 246, 246, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FFLOOR
},
468 { 246, 246, 1 << 3, ANYMUX
, V3D_QPU_A_FTOUZ
},
469 { 246, 246, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FCEIL
},
470 { 246, 246, 1 << 7, ANYMUX
, V3D_QPU_A_FTOC
},
472 { 247, 247, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FDX
},
473 { 247, 247, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FDY
},
475 /* The stvpms are distinguished by the waddr field. */
476 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMV
},
477 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMD
},
478 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMP
},
480 { 252, 252, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_ITOF
},
481 { 252, 252, 1 << 3, ANYMUX
, V3D_QPU_A_CLZ
},
482 { 252, 252, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_UTOF
},
485 static const struct opcode_desc mul_ops
[] = {
486 { 1, 1, ANYMUX
, ANYMUX
, V3D_QPU_M_ADD
},
487 { 2, 2, ANYMUX
, ANYMUX
, V3D_QPU_M_SUB
},
488 { 3, 3, ANYMUX
, ANYMUX
, V3D_QPU_M_UMUL24
},
489 { 4, 8, ANYMUX
, ANYMUX
, V3D_QPU_M_VFMUL
},
490 { 9, 9, ANYMUX
, ANYMUX
, V3D_QPU_M_SMUL24
},
491 { 10, 10, ANYMUX
, ANYMUX
, V3D_QPU_M_MULTOP
},
492 { 14, 14, ANYMUX
, ANYMUX
, V3D_QPU_M_FMOV
},
493 { 15, 15, MUX_MASK(0, 3), ANYMUX
, V3D_QPU_M_FMOV
},
494 { 15, 15, 1 << 4, 1 << 0, V3D_QPU_M_NOP
, 0 },
495 { 15, 15, 1 << 7, ANYMUX
, V3D_QPU_M_MOV
},
496 { 16, 63, ANYMUX
, ANYMUX
, V3D_QPU_M_FMUL
},
499 static const struct opcode_desc
*
500 lookup_opcode(const struct opcode_desc
*opcodes
, size_t num_opcodes
,
501 uint32_t opcode
, uint32_t mux_a
, uint32_t mux_b
)
503 for (int i
= 0; i
< num_opcodes
; i
++) {
504 const struct opcode_desc
*op_desc
= &opcodes
[i
];
506 if (opcode
< op_desc
->opcode_first
||
507 opcode
> op_desc
->opcode_last
)
510 if (!(op_desc
->mux_b_mask
& (1 << mux_b
)))
513 if (!(op_desc
->mux_a_mask
& (1 << mux_a
)))
523 v3d_qpu_float32_unpack_unpack(uint32_t packed
,
524 enum v3d_qpu_input_unpack
*unpacked
)
528 *unpacked
= V3D_QPU_UNPACK_ABS
;
531 *unpacked
= V3D_QPU_UNPACK_NONE
;
534 *unpacked
= V3D_QPU_UNPACK_L
;
537 *unpacked
= V3D_QPU_UNPACK_H
;
545 v3d_qpu_float32_unpack_pack(enum v3d_qpu_input_unpack unpacked
,
549 case V3D_QPU_UNPACK_ABS
:
552 case V3D_QPU_UNPACK_NONE
:
555 case V3D_QPU_UNPACK_L
:
558 case V3D_QPU_UNPACK_H
:
567 v3d_qpu_float16_unpack_unpack(uint32_t packed
,
568 enum v3d_qpu_input_unpack
*unpacked
)
572 *unpacked
= V3D_QPU_UNPACK_NONE
;
575 *unpacked
= V3D_QPU_UNPACK_REPLICATE_32F_16
;
578 *unpacked
= V3D_QPU_UNPACK_REPLICATE_L_16
;
581 *unpacked
= V3D_QPU_UNPACK_REPLICATE_H_16
;
584 *unpacked
= V3D_QPU_UNPACK_SWAP_16
;
592 v3d_qpu_float16_unpack_pack(enum v3d_qpu_input_unpack unpacked
,
596 case V3D_QPU_UNPACK_NONE
:
599 case V3D_QPU_UNPACK_REPLICATE_32F_16
:
602 case V3D_QPU_UNPACK_REPLICATE_L_16
:
605 case V3D_QPU_UNPACK_REPLICATE_H_16
:
608 case V3D_QPU_UNPACK_SWAP_16
:
617 v3d_qpu_float32_pack_pack(enum v3d_qpu_input_unpack unpacked
,
621 case V3D_QPU_PACK_NONE
:
636 v3d_qpu_add_unpack(const struct v3d_device_info
*devinfo
, uint64_t packed_inst
,
637 struct v3d_qpu_instr
*instr
)
639 uint32_t op
= QPU_GET_FIELD(packed_inst
, VC5_QPU_OP_ADD
);
640 uint32_t mux_a
= QPU_GET_FIELD(packed_inst
, VC5_QPU_ADD_A
);
641 uint32_t mux_b
= QPU_GET_FIELD(packed_inst
, VC5_QPU_ADD_B
);
642 uint32_t waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_A
);
644 uint32_t map_op
= op
;
645 /* Some big clusters of opcodes are replicated with unpack
648 if (map_op
>= 249 && map_op
<= 251)
649 map_op
= (map_op
- 249 + 245);
650 if (map_op
>= 253 && map_op
<= 255)
651 map_op
= (map_op
- 253 + 245);
653 const struct opcode_desc
*desc
=
654 lookup_opcode(add_ops
, ARRAY_SIZE(add_ops
),
655 map_op
, mux_a
, mux_b
);
659 instr
->alu
.add
.op
= desc
->op
;
661 /* FADD/FADDNF and FMIN/FMAX are determined by the orders of the
664 if (((op
>> 2) & 3) * 8 + mux_a
> (op
& 3) * 8 + mux_b
) {
665 if (instr
->alu
.add
.op
== V3D_QPU_A_FMIN
)
666 instr
->alu
.add
.op
= V3D_QPU_A_FMAX
;
667 if (instr
->alu
.add
.op
== V3D_QPU_A_FADD
)
668 instr
->alu
.add
.op
= V3D_QPU_A_FADDNF
;
671 /* Some QPU ops require a bit more than just basic opcode and mux a/b
672 * comparisons to distinguish them.
674 switch (instr
->alu
.add
.op
) {
675 case V3D_QPU_A_STVPMV
:
676 case V3D_QPU_A_STVPMD
:
677 case V3D_QPU_A_STVPMP
:
680 instr
->alu
.add
.op
= V3D_QPU_A_STVPMV
;
683 instr
->alu
.add
.op
= V3D_QPU_A_STVPMD
;
686 instr
->alu
.add
.op
= V3D_QPU_A_STVPMP
;
696 switch (instr
->alu
.add
.op
) {
698 case V3D_QPU_A_FADDNF
:
703 instr
->alu
.add
.output_pack
= (op
>> 4) & 0x3;
705 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
706 &instr
->alu
.add
.a_unpack
)) {
710 if (!v3d_qpu_float32_unpack_unpack((op
>> 0) & 0x3,
711 &instr
->alu
.add
.b_unpack
)) {
716 case V3D_QPU_A_FFLOOR
:
717 case V3D_QPU_A_FROUND
:
718 case V3D_QPU_A_FTRUNC
:
719 case V3D_QPU_A_FCEIL
:
722 instr
->alu
.add
.output_pack
= mux_b
& 0x3;
724 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
725 &instr
->alu
.add
.a_unpack
)) {
730 case V3D_QPU_A_FTOIN
:
731 case V3D_QPU_A_FTOIZ
:
732 case V3D_QPU_A_FTOUZ
:
734 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
736 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
737 &instr
->alu
.add
.a_unpack
)) {
742 case V3D_QPU_A_VFMIN
:
743 case V3D_QPU_A_VFMAX
:
744 if (!v3d_qpu_float16_unpack_unpack(op
& 0x7,
745 &instr
->alu
.add
.a_unpack
)) {
749 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
750 instr
->alu
.add
.b_unpack
= V3D_QPU_UNPACK_NONE
;
754 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
755 instr
->alu
.add
.a_unpack
= V3D_QPU_UNPACK_NONE
;
756 instr
->alu
.add
.b_unpack
= V3D_QPU_UNPACK_NONE
;
760 instr
->alu
.add
.a
= mux_a
;
761 instr
->alu
.add
.b
= mux_b
;
762 instr
->alu
.add
.waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_A
);
763 instr
->alu
.add
.magic_write
= packed_inst
& VC5_QPU_MA
;
769 v3d_qpu_mul_unpack(const struct v3d_device_info
*devinfo
, uint64_t packed_inst
,
770 struct v3d_qpu_instr
*instr
)
772 uint32_t op
= QPU_GET_FIELD(packed_inst
, VC5_QPU_OP_MUL
);
773 uint32_t mux_a
= QPU_GET_FIELD(packed_inst
, VC5_QPU_MUL_A
);
774 uint32_t mux_b
= QPU_GET_FIELD(packed_inst
, VC5_QPU_MUL_B
);
777 const struct opcode_desc
*desc
=
778 lookup_opcode(mul_ops
, ARRAY_SIZE(mul_ops
),
783 instr
->alu
.mul
.op
= desc
->op
;
786 switch (instr
->alu
.mul
.op
) {
788 instr
->alu
.mul
.output_pack
= ((op
>> 4) & 0x3) - 1;
790 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
791 &instr
->alu
.mul
.a_unpack
)) {
795 if (!v3d_qpu_float32_unpack_unpack((op
>> 0) & 0x3,
796 &instr
->alu
.mul
.b_unpack
)) {
803 instr
->alu
.mul
.output_pack
= (((op
& 1) << 1) +
806 if (!v3d_qpu_float32_unpack_unpack(mux_b
& 0x3,
807 &instr
->alu
.mul
.a_unpack
)) {
813 case V3D_QPU_M_VFMUL
:
814 instr
->alu
.mul
.output_pack
= V3D_QPU_PACK_NONE
;
816 if (!v3d_qpu_float16_unpack_unpack(((op
& 0x7) - 4) & 7,
817 &instr
->alu
.mul
.a_unpack
)) {
821 instr
->alu
.mul
.b_unpack
= V3D_QPU_UNPACK_NONE
;
826 instr
->alu
.mul
.output_pack
= V3D_QPU_PACK_NONE
;
827 instr
->alu
.mul
.a_unpack
= V3D_QPU_UNPACK_NONE
;
828 instr
->alu
.mul
.b_unpack
= V3D_QPU_UNPACK_NONE
;
832 instr
->alu
.mul
.a
= mux_a
;
833 instr
->alu
.mul
.b
= mux_b
;
834 instr
->alu
.mul
.waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_M
);
835 instr
->alu
.mul
.magic_write
= packed_inst
& VC5_QPU_MM
;
841 v3d_qpu_add_pack(const struct v3d_device_info
*devinfo
,
842 const struct v3d_qpu_instr
*instr
, uint64_t *packed_instr
)
844 uint32_t waddr
= instr
->alu
.add
.waddr
;
845 uint32_t mux_a
= instr
->alu
.add
.a
;
846 uint32_t mux_b
= instr
->alu
.add
.b
;
847 int nsrc
= v3d_qpu_add_op_num_src(instr
->alu
.add
.op
);
848 const struct opcode_desc
*desc
;
851 for (desc
= add_ops
; desc
!= &add_ops
[ARRAY_SIZE(add_ops
)];
853 if (desc
->op
== instr
->alu
.add
.op
)
856 if (desc
== &add_ops
[ARRAY_SIZE(add_ops
)])
859 opcode
= desc
->opcode_first
;
861 /* If an operation doesn't use an arg, its mux values may be used to
862 * identify the operation type.
865 mux_b
= ffs(desc
->mux_b_mask
) - 1;
868 mux_a
= ffs(desc
->mux_a_mask
) - 1;
870 switch (instr
->alu
.add
.op
) {
871 case V3D_QPU_A_STVPMV
:
874 case V3D_QPU_A_STVPMD
:
877 case V3D_QPU_A_STVPMP
:
884 switch (instr
->alu
.add
.op
) {
886 case V3D_QPU_A_FADDNF
:
890 case V3D_QPU_A_FCMP
: {
891 uint32_t output_pack
;
895 if (!v3d_qpu_float32_pack_pack(instr
->alu
.add
.output_pack
,
899 opcode
|= output_pack
<< 4;
901 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
906 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.b_unpack
,
911 /* These operations with commutative operands are
912 * distinguished by which order their operands come in.
914 bool ordering
= a_unpack
* 8 + mux_a
> b_unpack
* 8 + mux_b
;
915 if (((instr
->alu
.add
.op
== V3D_QPU_A_FMIN
||
916 instr
->alu
.add
.op
== V3D_QPU_A_FADD
) && ordering
) ||
917 ((instr
->alu
.add
.op
== V3D_QPU_A_FMAX
||
918 instr
->alu
.add
.op
== V3D_QPU_A_FADDNF
) && !ordering
)) {
930 opcode
|= a_unpack
<< 2;
931 opcode
|= b_unpack
<< 0;
935 case V3D_QPU_A_FFLOOR
:
936 case V3D_QPU_A_FROUND
:
937 case V3D_QPU_A_FTRUNC
:
938 case V3D_QPU_A_FCEIL
:
940 case V3D_QPU_A_FDY
: {
943 if (!v3d_qpu_float32_pack_pack(instr
->alu
.add
.output_pack
,
949 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
955 opcode
|= packed
<< 2;
959 case V3D_QPU_A_FTOIN
:
960 case V3D_QPU_A_FTOIZ
:
961 case V3D_QPU_A_FTOUZ
:
963 if (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
)
967 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
973 opcode
|= packed
<< 2;
977 case V3D_QPU_A_VFMIN
:
978 case V3D_QPU_A_VFMAX
:
979 if (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
980 instr
->alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
) {
984 if (!v3d_qpu_float16_unpack_pack(instr
->alu
.add
.a_unpack
,
992 if (instr
->alu
.add
.op
!= V3D_QPU_A_NOP
&&
993 (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
994 instr
->alu
.add
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
995 instr
->alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
)) {
1001 *packed_instr
|= QPU_SET_FIELD(mux_a
, VC5_QPU_ADD_A
);
1002 *packed_instr
|= QPU_SET_FIELD(mux_b
, VC5_QPU_ADD_B
);
1003 *packed_instr
|= QPU_SET_FIELD(opcode
, VC5_QPU_OP_ADD
);
1004 *packed_instr
|= QPU_SET_FIELD(waddr
, V3D_QPU_WADDR_A
);
1005 if (instr
->alu
.add
.magic_write
)
1006 *packed_instr
|= VC5_QPU_MA
;
1012 v3d_qpu_mul_pack(const struct v3d_device_info
*devinfo
,
1013 const struct v3d_qpu_instr
*instr
, uint64_t *packed_instr
)
1015 uint32_t mux_a
= instr
->alu
.mul
.a
;
1016 uint32_t mux_b
= instr
->alu
.mul
.b
;
1017 int nsrc
= v3d_qpu_mul_op_num_src(instr
->alu
.mul
.op
);
1018 const struct opcode_desc
*desc
;
1020 for (desc
= mul_ops
; desc
!= &mul_ops
[ARRAY_SIZE(mul_ops
)];
1022 if (desc
->op
== instr
->alu
.mul
.op
)
1025 if (desc
== &mul_ops
[ARRAY_SIZE(mul_ops
)])
1028 uint32_t opcode
= desc
->opcode_first
;
1030 /* Some opcodes have a single valid value for their mux a/b, so set
1031 * that here. If mux a/b determine packing, it will be set below.
1034 mux_b
= ffs(desc
->mux_b_mask
) - 1;
1037 mux_a
= ffs(desc
->mux_a_mask
) - 1;
1039 switch (instr
->alu
.mul
.op
) {
1040 case V3D_QPU_M_FMUL
: {
1043 if (!v3d_qpu_float32_pack_pack(instr
->alu
.mul
.output_pack
,
1047 /* No need for a +1 because desc->opcode_first has a 1 in this
1050 opcode
+= packed
<< 4;
1052 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.a_unpack
,
1056 opcode
|= packed
<< 2;
1058 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.b_unpack
,
1062 opcode
|= packed
<< 0;
1066 case V3D_QPU_M_FMOV
: {
1069 if (!v3d_qpu_float32_pack_pack(instr
->alu
.mul
.output_pack
,
1073 opcode
|= (packed
>> 1) & 1;
1074 mux_b
= (packed
& 1) << 2;
1076 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.a_unpack
,
1084 case V3D_QPU_M_VFMUL
: {
1087 if (instr
->alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
)
1090 if (!v3d_qpu_float16_unpack_pack(instr
->alu
.mul
.a_unpack
,
1094 if (instr
->alu
.mul
.a_unpack
== V3D_QPU_UNPACK_SWAP_16
)
1097 opcode
|= (packed
+ 4) & 7;
1099 if (instr
->alu
.mul
.b_unpack
!= V3D_QPU_UNPACK_NONE
)
1109 *packed_instr
|= QPU_SET_FIELD(mux_a
, VC5_QPU_MUL_A
);
1110 *packed_instr
|= QPU_SET_FIELD(mux_b
, VC5_QPU_MUL_B
);
1112 *packed_instr
|= QPU_SET_FIELD(opcode
, VC5_QPU_OP_MUL
);
1113 *packed_instr
|= QPU_SET_FIELD(instr
->alu
.mul
.waddr
, V3D_QPU_WADDR_M
);
1114 if (instr
->alu
.mul
.magic_write
)
1115 *packed_instr
|= VC5_QPU_MM
;
1121 v3d_qpu_instr_unpack_alu(const struct v3d_device_info
*devinfo
,
1122 uint64_t packed_instr
,
1123 struct v3d_qpu_instr
*instr
)
1125 instr
->type
= V3D_QPU_INSTR_TYPE_ALU
;
1127 if (!v3d_qpu_sig_unpack(devinfo
,
1128 QPU_GET_FIELD(packed_instr
, VC5_QPU_SIG
),
1132 uint32_t packed_cond
= QPU_GET_FIELD(packed_instr
, VC5_QPU_COND
);
1133 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
)) {
1134 instr
->sig_addr
= packed_cond
& ~VC5_QPU_COND_SIG_MAGIC_ADDR
;
1135 instr
->sig_magic
= packed_cond
& VC5_QPU_COND_SIG_MAGIC_ADDR
;
1137 instr
->flags
.ac
= V3D_QPU_COND_NONE
;
1138 instr
->flags
.mc
= V3D_QPU_COND_NONE
;
1139 instr
->flags
.apf
= V3D_QPU_PF_NONE
;
1140 instr
->flags
.mpf
= V3D_QPU_PF_NONE
;
1141 instr
->flags
.auf
= V3D_QPU_UF_NONE
;
1142 instr
->flags
.muf
= V3D_QPU_UF_NONE
;
1144 if (!v3d_qpu_flags_unpack(devinfo
, packed_cond
, &instr
->flags
))
1148 instr
->raddr_a
= QPU_GET_FIELD(packed_instr
, VC5_QPU_RADDR_A
);
1149 instr
->raddr_b
= QPU_GET_FIELD(packed_instr
, VC5_QPU_RADDR_B
);
1151 if (!v3d_qpu_add_unpack(devinfo
, packed_instr
, instr
))
1154 if (!v3d_qpu_mul_unpack(devinfo
, packed_instr
, instr
))
1161 v3d_qpu_instr_unpack_branch(const struct v3d_device_info
*devinfo
,
1162 uint64_t packed_instr
,
1163 struct v3d_qpu_instr
*instr
)
1165 instr
->type
= V3D_QPU_INSTR_TYPE_BRANCH
;
1167 uint32_t cond
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_COND
);
1169 instr
->branch
.cond
= V3D_QPU_BRANCH_COND_ALWAYS
;
1170 else if (V3D_QPU_BRANCH_COND_A0
+ (cond
- 2) <=
1171 V3D_QPU_BRANCH_COND_ALLNA
)
1172 instr
->branch
.cond
= V3D_QPU_BRANCH_COND_A0
+ (cond
- 2);
1176 uint32_t msfign
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_MSFIGN
);
1179 instr
->branch
.msfign
= msfign
;
1181 instr
->branch
.bdi
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_BDI
);
1183 instr
->branch
.ub
= packed_instr
& VC5_QPU_BRANCH_UB
;
1184 if (instr
->branch
.ub
) {
1185 instr
->branch
.bdu
= QPU_GET_FIELD(packed_instr
,
1186 VC5_QPU_BRANCH_BDU
);
1189 instr
->branch
.raddr_a
= QPU_GET_FIELD(packed_instr
,
1192 instr
->branch
.offset
= 0;
1194 instr
->branch
.offset
+=
1195 QPU_GET_FIELD(packed_instr
,
1196 VC5_QPU_BRANCH_ADDR_LOW
) << 3;
1198 instr
->branch
.offset
+=
1199 QPU_GET_FIELD(packed_instr
,
1200 VC5_QPU_BRANCH_ADDR_HIGH
) << 24;
1206 v3d_qpu_instr_unpack(const struct v3d_device_info
*devinfo
,
1207 uint64_t packed_instr
,
1208 struct v3d_qpu_instr
*instr
)
1210 if (QPU_GET_FIELD(packed_instr
, VC5_QPU_OP_MUL
) != 0) {
1211 return v3d_qpu_instr_unpack_alu(devinfo
, packed_instr
, instr
);
1213 uint32_t sig
= QPU_GET_FIELD(packed_instr
, VC5_QPU_SIG
);
1215 if ((sig
& 24) == 16) {
1216 return v3d_qpu_instr_unpack_branch(devinfo
, packed_instr
,
1225 v3d_qpu_instr_pack_alu(const struct v3d_device_info
*devinfo
,
1226 const struct v3d_qpu_instr
*instr
,
1227 uint64_t *packed_instr
)
1230 if (!v3d_qpu_sig_pack(devinfo
, &instr
->sig
, &sig
))
1232 *packed_instr
|= QPU_SET_FIELD(sig
, VC5_QPU_SIG
);
1234 if (instr
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
1235 *packed_instr
|= QPU_SET_FIELD(instr
->raddr_a
, VC5_QPU_RADDR_A
);
1236 *packed_instr
|= QPU_SET_FIELD(instr
->raddr_b
, VC5_QPU_RADDR_B
);
1238 if (!v3d_qpu_add_pack(devinfo
, instr
, packed_instr
))
1240 if (!v3d_qpu_mul_pack(devinfo
, instr
, packed_instr
))
1244 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
)) {
1245 if (instr
->flags
.ac
!= V3D_QPU_COND_NONE
||
1246 instr
->flags
.mc
!= V3D_QPU_COND_NONE
||
1247 instr
->flags
.apf
!= V3D_QPU_PF_NONE
||
1248 instr
->flags
.mpf
!= V3D_QPU_PF_NONE
||
1249 instr
->flags
.auf
!= V3D_QPU_UF_NONE
||
1250 instr
->flags
.muf
!= V3D_QPU_UF_NONE
) {
1254 flags
= instr
->sig_addr
;
1255 if (instr
->sig_magic
)
1256 flags
|= VC5_QPU_COND_SIG_MAGIC_ADDR
;
1258 if (!v3d_qpu_flags_pack(devinfo
, &instr
->flags
, &flags
))
1262 *packed_instr
|= QPU_SET_FIELD(flags
, VC5_QPU_COND
);
1264 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
))
1272 v3d_qpu_instr_pack_branch(const struct v3d_device_info
*devinfo
,
1273 const struct v3d_qpu_instr
*instr
,
1274 uint64_t *packed_instr
)
1276 *packed_instr
|= QPU_SET_FIELD(16, VC5_QPU_SIG
);
1278 if (instr
->branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
) {
1279 *packed_instr
|= QPU_SET_FIELD(2 + (instr
->branch
.cond
-
1280 V3D_QPU_BRANCH_COND_A0
),
1281 VC5_QPU_BRANCH_COND
);
1284 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.msfign
,
1285 VC5_QPU_BRANCH_MSFIGN
);
1287 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.bdi
,
1288 VC5_QPU_BRANCH_BDI
);
1290 if (instr
->branch
.ub
) {
1291 *packed_instr
|= VC5_QPU_BRANCH_UB
;
1292 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.bdu
,
1293 VC5_QPU_BRANCH_BDU
);
1296 switch (instr
->branch
.bdi
) {
1297 case V3D_QPU_BRANCH_DEST_ABS
:
1298 case V3D_QPU_BRANCH_DEST_REL
:
1299 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.msfign
,
1300 VC5_QPU_BRANCH_MSFIGN
);
1302 *packed_instr
|= QPU_SET_FIELD((instr
->branch
.offset
&
1304 VC5_QPU_BRANCH_ADDR_LOW
);
1306 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.offset
>> 24,
1307 VC5_QPU_BRANCH_ADDR_HIGH
);
1309 case V3D_QPU_BRANCH_DEST_REGFILE
:
1310 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.raddr_a
,
1322 v3d_qpu_instr_pack(const struct v3d_device_info
*devinfo
,
1323 const struct v3d_qpu_instr
*instr
,
1324 uint64_t *packed_instr
)
1328 switch (instr
->type
) {
1329 case V3D_QPU_INSTR_TYPE_ALU
:
1330 return v3d_qpu_instr_pack_alu(devinfo
, instr
, packed_instr
);
1331 case V3D_QPU_INSTR_TYPE_BRANCH
:
1332 return v3d_qpu_instr_pack_branch(devinfo
, instr
, packed_instr
);