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nir: Switch the indexing of block->live_in/out arrays.
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->variables);
48
49 shader->options = options;
50
51 if (si) {
52 assert(si->stage == stage);
53 shader->info = *si;
54 } else {
55 shader->info.stage = stage;
56 }
57
58 exec_list_make_empty(&shader->functions);
59
60 shader->num_inputs = 0;
61 shader->num_outputs = 0;
62 shader->num_uniforms = 0;
63 shader->num_shared = 0;
64
65 return shader;
66 }
67
68 static nir_register *
69 reg_create(void *mem_ctx, struct exec_list *list)
70 {
71 nir_register *reg = ralloc(mem_ctx, nir_register);
72
73 list_inithead(&reg->uses);
74 list_inithead(&reg->defs);
75 list_inithead(&reg->if_uses);
76
77 reg->num_components = 0;
78 reg->bit_size = 32;
79 reg->num_array_elems = 0;
80 reg->name = NULL;
81
82 exec_list_push_tail(list, &reg->node);
83
84 return reg;
85 }
86
87 nir_register *
88 nir_local_reg_create(nir_function_impl *impl)
89 {
90 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
91 reg->index = impl->reg_alloc++;
92
93 return reg;
94 }
95
96 void
97 nir_reg_remove(nir_register *reg)
98 {
99 exec_node_remove(&reg->node);
100 }
101
102 void
103 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
104 {
105 switch (var->data.mode) {
106 case nir_var_function_temp:
107 assert(!"nir_shader_add_variable cannot be used for local variables");
108 return;
109
110 case nir_var_shader_temp:
111 case nir_var_shader_in:
112 case nir_var_shader_out:
113 case nir_var_uniform:
114 case nir_var_mem_ubo:
115 case nir_var_mem_ssbo:
116 case nir_var_mem_shared:
117 case nir_var_system_value:
118 break;
119
120 case nir_var_mem_global:
121 assert(!"nir_shader_add_variable cannot be used for global memory");
122 return;
123
124 case nir_var_mem_push_const:
125 assert(!"nir_var_push_constant is not supposed to be used for variables");
126 return;
127
128 default:
129 assert(!"invalid mode");
130 return;
131 }
132
133 exec_list_push_tail(&shader->variables, &var->node);
134 }
135
136 nir_variable *
137 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
138 const struct glsl_type *type, const char *name)
139 {
140 nir_variable *var = rzalloc(shader, nir_variable);
141 var->name = ralloc_strdup(var, name);
142 var->type = type;
143 var->data.mode = mode;
144 var->data.how_declared = nir_var_declared_normally;
145
146 if ((mode == nir_var_shader_in &&
147 shader->info.stage != MESA_SHADER_VERTEX &&
148 shader->info.stage != MESA_SHADER_KERNEL) ||
149 (mode == nir_var_shader_out &&
150 shader->info.stage != MESA_SHADER_FRAGMENT))
151 var->data.interpolation = INTERP_MODE_SMOOTH;
152
153 if (mode == nir_var_shader_in || mode == nir_var_uniform)
154 var->data.read_only = true;
155
156 nir_shader_add_variable(shader, var);
157
158 return var;
159 }
160
161 nir_variable *
162 nir_local_variable_create(nir_function_impl *impl,
163 const struct glsl_type *type, const char *name)
164 {
165 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
166 var->name = ralloc_strdup(var, name);
167 var->type = type;
168 var->data.mode = nir_var_function_temp;
169
170 nir_function_impl_add_variable(impl, var);
171
172 return var;
173 }
174
175 nir_variable *
176 nir_find_variable_with_location(nir_shader *shader,
177 nir_variable_mode mode,
178 unsigned location)
179 {
180 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
181 nir_foreach_variable_with_modes(var, shader, mode) {
182 if (var->data.location == location)
183 return var;
184 }
185 return NULL;
186 }
187
188 nir_variable *
189 nir_find_variable_with_driver_location(nir_shader *shader,
190 nir_variable_mode mode,
191 unsigned location)
192 {
193 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
194 nir_foreach_variable_with_modes(var, shader, mode) {
195 if (var->data.driver_location == location)
196 return var;
197 }
198 return NULL;
199 }
200
201 nir_function *
202 nir_function_create(nir_shader *shader, const char *name)
203 {
204 nir_function *func = ralloc(shader, nir_function);
205
206 exec_list_push_tail(&shader->functions, &func->node);
207
208 func->name = ralloc_strdup(func, name);
209 func->shader = shader;
210 func->num_params = 0;
211 func->params = NULL;
212 func->impl = NULL;
213 func->is_entrypoint = false;
214
215 return func;
216 }
217
218 /* NOTE: if the instruction you are copying a src to is already added
219 * to the IR, use nir_instr_rewrite_src() instead.
220 */
221 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
222 {
223 dest->is_ssa = src->is_ssa;
224 if (src->is_ssa) {
225 dest->ssa = src->ssa;
226 } else {
227 dest->reg.base_offset = src->reg.base_offset;
228 dest->reg.reg = src->reg.reg;
229 if (src->reg.indirect) {
230 dest->reg.indirect = ralloc(mem_ctx, nir_src);
231 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
232 } else {
233 dest->reg.indirect = NULL;
234 }
235 }
236 }
237
238 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
239 {
240 /* Copying an SSA definition makes no sense whatsoever. */
241 assert(!src->is_ssa);
242
243 dest->is_ssa = false;
244
245 dest->reg.base_offset = src->reg.base_offset;
246 dest->reg.reg = src->reg.reg;
247 if (src->reg.indirect) {
248 dest->reg.indirect = ralloc(instr, nir_src);
249 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
250 } else {
251 dest->reg.indirect = NULL;
252 }
253 }
254
255 void
256 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
257 nir_alu_instr *instr)
258 {
259 nir_src_copy(&dest->src, &src->src, &instr->instr);
260 dest->abs = src->abs;
261 dest->negate = src->negate;
262 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
263 dest->swizzle[i] = src->swizzle[i];
264 }
265
266 void
267 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
268 nir_alu_instr *instr)
269 {
270 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
271 dest->write_mask = src->write_mask;
272 dest->saturate = src->saturate;
273 }
274
275
276 static void
277 cf_init(nir_cf_node *node, nir_cf_node_type type)
278 {
279 exec_node_init(&node->node);
280 node->parent = NULL;
281 node->type = type;
282 }
283
284 nir_function_impl *
285 nir_function_impl_create_bare(nir_shader *shader)
286 {
287 nir_function_impl *impl = ralloc(shader, nir_function_impl);
288
289 impl->function = NULL;
290
291 cf_init(&impl->cf_node, nir_cf_node_function);
292
293 exec_list_make_empty(&impl->body);
294 exec_list_make_empty(&impl->registers);
295 exec_list_make_empty(&impl->locals);
296 impl->reg_alloc = 0;
297 impl->ssa_alloc = 0;
298 impl->valid_metadata = nir_metadata_none;
299 impl->structured = true;
300
301 /* create start & end blocks */
302 nir_block *start_block = nir_block_create(shader);
303 nir_block *end_block = nir_block_create(shader);
304 start_block->cf_node.parent = &impl->cf_node;
305 end_block->cf_node.parent = &impl->cf_node;
306 impl->end_block = end_block;
307
308 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
309
310 start_block->successors[0] = end_block;
311 _mesa_set_add(end_block->predecessors, start_block);
312 return impl;
313 }
314
315 nir_function_impl *
316 nir_function_impl_create(nir_function *function)
317 {
318 assert(function->impl == NULL);
319
320 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
321
322 function->impl = impl;
323 impl->function = function;
324
325 return impl;
326 }
327
328 nir_block *
329 nir_block_create(nir_shader *shader)
330 {
331 nir_block *block = rzalloc(shader, nir_block);
332
333 cf_init(&block->cf_node, nir_cf_node_block);
334
335 block->successors[0] = block->successors[1] = NULL;
336 block->predecessors = _mesa_pointer_set_create(block);
337 block->imm_dom = NULL;
338 /* XXX maybe it would be worth it to defer allocation? This
339 * way it doesn't get allocated for shader refs that never run
340 * nir_calc_dominance? For example, state-tracker creates an
341 * initial IR, clones that, runs appropriate lowering pass, passes
342 * to driver which does common lowering/opt, and then stores ref
343 * which is later used to do state specific lowering and futher
344 * opt. Do any of the references not need dominance metadata?
345 */
346 block->dom_frontier = _mesa_pointer_set_create(block);
347
348 exec_list_make_empty(&block->instr_list);
349
350 return block;
351 }
352
353 static inline void
354 src_init(nir_src *src)
355 {
356 src->is_ssa = false;
357 src->reg.reg = NULL;
358 src->reg.indirect = NULL;
359 src->reg.base_offset = 0;
360 }
361
362 nir_if *
363 nir_if_create(nir_shader *shader)
364 {
365 nir_if *if_stmt = ralloc(shader, nir_if);
366
367 if_stmt->control = nir_selection_control_none;
368
369 cf_init(&if_stmt->cf_node, nir_cf_node_if);
370 src_init(&if_stmt->condition);
371
372 nir_block *then = nir_block_create(shader);
373 exec_list_make_empty(&if_stmt->then_list);
374 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
375 then->cf_node.parent = &if_stmt->cf_node;
376
377 nir_block *else_stmt = nir_block_create(shader);
378 exec_list_make_empty(&if_stmt->else_list);
379 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
380 else_stmt->cf_node.parent = &if_stmt->cf_node;
381
382 return if_stmt;
383 }
384
385 nir_loop *
386 nir_loop_create(nir_shader *shader)
387 {
388 nir_loop *loop = rzalloc(shader, nir_loop);
389
390 cf_init(&loop->cf_node, nir_cf_node_loop);
391
392 nir_block *body = nir_block_create(shader);
393 exec_list_make_empty(&loop->body);
394 exec_list_push_tail(&loop->body, &body->cf_node.node);
395 body->cf_node.parent = &loop->cf_node;
396
397 body->successors[0] = body;
398 _mesa_set_add(body->predecessors, body);
399
400 return loop;
401 }
402
403 static void
404 instr_init(nir_instr *instr, nir_instr_type type)
405 {
406 instr->type = type;
407 instr->block = NULL;
408 exec_node_init(&instr->node);
409 }
410
411 static void
412 dest_init(nir_dest *dest)
413 {
414 dest->is_ssa = false;
415 dest->reg.reg = NULL;
416 dest->reg.indirect = NULL;
417 dest->reg.base_offset = 0;
418 }
419
420 static void
421 alu_dest_init(nir_alu_dest *dest)
422 {
423 dest_init(&dest->dest);
424 dest->saturate = false;
425 dest->write_mask = 0xf;
426 }
427
428 static void
429 alu_src_init(nir_alu_src *src)
430 {
431 src_init(&src->src);
432 src->abs = src->negate = false;
433 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
434 src->swizzle[i] = i;
435 }
436
437 nir_alu_instr *
438 nir_alu_instr_create(nir_shader *shader, nir_op op)
439 {
440 unsigned num_srcs = nir_op_infos[op].num_inputs;
441 /* TODO: don't use rzalloc */
442 nir_alu_instr *instr =
443 rzalloc_size(shader,
444 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
445
446 instr_init(&instr->instr, nir_instr_type_alu);
447 instr->op = op;
448 alu_dest_init(&instr->dest);
449 for (unsigned i = 0; i < num_srcs; i++)
450 alu_src_init(&instr->src[i]);
451
452 return instr;
453 }
454
455 nir_deref_instr *
456 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
457 {
458 nir_deref_instr *instr =
459 rzalloc_size(shader, sizeof(nir_deref_instr));
460
461 instr_init(&instr->instr, nir_instr_type_deref);
462
463 instr->deref_type = deref_type;
464 if (deref_type != nir_deref_type_var)
465 src_init(&instr->parent);
466
467 if (deref_type == nir_deref_type_array ||
468 deref_type == nir_deref_type_ptr_as_array)
469 src_init(&instr->arr.index);
470
471 dest_init(&instr->dest);
472
473 return instr;
474 }
475
476 nir_jump_instr *
477 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
478 {
479 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
480 instr_init(&instr->instr, nir_instr_type_jump);
481 src_init(&instr->condition);
482 instr->type = type;
483 instr->target = NULL;
484 instr->else_target = NULL;
485 return instr;
486 }
487
488 nir_load_const_instr *
489 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
490 unsigned bit_size)
491 {
492 nir_load_const_instr *instr =
493 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
494 instr_init(&instr->instr, nir_instr_type_load_const);
495
496 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
497
498 return instr;
499 }
500
501 nir_intrinsic_instr *
502 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
503 {
504 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
505 /* TODO: don't use rzalloc */
506 nir_intrinsic_instr *instr =
507 rzalloc_size(shader,
508 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
509
510 instr_init(&instr->instr, nir_instr_type_intrinsic);
511 instr->intrinsic = op;
512
513 if (nir_intrinsic_infos[op].has_dest)
514 dest_init(&instr->dest);
515
516 for (unsigned i = 0; i < num_srcs; i++)
517 src_init(&instr->src[i]);
518
519 return instr;
520 }
521
522 nir_call_instr *
523 nir_call_instr_create(nir_shader *shader, nir_function *callee)
524 {
525 const unsigned num_params = callee->num_params;
526 nir_call_instr *instr =
527 rzalloc_size(shader, sizeof(*instr) +
528 num_params * sizeof(instr->params[0]));
529
530 instr_init(&instr->instr, nir_instr_type_call);
531 instr->callee = callee;
532 instr->num_params = num_params;
533 for (unsigned i = 0; i < num_params; i++)
534 src_init(&instr->params[i]);
535
536 return instr;
537 }
538
539 static int8_t default_tg4_offsets[4][2] =
540 {
541 { 0, 1 },
542 { 1, 1 },
543 { 1, 0 },
544 { 0, 0 },
545 };
546
547 nir_tex_instr *
548 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
549 {
550 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
551 instr_init(&instr->instr, nir_instr_type_tex);
552
553 dest_init(&instr->dest);
554
555 instr->num_srcs = num_srcs;
556 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
557 for (unsigned i = 0; i < num_srcs; i++)
558 src_init(&instr->src[i].src);
559
560 instr->texture_index = 0;
561 instr->sampler_index = 0;
562 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
563
564 return instr;
565 }
566
567 void
568 nir_tex_instr_add_src(nir_tex_instr *tex,
569 nir_tex_src_type src_type,
570 nir_src src)
571 {
572 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
573 tex->num_srcs + 1);
574
575 for (unsigned i = 0; i < tex->num_srcs; i++) {
576 new_srcs[i].src_type = tex->src[i].src_type;
577 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
578 &tex->src[i].src);
579 }
580
581 ralloc_free(tex->src);
582 tex->src = new_srcs;
583
584 tex->src[tex->num_srcs].src_type = src_type;
585 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
586 tex->num_srcs++;
587 }
588
589 void
590 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
591 {
592 assert(src_idx < tex->num_srcs);
593
594 /* First rewrite the source to NIR_SRC_INIT */
595 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
596
597 /* Now, move all of the other sources down */
598 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
599 tex->src[i-1].src_type = tex->src[i].src_type;
600 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
601 }
602 tex->num_srcs--;
603 }
604
605 bool
606 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
607 {
608 if (tex->op != nir_texop_tg4)
609 return false;
610 return memcmp(tex->tg4_offsets, default_tg4_offsets,
611 sizeof(tex->tg4_offsets)) != 0;
612 }
613
614 nir_phi_instr *
615 nir_phi_instr_create(nir_shader *shader)
616 {
617 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
618 instr_init(&instr->instr, nir_instr_type_phi);
619
620 dest_init(&instr->dest);
621 exec_list_make_empty(&instr->srcs);
622 return instr;
623 }
624
625 nir_parallel_copy_instr *
626 nir_parallel_copy_instr_create(nir_shader *shader)
627 {
628 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
629 instr_init(&instr->instr, nir_instr_type_parallel_copy);
630
631 exec_list_make_empty(&instr->entries);
632
633 return instr;
634 }
635
636 nir_ssa_undef_instr *
637 nir_ssa_undef_instr_create(nir_shader *shader,
638 unsigned num_components,
639 unsigned bit_size)
640 {
641 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
642 instr_init(&instr->instr, nir_instr_type_ssa_undef);
643
644 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
645
646 return instr;
647 }
648
649 static nir_const_value
650 const_value_float(double d, unsigned bit_size)
651 {
652 nir_const_value v;
653 memset(&v, 0, sizeof(v));
654 switch (bit_size) {
655 case 16: v.u16 = _mesa_float_to_half(d); break;
656 case 32: v.f32 = d; break;
657 case 64: v.f64 = d; break;
658 default:
659 unreachable("Invalid bit size");
660 }
661 return v;
662 }
663
664 static nir_const_value
665 const_value_int(int64_t i, unsigned bit_size)
666 {
667 nir_const_value v;
668 memset(&v, 0, sizeof(v));
669 switch (bit_size) {
670 case 1: v.b = i & 1; break;
671 case 8: v.i8 = i; break;
672 case 16: v.i16 = i; break;
673 case 32: v.i32 = i; break;
674 case 64: v.i64 = i; break;
675 default:
676 unreachable("Invalid bit size");
677 }
678 return v;
679 }
680
681 nir_const_value
682 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
683 {
684 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
685 const int64_t min_int = -max_int - 1;
686 switch (binop) {
687 case nir_op_iadd:
688 return const_value_int(0, bit_size);
689 case nir_op_fadd:
690 return const_value_float(0, bit_size);
691 case nir_op_imul:
692 return const_value_int(1, bit_size);
693 case nir_op_fmul:
694 return const_value_float(1, bit_size);
695 case nir_op_imin:
696 return const_value_int(max_int, bit_size);
697 case nir_op_umin:
698 return const_value_int(~0ull, bit_size);
699 case nir_op_fmin:
700 return const_value_float(INFINITY, bit_size);
701 case nir_op_imax:
702 return const_value_int(min_int, bit_size);
703 case nir_op_umax:
704 return const_value_int(0, bit_size);
705 case nir_op_fmax:
706 return const_value_float(-INFINITY, bit_size);
707 case nir_op_iand:
708 return const_value_int(~0ull, bit_size);
709 case nir_op_ior:
710 return const_value_int(0, bit_size);
711 case nir_op_ixor:
712 return const_value_int(0, bit_size);
713 default:
714 unreachable("Invalid reduction operation");
715 }
716 }
717
718 nir_function_impl *
719 nir_cf_node_get_function(nir_cf_node *node)
720 {
721 while (node->type != nir_cf_node_function) {
722 node = node->parent;
723 }
724
725 return nir_cf_node_as_function(node);
726 }
727
728 /* Reduces a cursor by trying to convert everything to after and trying to
729 * go up to block granularity when possible.
730 */
731 static nir_cursor
732 reduce_cursor(nir_cursor cursor)
733 {
734 switch (cursor.option) {
735 case nir_cursor_before_block:
736 if (exec_list_is_empty(&cursor.block->instr_list)) {
737 /* Empty block. After is as good as before. */
738 cursor.option = nir_cursor_after_block;
739 }
740 return cursor;
741
742 case nir_cursor_after_block:
743 return cursor;
744
745 case nir_cursor_before_instr: {
746 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
747 if (prev_instr) {
748 /* Before this instruction is after the previous */
749 cursor.instr = prev_instr;
750 cursor.option = nir_cursor_after_instr;
751 } else {
752 /* No previous instruction. Switch to before block */
753 cursor.block = cursor.instr->block;
754 cursor.option = nir_cursor_before_block;
755 }
756 return reduce_cursor(cursor);
757 }
758
759 case nir_cursor_after_instr:
760 if (nir_instr_next(cursor.instr) == NULL) {
761 /* This is the last instruction, switch to after block */
762 cursor.option = nir_cursor_after_block;
763 cursor.block = cursor.instr->block;
764 }
765 return cursor;
766
767 default:
768 unreachable("Inavlid cursor option");
769 }
770 }
771
772 bool
773 nir_cursors_equal(nir_cursor a, nir_cursor b)
774 {
775 /* Reduced cursors should be unique */
776 a = reduce_cursor(a);
777 b = reduce_cursor(b);
778
779 return a.block == b.block && a.option == b.option;
780 }
781
782 static bool
783 add_use_cb(nir_src *src, void *state)
784 {
785 nir_instr *instr = state;
786
787 src->parent_instr = instr;
788 list_addtail(&src->use_link,
789 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
790
791 return true;
792 }
793
794 static bool
795 add_ssa_def_cb(nir_ssa_def *def, void *state)
796 {
797 nir_instr *instr = state;
798
799 if (instr->block && def->index == UINT_MAX) {
800 nir_function_impl *impl =
801 nir_cf_node_get_function(&instr->block->cf_node);
802
803 def->index = impl->ssa_alloc++;
804
805 impl->valid_metadata &= ~nir_metadata_live_ssa_defs;
806 }
807
808 return true;
809 }
810
811 static bool
812 add_reg_def_cb(nir_dest *dest, void *state)
813 {
814 nir_instr *instr = state;
815
816 if (!dest->is_ssa) {
817 dest->reg.parent_instr = instr;
818 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
819 }
820
821 return true;
822 }
823
824 static void
825 add_defs_uses(nir_instr *instr)
826 {
827 nir_foreach_src(instr, add_use_cb, instr);
828 nir_foreach_dest(instr, add_reg_def_cb, instr);
829 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
830 }
831
832 void
833 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
834 {
835 switch (cursor.option) {
836 case nir_cursor_before_block:
837 /* Only allow inserting jumps into empty blocks. */
838 if (instr->type == nir_instr_type_jump)
839 assert(exec_list_is_empty(&cursor.block->instr_list));
840
841 instr->block = cursor.block;
842 add_defs_uses(instr);
843 exec_list_push_head(&cursor.block->instr_list, &instr->node);
844 break;
845 case nir_cursor_after_block: {
846 /* Inserting instructions after a jump is illegal. */
847 nir_instr *last = nir_block_last_instr(cursor.block);
848 assert(last == NULL || last->type != nir_instr_type_jump);
849 (void) last;
850
851 instr->block = cursor.block;
852 add_defs_uses(instr);
853 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
854 break;
855 }
856 case nir_cursor_before_instr:
857 assert(instr->type != nir_instr_type_jump);
858 instr->block = cursor.instr->block;
859 add_defs_uses(instr);
860 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
861 break;
862 case nir_cursor_after_instr:
863 /* Inserting instructions after a jump is illegal. */
864 assert(cursor.instr->type != nir_instr_type_jump);
865
866 /* Only allow inserting jumps at the end of the block. */
867 if (instr->type == nir_instr_type_jump)
868 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
869
870 instr->block = cursor.instr->block;
871 add_defs_uses(instr);
872 exec_node_insert_after(&cursor.instr->node, &instr->node);
873 break;
874 }
875
876 if (instr->type == nir_instr_type_jump)
877 nir_handle_add_jump(instr->block);
878 }
879
880 static bool
881 src_is_valid(const nir_src *src)
882 {
883 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
884 }
885
886 static bool
887 remove_use_cb(nir_src *src, void *state)
888 {
889 (void) state;
890
891 if (src_is_valid(src))
892 list_del(&src->use_link);
893
894 return true;
895 }
896
897 static bool
898 remove_def_cb(nir_dest *dest, void *state)
899 {
900 (void) state;
901
902 if (!dest->is_ssa)
903 list_del(&dest->reg.def_link);
904
905 return true;
906 }
907
908 static void
909 remove_defs_uses(nir_instr *instr)
910 {
911 nir_foreach_dest(instr, remove_def_cb, instr);
912 nir_foreach_src(instr, remove_use_cb, instr);
913 }
914
915 void nir_instr_remove_v(nir_instr *instr)
916 {
917 remove_defs_uses(instr);
918 exec_node_remove(&instr->node);
919
920 if (instr->type == nir_instr_type_jump) {
921 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
922 nir_handle_remove_jump(instr->block, jump_instr->type);
923 }
924 }
925
926 /*@}*/
927
928 void
929 nir_index_local_regs(nir_function_impl *impl)
930 {
931 unsigned index = 0;
932 foreach_list_typed(nir_register, reg, node, &impl->registers) {
933 reg->index = index++;
934 }
935 impl->reg_alloc = index;
936 }
937
938 static bool
939 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
940 {
941 return cb(&instr->dest.dest, state);
942 }
943
944 static bool
945 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
946 {
947 return cb(&instr->dest, state);
948 }
949
950 static bool
951 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
952 void *state)
953 {
954 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
955 return cb(&instr->dest, state);
956
957 return true;
958 }
959
960 static bool
961 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
962 void *state)
963 {
964 return cb(&instr->dest, state);
965 }
966
967 static bool
968 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
969 {
970 return cb(&instr->dest, state);
971 }
972
973 static bool
974 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
975 nir_foreach_dest_cb cb, void *state)
976 {
977 nir_foreach_parallel_copy_entry(entry, instr) {
978 if (!cb(&entry->dest, state))
979 return false;
980 }
981
982 return true;
983 }
984
985 bool
986 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
987 {
988 switch (instr->type) {
989 case nir_instr_type_alu:
990 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
991 case nir_instr_type_deref:
992 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
993 case nir_instr_type_intrinsic:
994 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
995 case nir_instr_type_tex:
996 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
997 case nir_instr_type_phi:
998 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
999 case nir_instr_type_parallel_copy:
1000 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
1001 cb, state);
1002
1003 case nir_instr_type_load_const:
1004 case nir_instr_type_ssa_undef:
1005 case nir_instr_type_call:
1006 case nir_instr_type_jump:
1007 break;
1008
1009 default:
1010 unreachable("Invalid instruction type");
1011 break;
1012 }
1013
1014 return true;
1015 }
1016
1017 struct foreach_ssa_def_state {
1018 nir_foreach_ssa_def_cb cb;
1019 void *client_state;
1020 };
1021
1022 static inline bool
1023 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1024 {
1025 struct foreach_ssa_def_state *state = void_state;
1026
1027 if (dest->is_ssa)
1028 return state->cb(&dest->ssa, state->client_state);
1029 else
1030 return true;
1031 }
1032
1033 bool
1034 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1035 {
1036 switch (instr->type) {
1037 case nir_instr_type_alu:
1038 case nir_instr_type_deref:
1039 case nir_instr_type_tex:
1040 case nir_instr_type_intrinsic:
1041 case nir_instr_type_phi:
1042 case nir_instr_type_parallel_copy: {
1043 struct foreach_ssa_def_state foreach_state = {cb, state};
1044 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1045 }
1046
1047 case nir_instr_type_load_const:
1048 return cb(&nir_instr_as_load_const(instr)->def, state);
1049 case nir_instr_type_ssa_undef:
1050 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1051 case nir_instr_type_call:
1052 case nir_instr_type_jump:
1053 return true;
1054 default:
1055 unreachable("Invalid instruction type");
1056 }
1057 }
1058
1059 nir_ssa_def *
1060 nir_instr_ssa_def(nir_instr *instr)
1061 {
1062 switch (instr->type) {
1063 case nir_instr_type_alu:
1064 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1065 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1066
1067 case nir_instr_type_deref:
1068 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1069 return &nir_instr_as_deref(instr)->dest.ssa;
1070
1071 case nir_instr_type_tex:
1072 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1073 return &nir_instr_as_tex(instr)->dest.ssa;
1074
1075 case nir_instr_type_intrinsic: {
1076 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1077 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1078 assert(intrin->dest.is_ssa);
1079 return &intrin->dest.ssa;
1080 } else {
1081 return NULL;
1082 }
1083 }
1084
1085 case nir_instr_type_phi:
1086 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1087 return &nir_instr_as_phi(instr)->dest.ssa;
1088
1089 case nir_instr_type_parallel_copy:
1090 unreachable("Parallel copies are unsupported by this function");
1091
1092 case nir_instr_type_load_const:
1093 return &nir_instr_as_load_const(instr)->def;
1094
1095 case nir_instr_type_ssa_undef:
1096 return &nir_instr_as_ssa_undef(instr)->def;
1097
1098 case nir_instr_type_call:
1099 case nir_instr_type_jump:
1100 return NULL;
1101 }
1102
1103 unreachable("Invalid instruction type");
1104 }
1105
1106 static bool
1107 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1108 {
1109 if (!cb(src, state))
1110 return false;
1111 if (!src->is_ssa && src->reg.indirect)
1112 return cb(src->reg.indirect, state);
1113 return true;
1114 }
1115
1116 static bool
1117 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1118 {
1119 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1120 if (!visit_src(&instr->src[i].src, cb, state))
1121 return false;
1122
1123 return true;
1124 }
1125
1126 static bool
1127 visit_deref_instr_src(nir_deref_instr *instr,
1128 nir_foreach_src_cb cb, void *state)
1129 {
1130 if (instr->deref_type != nir_deref_type_var) {
1131 if (!visit_src(&instr->parent, cb, state))
1132 return false;
1133 }
1134
1135 if (instr->deref_type == nir_deref_type_array ||
1136 instr->deref_type == nir_deref_type_ptr_as_array) {
1137 if (!visit_src(&instr->arr.index, cb, state))
1138 return false;
1139 }
1140
1141 return true;
1142 }
1143
1144 static bool
1145 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1146 {
1147 for (unsigned i = 0; i < instr->num_srcs; i++) {
1148 if (!visit_src(&instr->src[i].src, cb, state))
1149 return false;
1150 }
1151
1152 return true;
1153 }
1154
1155 static bool
1156 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1157 void *state)
1158 {
1159 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1160 for (unsigned i = 0; i < num_srcs; i++) {
1161 if (!visit_src(&instr->src[i], cb, state))
1162 return false;
1163 }
1164
1165 return true;
1166 }
1167
1168 static bool
1169 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1170 {
1171 for (unsigned i = 0; i < instr->num_params; i++) {
1172 if (!visit_src(&instr->params[i], cb, state))
1173 return false;
1174 }
1175
1176 return true;
1177 }
1178
1179 static bool
1180 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1181 {
1182 nir_foreach_phi_src(src, instr) {
1183 if (!visit_src(&src->src, cb, state))
1184 return false;
1185 }
1186
1187 return true;
1188 }
1189
1190 static bool
1191 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1192 nir_foreach_src_cb cb, void *state)
1193 {
1194 nir_foreach_parallel_copy_entry(entry, instr) {
1195 if (!visit_src(&entry->src, cb, state))
1196 return false;
1197 }
1198
1199 return true;
1200 }
1201
1202 static bool
1203 visit_jump_src(nir_jump_instr *instr, nir_foreach_src_cb cb, void *state)
1204 {
1205 if (instr->type != nir_jump_goto_if)
1206 return true;
1207
1208 return visit_src(&instr->condition, cb, state);
1209 }
1210
1211 typedef struct {
1212 void *state;
1213 nir_foreach_src_cb cb;
1214 } visit_dest_indirect_state;
1215
1216 static bool
1217 visit_dest_indirect(nir_dest *dest, void *_state)
1218 {
1219 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1220
1221 if (!dest->is_ssa && dest->reg.indirect)
1222 return state->cb(dest->reg.indirect, state->state);
1223
1224 return true;
1225 }
1226
1227 bool
1228 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1229 {
1230 switch (instr->type) {
1231 case nir_instr_type_alu:
1232 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1233 return false;
1234 break;
1235 case nir_instr_type_deref:
1236 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1237 return false;
1238 break;
1239 case nir_instr_type_intrinsic:
1240 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1241 return false;
1242 break;
1243 case nir_instr_type_tex:
1244 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1245 return false;
1246 break;
1247 case nir_instr_type_call:
1248 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1249 return false;
1250 break;
1251 case nir_instr_type_load_const:
1252 /* Constant load instructions have no regular sources */
1253 break;
1254 case nir_instr_type_phi:
1255 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1256 return false;
1257 break;
1258 case nir_instr_type_parallel_copy:
1259 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1260 cb, state))
1261 return false;
1262 break;
1263 case nir_instr_type_jump:
1264 return visit_jump_src(nir_instr_as_jump(instr), cb, state);
1265 case nir_instr_type_ssa_undef:
1266 return true;
1267
1268 default:
1269 unreachable("Invalid instruction type");
1270 break;
1271 }
1272
1273 visit_dest_indirect_state dest_state;
1274 dest_state.state = state;
1275 dest_state.cb = cb;
1276 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1277 }
1278
1279 bool
1280 nir_foreach_phi_src_leaving_block(nir_block *block,
1281 nir_foreach_src_cb cb,
1282 void *state)
1283 {
1284 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1285 if (block->successors[i] == NULL)
1286 continue;
1287
1288 nir_foreach_instr(instr, block->successors[i]) {
1289 if (instr->type != nir_instr_type_phi)
1290 break;
1291
1292 nir_phi_instr *phi = nir_instr_as_phi(instr);
1293 nir_foreach_phi_src(phi_src, phi) {
1294 if (phi_src->pred == block) {
1295 if (!cb(&phi_src->src, state))
1296 return false;
1297 }
1298 }
1299 }
1300 }
1301
1302 return true;
1303 }
1304
1305 nir_const_value
1306 nir_const_value_for_float(double f, unsigned bit_size)
1307 {
1308 nir_const_value v;
1309 memset(&v, 0, sizeof(v));
1310
1311 switch (bit_size) {
1312 case 16:
1313 v.u16 = _mesa_float_to_half(f);
1314 break;
1315 case 32:
1316 v.f32 = f;
1317 break;
1318 case 64:
1319 v.f64 = f;
1320 break;
1321 default:
1322 unreachable("Invalid bit size");
1323 }
1324
1325 return v;
1326 }
1327
1328 double
1329 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1330 {
1331 switch (bit_size) {
1332 case 16: return _mesa_half_to_float(value.u16);
1333 case 32: return value.f32;
1334 case 64: return value.f64;
1335 default:
1336 unreachable("Invalid bit size");
1337 }
1338 }
1339
1340 nir_const_value *
1341 nir_src_as_const_value(nir_src src)
1342 {
1343 if (!src.is_ssa)
1344 return NULL;
1345
1346 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1347 return NULL;
1348
1349 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1350
1351 return load->value;
1352 }
1353
1354 /**
1355 * Returns true if the source is known to be dynamically uniform. Otherwise it
1356 * returns false which means it may or may not be dynamically uniform but it
1357 * can't be determined.
1358 */
1359 bool
1360 nir_src_is_dynamically_uniform(nir_src src)
1361 {
1362 if (!src.is_ssa)
1363 return false;
1364
1365 /* Constants are trivially dynamically uniform */
1366 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1367 return true;
1368
1369 /* As are uniform variables */
1370 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1371 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1372 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1373 nir_src_is_dynamically_uniform(intr->src[0]))
1374 return true;
1375 }
1376
1377 /* Operating together dynamically uniform expressions produces a
1378 * dynamically uniform result
1379 */
1380 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1381 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1382 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1383 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1384 return false;
1385 }
1386
1387 return true;
1388 }
1389
1390 /* XXX: this could have many more tests, such as when a sampler function is
1391 * called with dynamically uniform arguments.
1392 */
1393 return false;
1394 }
1395
1396 static void
1397 src_remove_all_uses(nir_src *src)
1398 {
1399 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1400 if (!src_is_valid(src))
1401 continue;
1402
1403 list_del(&src->use_link);
1404 }
1405 }
1406
1407 static void
1408 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1409 {
1410 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1411 if (!src_is_valid(src))
1412 continue;
1413
1414 if (parent_instr) {
1415 src->parent_instr = parent_instr;
1416 if (src->is_ssa)
1417 list_addtail(&src->use_link, &src->ssa->uses);
1418 else
1419 list_addtail(&src->use_link, &src->reg.reg->uses);
1420 } else {
1421 assert(parent_if);
1422 src->parent_if = parent_if;
1423 if (src->is_ssa)
1424 list_addtail(&src->use_link, &src->ssa->if_uses);
1425 else
1426 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1427 }
1428 }
1429 }
1430
1431 void
1432 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1433 {
1434 assert(!src_is_valid(src) || src->parent_instr == instr);
1435
1436 src_remove_all_uses(src);
1437 *src = new_src;
1438 src_add_all_uses(src, instr, NULL);
1439 }
1440
1441 void
1442 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1443 {
1444 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1445
1446 src_remove_all_uses(dest);
1447 src_remove_all_uses(src);
1448 *dest = *src;
1449 *src = NIR_SRC_INIT;
1450 src_add_all_uses(dest, dest_instr, NULL);
1451 }
1452
1453 void
1454 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1455 {
1456 nir_src *src = &if_stmt->condition;
1457 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1458
1459 src_remove_all_uses(src);
1460 *src = new_src;
1461 src_add_all_uses(src, NULL, if_stmt);
1462 }
1463
1464 void
1465 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1466 {
1467 if (dest->is_ssa) {
1468 /* We can only overwrite an SSA destination if it has no uses. */
1469 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1470 } else {
1471 list_del(&dest->reg.def_link);
1472 if (dest->reg.indirect)
1473 src_remove_all_uses(dest->reg.indirect);
1474 }
1475
1476 /* We can't re-write with an SSA def */
1477 assert(!new_dest.is_ssa);
1478
1479 nir_dest_copy(dest, &new_dest, instr);
1480
1481 dest->reg.parent_instr = instr;
1482 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1483
1484 if (dest->reg.indirect)
1485 src_add_all_uses(dest->reg.indirect, instr, NULL);
1486 }
1487
1488 /* note: does *not* take ownership of 'name' */
1489 void
1490 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1491 unsigned num_components,
1492 unsigned bit_size, const char *name)
1493 {
1494 def->name = ralloc_strdup(instr, name);
1495 def->live_index = UINT_MAX; /* Something clearly OOB */
1496 def->parent_instr = instr;
1497 list_inithead(&def->uses);
1498 list_inithead(&def->if_uses);
1499 def->num_components = num_components;
1500 def->bit_size = bit_size;
1501 def->divergent = true; /* This is the safer default */
1502
1503 if (instr->block) {
1504 nir_function_impl *impl =
1505 nir_cf_node_get_function(&instr->block->cf_node);
1506
1507 def->index = impl->ssa_alloc++;
1508
1509 impl->valid_metadata &= ~nir_metadata_live_ssa_defs;
1510 } else {
1511 def->index = UINT_MAX;
1512 }
1513 }
1514
1515 /* note: does *not* take ownership of 'name' */
1516 void
1517 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1518 unsigned num_components, unsigned bit_size,
1519 const char *name)
1520 {
1521 dest->is_ssa = true;
1522 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1523 }
1524
1525 void
1526 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1527 {
1528 assert(!new_src.is_ssa || def != new_src.ssa);
1529
1530 nir_foreach_use_safe(use_src, def)
1531 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1532
1533 nir_foreach_if_use_safe(use_src, def)
1534 nir_if_rewrite_condition(use_src->parent_if, new_src);
1535 }
1536
1537 static bool
1538 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1539 {
1540 assert(start->block == end->block);
1541
1542 if (between->block != start->block)
1543 return false;
1544
1545 /* Search backwards looking for "between" */
1546 while (start != end) {
1547 if (between == end)
1548 return true;
1549
1550 end = nir_instr_prev(end);
1551 assert(end);
1552 }
1553
1554 return false;
1555 }
1556
1557 /* Replaces all uses of the given SSA def with the given source but only if
1558 * the use comes after the after_me instruction. This can be useful if you
1559 * are emitting code to fix up the result of some instruction: you can freely
1560 * use the result in that code and then call rewrite_uses_after and pass the
1561 * last fixup instruction as after_me and it will replace all of the uses you
1562 * want without touching the fixup code.
1563 *
1564 * This function assumes that after_me is in the same block as
1565 * def->parent_instr and that after_me comes after def->parent_instr.
1566 */
1567 void
1568 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1569 nir_instr *after_me)
1570 {
1571 if (new_src.is_ssa && def == new_src.ssa)
1572 return;
1573
1574 nir_foreach_use_safe(use_src, def) {
1575 assert(use_src->parent_instr != def->parent_instr);
1576 /* Since def already dominates all of its uses, the only way a use can
1577 * not be dominated by after_me is if it is between def and after_me in
1578 * the instruction list.
1579 */
1580 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1581 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1582 }
1583
1584 nir_foreach_if_use_safe(use_src, def)
1585 nir_if_rewrite_condition(use_src->parent_if, new_src);
1586 }
1587
1588 nir_component_mask_t
1589 nir_ssa_def_components_read(const nir_ssa_def *def)
1590 {
1591 nir_component_mask_t read_mask = 0;
1592 nir_foreach_use(use, def) {
1593 if (use->parent_instr->type == nir_instr_type_alu) {
1594 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1595 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1596 int src_idx = alu_src - &alu->src[0];
1597 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1598 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1599 } else {
1600 return (1 << def->num_components) - 1;
1601 }
1602 }
1603
1604 if (!list_is_empty(&def->if_uses))
1605 read_mask |= 1;
1606
1607 return read_mask;
1608 }
1609
1610 nir_block *
1611 nir_block_unstructured_next(nir_block *block)
1612 {
1613 if (block == NULL) {
1614 /* nir_foreach_block_unstructured_safe() will call this function on a
1615 * NULL block after the last iteration, but it won't use the result so
1616 * just return NULL here.
1617 */
1618 return NULL;
1619 }
1620
1621 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1622 if (cf_next == NULL && block->cf_node.parent->type == nir_cf_node_function)
1623 return NULL;
1624
1625 if (cf_next && cf_next->type == nir_cf_node_block)
1626 return nir_cf_node_as_block(cf_next);
1627
1628 return nir_block_cf_tree_next(block);
1629 }
1630
1631 nir_block *
1632 nir_unstructured_start_block(nir_function_impl *impl)
1633 {
1634 return nir_start_block(impl);
1635 }
1636
1637 nir_block *
1638 nir_block_cf_tree_next(nir_block *block)
1639 {
1640 if (block == NULL) {
1641 /* nir_foreach_block_safe() will call this function on a NULL block
1642 * after the last iteration, but it won't use the result so just return
1643 * NULL here.
1644 */
1645 return NULL;
1646 }
1647
1648 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1649
1650 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1651 if (cf_next)
1652 return nir_cf_node_cf_tree_first(cf_next);
1653
1654 nir_cf_node *parent = block->cf_node.parent;
1655
1656 switch (parent->type) {
1657 case nir_cf_node_if: {
1658 /* Are we at the end of the if? Go to the beginning of the else */
1659 nir_if *if_stmt = nir_cf_node_as_if(parent);
1660 if (block == nir_if_last_then_block(if_stmt))
1661 return nir_if_first_else_block(if_stmt);
1662
1663 assert(block == nir_if_last_else_block(if_stmt));
1664 }
1665 /* fallthrough */
1666
1667 case nir_cf_node_loop:
1668 return nir_cf_node_as_block(nir_cf_node_next(parent));
1669
1670 case nir_cf_node_function:
1671 return NULL;
1672
1673 default:
1674 unreachable("unknown cf node type");
1675 }
1676 }
1677
1678 nir_block *
1679 nir_block_cf_tree_prev(nir_block *block)
1680 {
1681 if (block == NULL) {
1682 /* do this for consistency with nir_block_cf_tree_next() */
1683 return NULL;
1684 }
1685
1686 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1687
1688 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1689 if (cf_prev)
1690 return nir_cf_node_cf_tree_last(cf_prev);
1691
1692 nir_cf_node *parent = block->cf_node.parent;
1693
1694 switch (parent->type) {
1695 case nir_cf_node_if: {
1696 /* Are we at the beginning of the else? Go to the end of the if */
1697 nir_if *if_stmt = nir_cf_node_as_if(parent);
1698 if (block == nir_if_first_else_block(if_stmt))
1699 return nir_if_last_then_block(if_stmt);
1700
1701 assert(block == nir_if_first_then_block(if_stmt));
1702 }
1703 /* fallthrough */
1704
1705 case nir_cf_node_loop:
1706 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1707
1708 case nir_cf_node_function:
1709 return NULL;
1710
1711 default:
1712 unreachable("unknown cf node type");
1713 }
1714 }
1715
1716 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1717 {
1718 switch (node->type) {
1719 case nir_cf_node_function: {
1720 nir_function_impl *impl = nir_cf_node_as_function(node);
1721 return nir_start_block(impl);
1722 }
1723
1724 case nir_cf_node_if: {
1725 nir_if *if_stmt = nir_cf_node_as_if(node);
1726 return nir_if_first_then_block(if_stmt);
1727 }
1728
1729 case nir_cf_node_loop: {
1730 nir_loop *loop = nir_cf_node_as_loop(node);
1731 return nir_loop_first_block(loop);
1732 }
1733
1734 case nir_cf_node_block: {
1735 return nir_cf_node_as_block(node);
1736 }
1737
1738 default:
1739 unreachable("unknown node type");
1740 }
1741 }
1742
1743 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1744 {
1745 switch (node->type) {
1746 case nir_cf_node_function: {
1747 nir_function_impl *impl = nir_cf_node_as_function(node);
1748 return nir_impl_last_block(impl);
1749 }
1750
1751 case nir_cf_node_if: {
1752 nir_if *if_stmt = nir_cf_node_as_if(node);
1753 return nir_if_last_else_block(if_stmt);
1754 }
1755
1756 case nir_cf_node_loop: {
1757 nir_loop *loop = nir_cf_node_as_loop(node);
1758 return nir_loop_last_block(loop);
1759 }
1760
1761 case nir_cf_node_block: {
1762 return nir_cf_node_as_block(node);
1763 }
1764
1765 default:
1766 unreachable("unknown node type");
1767 }
1768 }
1769
1770 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1771 {
1772 if (node->type == nir_cf_node_block)
1773 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1774 else if (node->type == nir_cf_node_function)
1775 return NULL;
1776 else
1777 return nir_cf_node_as_block(nir_cf_node_next(node));
1778 }
1779
1780 nir_if *
1781 nir_block_get_following_if(nir_block *block)
1782 {
1783 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1784 return NULL;
1785
1786 if (nir_cf_node_is_last(&block->cf_node))
1787 return NULL;
1788
1789 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1790
1791 if (next_node->type != nir_cf_node_if)
1792 return NULL;
1793
1794 return nir_cf_node_as_if(next_node);
1795 }
1796
1797 nir_loop *
1798 nir_block_get_following_loop(nir_block *block)
1799 {
1800 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1801 return NULL;
1802
1803 if (nir_cf_node_is_last(&block->cf_node))
1804 return NULL;
1805
1806 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1807
1808 if (next_node->type != nir_cf_node_loop)
1809 return NULL;
1810
1811 return nir_cf_node_as_loop(next_node);
1812 }
1813
1814 void
1815 nir_index_blocks(nir_function_impl *impl)
1816 {
1817 unsigned index = 0;
1818
1819 if (impl->valid_metadata & nir_metadata_block_index)
1820 return;
1821
1822 nir_foreach_block_unstructured(block, impl) {
1823 block->index = index++;
1824 }
1825
1826 /* The end_block isn't really part of the program, which is why its index
1827 * is >= num_blocks.
1828 */
1829 impl->num_blocks = impl->end_block->index = index;
1830 }
1831
1832 static bool
1833 index_ssa_def_cb(nir_ssa_def *def, void *state)
1834 {
1835 unsigned *index = (unsigned *) state;
1836 def->index = (*index)++;
1837
1838 return true;
1839 }
1840
1841 /**
1842 * The indices are applied top-to-bottom which has the very nice property
1843 * that, if A dominates B, then A->index <= B->index.
1844 */
1845 void
1846 nir_index_ssa_defs(nir_function_impl *impl)
1847 {
1848 unsigned index = 0;
1849
1850 impl->valid_metadata &= ~nir_metadata_live_ssa_defs;
1851
1852 nir_foreach_block_unstructured(block, impl) {
1853 nir_foreach_instr(instr, block)
1854 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1855 }
1856
1857 impl->ssa_alloc = index;
1858 }
1859
1860 /**
1861 * The indices are applied top-to-bottom which has the very nice property
1862 * that, if A dominates B, then A->index <= B->index.
1863 */
1864 unsigned
1865 nir_index_instrs(nir_function_impl *impl)
1866 {
1867 unsigned index = 0;
1868
1869 nir_foreach_block(block, impl) {
1870 nir_foreach_instr(instr, block)
1871 instr->index = index++;
1872 }
1873
1874 return index;
1875 }
1876
1877 unsigned
1878 nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes)
1879 {
1880 unsigned count = 0;
1881 nir_foreach_variable_with_modes(var, shader, modes)
1882 var->index = count++;
1883 return count;
1884 }
1885
1886 unsigned
1887 nir_function_impl_index_vars(nir_function_impl *impl)
1888 {
1889 unsigned count = 0;
1890 nir_foreach_function_temp_variable(var, impl)
1891 var->index = count++;
1892 return count;
1893 }
1894
1895 static nir_instr *
1896 cursor_next_instr(nir_cursor cursor)
1897 {
1898 switch (cursor.option) {
1899 case nir_cursor_before_block:
1900 for (nir_block *block = cursor.block; block;
1901 block = nir_block_cf_tree_next(block)) {
1902 nir_instr *instr = nir_block_first_instr(block);
1903 if (instr)
1904 return instr;
1905 }
1906 return NULL;
1907
1908 case nir_cursor_after_block:
1909 cursor.block = nir_block_cf_tree_next(cursor.block);
1910 if (cursor.block == NULL)
1911 return NULL;
1912
1913 cursor.option = nir_cursor_before_block;
1914 return cursor_next_instr(cursor);
1915
1916 case nir_cursor_before_instr:
1917 return cursor.instr;
1918
1919 case nir_cursor_after_instr:
1920 if (nir_instr_next(cursor.instr))
1921 return nir_instr_next(cursor.instr);
1922
1923 cursor.option = nir_cursor_after_block;
1924 cursor.block = cursor.instr->block;
1925 return cursor_next_instr(cursor);
1926 }
1927
1928 unreachable("Inavlid cursor option");
1929 }
1930
1931 ASSERTED static bool
1932 dest_is_ssa(nir_dest *dest, void *_state)
1933 {
1934 (void) _state;
1935 return dest->is_ssa;
1936 }
1937
1938 bool
1939 nir_function_impl_lower_instructions(nir_function_impl *impl,
1940 nir_instr_filter_cb filter,
1941 nir_lower_instr_cb lower,
1942 void *cb_data)
1943 {
1944 nir_builder b;
1945 nir_builder_init(&b, impl);
1946
1947 nir_metadata preserved = nir_metadata_block_index |
1948 nir_metadata_dominance;
1949
1950 bool progress = false;
1951 nir_cursor iter = nir_before_cf_list(&impl->body);
1952 nir_instr *instr;
1953 while ((instr = cursor_next_instr(iter)) != NULL) {
1954 if (filter && !filter(instr, cb_data)) {
1955 iter = nir_after_instr(instr);
1956 continue;
1957 }
1958
1959 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1960 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1961 if (old_def == NULL) {
1962 iter = nir_after_instr(instr);
1963 continue;
1964 }
1965
1966 /* We're about to ask the callback to generate a replacement for instr.
1967 * Save off the uses from instr's SSA def so we know what uses to
1968 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1969 * case where the generated replacement code uses the result of instr
1970 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1971 * normal solution to this problem), it doesn't work well if control-
1972 * flow is inserted as part of the replacement, doesn't handle cases
1973 * where the replacement is something consumed by instr, and suffers
1974 * from performance issues. This is the only way to 100% guarantee
1975 * that we rewrite the correct set efficiently.
1976 */
1977 struct list_head old_uses, old_if_uses;
1978 list_replace(&old_def->uses, &old_uses);
1979 list_inithead(&old_def->uses);
1980 list_replace(&old_def->if_uses, &old_if_uses);
1981 list_inithead(&old_def->if_uses);
1982
1983 b.cursor = nir_after_instr(instr);
1984 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1985 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1986 assert(old_def != NULL);
1987 if (new_def->parent_instr->block != instr->block)
1988 preserved = nir_metadata_none;
1989
1990 nir_src new_src = nir_src_for_ssa(new_def);
1991 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1992 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1993
1994 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1995 nir_if_rewrite_condition(use_src->parent_if, new_src);
1996
1997 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1998 iter = nir_instr_remove(instr);
1999 } else {
2000 iter = nir_after_instr(instr);
2001 }
2002 progress = true;
2003 } else {
2004 /* We didn't end up lowering after all. Put the uses back */
2005 if (old_def) {
2006 list_replace(&old_uses, &old_def->uses);
2007 list_replace(&old_if_uses, &old_def->if_uses);
2008 }
2009 iter = nir_after_instr(instr);
2010
2011 if (new_def == NIR_LOWER_INSTR_PROGRESS)
2012 progress = true;
2013 }
2014 }
2015
2016 if (progress) {
2017 nir_metadata_preserve(impl, preserved);
2018 } else {
2019 nir_metadata_preserve(impl, nir_metadata_all);
2020 }
2021
2022 return progress;
2023 }
2024
2025 bool
2026 nir_shader_lower_instructions(nir_shader *shader,
2027 nir_instr_filter_cb filter,
2028 nir_lower_instr_cb lower,
2029 void *cb_data)
2030 {
2031 bool progress = false;
2032
2033 nir_foreach_function(function, shader) {
2034 if (function->impl &&
2035 nir_function_impl_lower_instructions(function->impl,
2036 filter, lower, cb_data))
2037 progress = true;
2038 }
2039
2040 return progress;
2041 }
2042
2043 nir_intrinsic_op
2044 nir_intrinsic_from_system_value(gl_system_value val)
2045 {
2046 switch (val) {
2047 case SYSTEM_VALUE_VERTEX_ID:
2048 return nir_intrinsic_load_vertex_id;
2049 case SYSTEM_VALUE_INSTANCE_ID:
2050 return nir_intrinsic_load_instance_id;
2051 case SYSTEM_VALUE_DRAW_ID:
2052 return nir_intrinsic_load_draw_id;
2053 case SYSTEM_VALUE_BASE_INSTANCE:
2054 return nir_intrinsic_load_base_instance;
2055 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2056 return nir_intrinsic_load_vertex_id_zero_base;
2057 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2058 return nir_intrinsic_load_is_indexed_draw;
2059 case SYSTEM_VALUE_FIRST_VERTEX:
2060 return nir_intrinsic_load_first_vertex;
2061 case SYSTEM_VALUE_BASE_VERTEX:
2062 return nir_intrinsic_load_base_vertex;
2063 case SYSTEM_VALUE_INVOCATION_ID:
2064 return nir_intrinsic_load_invocation_id;
2065 case SYSTEM_VALUE_FRAG_COORD:
2066 return nir_intrinsic_load_frag_coord;
2067 case SYSTEM_VALUE_POINT_COORD:
2068 return nir_intrinsic_load_point_coord;
2069 case SYSTEM_VALUE_LINE_COORD:
2070 return nir_intrinsic_load_line_coord;
2071 case SYSTEM_VALUE_FRONT_FACE:
2072 return nir_intrinsic_load_front_face;
2073 case SYSTEM_VALUE_SAMPLE_ID:
2074 return nir_intrinsic_load_sample_id;
2075 case SYSTEM_VALUE_SAMPLE_POS:
2076 return nir_intrinsic_load_sample_pos;
2077 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2078 return nir_intrinsic_load_sample_mask_in;
2079 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2080 return nir_intrinsic_load_local_invocation_id;
2081 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2082 return nir_intrinsic_load_local_invocation_index;
2083 case SYSTEM_VALUE_WORK_GROUP_ID:
2084 return nir_intrinsic_load_work_group_id;
2085 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2086 return nir_intrinsic_load_num_work_groups;
2087 case SYSTEM_VALUE_PRIMITIVE_ID:
2088 return nir_intrinsic_load_primitive_id;
2089 case SYSTEM_VALUE_TESS_COORD:
2090 return nir_intrinsic_load_tess_coord;
2091 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2092 return nir_intrinsic_load_tess_level_outer;
2093 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2094 return nir_intrinsic_load_tess_level_inner;
2095 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2096 return nir_intrinsic_load_tess_level_outer_default;
2097 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2098 return nir_intrinsic_load_tess_level_inner_default;
2099 case SYSTEM_VALUE_VERTICES_IN:
2100 return nir_intrinsic_load_patch_vertices_in;
2101 case SYSTEM_VALUE_HELPER_INVOCATION:
2102 return nir_intrinsic_load_helper_invocation;
2103 case SYSTEM_VALUE_COLOR0:
2104 return nir_intrinsic_load_color0;
2105 case SYSTEM_VALUE_COLOR1:
2106 return nir_intrinsic_load_color1;
2107 case SYSTEM_VALUE_VIEW_INDEX:
2108 return nir_intrinsic_load_view_index;
2109 case SYSTEM_VALUE_SUBGROUP_SIZE:
2110 return nir_intrinsic_load_subgroup_size;
2111 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2112 return nir_intrinsic_load_subgroup_invocation;
2113 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2114 return nir_intrinsic_load_subgroup_eq_mask;
2115 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2116 return nir_intrinsic_load_subgroup_ge_mask;
2117 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2118 return nir_intrinsic_load_subgroup_gt_mask;
2119 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2120 return nir_intrinsic_load_subgroup_le_mask;
2121 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2122 return nir_intrinsic_load_subgroup_lt_mask;
2123 case SYSTEM_VALUE_NUM_SUBGROUPS:
2124 return nir_intrinsic_load_num_subgroups;
2125 case SYSTEM_VALUE_SUBGROUP_ID:
2126 return nir_intrinsic_load_subgroup_id;
2127 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2128 return nir_intrinsic_load_local_group_size;
2129 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2130 return nir_intrinsic_load_global_invocation_id;
2131 case SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID:
2132 return nir_intrinsic_load_base_global_invocation_id;
2133 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2134 return nir_intrinsic_load_global_invocation_index;
2135 case SYSTEM_VALUE_WORK_DIM:
2136 return nir_intrinsic_load_work_dim;
2137 case SYSTEM_VALUE_USER_DATA_AMD:
2138 return nir_intrinsic_load_user_data_amd;
2139 default:
2140 unreachable("system value does not directly correspond to intrinsic");
2141 }
2142 }
2143
2144 gl_system_value
2145 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2146 {
2147 switch (intrin) {
2148 case nir_intrinsic_load_vertex_id:
2149 return SYSTEM_VALUE_VERTEX_ID;
2150 case nir_intrinsic_load_instance_id:
2151 return SYSTEM_VALUE_INSTANCE_ID;
2152 case nir_intrinsic_load_draw_id:
2153 return SYSTEM_VALUE_DRAW_ID;
2154 case nir_intrinsic_load_base_instance:
2155 return SYSTEM_VALUE_BASE_INSTANCE;
2156 case nir_intrinsic_load_vertex_id_zero_base:
2157 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2158 case nir_intrinsic_load_first_vertex:
2159 return SYSTEM_VALUE_FIRST_VERTEX;
2160 case nir_intrinsic_load_is_indexed_draw:
2161 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2162 case nir_intrinsic_load_base_vertex:
2163 return SYSTEM_VALUE_BASE_VERTEX;
2164 case nir_intrinsic_load_invocation_id:
2165 return SYSTEM_VALUE_INVOCATION_ID;
2166 case nir_intrinsic_load_frag_coord:
2167 return SYSTEM_VALUE_FRAG_COORD;
2168 case nir_intrinsic_load_point_coord:
2169 return SYSTEM_VALUE_POINT_COORD;
2170 case nir_intrinsic_load_line_coord:
2171 return SYSTEM_VALUE_LINE_COORD;
2172 case nir_intrinsic_load_front_face:
2173 return SYSTEM_VALUE_FRONT_FACE;
2174 case nir_intrinsic_load_sample_id:
2175 return SYSTEM_VALUE_SAMPLE_ID;
2176 case nir_intrinsic_load_sample_pos:
2177 return SYSTEM_VALUE_SAMPLE_POS;
2178 case nir_intrinsic_load_sample_mask_in:
2179 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2180 case nir_intrinsic_load_local_invocation_id:
2181 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2182 case nir_intrinsic_load_local_invocation_index:
2183 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2184 case nir_intrinsic_load_num_work_groups:
2185 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2186 case nir_intrinsic_load_work_group_id:
2187 return SYSTEM_VALUE_WORK_GROUP_ID;
2188 case nir_intrinsic_load_primitive_id:
2189 return SYSTEM_VALUE_PRIMITIVE_ID;
2190 case nir_intrinsic_load_tess_coord:
2191 return SYSTEM_VALUE_TESS_COORD;
2192 case nir_intrinsic_load_tess_level_outer:
2193 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2194 case nir_intrinsic_load_tess_level_inner:
2195 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2196 case nir_intrinsic_load_tess_level_outer_default:
2197 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2198 case nir_intrinsic_load_tess_level_inner_default:
2199 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2200 case nir_intrinsic_load_patch_vertices_in:
2201 return SYSTEM_VALUE_VERTICES_IN;
2202 case nir_intrinsic_load_helper_invocation:
2203 return SYSTEM_VALUE_HELPER_INVOCATION;
2204 case nir_intrinsic_load_color0:
2205 return SYSTEM_VALUE_COLOR0;
2206 case nir_intrinsic_load_color1:
2207 return SYSTEM_VALUE_COLOR1;
2208 case nir_intrinsic_load_view_index:
2209 return SYSTEM_VALUE_VIEW_INDEX;
2210 case nir_intrinsic_load_subgroup_size:
2211 return SYSTEM_VALUE_SUBGROUP_SIZE;
2212 case nir_intrinsic_load_subgroup_invocation:
2213 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2214 case nir_intrinsic_load_subgroup_eq_mask:
2215 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2216 case nir_intrinsic_load_subgroup_ge_mask:
2217 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2218 case nir_intrinsic_load_subgroup_gt_mask:
2219 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2220 case nir_intrinsic_load_subgroup_le_mask:
2221 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2222 case nir_intrinsic_load_subgroup_lt_mask:
2223 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2224 case nir_intrinsic_load_num_subgroups:
2225 return SYSTEM_VALUE_NUM_SUBGROUPS;
2226 case nir_intrinsic_load_subgroup_id:
2227 return SYSTEM_VALUE_SUBGROUP_ID;
2228 case nir_intrinsic_load_local_group_size:
2229 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2230 case nir_intrinsic_load_global_invocation_id:
2231 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2232 case nir_intrinsic_load_base_global_invocation_id:
2233 return SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID;
2234 case nir_intrinsic_load_global_invocation_index:
2235 return SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX;
2236 case nir_intrinsic_load_work_dim:
2237 return SYSTEM_VALUE_WORK_DIM;
2238 case nir_intrinsic_load_user_data_amd:
2239 return SYSTEM_VALUE_USER_DATA_AMD;
2240 default:
2241 unreachable("intrinsic doesn't produce a system value");
2242 }
2243 }
2244
2245 /* OpenGL utility method that remaps the location attributes if they are
2246 * doubles. Not needed for vulkan due the differences on the input location
2247 * count for doubles on vulkan vs OpenGL
2248 *
2249 * The bitfield returned in dual_slot is one bit for each double input slot in
2250 * the original OpenGL single-slot input numbering. The mapping from old
2251 * locations to new locations is as follows:
2252 *
2253 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2254 */
2255 void
2256 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2257 {
2258 assert(shader->info.stage == MESA_SHADER_VERTEX);
2259
2260 *dual_slot = 0;
2261 nir_foreach_shader_in_variable(var, shader) {
2262 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2263 unsigned slots = glsl_count_attribute_slots(var->type, true);
2264 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2265 }
2266 }
2267
2268 nir_foreach_shader_in_variable(var, shader) {
2269 var->data.location +=
2270 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2271 }
2272 }
2273
2274 /* Returns an attribute mask that has been re-compacted using the given
2275 * dual_slot mask.
2276 */
2277 uint64_t
2278 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2279 {
2280 while (dual_slot) {
2281 unsigned loc = u_bit_scan64(&dual_slot);
2282 /* mask of all bits up to and including loc */
2283 uint64_t mask = BITFIELD64_MASK(loc + 1);
2284 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2285 }
2286 return attribs;
2287 }
2288
2289 void
2290 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2291 bool bindless)
2292 {
2293 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2294
2295 switch (intrin->intrinsic) {
2296 #define CASE(op) \
2297 case nir_intrinsic_image_deref_##op: \
2298 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2299 : nir_intrinsic_image_##op; \
2300 break;
2301 CASE(load)
2302 CASE(store)
2303 CASE(atomic_add)
2304 CASE(atomic_imin)
2305 CASE(atomic_umin)
2306 CASE(atomic_imax)
2307 CASE(atomic_umax)
2308 CASE(atomic_and)
2309 CASE(atomic_or)
2310 CASE(atomic_xor)
2311 CASE(atomic_exchange)
2312 CASE(atomic_comp_swap)
2313 CASE(atomic_fadd)
2314 CASE(atomic_inc_wrap)
2315 CASE(atomic_dec_wrap)
2316 CASE(size)
2317 CASE(samples)
2318 CASE(load_raw_intel)
2319 CASE(store_raw_intel)
2320 #undef CASE
2321 default:
2322 unreachable("Unhanded image intrinsic");
2323 }
2324
2325 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2326 nir_variable *var = nir_deref_instr_get_variable(deref);
2327
2328 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2329 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2330 nir_intrinsic_set_access(intrin, access | var->data.access);
2331 nir_intrinsic_set_format(intrin, var->data.image.format);
2332
2333 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2334 nir_src_for_ssa(src));
2335 }
2336
2337 unsigned
2338 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2339 {
2340 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2341 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2342 if (dim == GLSL_SAMPLER_DIM_CUBE)
2343 return coords;
2344 else
2345 return coords + nir_intrinsic_image_array(instr);
2346 }