nir: Add a helper for creating a "bare" nir_function_impl
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_control_flow_private.h"
30 #include <assert.h>
31
32 nir_shader *
33 nir_shader_create(void *mem_ctx,
34 gl_shader_stage stage,
35 const nir_shader_compiler_options *options)
36 {
37 nir_shader *shader = ralloc(mem_ctx, nir_shader);
38
39 exec_list_make_empty(&shader->uniforms);
40 exec_list_make_empty(&shader->inputs);
41 exec_list_make_empty(&shader->outputs);
42
43 shader->options = options;
44 memset(&shader->info, 0, sizeof(shader->info));
45
46 exec_list_make_empty(&shader->functions);
47 exec_list_make_empty(&shader->registers);
48 exec_list_make_empty(&shader->globals);
49 exec_list_make_empty(&shader->system_values);
50 shader->reg_alloc = 0;
51
52 shader->num_inputs = 0;
53 shader->num_outputs = 0;
54 shader->num_uniforms = 0;
55
56 shader->stage = stage;
57
58 return shader;
59 }
60
61 static nir_register *
62 reg_create(void *mem_ctx, struct exec_list *list)
63 {
64 nir_register *reg = ralloc(mem_ctx, nir_register);
65
66 list_inithead(&reg->uses);
67 list_inithead(&reg->defs);
68 list_inithead(&reg->if_uses);
69
70 reg->num_components = 0;
71 reg->num_array_elems = 0;
72 reg->is_packed = false;
73 reg->name = NULL;
74
75 exec_list_push_tail(list, &reg->node);
76
77 return reg;
78 }
79
80 nir_register *
81 nir_global_reg_create(nir_shader *shader)
82 {
83 nir_register *reg = reg_create(shader, &shader->registers);
84 reg->index = shader->reg_alloc++;
85 reg->is_global = true;
86
87 return reg;
88 }
89
90 nir_register *
91 nir_local_reg_create(nir_function_impl *impl)
92 {
93 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
94 reg->index = impl->reg_alloc++;
95 reg->is_global = false;
96
97 return reg;
98 }
99
100 void
101 nir_reg_remove(nir_register *reg)
102 {
103 exec_node_remove(&reg->node);
104 }
105
106 void
107 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
108 {
109 switch (var->data.mode) {
110 case nir_var_all:
111 assert(!"invalid mode");
112 break;
113
114 case nir_var_local:
115 assert(!"nir_shader_add_variable cannot be used for local variables");
116 break;
117
118 case nir_var_param:
119 assert(!"nir_shader_add_variable cannot be used for function parameters");
120 break;
121
122 case nir_var_global:
123 exec_list_push_tail(&shader->globals, &var->node);
124 break;
125
126 case nir_var_shader_in:
127 exec_list_push_tail(&shader->inputs, &var->node);
128 break;
129
130 case nir_var_shader_out:
131 exec_list_push_tail(&shader->outputs, &var->node);
132 break;
133
134 case nir_var_uniform:
135 case nir_var_shader_storage:
136 exec_list_push_tail(&shader->uniforms, &var->node);
137 break;
138
139 case nir_var_system_value:
140 exec_list_push_tail(&shader->system_values, &var->node);
141 break;
142 }
143 }
144
145 nir_variable *
146 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
147 const struct glsl_type *type, const char *name)
148 {
149 nir_variable *var = rzalloc(shader, nir_variable);
150 var->name = ralloc_strdup(var, name);
151 var->type = type;
152 var->data.mode = mode;
153
154 if ((mode == nir_var_shader_in && shader->stage != MESA_SHADER_VERTEX) ||
155 (mode == nir_var_shader_out && shader->stage != MESA_SHADER_FRAGMENT))
156 var->data.interpolation = INTERP_QUALIFIER_SMOOTH;
157
158 if (mode == nir_var_shader_in || mode == nir_var_uniform)
159 var->data.read_only = true;
160
161 nir_shader_add_variable(shader, var);
162
163 return var;
164 }
165
166 nir_variable *
167 nir_local_variable_create(nir_function_impl *impl,
168 const struct glsl_type *type, const char *name)
169 {
170 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
171 var->name = ralloc_strdup(var, name);
172 var->type = type;
173 var->data.mode = nir_var_local;
174
175 nir_function_impl_add_variable(impl, var);
176
177 return var;
178 }
179
180 nir_function *
181 nir_function_create(nir_shader *shader, const char *name)
182 {
183 nir_function *func = ralloc(shader, nir_function);
184
185 exec_list_push_tail(&shader->functions, &func->node);
186
187 func->name = ralloc_strdup(func, name);
188 func->shader = shader;
189 func->num_params = 0;
190 func->params = NULL;
191 func->return_type = glsl_void_type();
192 func->impl = NULL;
193
194 return func;
195 }
196
197 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
198 {
199 dest->is_ssa = src->is_ssa;
200 if (src->is_ssa) {
201 dest->ssa = src->ssa;
202 } else {
203 dest->reg.base_offset = src->reg.base_offset;
204 dest->reg.reg = src->reg.reg;
205 if (src->reg.indirect) {
206 dest->reg.indirect = ralloc(mem_ctx, nir_src);
207 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
208 } else {
209 dest->reg.indirect = NULL;
210 }
211 }
212 }
213
214 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
215 {
216 /* Copying an SSA definition makes no sense whatsoever. */
217 assert(!src->is_ssa);
218
219 dest->is_ssa = false;
220
221 dest->reg.base_offset = src->reg.base_offset;
222 dest->reg.reg = src->reg.reg;
223 if (src->reg.indirect) {
224 dest->reg.indirect = ralloc(instr, nir_src);
225 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
226 } else {
227 dest->reg.indirect = NULL;
228 }
229 }
230
231 void
232 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
233 nir_alu_instr *instr)
234 {
235 nir_src_copy(&dest->src, &src->src, &instr->instr);
236 dest->abs = src->abs;
237 dest->negate = src->negate;
238 for (unsigned i = 0; i < 4; i++)
239 dest->swizzle[i] = src->swizzle[i];
240 }
241
242 void
243 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
244 nir_alu_instr *instr)
245 {
246 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
247 dest->write_mask = src->write_mask;
248 dest->saturate = src->saturate;
249 }
250
251
252 static void
253 cf_init(nir_cf_node *node, nir_cf_node_type type)
254 {
255 exec_node_init(&node->node);
256 node->parent = NULL;
257 node->type = type;
258 }
259
260 nir_function_impl *
261 nir_function_impl_create_bare(nir_shader *shader)
262 {
263 nir_function_impl *impl = ralloc(shader, nir_function_impl);
264
265 impl->function = NULL;
266
267 cf_init(&impl->cf_node, nir_cf_node_function);
268
269 exec_list_make_empty(&impl->body);
270 exec_list_make_empty(&impl->registers);
271 exec_list_make_empty(&impl->locals);
272 impl->num_params = 0;
273 impl->params = NULL;
274 impl->return_var = NULL;
275 impl->reg_alloc = 0;
276 impl->ssa_alloc = 0;
277 impl->valid_metadata = nir_metadata_none;
278
279 /* create start & end blocks */
280 nir_block *start_block = nir_block_create(shader);
281 nir_block *end_block = nir_block_create(shader);
282 start_block->cf_node.parent = &impl->cf_node;
283 end_block->cf_node.parent = &impl->cf_node;
284 impl->end_block = end_block;
285
286 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
287
288 start_block->successors[0] = end_block;
289 _mesa_set_add(end_block->predecessors, start_block);
290 return impl;
291 }
292
293 nir_function_impl *
294 nir_function_impl_create(nir_function *function)
295 {
296 assert(function->impl == NULL);
297
298 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
299
300 function->impl = impl;
301 impl->function = function;
302
303 return impl;
304 }
305
306 nir_block *
307 nir_block_create(nir_shader *shader)
308 {
309 nir_block *block = ralloc(shader, nir_block);
310
311 cf_init(&block->cf_node, nir_cf_node_block);
312
313 block->successors[0] = block->successors[1] = NULL;
314 block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
315 _mesa_key_pointer_equal);
316 block->imm_dom = NULL;
317 /* XXX maybe it would be worth it to defer allocation? This
318 * way it doesn't get allocated for shader ref's that never run
319 * nir_calc_dominance? For example, state-tracker creates an
320 * initial IR, clones that, runs appropriate lowering pass, passes
321 * to driver which does common lowering/opt, and then stores ref
322 * which is later used to do state specific lowering and futher
323 * opt. Do any of the references not need dominance metadata?
324 */
325 block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
326 _mesa_key_pointer_equal);
327
328 exec_list_make_empty(&block->instr_list);
329
330 return block;
331 }
332
333 static inline void
334 src_init(nir_src *src)
335 {
336 src->is_ssa = false;
337 src->reg.reg = NULL;
338 src->reg.indirect = NULL;
339 src->reg.base_offset = 0;
340 }
341
342 nir_if *
343 nir_if_create(nir_shader *shader)
344 {
345 nir_if *if_stmt = ralloc(shader, nir_if);
346
347 cf_init(&if_stmt->cf_node, nir_cf_node_if);
348 src_init(&if_stmt->condition);
349
350 nir_block *then = nir_block_create(shader);
351 exec_list_make_empty(&if_stmt->then_list);
352 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
353 then->cf_node.parent = &if_stmt->cf_node;
354
355 nir_block *else_stmt = nir_block_create(shader);
356 exec_list_make_empty(&if_stmt->else_list);
357 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
358 else_stmt->cf_node.parent = &if_stmt->cf_node;
359
360 return if_stmt;
361 }
362
363 nir_loop *
364 nir_loop_create(nir_shader *shader)
365 {
366 nir_loop *loop = ralloc(shader, nir_loop);
367
368 cf_init(&loop->cf_node, nir_cf_node_loop);
369
370 nir_block *body = nir_block_create(shader);
371 exec_list_make_empty(&loop->body);
372 exec_list_push_tail(&loop->body, &body->cf_node.node);
373 body->cf_node.parent = &loop->cf_node;
374
375 body->successors[0] = body;
376 _mesa_set_add(body->predecessors, body);
377
378 return loop;
379 }
380
381 static void
382 instr_init(nir_instr *instr, nir_instr_type type)
383 {
384 instr->type = type;
385 instr->block = NULL;
386 exec_node_init(&instr->node);
387 }
388
389 static void
390 dest_init(nir_dest *dest)
391 {
392 dest->is_ssa = false;
393 dest->reg.reg = NULL;
394 dest->reg.indirect = NULL;
395 dest->reg.base_offset = 0;
396 }
397
398 static void
399 alu_dest_init(nir_alu_dest *dest)
400 {
401 dest_init(&dest->dest);
402 dest->saturate = false;
403 dest->write_mask = 0xf;
404 }
405
406 static void
407 alu_src_init(nir_alu_src *src)
408 {
409 src_init(&src->src);
410 src->abs = src->negate = false;
411 src->swizzle[0] = 0;
412 src->swizzle[1] = 1;
413 src->swizzle[2] = 2;
414 src->swizzle[3] = 3;
415 }
416
417 nir_alu_instr *
418 nir_alu_instr_create(nir_shader *shader, nir_op op)
419 {
420 unsigned num_srcs = nir_op_infos[op].num_inputs;
421 nir_alu_instr *instr =
422 ralloc_size(shader,
423 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
424
425 instr_init(&instr->instr, nir_instr_type_alu);
426 instr->op = op;
427 alu_dest_init(&instr->dest);
428 for (unsigned i = 0; i < num_srcs; i++)
429 alu_src_init(&instr->src[i]);
430
431 return instr;
432 }
433
434 nir_jump_instr *
435 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
436 {
437 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
438 instr_init(&instr->instr, nir_instr_type_jump);
439 instr->type = type;
440 return instr;
441 }
442
443 nir_load_const_instr *
444 nir_load_const_instr_create(nir_shader *shader, unsigned num_components)
445 {
446 nir_load_const_instr *instr = ralloc(shader, nir_load_const_instr);
447 instr_init(&instr->instr, nir_instr_type_load_const);
448
449 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
450
451 return instr;
452 }
453
454 nir_intrinsic_instr *
455 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
456 {
457 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
458 nir_intrinsic_instr *instr =
459 ralloc_size(shader,
460 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
461
462 instr_init(&instr->instr, nir_instr_type_intrinsic);
463 instr->intrinsic = op;
464
465 if (nir_intrinsic_infos[op].has_dest)
466 dest_init(&instr->dest);
467
468 for (unsigned i = 0; i < num_srcs; i++)
469 src_init(&instr->src[i]);
470
471 return instr;
472 }
473
474 nir_call_instr *
475 nir_call_instr_create(nir_shader *shader, nir_function *callee)
476 {
477 nir_call_instr *instr = ralloc(shader, nir_call_instr);
478 instr_init(&instr->instr, nir_instr_type_call);
479
480 instr->callee = callee;
481 instr->num_params = callee->num_params;
482 instr->params = ralloc_array(instr, nir_deref_var *, instr->num_params);
483 instr->return_deref = NULL;
484
485 return instr;
486 }
487
488 nir_tex_instr *
489 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
490 {
491 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
492 instr_init(&instr->instr, nir_instr_type_tex);
493
494 dest_init(&instr->dest);
495
496 instr->num_srcs = num_srcs;
497 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
498 for (unsigned i = 0; i < num_srcs; i++)
499 src_init(&instr->src[i].src);
500
501 instr->texture_index = 0;
502 instr->texture_array_size = 0;
503 instr->texture = NULL;
504 instr->sampler_index = 0;
505 instr->sampler = NULL;
506
507 return instr;
508 }
509
510 nir_phi_instr *
511 nir_phi_instr_create(nir_shader *shader)
512 {
513 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
514 instr_init(&instr->instr, nir_instr_type_phi);
515
516 dest_init(&instr->dest);
517 exec_list_make_empty(&instr->srcs);
518 return instr;
519 }
520
521 nir_parallel_copy_instr *
522 nir_parallel_copy_instr_create(nir_shader *shader)
523 {
524 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
525 instr_init(&instr->instr, nir_instr_type_parallel_copy);
526
527 exec_list_make_empty(&instr->entries);
528
529 return instr;
530 }
531
532 nir_ssa_undef_instr *
533 nir_ssa_undef_instr_create(nir_shader *shader, unsigned num_components)
534 {
535 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
536 instr_init(&instr->instr, nir_instr_type_ssa_undef);
537
538 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
539
540 return instr;
541 }
542
543 nir_deref_var *
544 nir_deref_var_create(void *mem_ctx, nir_variable *var)
545 {
546 nir_deref_var *deref = ralloc(mem_ctx, nir_deref_var);
547 deref->deref.deref_type = nir_deref_type_var;
548 deref->deref.child = NULL;
549 deref->deref.type = var->type;
550 deref->var = var;
551 return deref;
552 }
553
554 nir_deref_array *
555 nir_deref_array_create(void *mem_ctx)
556 {
557 nir_deref_array *deref = ralloc(mem_ctx, nir_deref_array);
558 deref->deref.deref_type = nir_deref_type_array;
559 deref->deref.child = NULL;
560 deref->deref_array_type = nir_deref_array_type_direct;
561 src_init(&deref->indirect);
562 deref->base_offset = 0;
563 return deref;
564 }
565
566 nir_deref_struct *
567 nir_deref_struct_create(void *mem_ctx, unsigned field_index)
568 {
569 nir_deref_struct *deref = ralloc(mem_ctx, nir_deref_struct);
570 deref->deref.deref_type = nir_deref_type_struct;
571 deref->deref.child = NULL;
572 deref->index = field_index;
573 return deref;
574 }
575
576 static nir_deref_var *
577 copy_deref_var(void *mem_ctx, nir_deref_var *deref)
578 {
579 nir_deref_var *ret = nir_deref_var_create(mem_ctx, deref->var);
580 ret->deref.type = deref->deref.type;
581 if (deref->deref.child)
582 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
583 return ret;
584 }
585
586 static nir_deref_array *
587 copy_deref_array(void *mem_ctx, nir_deref_array *deref)
588 {
589 nir_deref_array *ret = nir_deref_array_create(mem_ctx);
590 ret->base_offset = deref->base_offset;
591 ret->deref_array_type = deref->deref_array_type;
592 if (deref->deref_array_type == nir_deref_array_type_indirect) {
593 nir_src_copy(&ret->indirect, &deref->indirect, mem_ctx);
594 }
595 ret->deref.type = deref->deref.type;
596 if (deref->deref.child)
597 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
598 return ret;
599 }
600
601 static nir_deref_struct *
602 copy_deref_struct(void *mem_ctx, nir_deref_struct *deref)
603 {
604 nir_deref_struct *ret = nir_deref_struct_create(mem_ctx, deref->index);
605 ret->deref.type = deref->deref.type;
606 if (deref->deref.child)
607 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
608 return ret;
609 }
610
611 nir_deref *
612 nir_copy_deref(void *mem_ctx, nir_deref *deref)
613 {
614 switch (deref->deref_type) {
615 case nir_deref_type_var:
616 return &copy_deref_var(mem_ctx, nir_deref_as_var(deref))->deref;
617 case nir_deref_type_array:
618 return &copy_deref_array(mem_ctx, nir_deref_as_array(deref))->deref;
619 case nir_deref_type_struct:
620 return &copy_deref_struct(mem_ctx, nir_deref_as_struct(deref))->deref;
621 default:
622 unreachable("Invalid dereference type");
623 }
624
625 return NULL;
626 }
627
628 /* Returns a load_const instruction that represents the constant
629 * initializer for the given deref chain. The caller is responsible for
630 * ensuring that there actually is a constant initializer.
631 */
632 nir_load_const_instr *
633 nir_deref_get_const_initializer_load(nir_shader *shader, nir_deref_var *deref)
634 {
635 nir_constant *constant = deref->var->constant_initializer;
636 assert(constant);
637
638 const nir_deref *tail = &deref->deref;
639 unsigned matrix_offset = 0;
640 while (tail->child) {
641 switch (tail->child->deref_type) {
642 case nir_deref_type_array: {
643 nir_deref_array *arr = nir_deref_as_array(tail->child);
644 assert(arr->deref_array_type == nir_deref_array_type_direct);
645 if (glsl_type_is_matrix(tail->type)) {
646 assert(arr->deref.child == NULL);
647 matrix_offset = arr->base_offset;
648 } else {
649 constant = constant->elements[arr->base_offset];
650 }
651 break;
652 }
653
654 case nir_deref_type_struct: {
655 constant = constant->elements[nir_deref_as_struct(tail->child)->index];
656 break;
657 }
658
659 default:
660 unreachable("Invalid deref child type");
661 }
662
663 tail = tail->child;
664 }
665
666 nir_load_const_instr *load =
667 nir_load_const_instr_create(shader, glsl_get_vector_elements(tail->type));
668
669 matrix_offset *= load->def.num_components;
670 for (unsigned i = 0; i < load->def.num_components; i++) {
671 switch (glsl_get_base_type(tail->type)) {
672 case GLSL_TYPE_FLOAT:
673 case GLSL_TYPE_INT:
674 case GLSL_TYPE_UINT:
675 load->value.u[i] = constant->value.u[matrix_offset + i];
676 break;
677 case GLSL_TYPE_BOOL:
678 load->value.u[i] = constant->value.b[matrix_offset + i] ?
679 NIR_TRUE : NIR_FALSE;
680 break;
681 default:
682 unreachable("Invalid immediate type");
683 }
684 }
685
686 return load;
687 }
688
689 nir_function_impl *
690 nir_cf_node_get_function(nir_cf_node *node)
691 {
692 while (node->type != nir_cf_node_function) {
693 node = node->parent;
694 }
695
696 return nir_cf_node_as_function(node);
697 }
698
699 static bool
700 add_use_cb(nir_src *src, void *state)
701 {
702 nir_instr *instr = state;
703
704 src->parent_instr = instr;
705 list_addtail(&src->use_link,
706 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
707
708 return true;
709 }
710
711 static bool
712 add_ssa_def_cb(nir_ssa_def *def, void *state)
713 {
714 nir_instr *instr = state;
715
716 if (instr->block && def->index == UINT_MAX) {
717 nir_function_impl *impl =
718 nir_cf_node_get_function(&instr->block->cf_node);
719
720 def->index = impl->ssa_alloc++;
721 }
722
723 return true;
724 }
725
726 static bool
727 add_reg_def_cb(nir_dest *dest, void *state)
728 {
729 nir_instr *instr = state;
730
731 if (!dest->is_ssa) {
732 dest->reg.parent_instr = instr;
733 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
734 }
735
736 return true;
737 }
738
739 static void
740 add_defs_uses(nir_instr *instr)
741 {
742 nir_foreach_src(instr, add_use_cb, instr);
743 nir_foreach_dest(instr, add_reg_def_cb, instr);
744 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
745 }
746
747 void
748 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
749 {
750 switch (cursor.option) {
751 case nir_cursor_before_block:
752 /* Only allow inserting jumps into empty blocks. */
753 if (instr->type == nir_instr_type_jump)
754 assert(exec_list_is_empty(&cursor.block->instr_list));
755
756 instr->block = cursor.block;
757 add_defs_uses(instr);
758 exec_list_push_head(&cursor.block->instr_list, &instr->node);
759 break;
760 case nir_cursor_after_block: {
761 /* Inserting instructions after a jump is illegal. */
762 nir_instr *last = nir_block_last_instr(cursor.block);
763 assert(last == NULL || last->type != nir_instr_type_jump);
764 (void) last;
765
766 instr->block = cursor.block;
767 add_defs_uses(instr);
768 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
769 break;
770 }
771 case nir_cursor_before_instr:
772 assert(instr->type != nir_instr_type_jump);
773 instr->block = cursor.instr->block;
774 add_defs_uses(instr);
775 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
776 break;
777 case nir_cursor_after_instr:
778 /* Inserting instructions after a jump is illegal. */
779 assert(cursor.instr->type != nir_instr_type_jump);
780
781 /* Only allow inserting jumps at the end of the block. */
782 if (instr->type == nir_instr_type_jump)
783 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
784
785 instr->block = cursor.instr->block;
786 add_defs_uses(instr);
787 exec_node_insert_after(&cursor.instr->node, &instr->node);
788 break;
789 }
790
791 if (instr->type == nir_instr_type_jump)
792 nir_handle_add_jump(instr->block);
793 }
794
795 static bool
796 src_is_valid(const nir_src *src)
797 {
798 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
799 }
800
801 static bool
802 remove_use_cb(nir_src *src, void *state)
803 {
804 if (src_is_valid(src))
805 list_del(&src->use_link);
806
807 return true;
808 }
809
810 static bool
811 remove_def_cb(nir_dest *dest, void *state)
812 {
813 if (!dest->is_ssa)
814 list_del(&dest->reg.def_link);
815
816 return true;
817 }
818
819 static void
820 remove_defs_uses(nir_instr *instr)
821 {
822 nir_foreach_dest(instr, remove_def_cb, instr);
823 nir_foreach_src(instr, remove_use_cb, instr);
824 }
825
826 void nir_instr_remove(nir_instr *instr)
827 {
828 remove_defs_uses(instr);
829 exec_node_remove(&instr->node);
830
831 if (instr->type == nir_instr_type_jump) {
832 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
833 nir_handle_remove_jump(instr->block, jump_instr->type);
834 }
835 }
836
837 /*@}*/
838
839 void
840 nir_index_local_regs(nir_function_impl *impl)
841 {
842 unsigned index = 0;
843 foreach_list_typed(nir_register, reg, node, &impl->registers) {
844 reg->index = index++;
845 }
846 impl->reg_alloc = index;
847 }
848
849 void
850 nir_index_global_regs(nir_shader *shader)
851 {
852 unsigned index = 0;
853 foreach_list_typed(nir_register, reg, node, &shader->registers) {
854 reg->index = index++;
855 }
856 shader->reg_alloc = index;
857 }
858
859 static bool
860 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
861 {
862 return cb(&instr->dest.dest, state);
863 }
864
865 static bool
866 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
867 void *state)
868 {
869 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
870 return cb(&instr->dest, state);
871
872 return true;
873 }
874
875 static bool
876 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
877 void *state)
878 {
879 return cb(&instr->dest, state);
880 }
881
882 static bool
883 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
884 {
885 return cb(&instr->dest, state);
886 }
887
888 static bool
889 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
890 nir_foreach_dest_cb cb, void *state)
891 {
892 nir_foreach_parallel_copy_entry(instr, entry) {
893 if (!cb(&entry->dest, state))
894 return false;
895 }
896
897 return true;
898 }
899
900 bool
901 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
902 {
903 switch (instr->type) {
904 case nir_instr_type_alu:
905 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
906 case nir_instr_type_intrinsic:
907 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
908 case nir_instr_type_tex:
909 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
910 case nir_instr_type_phi:
911 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
912 case nir_instr_type_parallel_copy:
913 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
914 cb, state);
915
916 case nir_instr_type_load_const:
917 case nir_instr_type_ssa_undef:
918 case nir_instr_type_call:
919 case nir_instr_type_jump:
920 break;
921
922 default:
923 unreachable("Invalid instruction type");
924 break;
925 }
926
927 return true;
928 }
929
930 struct foreach_ssa_def_state {
931 nir_foreach_ssa_def_cb cb;
932 void *client_state;
933 };
934
935 static inline bool
936 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
937 {
938 struct foreach_ssa_def_state *state = void_state;
939
940 if (dest->is_ssa)
941 return state->cb(&dest->ssa, state->client_state);
942 else
943 return true;
944 }
945
946 bool
947 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
948 {
949 switch (instr->type) {
950 case nir_instr_type_alu:
951 case nir_instr_type_tex:
952 case nir_instr_type_intrinsic:
953 case nir_instr_type_phi:
954 case nir_instr_type_parallel_copy: {
955 struct foreach_ssa_def_state foreach_state = {cb, state};
956 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
957 }
958
959 case nir_instr_type_load_const:
960 return cb(&nir_instr_as_load_const(instr)->def, state);
961 case nir_instr_type_ssa_undef:
962 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
963 case nir_instr_type_call:
964 case nir_instr_type_jump:
965 return true;
966 default:
967 unreachable("Invalid instruction type");
968 }
969 }
970
971 static bool
972 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
973 {
974 if (!cb(src, state))
975 return false;
976 if (!src->is_ssa && src->reg.indirect)
977 return cb(src->reg.indirect, state);
978 return true;
979 }
980
981 static bool
982 visit_deref_array_src(nir_deref_array *deref, nir_foreach_src_cb cb,
983 void *state)
984 {
985 if (deref->deref_array_type == nir_deref_array_type_indirect)
986 return visit_src(&deref->indirect, cb, state);
987 return true;
988 }
989
990 static bool
991 visit_deref_src(nir_deref_var *deref, nir_foreach_src_cb cb, void *state)
992 {
993 nir_deref *cur = &deref->deref;
994 while (cur != NULL) {
995 if (cur->deref_type == nir_deref_type_array) {
996 if (!visit_deref_array_src(nir_deref_as_array(cur), cb, state))
997 return false;
998 }
999
1000 cur = cur->child;
1001 }
1002
1003 return true;
1004 }
1005
1006 static bool
1007 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1008 {
1009 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1010 if (!visit_src(&instr->src[i].src, cb, state))
1011 return false;
1012
1013 return true;
1014 }
1015
1016 static bool
1017 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1018 {
1019 for (unsigned i = 0; i < instr->num_srcs; i++) {
1020 if (!visit_src(&instr->src[i].src, cb, state))
1021 return false;
1022 }
1023
1024 if (instr->texture != NULL) {
1025 if (!visit_deref_src(instr->texture, cb, state))
1026 return false;
1027 }
1028
1029 if (instr->sampler != NULL) {
1030 if (!visit_deref_src(instr->sampler, cb, state))
1031 return false;
1032 }
1033
1034 return true;
1035 }
1036
1037 static bool
1038 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1039 void *state)
1040 {
1041 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1042 for (unsigned i = 0; i < num_srcs; i++) {
1043 if (!visit_src(&instr->src[i], cb, state))
1044 return false;
1045 }
1046
1047 unsigned num_vars =
1048 nir_intrinsic_infos[instr->intrinsic].num_variables;
1049 for (unsigned i = 0; i < num_vars; i++) {
1050 if (!visit_deref_src(instr->variables[i], cb, state))
1051 return false;
1052 }
1053
1054 return true;
1055 }
1056
1057 static bool
1058 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1059 {
1060 return true;
1061 }
1062
1063 static bool
1064 visit_load_const_src(nir_load_const_instr *instr, nir_foreach_src_cb cb,
1065 void *state)
1066 {
1067 return true;
1068 }
1069
1070 static bool
1071 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1072 {
1073 nir_foreach_phi_src(instr, src) {
1074 if (!visit_src(&src->src, cb, state))
1075 return false;
1076 }
1077
1078 return true;
1079 }
1080
1081 static bool
1082 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1083 nir_foreach_src_cb cb, void *state)
1084 {
1085 nir_foreach_parallel_copy_entry(instr, entry) {
1086 if (!visit_src(&entry->src, cb, state))
1087 return false;
1088 }
1089
1090 return true;
1091 }
1092
1093 typedef struct {
1094 void *state;
1095 nir_foreach_src_cb cb;
1096 } visit_dest_indirect_state;
1097
1098 static bool
1099 visit_dest_indirect(nir_dest *dest, void *_state)
1100 {
1101 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1102
1103 if (!dest->is_ssa && dest->reg.indirect)
1104 return state->cb(dest->reg.indirect, state->state);
1105
1106 return true;
1107 }
1108
1109 bool
1110 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1111 {
1112 switch (instr->type) {
1113 case nir_instr_type_alu:
1114 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1115 return false;
1116 break;
1117 case nir_instr_type_intrinsic:
1118 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1119 return false;
1120 break;
1121 case nir_instr_type_tex:
1122 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1123 return false;
1124 break;
1125 case nir_instr_type_call:
1126 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1127 return false;
1128 break;
1129 case nir_instr_type_load_const:
1130 if (!visit_load_const_src(nir_instr_as_load_const(instr), cb, state))
1131 return false;
1132 break;
1133 case nir_instr_type_phi:
1134 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1135 return false;
1136 break;
1137 case nir_instr_type_parallel_copy:
1138 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1139 cb, state))
1140 return false;
1141 break;
1142 case nir_instr_type_jump:
1143 case nir_instr_type_ssa_undef:
1144 return true;
1145
1146 default:
1147 unreachable("Invalid instruction type");
1148 break;
1149 }
1150
1151 visit_dest_indirect_state dest_state;
1152 dest_state.state = state;
1153 dest_state.cb = cb;
1154 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1155 }
1156
1157 nir_const_value *
1158 nir_src_as_const_value(nir_src src)
1159 {
1160 if (!src.is_ssa)
1161 return NULL;
1162
1163 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1164 return NULL;
1165
1166 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1167
1168 return &load->value;
1169 }
1170
1171 /**
1172 * Returns true if the source is known to be dynamically uniform. Otherwise it
1173 * returns false which means it may or may not be dynamically uniform but it
1174 * can't be determined.
1175 */
1176 bool
1177 nir_src_is_dynamically_uniform(nir_src src)
1178 {
1179 if (!src.is_ssa)
1180 return false;
1181
1182 /* Constants are trivially dynamically uniform */
1183 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1184 return true;
1185
1186 /* As are uniform variables */
1187 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1188 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1189
1190 if (intr->intrinsic == nir_intrinsic_load_uniform)
1191 return true;
1192 }
1193
1194 /* XXX: this could have many more tests, such as when a sampler function is
1195 * called with dynamically uniform arguments.
1196 */
1197 return false;
1198 }
1199
1200 static void
1201 src_remove_all_uses(nir_src *src)
1202 {
1203 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1204 if (!src_is_valid(src))
1205 continue;
1206
1207 list_del(&src->use_link);
1208 }
1209 }
1210
1211 static void
1212 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1213 {
1214 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1215 if (!src_is_valid(src))
1216 continue;
1217
1218 if (parent_instr) {
1219 src->parent_instr = parent_instr;
1220 if (src->is_ssa)
1221 list_addtail(&src->use_link, &src->ssa->uses);
1222 else
1223 list_addtail(&src->use_link, &src->reg.reg->uses);
1224 } else {
1225 assert(parent_if);
1226 src->parent_if = parent_if;
1227 if (src->is_ssa)
1228 list_addtail(&src->use_link, &src->ssa->if_uses);
1229 else
1230 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1231 }
1232 }
1233 }
1234
1235 void
1236 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1237 {
1238 assert(!src_is_valid(src) || src->parent_instr == instr);
1239
1240 src_remove_all_uses(src);
1241 *src = new_src;
1242 src_add_all_uses(src, instr, NULL);
1243 }
1244
1245 void
1246 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1247 {
1248 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1249
1250 src_remove_all_uses(dest);
1251 src_remove_all_uses(src);
1252 *dest = *src;
1253 *src = NIR_SRC_INIT;
1254 src_add_all_uses(dest, dest_instr, NULL);
1255 }
1256
1257 void
1258 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1259 {
1260 nir_src *src = &if_stmt->condition;
1261 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1262
1263 src_remove_all_uses(src);
1264 *src = new_src;
1265 src_add_all_uses(src, NULL, if_stmt);
1266 }
1267
1268 void
1269 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1270 {
1271 if (dest->is_ssa) {
1272 /* We can only overwrite an SSA destination if it has no uses. */
1273 assert(list_empty(&dest->ssa.uses) && list_empty(&dest->ssa.if_uses));
1274 } else {
1275 list_del(&dest->reg.def_link);
1276 if (dest->reg.indirect)
1277 src_remove_all_uses(dest->reg.indirect);
1278 }
1279
1280 /* We can't re-write with an SSA def */
1281 assert(!new_dest.is_ssa);
1282
1283 nir_dest_copy(dest, &new_dest, instr);
1284
1285 dest->reg.parent_instr = instr;
1286 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1287
1288 if (dest->reg.indirect)
1289 src_add_all_uses(dest->reg.indirect, instr, NULL);
1290 }
1291
1292 void
1293 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1294 unsigned num_components, const char *name)
1295 {
1296 def->name = name;
1297 def->parent_instr = instr;
1298 list_inithead(&def->uses);
1299 list_inithead(&def->if_uses);
1300 def->num_components = num_components;
1301
1302 if (instr->block) {
1303 nir_function_impl *impl =
1304 nir_cf_node_get_function(&instr->block->cf_node);
1305
1306 def->index = impl->ssa_alloc++;
1307 } else {
1308 def->index = UINT_MAX;
1309 }
1310 }
1311
1312 void
1313 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1314 unsigned num_components, const char *name)
1315 {
1316 dest->is_ssa = true;
1317 nir_ssa_def_init(instr, &dest->ssa, num_components, name);
1318 }
1319
1320 void
1321 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1322 {
1323 assert(!new_src.is_ssa || def != new_src.ssa);
1324
1325 nir_foreach_use_safe(def, use_src)
1326 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1327
1328 nir_foreach_if_use_safe(def, use_src)
1329 nir_if_rewrite_condition(use_src->parent_if, new_src);
1330 }
1331
1332 static bool
1333 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1334 {
1335 assert(start->block == end->block);
1336
1337 if (between->block != start->block)
1338 return false;
1339
1340 /* Search backwards looking for "between" */
1341 while (start != end) {
1342 if (between == end)
1343 return true;
1344
1345 end = nir_instr_prev(end);
1346 assert(end);
1347 }
1348
1349 return false;
1350 }
1351
1352 /* Replaces all uses of the given SSA def with the given source but only if
1353 * the use comes after the after_me instruction. This can be useful if you
1354 * are emitting code to fix up the result of some instruction: you can freely
1355 * use the result in that code and then call rewrite_uses_after and pass the
1356 * last fixup instruction as after_me and it will replace all of the uses you
1357 * want without touching the fixup code.
1358 *
1359 * This function assumes that after_me is in the same block as
1360 * def->parent_instr and that after_me comes after def->parent_instr.
1361 */
1362 void
1363 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1364 nir_instr *after_me)
1365 {
1366 assert(!new_src.is_ssa || def != new_src.ssa);
1367
1368 nir_foreach_use_safe(def, use_src) {
1369 assert(use_src->parent_instr != def->parent_instr);
1370 /* Since def already dominates all of its uses, the only way a use can
1371 * not be dominated by after_me is if it is between def and after_me in
1372 * the instruction list.
1373 */
1374 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1375 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1376 }
1377
1378 nir_foreach_if_use_safe(def, use_src)
1379 nir_if_rewrite_condition(use_src->parent_if, new_src);
1380 }
1381
1382 static bool foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1383 bool reverse, void *state);
1384
1385 static inline bool
1386 foreach_if(nir_if *if_stmt, nir_foreach_block_cb cb, bool reverse, void *state)
1387 {
1388 if (reverse) {
1389 foreach_list_typed_reverse_safe(nir_cf_node, node, node,
1390 &if_stmt->else_list) {
1391 if (!foreach_cf_node(node, cb, reverse, state))
1392 return false;
1393 }
1394
1395 foreach_list_typed_reverse_safe(nir_cf_node, node, node,
1396 &if_stmt->then_list) {
1397 if (!foreach_cf_node(node, cb, reverse, state))
1398 return false;
1399 }
1400 } else {
1401 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->then_list) {
1402 if (!foreach_cf_node(node, cb, reverse, state))
1403 return false;
1404 }
1405
1406 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->else_list) {
1407 if (!foreach_cf_node(node, cb, reverse, state))
1408 return false;
1409 }
1410 }
1411
1412 return true;
1413 }
1414
1415 static inline bool
1416 foreach_loop(nir_loop *loop, nir_foreach_block_cb cb, bool reverse, void *state)
1417 {
1418 if (reverse) {
1419 foreach_list_typed_reverse_safe(nir_cf_node, node, node, &loop->body) {
1420 if (!foreach_cf_node(node, cb, reverse, state))
1421 return false;
1422 }
1423 } else {
1424 foreach_list_typed_safe(nir_cf_node, node, node, &loop->body) {
1425 if (!foreach_cf_node(node, cb, reverse, state))
1426 return false;
1427 }
1428 }
1429
1430 return true;
1431 }
1432
1433 static bool
1434 foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1435 bool reverse, void *state)
1436 {
1437 switch (node->type) {
1438 case nir_cf_node_block:
1439 return cb(nir_cf_node_as_block(node), state);
1440 case nir_cf_node_if:
1441 return foreach_if(nir_cf_node_as_if(node), cb, reverse, state);
1442 case nir_cf_node_loop:
1443 return foreach_loop(nir_cf_node_as_loop(node), cb, reverse, state);
1444 break;
1445
1446 default:
1447 unreachable("Invalid CFG node type");
1448 break;
1449 }
1450
1451 return false;
1452 }
1453
1454 bool
1455 nir_foreach_block_in_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1456 void *state)
1457 {
1458 return foreach_cf_node(node, cb, false, state);
1459 }
1460
1461 bool
1462 nir_foreach_block(nir_function_impl *impl, nir_foreach_block_cb cb, void *state)
1463 {
1464 foreach_list_typed_safe(nir_cf_node, node, node, &impl->body) {
1465 if (!foreach_cf_node(node, cb, false, state))
1466 return false;
1467 }
1468
1469 return cb(impl->end_block, state);
1470 }
1471
1472 bool
1473 nir_foreach_block_reverse(nir_function_impl *impl, nir_foreach_block_cb cb,
1474 void *state)
1475 {
1476 if (!cb(impl->end_block, state))
1477 return false;
1478
1479 foreach_list_typed_reverse_safe(nir_cf_node, node, node, &impl->body) {
1480 if (!foreach_cf_node(node, cb, true, state))
1481 return false;
1482 }
1483
1484 return true;
1485 }
1486
1487 nir_if *
1488 nir_block_get_following_if(nir_block *block)
1489 {
1490 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1491 return NULL;
1492
1493 if (nir_cf_node_is_last(&block->cf_node))
1494 return NULL;
1495
1496 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1497
1498 if (next_node->type != nir_cf_node_if)
1499 return NULL;
1500
1501 return nir_cf_node_as_if(next_node);
1502 }
1503
1504 nir_loop *
1505 nir_block_get_following_loop(nir_block *block)
1506 {
1507 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1508 return NULL;
1509
1510 if (nir_cf_node_is_last(&block->cf_node))
1511 return NULL;
1512
1513 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1514
1515 if (next_node->type != nir_cf_node_loop)
1516 return NULL;
1517
1518 return nir_cf_node_as_loop(next_node);
1519 }
1520 static bool
1521 index_block(nir_block *block, void *state)
1522 {
1523 unsigned *index = state;
1524 block->index = (*index)++;
1525 return true;
1526 }
1527
1528 void
1529 nir_index_blocks(nir_function_impl *impl)
1530 {
1531 unsigned index = 0;
1532
1533 if (impl->valid_metadata & nir_metadata_block_index)
1534 return;
1535
1536 nir_foreach_block(impl, index_block, &index);
1537
1538 impl->num_blocks = index;
1539 }
1540
1541 static bool
1542 index_ssa_def_cb(nir_ssa_def *def, void *state)
1543 {
1544 unsigned *index = (unsigned *) state;
1545 def->index = (*index)++;
1546
1547 return true;
1548 }
1549
1550 static bool
1551 index_ssa_block(nir_block *block, void *state)
1552 {
1553 nir_foreach_instr(block, instr)
1554 nir_foreach_ssa_def(instr, index_ssa_def_cb, state);
1555
1556 return true;
1557 }
1558
1559 /**
1560 * The indices are applied top-to-bottom which has the very nice property
1561 * that, if A dominates B, then A->index <= B->index.
1562 */
1563 void
1564 nir_index_ssa_defs(nir_function_impl *impl)
1565 {
1566 unsigned index = 0;
1567 nir_foreach_block(impl, index_ssa_block, &index);
1568 impl->ssa_alloc = index;
1569 }
1570
1571 static bool
1572 index_instrs_block(nir_block *block, void *state)
1573 {
1574 unsigned *index = state;
1575 nir_foreach_instr(block, instr)
1576 instr->index = (*index)++;
1577
1578 return true;
1579 }
1580
1581 /**
1582 * The indices are applied top-to-bottom which has the very nice property
1583 * that, if A dominates B, then A->index <= B->index.
1584 */
1585 unsigned
1586 nir_index_instrs(nir_function_impl *impl)
1587 {
1588 unsigned index = 0;
1589 nir_foreach_block(impl, index_instrs_block, &index);
1590 return index;
1591 }
1592
1593 nir_intrinsic_op
1594 nir_intrinsic_from_system_value(gl_system_value val)
1595 {
1596 switch (val) {
1597 case SYSTEM_VALUE_VERTEX_ID:
1598 return nir_intrinsic_load_vertex_id;
1599 case SYSTEM_VALUE_INSTANCE_ID:
1600 return nir_intrinsic_load_instance_id;
1601 case SYSTEM_VALUE_DRAW_ID:
1602 return nir_intrinsic_load_draw_id;
1603 case SYSTEM_VALUE_BASE_INSTANCE:
1604 return nir_intrinsic_load_base_instance;
1605 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1606 return nir_intrinsic_load_vertex_id_zero_base;
1607 case SYSTEM_VALUE_BASE_VERTEX:
1608 return nir_intrinsic_load_base_vertex;
1609 case SYSTEM_VALUE_INVOCATION_ID:
1610 return nir_intrinsic_load_invocation_id;
1611 case SYSTEM_VALUE_FRONT_FACE:
1612 return nir_intrinsic_load_front_face;
1613 case SYSTEM_VALUE_SAMPLE_ID:
1614 return nir_intrinsic_load_sample_id;
1615 case SYSTEM_VALUE_SAMPLE_POS:
1616 return nir_intrinsic_load_sample_pos;
1617 case SYSTEM_VALUE_SAMPLE_MASK_IN:
1618 return nir_intrinsic_load_sample_mask_in;
1619 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1620 return nir_intrinsic_load_local_invocation_id;
1621 case SYSTEM_VALUE_WORK_GROUP_ID:
1622 return nir_intrinsic_load_work_group_id;
1623 case SYSTEM_VALUE_NUM_WORK_GROUPS:
1624 return nir_intrinsic_load_num_work_groups;
1625 case SYSTEM_VALUE_PRIMITIVE_ID:
1626 return nir_intrinsic_load_primitive_id;
1627 case SYSTEM_VALUE_TESS_COORD:
1628 return nir_intrinsic_load_tess_coord;
1629 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1630 return nir_intrinsic_load_tess_level_outer;
1631 case SYSTEM_VALUE_TESS_LEVEL_INNER:
1632 return nir_intrinsic_load_tess_level_inner;
1633 case SYSTEM_VALUE_VERTICES_IN:
1634 return nir_intrinsic_load_patch_vertices_in;
1635 case SYSTEM_VALUE_HELPER_INVOCATION:
1636 return nir_intrinsic_load_helper_invocation;
1637 default:
1638 unreachable("system value does not directly correspond to intrinsic");
1639 }
1640 }
1641
1642 gl_system_value
1643 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
1644 {
1645 switch (intrin) {
1646 case nir_intrinsic_load_vertex_id:
1647 return SYSTEM_VALUE_VERTEX_ID;
1648 case nir_intrinsic_load_instance_id:
1649 return SYSTEM_VALUE_INSTANCE_ID;
1650 case nir_intrinsic_load_draw_id:
1651 return SYSTEM_VALUE_DRAW_ID;
1652 case nir_intrinsic_load_base_instance:
1653 return SYSTEM_VALUE_BASE_INSTANCE;
1654 case nir_intrinsic_load_vertex_id_zero_base:
1655 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1656 case nir_intrinsic_load_base_vertex:
1657 return SYSTEM_VALUE_BASE_VERTEX;
1658 case nir_intrinsic_load_invocation_id:
1659 return SYSTEM_VALUE_INVOCATION_ID;
1660 case nir_intrinsic_load_front_face:
1661 return SYSTEM_VALUE_FRONT_FACE;
1662 case nir_intrinsic_load_sample_id:
1663 return SYSTEM_VALUE_SAMPLE_ID;
1664 case nir_intrinsic_load_sample_pos:
1665 return SYSTEM_VALUE_SAMPLE_POS;
1666 case nir_intrinsic_load_sample_mask_in:
1667 return SYSTEM_VALUE_SAMPLE_MASK_IN;
1668 case nir_intrinsic_load_local_invocation_id:
1669 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
1670 case nir_intrinsic_load_num_work_groups:
1671 return SYSTEM_VALUE_NUM_WORK_GROUPS;
1672 case nir_intrinsic_load_work_group_id:
1673 return SYSTEM_VALUE_WORK_GROUP_ID;
1674 case nir_intrinsic_load_primitive_id:
1675 return SYSTEM_VALUE_PRIMITIVE_ID;
1676 case nir_intrinsic_load_tess_coord:
1677 return SYSTEM_VALUE_TESS_COORD;
1678 case nir_intrinsic_load_tess_level_outer:
1679 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
1680 case nir_intrinsic_load_tess_level_inner:
1681 return SYSTEM_VALUE_TESS_LEVEL_INNER;
1682 case nir_intrinsic_load_patch_vertices_in:
1683 return SYSTEM_VALUE_VERTICES_IN;
1684 case nir_intrinsic_load_helper_invocation:
1685 return SYSTEM_VALUE_HELPER_INVOCATION;
1686 default:
1687 unreachable("intrinsic doesn't produce a system value");
1688 }
1689 }