283eb2b1f198dcb73fd138f5db8fbe4630f7cbdb
[mesa.git] / src / compiler / nir / nir_builder.h
1 /*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef NIR_BUILDER_H
25 #define NIR_BUILDER_H
26
27 #include "nir_control_flow.h"
28 #include "util/bitscan.h"
29 #include "util/half_float.h"
30
31 struct exec_list;
32
33 typedef struct nir_builder {
34 nir_cursor cursor;
35
36 /* Whether new ALU instructions will be marked "exact" */
37 bool exact;
38
39 nir_shader *shader;
40 nir_function_impl *impl;
41 } nir_builder;
42
43 static inline void
44 nir_builder_init(nir_builder *build, nir_function_impl *impl)
45 {
46 memset(build, 0, sizeof(*build));
47 build->exact = false;
48 build->impl = impl;
49 build->shader = impl->function->shader;
50 }
51
52 static inline void
53 nir_builder_init_simple_shader(nir_builder *build, void *mem_ctx,
54 gl_shader_stage stage,
55 const nir_shader_compiler_options *options)
56 {
57 build->shader = nir_shader_create(mem_ctx, stage, options, NULL);
58 nir_function *func = nir_function_create(build->shader, "main");
59 func->is_entrypoint = true;
60 build->exact = false;
61 build->impl = nir_function_impl_create(func);
62 build->cursor = nir_after_cf_list(&build->impl->body);
63 }
64
65 static inline void
66 nir_builder_instr_insert(nir_builder *build, nir_instr *instr)
67 {
68 nir_instr_insert(build->cursor, instr);
69
70 /* Move the cursor forward. */
71 build->cursor = nir_after_instr(instr);
72 }
73
74 static inline nir_instr *
75 nir_builder_last_instr(nir_builder *build)
76 {
77 assert(build->cursor.option == nir_cursor_after_instr);
78 return build->cursor.instr;
79 }
80
81 static inline void
82 nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf)
83 {
84 nir_cf_node_insert(build->cursor, cf);
85 }
86
87 static inline bool
88 nir_builder_is_inside_cf(nir_builder *build, nir_cf_node *cf_node)
89 {
90 nir_block *block = nir_cursor_current_block(build->cursor);
91 for (nir_cf_node *n = &block->cf_node; n; n = n->parent) {
92 if (n == cf_node)
93 return true;
94 }
95 return false;
96 }
97
98 static inline nir_if *
99 nir_push_if(nir_builder *build, nir_ssa_def *condition)
100 {
101 nir_if *nif = nir_if_create(build->shader);
102 nif->condition = nir_src_for_ssa(condition);
103 nir_builder_cf_insert(build, &nif->cf_node);
104 build->cursor = nir_before_cf_list(&nif->then_list);
105 return nif;
106 }
107
108 static inline nir_if *
109 nir_push_else(nir_builder *build, nir_if *nif)
110 {
111 if (nif) {
112 assert(nir_builder_is_inside_cf(build, &nif->cf_node));
113 } else {
114 nir_block *block = nir_cursor_current_block(build->cursor);
115 nif = nir_cf_node_as_if(block->cf_node.parent);
116 }
117 build->cursor = nir_before_cf_list(&nif->else_list);
118 return nif;
119 }
120
121 static inline void
122 nir_pop_if(nir_builder *build, nir_if *nif)
123 {
124 if (nif) {
125 assert(nir_builder_is_inside_cf(build, &nif->cf_node));
126 } else {
127 nir_block *block = nir_cursor_current_block(build->cursor);
128 nif = nir_cf_node_as_if(block->cf_node.parent);
129 }
130 build->cursor = nir_after_cf_node(&nif->cf_node);
131 }
132
133 static inline nir_ssa_def *
134 nir_if_phi(nir_builder *build, nir_ssa_def *then_def, nir_ssa_def *else_def)
135 {
136 nir_block *block = nir_cursor_current_block(build->cursor);
137 nir_if *nif = nir_cf_node_as_if(nir_cf_node_prev(&block->cf_node));
138
139 nir_phi_instr *phi = nir_phi_instr_create(build->shader);
140
141 nir_phi_src *src = ralloc(phi, nir_phi_src);
142 src->pred = nir_if_last_then_block(nif);
143 src->src = nir_src_for_ssa(then_def);
144 exec_list_push_tail(&phi->srcs, &src->node);
145
146 src = ralloc(phi, nir_phi_src);
147 src->pred = nir_if_last_else_block(nif);
148 src->src = nir_src_for_ssa(else_def);
149 exec_list_push_tail(&phi->srcs, &src->node);
150
151 assert(then_def->num_components == else_def->num_components);
152 assert(then_def->bit_size == else_def->bit_size);
153 nir_ssa_dest_init(&phi->instr, &phi->dest,
154 then_def->num_components, then_def->bit_size, NULL);
155
156 nir_builder_instr_insert(build, &phi->instr);
157
158 return &phi->dest.ssa;
159 }
160
161 static inline nir_loop *
162 nir_push_loop(nir_builder *build)
163 {
164 nir_loop *loop = nir_loop_create(build->shader);
165 nir_builder_cf_insert(build, &loop->cf_node);
166 build->cursor = nir_before_cf_list(&loop->body);
167 return loop;
168 }
169
170 static inline void
171 nir_pop_loop(nir_builder *build, nir_loop *loop)
172 {
173 if (loop) {
174 assert(nir_builder_is_inside_cf(build, &loop->cf_node));
175 } else {
176 nir_block *block = nir_cursor_current_block(build->cursor);
177 loop = nir_cf_node_as_loop(block->cf_node.parent);
178 }
179 build->cursor = nir_after_cf_node(&loop->cf_node);
180 }
181
182 static inline nir_ssa_def *
183 nir_ssa_undef(nir_builder *build, unsigned num_components, unsigned bit_size)
184 {
185 nir_ssa_undef_instr *undef =
186 nir_ssa_undef_instr_create(build->shader, num_components, bit_size);
187 if (!undef)
188 return NULL;
189
190 nir_instr_insert(nir_before_cf_list(&build->impl->body), &undef->instr);
191
192 return &undef->def;
193 }
194
195 static inline nir_ssa_def *
196 nir_build_imm(nir_builder *build, unsigned num_components,
197 unsigned bit_size, const nir_const_value *value)
198 {
199 nir_load_const_instr *load_const =
200 nir_load_const_instr_create(build->shader, num_components, bit_size);
201 if (!load_const)
202 return NULL;
203
204 memcpy(load_const->value, value, sizeof(nir_const_value) * num_components);
205
206 nir_builder_instr_insert(build, &load_const->instr);
207
208 return &load_const->def;
209 }
210
211 static inline nir_ssa_def *
212 nir_imm_zero(nir_builder *build, unsigned num_components, unsigned bit_size)
213 {
214 nir_load_const_instr *load_const =
215 nir_load_const_instr_create(build->shader, num_components, bit_size);
216
217 /* nir_load_const_instr_create uses rzalloc so it's already zero */
218
219 nir_builder_instr_insert(build, &load_const->instr);
220
221 return &load_const->def;
222 }
223
224 static inline nir_ssa_def *
225 nir_imm_boolN_t(nir_builder *build, bool x, unsigned bit_size)
226 {
227 nir_const_value v = nir_const_value_for_bool(x, bit_size);
228 return nir_build_imm(build, 1, bit_size, &v);
229 }
230
231 static inline nir_ssa_def *
232 nir_imm_bool(nir_builder *build, bool x)
233 {
234 return nir_imm_boolN_t(build, x, 1);
235 }
236
237 static inline nir_ssa_def *
238 nir_imm_true(nir_builder *build)
239 {
240 return nir_imm_bool(build, true);
241 }
242
243 static inline nir_ssa_def *
244 nir_imm_false(nir_builder *build)
245 {
246 return nir_imm_bool(build, false);
247 }
248
249 static inline nir_ssa_def *
250 nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
251 {
252 nir_const_value v = nir_const_value_for_float(x, bit_size);
253 return nir_build_imm(build, 1, bit_size, &v);
254 }
255
256 static inline nir_ssa_def *
257 nir_imm_float16(nir_builder *build, float x)
258 {
259 return nir_imm_floatN_t(build, x, 16);
260 }
261
262 static inline nir_ssa_def *
263 nir_imm_float(nir_builder *build, float x)
264 {
265 return nir_imm_floatN_t(build, x, 32);
266 }
267
268 static inline nir_ssa_def *
269 nir_imm_double(nir_builder *build, double x)
270 {
271 return nir_imm_floatN_t(build, x, 64);
272 }
273
274 static inline nir_ssa_def *
275 nir_imm_vec2(nir_builder *build, float x, float y)
276 {
277 nir_const_value v[2] = {
278 nir_const_value_for_float(x, 32),
279 nir_const_value_for_float(y, 32),
280 };
281 return nir_build_imm(build, 2, 32, v);
282 }
283
284 static inline nir_ssa_def *
285 nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
286 {
287 nir_const_value v[4] = {
288 nir_const_value_for_float(x, 32),
289 nir_const_value_for_float(y, 32),
290 nir_const_value_for_float(z, 32),
291 nir_const_value_for_float(w, 32),
292 };
293
294 return nir_build_imm(build, 4, 32, v);
295 }
296
297 static inline nir_ssa_def *
298 nir_imm_vec4_16(nir_builder *build, float x, float y, float z, float w)
299 {
300 nir_const_value v[4] = {
301 nir_const_value_for_float(x, 16),
302 nir_const_value_for_float(y, 16),
303 nir_const_value_for_float(z, 16),
304 nir_const_value_for_float(w, 16),
305 };
306
307 return nir_build_imm(build, 4, 16, v);
308 }
309
310 static inline nir_ssa_def *
311 nir_imm_intN_t(nir_builder *build, uint64_t x, unsigned bit_size)
312 {
313 nir_const_value v = nir_const_value_for_raw_uint(x, bit_size);
314 return nir_build_imm(build, 1, bit_size, &v);
315 }
316
317 static inline nir_ssa_def *
318 nir_imm_int(nir_builder *build, int x)
319 {
320 return nir_imm_intN_t(build, x, 32);
321 }
322
323 static inline nir_ssa_def *
324 nir_imm_int64(nir_builder *build, int64_t x)
325 {
326 return nir_imm_intN_t(build, x, 64);
327 }
328
329 static inline nir_ssa_def *
330 nir_imm_ivec2(nir_builder *build, int x, int y)
331 {
332 nir_const_value v[2] = {
333 nir_const_value_for_int(x, 32),
334 nir_const_value_for_int(y, 32),
335 };
336
337 return nir_build_imm(build, 2, 32, v);
338 }
339
340 static inline nir_ssa_def *
341 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
342 {
343 nir_const_value v[4] = {
344 nir_const_value_for_int(x, 32),
345 nir_const_value_for_int(y, 32),
346 nir_const_value_for_int(z, 32),
347 nir_const_value_for_int(w, 32),
348 };
349
350 return nir_build_imm(build, 4, 32, v);
351 }
352
353 static inline nir_ssa_def *
354 nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr)
355 {
356 const nir_op_info *op_info = &nir_op_infos[instr->op];
357
358 instr->exact = build->exact;
359
360 /* Guess the number of components the destination temporary should have
361 * based on our input sizes, if it's not fixed for the op.
362 */
363 unsigned num_components = op_info->output_size;
364 if (num_components == 0) {
365 for (unsigned i = 0; i < op_info->num_inputs; i++) {
366 if (op_info->input_sizes[i] == 0)
367 num_components = MAX2(num_components,
368 instr->src[i].src.ssa->num_components);
369 }
370 }
371 assert(num_components != 0);
372
373 /* Figure out the bitwidth based on the source bitwidth if the instruction
374 * is variable-width.
375 */
376 unsigned bit_size = nir_alu_type_get_type_size(op_info->output_type);
377 if (bit_size == 0) {
378 for (unsigned i = 0; i < op_info->num_inputs; i++) {
379 unsigned src_bit_size = instr->src[i].src.ssa->bit_size;
380 if (nir_alu_type_get_type_size(op_info->input_types[i]) == 0) {
381 if (bit_size)
382 assert(src_bit_size == bit_size);
383 else
384 bit_size = src_bit_size;
385 } else {
386 assert(src_bit_size ==
387 nir_alu_type_get_type_size(op_info->input_types[i]));
388 }
389 }
390 }
391
392 /* When in doubt, assume 32. */
393 if (bit_size == 0)
394 bit_size = 32;
395
396 /* Make sure we don't swizzle from outside of our source vector (like if a
397 * scalar value was passed into a multiply with a vector).
398 */
399 for (unsigned i = 0; i < op_info->num_inputs; i++) {
400 for (unsigned j = instr->src[i].src.ssa->num_components;
401 j < NIR_MAX_VEC_COMPONENTS; j++) {
402 instr->src[i].swizzle[j] = instr->src[i].src.ssa->num_components - 1;
403 }
404 }
405
406 nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
407 bit_size, NULL);
408 instr->dest.write_mask = (1 << num_components) - 1;
409
410 nir_builder_instr_insert(build, &instr->instr);
411
412 return &instr->dest.dest.ssa;
413 }
414
415 static inline nir_ssa_def *
416 nir_build_alu(nir_builder *build, nir_op op, nir_ssa_def *src0,
417 nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
418 {
419 nir_alu_instr *instr = nir_alu_instr_create(build->shader, op);
420 if (!instr)
421 return NULL;
422
423 instr->src[0].src = nir_src_for_ssa(src0);
424 if (src1)
425 instr->src[1].src = nir_src_for_ssa(src1);
426 if (src2)
427 instr->src[2].src = nir_src_for_ssa(src2);
428 if (src3)
429 instr->src[3].src = nir_src_for_ssa(src3);
430
431 return nir_builder_alu_instr_finish_and_insert(build, instr);
432 }
433
434 /* for the couple special cases with more than 4 src args: */
435 static inline nir_ssa_def *
436 nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_ssa_def **srcs)
437 {
438 const nir_op_info *op_info = &nir_op_infos[op];
439 nir_alu_instr *instr = nir_alu_instr_create(build->shader, op);
440 if (!instr)
441 return NULL;
442
443 for (unsigned i = 0; i < op_info->num_inputs; i++)
444 instr->src[i].src = nir_src_for_ssa(srcs[i]);
445
446 return nir_builder_alu_instr_finish_and_insert(build, instr);
447 }
448
449 #include "nir_builder_opcodes.h"
450
451 static inline nir_ssa_def *
452 nir_vec(nir_builder *build, nir_ssa_def **comp, unsigned num_components)
453 {
454 return nir_build_alu_src_arr(build, nir_op_vec(num_components), comp);
455 }
456
457 static inline nir_ssa_def *
458 nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
459 {
460 assert(!src.abs && !src.negate);
461 if (src.src.is_ssa && src.src.ssa->num_components == num_components) {
462 bool any_swizzles = false;
463 for (unsigned i = 0; i < num_components; i++) {
464 if (src.swizzle[i] != i)
465 any_swizzles = true;
466 }
467 if (!any_swizzles)
468 return src.src.ssa;
469 }
470
471 nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
472 nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components,
473 nir_src_bit_size(src.src), NULL);
474 mov->exact = build->exact;
475 mov->dest.write_mask = (1 << num_components) - 1;
476 mov->src[0] = src;
477 nir_builder_instr_insert(build, &mov->instr);
478
479 return &mov->dest.dest.ssa;
480 }
481
482 /**
483 * Construct an fmov or imov that reswizzles the source's components.
484 */
485 static inline nir_ssa_def *
486 nir_swizzle(nir_builder *build, nir_ssa_def *src, const unsigned *swiz,
487 unsigned num_components)
488 {
489 assert(num_components <= NIR_MAX_VEC_COMPONENTS);
490 nir_alu_src alu_src = { NIR_SRC_INIT };
491 alu_src.src = nir_src_for_ssa(src);
492
493 bool is_identity_swizzle = true;
494 for (unsigned i = 0; i < num_components && i < NIR_MAX_VEC_COMPONENTS; i++) {
495 if (swiz[i] != i)
496 is_identity_swizzle = false;
497 alu_src.swizzle[i] = swiz[i];
498 }
499
500 if (num_components == src->num_components && is_identity_swizzle)
501 return src;
502
503 return nir_mov_alu(build, alu_src, num_components);
504 }
505
506 /* Selects the right fdot given the number of components in each source. */
507 static inline nir_ssa_def *
508 nir_fdot(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
509 {
510 assert(src0->num_components == src1->num_components);
511 switch (src0->num_components) {
512 case 1: return nir_fmul(build, src0, src1);
513 case 2: return nir_fdot2(build, src0, src1);
514 case 3: return nir_fdot3(build, src0, src1);
515 case 4: return nir_fdot4(build, src0, src1);
516 case 8: return nir_fdot8(build, src0, src1);
517 case 16: return nir_fdot16(build, src0, src1);
518 default:
519 unreachable("bad component size");
520 }
521
522 return NULL;
523 }
524
525 static inline nir_ssa_def *
526 nir_ball_iequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
527 {
528 switch (src0->num_components) {
529 case 1: return nir_ieq(b, src0, src1);
530 case 2: return nir_ball_iequal2(b, src0, src1);
531 case 3: return nir_ball_iequal3(b, src0, src1);
532 case 4: return nir_ball_iequal4(b, src0, src1);
533 case 8: return nir_ball_iequal8(b, src0, src1);
534 case 16: return nir_ball_iequal16(b, src0, src1);
535 default:
536 unreachable("bad component size");
537 }
538 }
539
540 static inline nir_ssa_def *
541 nir_bany_inequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
542 {
543 switch (src0->num_components) {
544 case 1: return nir_ine(b, src0, src1);
545 case 2: return nir_bany_inequal2(b, src0, src1);
546 case 3: return nir_bany_inequal3(b, src0, src1);
547 case 4: return nir_bany_inequal4(b, src0, src1);
548 case 8: return nir_bany_inequal8(b, src0, src1);
549 case 16: return nir_bany_inequal16(b, src0, src1);
550 default:
551 unreachable("bad component size");
552 }
553 }
554
555 static inline nir_ssa_def *
556 nir_bany(nir_builder *b, nir_ssa_def *src)
557 {
558 return nir_bany_inequal(b, src, nir_imm_false(b));
559 }
560
561 static inline nir_ssa_def *
562 nir_channel(nir_builder *b, nir_ssa_def *def, unsigned c)
563 {
564 return nir_swizzle(b, def, &c, 1);
565 }
566
567 static inline nir_ssa_def *
568 nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask)
569 {
570 unsigned num_channels = 0, swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 };
571
572 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
573 if ((mask & (1 << i)) == 0)
574 continue;
575 swizzle[num_channels++] = i;
576 }
577
578 return nir_swizzle(b, def, swizzle, num_channels);
579 }
580
581 static inline nir_ssa_def *
582 _nir_vector_extract_helper(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c,
583 unsigned start, unsigned end)
584 {
585 if (start == end - 1) {
586 return nir_channel(b, vec, start);
587 } else {
588 unsigned mid = start + (end - start) / 2;
589 return nir_bcsel(b, nir_ilt(b, c, nir_imm_intN_t(b, mid, c->bit_size)),
590 _nir_vector_extract_helper(b, vec, c, start, mid),
591 _nir_vector_extract_helper(b, vec, c, mid, end));
592 }
593 }
594
595 static inline nir_ssa_def *
596 nir_vector_extract(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c)
597 {
598 nir_src c_src = nir_src_for_ssa(c);
599 if (nir_src_is_const(c_src)) {
600 uint64_t c_const = nir_src_as_uint(c_src);
601 if (c_const < vec->num_components)
602 return nir_channel(b, vec, c_const);
603 else
604 return nir_ssa_undef(b, 1, vec->bit_size);
605 } else {
606 return _nir_vector_extract_helper(b, vec, c, 0, vec->num_components);
607 }
608 }
609
610 /** Replaces the component of `vec` specified by `c` with `scalar` */
611 static inline nir_ssa_def *
612 nir_vector_insert_imm(nir_builder *b, nir_ssa_def *vec,
613 nir_ssa_def *scalar, unsigned c)
614 {
615 assert(scalar->num_components == 1);
616 assert(c < vec->num_components);
617
618 nir_op vec_op = nir_op_vec(vec->num_components);
619 nir_alu_instr *vec_instr = nir_alu_instr_create(b->shader, vec_op);
620
621 for (unsigned i = 0; i < vec->num_components; i++) {
622 if (i == c) {
623 vec_instr->src[i].src = nir_src_for_ssa(scalar);
624 vec_instr->src[i].swizzle[0] = 0;
625 } else {
626 vec_instr->src[i].src = nir_src_for_ssa(vec);
627 vec_instr->src[i].swizzle[0] = i;
628 }
629 }
630
631 return nir_builder_alu_instr_finish_and_insert(b, vec_instr);
632 }
633
634 /** Replaces the component of `vec` specified by `c` with `scalar` */
635 static inline nir_ssa_def *
636 nir_vector_insert(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *scalar,
637 nir_ssa_def *c)
638 {
639 assert(scalar->num_components == 1);
640 assert(c->num_components == 1);
641
642 nir_src c_src = nir_src_for_ssa(c);
643 if (nir_src_is_const(c_src)) {
644 uint64_t c_const = nir_src_as_uint(c_src);
645 if (c_const < vec->num_components)
646 return nir_vector_insert_imm(b, vec, scalar, c_const);
647 else
648 return vec;
649 } else {
650 nir_const_value per_comp_idx_const[NIR_MAX_VEC_COMPONENTS];
651 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
652 per_comp_idx_const[i] = nir_const_value_for_int(i, c->bit_size);
653 nir_ssa_def *per_comp_idx =
654 nir_build_imm(b, vec->num_components,
655 c->bit_size, per_comp_idx_const);
656
657 /* nir_builder will automatically splat out scalars to vectors so an
658 * insert is as simple as "if I'm the channel, replace me with the
659 * scalar."
660 */
661 return nir_bcsel(b, nir_ieq(b, c, per_comp_idx), scalar, vec);
662 }
663 }
664
665 static inline nir_ssa_def *
666 nir_i2i(nir_builder *build, nir_ssa_def *x, unsigned dest_bit_size)
667 {
668 if (x->bit_size == dest_bit_size)
669 return x;
670
671 switch (dest_bit_size) {
672 case 64: return nir_i2i64(build, x);
673 case 32: return nir_i2i32(build, x);
674 case 16: return nir_i2i16(build, x);
675 case 8: return nir_i2i8(build, x);
676 default: unreachable("Invalid bit size");
677 }
678 }
679
680 static inline nir_ssa_def *
681 nir_u2u(nir_builder *build, nir_ssa_def *x, unsigned dest_bit_size)
682 {
683 if (x->bit_size == dest_bit_size)
684 return x;
685
686 switch (dest_bit_size) {
687 case 64: return nir_u2u64(build, x);
688 case 32: return nir_u2u32(build, x);
689 case 16: return nir_u2u16(build, x);
690 case 8: return nir_u2u8(build, x);
691 default: unreachable("Invalid bit size");
692 }
693 }
694
695 static inline nir_ssa_def *
696 nir_iadd_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
697 {
698 assert(x->bit_size <= 64);
699 if (x->bit_size < 64)
700 y &= (1ull << x->bit_size) - 1;
701
702 if (y == 0) {
703 return x;
704 } else {
705 return nir_iadd(build, x, nir_imm_intN_t(build, y, x->bit_size));
706 }
707 }
708
709 static inline nir_ssa_def *
710 _nir_mul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y, bool amul)
711 {
712 assert(x->bit_size <= 64);
713 if (x->bit_size < 64)
714 y &= (1ull << x->bit_size) - 1;
715
716 if (y == 0) {
717 return nir_imm_intN_t(build, 0, x->bit_size);
718 } else if (y == 1) {
719 return x;
720 } else if (!build->shader->options->lower_bitops &&
721 util_is_power_of_two_or_zero64(y)) {
722 return nir_ishl(build, x, nir_imm_int(build, ffsll(y) - 1));
723 } else if (amul) {
724 return nir_amul(build, x, nir_imm_intN_t(build, y, x->bit_size));
725 } else {
726 return nir_imul(build, x, nir_imm_intN_t(build, y, x->bit_size));
727 }
728 }
729
730 static inline nir_ssa_def *
731 nir_imul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
732 {
733 return _nir_mul_imm(build, x, y, false);
734 }
735
736 static inline nir_ssa_def *
737 nir_amul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
738 {
739 return _nir_mul_imm(build, x, y, true);
740 }
741
742 static inline nir_ssa_def *
743 nir_fadd_imm(nir_builder *build, nir_ssa_def *x, double y)
744 {
745 return nir_fadd(build, x, nir_imm_floatN_t(build, y, x->bit_size));
746 }
747
748 static inline nir_ssa_def *
749 nir_fmul_imm(nir_builder *build, nir_ssa_def *x, double y)
750 {
751 return nir_fmul(build, x, nir_imm_floatN_t(build, y, x->bit_size));
752 }
753
754 static inline nir_ssa_def *
755 nir_pack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
756 {
757 assert(src->num_components * src->bit_size == dest_bit_size);
758
759 switch (dest_bit_size) {
760 case 64:
761 switch (src->bit_size) {
762 case 32: return nir_pack_64_2x32(b, src);
763 case 16: return nir_pack_64_4x16(b, src);
764 default: break;
765 }
766 break;
767
768 case 32:
769 if (src->bit_size == 16)
770 return nir_pack_32_2x16(b, src);
771 break;
772
773 default:
774 break;
775 }
776
777 /* If we got here, we have no dedicated unpack opcode. */
778 nir_ssa_def *dest = nir_imm_intN_t(b, 0, dest_bit_size);
779 for (unsigned i = 0; i < src->num_components; i++) {
780 nir_ssa_def *val = nir_u2u(b, nir_channel(b, src, i), dest_bit_size);
781 val = nir_ishl(b, val, nir_imm_int(b, i * src->bit_size));
782 dest = nir_ior(b, dest, val);
783 }
784 return dest;
785 }
786
787 static inline nir_ssa_def *
788 nir_unpack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
789 {
790 assert(src->num_components == 1);
791 assert(src->bit_size > dest_bit_size);
792 const unsigned dest_num_components = src->bit_size / dest_bit_size;
793 assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
794
795 switch (src->bit_size) {
796 case 64:
797 switch (dest_bit_size) {
798 case 32: return nir_unpack_64_2x32(b, src);
799 case 16: return nir_unpack_64_4x16(b, src);
800 default: break;
801 }
802 break;
803
804 case 32:
805 if (dest_bit_size == 16)
806 return nir_unpack_32_2x16(b, src);
807 break;
808
809 default:
810 break;
811 }
812
813 /* If we got here, we have no dedicated unpack opcode. */
814 nir_ssa_def *dest_comps[NIR_MAX_VEC_COMPONENTS];
815 for (unsigned i = 0; i < dest_num_components; i++) {
816 nir_ssa_def *val = nir_ushr(b, src, nir_imm_int(b, i * dest_bit_size));
817 dest_comps[i] = nir_u2u(b, val, dest_bit_size);
818 }
819 return nir_vec(b, dest_comps, dest_num_components);
820 }
821
822 /**
823 * Treats srcs as if it's one big blob of bits and extracts the range of bits
824 * given by
825 *
826 * [first_bit, first_bit + dest_num_components * dest_bit_size)
827 *
828 * The range can have any alignment or size as long as it's an integer number
829 * of destination components and fits inside the concatenated sources.
830 *
831 * TODO: The one caveat here is that we can't handle byte alignment if 64-bit
832 * values are involved because that would require pack/unpack to/from a vec8
833 * which NIR currently does not support.
834 */
835 static inline nir_ssa_def *
836 nir_extract_bits(nir_builder *b, nir_ssa_def **srcs, unsigned num_srcs,
837 unsigned first_bit,
838 unsigned dest_num_components, unsigned dest_bit_size)
839 {
840 const unsigned num_bits = dest_num_components * dest_bit_size;
841
842 /* Figure out the common bit size */
843 unsigned common_bit_size = dest_bit_size;
844 for (unsigned i = 0; i < num_srcs; i++)
845 common_bit_size = MIN2(common_bit_size, srcs[i]->bit_size);
846 if (first_bit > 0)
847 common_bit_size = MIN2(common_bit_size, (1u << (ffs(first_bit) - 1)));
848
849 /* We don't want to have to deal with 1-bit values */
850 assert(common_bit_size >= 8);
851
852 nir_ssa_def *common_comps[NIR_MAX_VEC_COMPONENTS * sizeof(uint64_t)];
853 assert(num_bits / common_bit_size <= ARRAY_SIZE(common_comps));
854
855 /* First, unpack to the common bit size and select the components from the
856 * source.
857 */
858 int src_idx = -1;
859 unsigned src_start_bit = 0;
860 unsigned src_end_bit = 0;
861 for (unsigned i = 0; i < num_bits / common_bit_size; i++) {
862 const unsigned bit = first_bit + (i * common_bit_size);
863 while (bit >= src_end_bit) {
864 src_idx++;
865 assert(src_idx < (int) num_srcs);
866 src_start_bit = src_end_bit;
867 src_end_bit += srcs[src_idx]->bit_size *
868 srcs[src_idx]->num_components;
869 }
870 assert(bit >= src_start_bit);
871 assert(bit + common_bit_size <= src_end_bit);
872 const unsigned rel_bit = bit - src_start_bit;
873 const unsigned src_bit_size = srcs[src_idx]->bit_size;
874
875 nir_ssa_def *comp = nir_channel(b, srcs[src_idx],
876 rel_bit / src_bit_size);
877 if (srcs[src_idx]->bit_size > common_bit_size) {
878 nir_ssa_def *unpacked = nir_unpack_bits(b, comp, common_bit_size);
879 comp = nir_channel(b, unpacked, (rel_bit % src_bit_size) /
880 common_bit_size);
881 }
882 common_comps[i] = comp;
883 }
884
885 /* Now, re-pack the destination if we have to */
886 if (dest_bit_size > common_bit_size) {
887 unsigned common_per_dest = dest_bit_size / common_bit_size;
888 nir_ssa_def *dest_comps[NIR_MAX_VEC_COMPONENTS];
889 for (unsigned i = 0; i < dest_num_components; i++) {
890 nir_ssa_def *unpacked = nir_vec(b, common_comps + i * common_per_dest,
891 common_per_dest);
892 dest_comps[i] = nir_pack_bits(b, unpacked, dest_bit_size);
893 }
894 return nir_vec(b, dest_comps, dest_num_components);
895 } else {
896 assert(dest_bit_size == common_bit_size);
897 return nir_vec(b, common_comps, dest_num_components);
898 }
899 }
900
901 static inline nir_ssa_def *
902 nir_bitcast_vector(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
903 {
904 assert((src->bit_size * src->num_components) % dest_bit_size == 0);
905 const unsigned dest_num_components =
906 (src->bit_size * src->num_components) / dest_bit_size;
907 assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
908
909 return nir_extract_bits(b, &src, 1, 0, dest_num_components, dest_bit_size);
910 }
911
912 /**
913 * Turns a nir_src into a nir_ssa_def * so it can be passed to
914 * nir_build_alu()-based builder calls.
915 *
916 * See nir_ssa_for_alu_src() for alu instructions.
917 */
918 static inline nir_ssa_def *
919 nir_ssa_for_src(nir_builder *build, nir_src src, int num_components)
920 {
921 if (src.is_ssa && src.ssa->num_components == num_components)
922 return src.ssa;
923
924 nir_alu_src alu = { NIR_SRC_INIT };
925 alu.src = src;
926 for (int j = 0; j < 4; j++)
927 alu.swizzle[j] = j;
928
929 return nir_mov_alu(build, alu, num_components);
930 }
931
932 /**
933 * Similar to nir_ssa_for_src(), but for alu srcs, respecting the
934 * nir_alu_src's swizzle.
935 */
936 static inline nir_ssa_def *
937 nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr *instr, unsigned srcn)
938 {
939 static uint8_t trivial_swizzle[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
940 STATIC_ASSERT(ARRAY_SIZE(trivial_swizzle) == NIR_MAX_VEC_COMPONENTS);
941
942 nir_alu_src *src = &instr->src[srcn];
943 unsigned num_components = nir_ssa_alu_instr_src_components(instr, srcn);
944
945 if (src->src.is_ssa && (src->src.ssa->num_components == num_components) &&
946 !src->abs && !src->negate &&
947 (memcmp(src->swizzle, trivial_swizzle, num_components) == 0))
948 return src->src.ssa;
949
950 return nir_mov_alu(build, *src, num_components);
951 }
952
953 static inline unsigned
954 nir_get_ptr_bitsize(nir_builder *build)
955 {
956 if (build->shader->info.stage == MESA_SHADER_KERNEL)
957 return build->shader->info.cs.ptr_size;
958 return 32;
959 }
960
961 static inline nir_deref_instr *
962 nir_build_deref_var(nir_builder *build, nir_variable *var)
963 {
964 nir_deref_instr *deref =
965 nir_deref_instr_create(build->shader, nir_deref_type_var);
966
967 deref->mode = var->data.mode;
968 deref->type = var->type;
969 deref->var = var;
970
971 nir_ssa_dest_init(&deref->instr, &deref->dest, 1,
972 nir_get_ptr_bitsize(build), NULL);
973
974 nir_builder_instr_insert(build, &deref->instr);
975
976 return deref;
977 }
978
979 static inline nir_deref_instr *
980 nir_build_deref_array(nir_builder *build, nir_deref_instr *parent,
981 nir_ssa_def *index)
982 {
983 assert(glsl_type_is_array(parent->type) ||
984 glsl_type_is_matrix(parent->type) ||
985 glsl_type_is_vector(parent->type));
986
987 assert(index->bit_size == parent->dest.ssa.bit_size);
988
989 nir_deref_instr *deref =
990 nir_deref_instr_create(build->shader, nir_deref_type_array);
991
992 deref->mode = parent->mode;
993 deref->type = glsl_get_array_element(parent->type);
994 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
995 deref->arr.index = nir_src_for_ssa(index);
996
997 nir_ssa_dest_init(&deref->instr, &deref->dest,
998 parent->dest.ssa.num_components,
999 parent->dest.ssa.bit_size, NULL);
1000
1001 nir_builder_instr_insert(build, &deref->instr);
1002
1003 return deref;
1004 }
1005
1006 static inline nir_deref_instr *
1007 nir_build_deref_array_imm(nir_builder *build, nir_deref_instr *parent,
1008 int64_t index)
1009 {
1010 assert(parent->dest.is_ssa);
1011 nir_ssa_def *idx_ssa = nir_imm_intN_t(build, index,
1012 parent->dest.ssa.bit_size);
1013
1014 return nir_build_deref_array(build, parent, idx_ssa);
1015 }
1016
1017 static inline nir_deref_instr *
1018 nir_build_deref_ptr_as_array(nir_builder *build, nir_deref_instr *parent,
1019 nir_ssa_def *index)
1020 {
1021 assert(parent->deref_type == nir_deref_type_array ||
1022 parent->deref_type == nir_deref_type_ptr_as_array ||
1023 parent->deref_type == nir_deref_type_cast);
1024
1025 assert(index->bit_size == parent->dest.ssa.bit_size);
1026
1027 nir_deref_instr *deref =
1028 nir_deref_instr_create(build->shader, nir_deref_type_ptr_as_array);
1029
1030 deref->mode = parent->mode;
1031 deref->type = parent->type;
1032 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
1033 deref->arr.index = nir_src_for_ssa(index);
1034
1035 nir_ssa_dest_init(&deref->instr, &deref->dest,
1036 parent->dest.ssa.num_components,
1037 parent->dest.ssa.bit_size, NULL);
1038
1039 nir_builder_instr_insert(build, &deref->instr);
1040
1041 return deref;
1042 }
1043
1044 static inline nir_deref_instr *
1045 nir_build_deref_array_wildcard(nir_builder *build, nir_deref_instr *parent)
1046 {
1047 assert(glsl_type_is_array(parent->type) ||
1048 glsl_type_is_matrix(parent->type));
1049
1050 nir_deref_instr *deref =
1051 nir_deref_instr_create(build->shader, nir_deref_type_array_wildcard);
1052
1053 deref->mode = parent->mode;
1054 deref->type = glsl_get_array_element(parent->type);
1055 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
1056
1057 nir_ssa_dest_init(&deref->instr, &deref->dest,
1058 parent->dest.ssa.num_components,
1059 parent->dest.ssa.bit_size, NULL);
1060
1061 nir_builder_instr_insert(build, &deref->instr);
1062
1063 return deref;
1064 }
1065
1066 static inline nir_deref_instr *
1067 nir_build_deref_struct(nir_builder *build, nir_deref_instr *parent,
1068 unsigned index)
1069 {
1070 assert(glsl_type_is_struct_or_ifc(parent->type));
1071
1072 nir_deref_instr *deref =
1073 nir_deref_instr_create(build->shader, nir_deref_type_struct);
1074
1075 deref->mode = parent->mode;
1076 deref->type = glsl_get_struct_field(parent->type, index);
1077 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
1078 deref->strct.index = index;
1079
1080 nir_ssa_dest_init(&deref->instr, &deref->dest,
1081 parent->dest.ssa.num_components,
1082 parent->dest.ssa.bit_size, NULL);
1083
1084 nir_builder_instr_insert(build, &deref->instr);
1085
1086 return deref;
1087 }
1088
1089 static inline nir_deref_instr *
1090 nir_build_deref_cast(nir_builder *build, nir_ssa_def *parent,
1091 nir_variable_mode mode, const struct glsl_type *type,
1092 unsigned ptr_stride)
1093 {
1094 nir_deref_instr *deref =
1095 nir_deref_instr_create(build->shader, nir_deref_type_cast);
1096
1097 deref->mode = mode;
1098 deref->type = type;
1099 deref->parent = nir_src_for_ssa(parent);
1100 deref->cast.ptr_stride = ptr_stride;
1101
1102 nir_ssa_dest_init(&deref->instr, &deref->dest,
1103 parent->num_components, parent->bit_size, NULL);
1104
1105 nir_builder_instr_insert(build, &deref->instr);
1106
1107 return deref;
1108 }
1109
1110 /** Returns a deref that follows another but starting from the given parent
1111 *
1112 * The new deref will be the same type and take the same array or struct index
1113 * as the leader deref but it may have a different parent. This is very
1114 * useful for walking deref paths.
1115 */
1116 static inline nir_deref_instr *
1117 nir_build_deref_follower(nir_builder *b, nir_deref_instr *parent,
1118 nir_deref_instr *leader)
1119 {
1120 /* If the derefs would have the same parent, don't make a new one */
1121 assert(leader->parent.is_ssa);
1122 if (leader->parent.ssa == &parent->dest.ssa)
1123 return leader;
1124
1125 UNUSED nir_deref_instr *leader_parent = nir_src_as_deref(leader->parent);
1126
1127 switch (leader->deref_type) {
1128 case nir_deref_type_var:
1129 unreachable("A var dereference cannot have a parent");
1130 break;
1131
1132 case nir_deref_type_array:
1133 case nir_deref_type_array_wildcard:
1134 assert(glsl_type_is_matrix(parent->type) ||
1135 glsl_type_is_array(parent->type) ||
1136 (leader->deref_type == nir_deref_type_array &&
1137 glsl_type_is_vector(parent->type)));
1138 assert(glsl_get_length(parent->type) ==
1139 glsl_get_length(leader_parent->type));
1140
1141 if (leader->deref_type == nir_deref_type_array) {
1142 assert(leader->arr.index.is_ssa);
1143 nir_ssa_def *index = nir_i2i(b, leader->arr.index.ssa,
1144 parent->dest.ssa.bit_size);
1145 return nir_build_deref_array(b, parent, index);
1146 } else {
1147 return nir_build_deref_array_wildcard(b, parent);
1148 }
1149
1150 case nir_deref_type_struct:
1151 assert(glsl_type_is_struct_or_ifc(parent->type));
1152 assert(glsl_get_length(parent->type) ==
1153 glsl_get_length(leader_parent->type));
1154
1155 return nir_build_deref_struct(b, parent, leader->strct.index);
1156
1157 default:
1158 unreachable("Invalid deref instruction type");
1159 }
1160 }
1161
1162 static inline nir_ssa_def *
1163 nir_load_reg(nir_builder *build, nir_register *reg)
1164 {
1165 return nir_ssa_for_src(build, nir_src_for_reg(reg), reg->num_components);
1166 }
1167
1168 static inline void
1169 nir_store_reg(nir_builder *build, nir_register *reg,
1170 nir_ssa_def *def, nir_component_mask_t write_mask)
1171 {
1172 assert(reg->num_components == def->num_components);
1173 assert(reg->bit_size == def->bit_size);
1174
1175 nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
1176 mov->src[0].src = nir_src_for_ssa(def);
1177 mov->dest.dest = nir_dest_for_reg(reg);
1178 mov->dest.write_mask = write_mask & BITFIELD_MASK(reg->num_components);
1179 nir_builder_instr_insert(build, &mov->instr);
1180 }
1181
1182 static inline nir_ssa_def *
1183 nir_load_deref_with_access(nir_builder *build, nir_deref_instr *deref,
1184 enum gl_access_qualifier access)
1185 {
1186 nir_intrinsic_instr *load =
1187 nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_deref);
1188 load->num_components = glsl_get_vector_elements(deref->type);
1189 load->src[0] = nir_src_for_ssa(&deref->dest.ssa);
1190 nir_ssa_dest_init(&load->instr, &load->dest, load->num_components,
1191 glsl_get_bit_size(deref->type), NULL);
1192 nir_intrinsic_set_access(load, access);
1193 nir_builder_instr_insert(build, &load->instr);
1194 return &load->dest.ssa;
1195 }
1196
1197 static inline nir_ssa_def *
1198 nir_load_deref(nir_builder *build, nir_deref_instr *deref)
1199 {
1200 return nir_load_deref_with_access(build, deref, (enum gl_access_qualifier)0);
1201 }
1202
1203 static inline void
1204 nir_store_deref_with_access(nir_builder *build, nir_deref_instr *deref,
1205 nir_ssa_def *value, unsigned writemask,
1206 enum gl_access_qualifier access)
1207 {
1208 nir_intrinsic_instr *store =
1209 nir_intrinsic_instr_create(build->shader, nir_intrinsic_store_deref);
1210 store->num_components = glsl_get_vector_elements(deref->type);
1211 store->src[0] = nir_src_for_ssa(&deref->dest.ssa);
1212 store->src[1] = nir_src_for_ssa(value);
1213 nir_intrinsic_set_write_mask(store,
1214 writemask & ((1 << store->num_components) - 1));
1215 nir_intrinsic_set_access(store, access);
1216 nir_builder_instr_insert(build, &store->instr);
1217 }
1218
1219 static inline void
1220 nir_store_deref(nir_builder *build, nir_deref_instr *deref,
1221 nir_ssa_def *value, unsigned writemask)
1222 {
1223 nir_store_deref_with_access(build, deref, value, writemask,
1224 (enum gl_access_qualifier)0);
1225 }
1226
1227 static inline void
1228 nir_copy_deref_with_access(nir_builder *build, nir_deref_instr *dest,
1229 nir_deref_instr *src,
1230 enum gl_access_qualifier dest_access,
1231 enum gl_access_qualifier src_access)
1232 {
1233 nir_intrinsic_instr *copy =
1234 nir_intrinsic_instr_create(build->shader, nir_intrinsic_copy_deref);
1235 copy->src[0] = nir_src_for_ssa(&dest->dest.ssa);
1236 copy->src[1] = nir_src_for_ssa(&src->dest.ssa);
1237 nir_intrinsic_set_dst_access(copy, dest_access);
1238 nir_intrinsic_set_src_access(copy, src_access);
1239 nir_builder_instr_insert(build, &copy->instr);
1240 }
1241
1242 static inline void
1243 nir_copy_deref(nir_builder *build, nir_deref_instr *dest, nir_deref_instr *src)
1244 {
1245 nir_copy_deref_with_access(build, dest, src,
1246 (enum gl_access_qualifier) 0,
1247 (enum gl_access_qualifier) 0);
1248 }
1249
1250 static inline nir_ssa_def *
1251 nir_load_var(nir_builder *build, nir_variable *var)
1252 {
1253 return nir_load_deref(build, nir_build_deref_var(build, var));
1254 }
1255
1256 static inline void
1257 nir_store_var(nir_builder *build, nir_variable *var, nir_ssa_def *value,
1258 unsigned writemask)
1259 {
1260 nir_store_deref(build, nir_build_deref_var(build, var), value, writemask);
1261 }
1262
1263 static inline void
1264 nir_copy_var(nir_builder *build, nir_variable *dest, nir_variable *src)
1265 {
1266 nir_copy_deref(build, nir_build_deref_var(build, dest),
1267 nir_build_deref_var(build, src));
1268 }
1269
1270 static inline nir_ssa_def *
1271 nir_load_param(nir_builder *build, uint32_t param_idx)
1272 {
1273 assert(param_idx < build->impl->function->num_params);
1274 nir_parameter *param = &build->impl->function->params[param_idx];
1275
1276 nir_intrinsic_instr *load =
1277 nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_param);
1278 nir_intrinsic_set_param_idx(load, param_idx);
1279 load->num_components = param->num_components;
1280 nir_ssa_dest_init(&load->instr, &load->dest,
1281 param->num_components, param->bit_size, NULL);
1282 nir_builder_instr_insert(build, &load->instr);
1283 return &load->dest.ssa;
1284 }
1285
1286 #include "nir_builder_opcodes.h"
1287
1288 static inline nir_ssa_def *
1289 nir_f2b(nir_builder *build, nir_ssa_def *f)
1290 {
1291 return nir_f2b1(build, f);
1292 }
1293
1294 static inline nir_ssa_def *
1295 nir_i2b(nir_builder *build, nir_ssa_def *i)
1296 {
1297 return nir_i2b1(build, i);
1298 }
1299
1300 static inline nir_ssa_def *
1301 nir_b2f(nir_builder *build, nir_ssa_def *b, uint32_t bit_size)
1302 {
1303 switch (bit_size) {
1304 case 64: return nir_b2f64(build, b);
1305 case 32: return nir_b2f32(build, b);
1306 case 16: return nir_b2f16(build, b);
1307 default:
1308 unreachable("Invalid bit-size");
1309 };
1310 }
1311
1312 static inline nir_ssa_def *
1313 nir_b2i(nir_builder *build, nir_ssa_def *b, uint32_t bit_size)
1314 {
1315 switch (bit_size) {
1316 case 64: return nir_b2i64(build, b);
1317 case 32: return nir_b2i32(build, b);
1318 case 16: return nir_b2i16(build, b);
1319 case 8: return nir_b2i8(build, b);
1320 default:
1321 unreachable("Invalid bit-size");
1322 };
1323 }
1324 static inline nir_ssa_def *
1325 nir_load_barycentric(nir_builder *build, nir_intrinsic_op op,
1326 unsigned interp_mode)
1327 {
1328 unsigned num_components = op == nir_intrinsic_load_barycentric_model ? 3 : 2;
1329 nir_intrinsic_instr *bary = nir_intrinsic_instr_create(build->shader, op);
1330 nir_ssa_dest_init(&bary->instr, &bary->dest, num_components, 32, NULL);
1331 nir_intrinsic_set_interp_mode(bary, interp_mode);
1332 nir_builder_instr_insert(build, &bary->instr);
1333 return &bary->dest.ssa;
1334 }
1335
1336 static inline void
1337 nir_jump(nir_builder *build, nir_jump_type jump_type)
1338 {
1339 nir_jump_instr *jump = nir_jump_instr_create(build->shader, jump_type);
1340 nir_builder_instr_insert(build, &jump->instr);
1341 }
1342
1343 static inline nir_ssa_def *
1344 nir_compare_func(nir_builder *b, enum compare_func func,
1345 nir_ssa_def *src0, nir_ssa_def *src1)
1346 {
1347 switch (func) {
1348 case COMPARE_FUNC_NEVER:
1349 return nir_imm_int(b, 0);
1350 case COMPARE_FUNC_ALWAYS:
1351 return nir_imm_int(b, ~0);
1352 case COMPARE_FUNC_EQUAL:
1353 return nir_feq(b, src0, src1);
1354 case COMPARE_FUNC_NOTEQUAL:
1355 return nir_fne(b, src0, src1);
1356 case COMPARE_FUNC_GREATER:
1357 return nir_flt(b, src1, src0);
1358 case COMPARE_FUNC_GEQUAL:
1359 return nir_fge(b, src0, src1);
1360 case COMPARE_FUNC_LESS:
1361 return nir_flt(b, src0, src1);
1362 case COMPARE_FUNC_LEQUAL:
1363 return nir_fge(b, src1, src0);
1364 }
1365 unreachable("bad compare func");
1366 }
1367
1368 static inline void
1369 nir_scoped_barrier(nir_builder *b,
1370 nir_scope exec_scope,
1371 nir_scope mem_scope,
1372 nir_memory_semantics mem_semantics,
1373 nir_variable_mode mem_modes)
1374 {
1375 nir_intrinsic_instr *intrin =
1376 nir_intrinsic_instr_create(b->shader, nir_intrinsic_scoped_barrier);
1377 nir_intrinsic_set_execution_scope(intrin, exec_scope);
1378 nir_intrinsic_set_memory_scope(intrin, mem_scope);
1379 nir_intrinsic_set_memory_semantics(intrin, mem_semantics);
1380 nir_intrinsic_set_memory_modes(intrin, mem_modes);
1381 nir_builder_instr_insert(b, &intrin->instr);
1382 }
1383
1384 static inline void
1385 nir_scoped_memory_barrier(nir_builder *b,
1386 nir_scope scope,
1387 nir_memory_semantics semantics,
1388 nir_variable_mode modes)
1389 {
1390 nir_scoped_barrier(b, NIR_SCOPE_NONE, scope, semantics, modes);
1391 }
1392
1393 static inline nir_ssa_def *
1394 nir_convert_to_bit_size(nir_builder *b,
1395 nir_ssa_def *src,
1396 nir_alu_type type,
1397 unsigned bit_size)
1398 {
1399 nir_alu_type base_type = nir_alu_type_get_base_type(type);
1400 nir_alu_type dst_type = (nir_alu_type)(bit_size | base_type);
1401
1402 nir_op opcode =
1403 nir_type_conversion_op(type, dst_type, nir_rounding_mode_undef);
1404
1405 return nir_build_alu(b, opcode, src, NULL, NULL, NULL);
1406 }
1407
1408 static inline nir_ssa_def *
1409 nir_i2iN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
1410 {
1411 return nir_convert_to_bit_size(b, src, nir_type_int, bit_size);
1412 }
1413
1414 static inline nir_ssa_def *
1415 nir_u2uN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
1416 {
1417 return nir_convert_to_bit_size(b, src, nir_type_uint, bit_size);
1418 }
1419
1420 static inline nir_ssa_def *
1421 nir_b2bN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
1422 {
1423 return nir_convert_to_bit_size(b, src, nir_type_bool, bit_size);
1424 }
1425
1426 static inline nir_ssa_def *
1427 nir_f2fN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
1428 {
1429 return nir_convert_to_bit_size(b, src, nir_type_float, bit_size);
1430 }
1431
1432 #endif /* NIR_BUILDER_H */