nir: Add a nir->info.uses_interp_var_at_offset flag.
[mesa.git] / src / compiler / nir / nir_gather_info.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "nir.h"
25
26 static void
27 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader)
28 {
29 switch (instr->intrinsic) {
30 case nir_intrinsic_discard:
31 case nir_intrinsic_discard_if:
32 assert(shader->stage == MESA_SHADER_FRAGMENT);
33 shader->info.fs.uses_discard = true;
34 break;
35
36 case nir_intrinsic_load_front_face:
37 case nir_intrinsic_load_vertex_id:
38 case nir_intrinsic_load_vertex_id_zero_base:
39 case nir_intrinsic_load_base_vertex:
40 case nir_intrinsic_load_instance_id:
41 case nir_intrinsic_load_sample_id:
42 case nir_intrinsic_load_sample_pos:
43 case nir_intrinsic_load_sample_mask_in:
44 case nir_intrinsic_load_primitive_id:
45 case nir_intrinsic_load_invocation_id:
46 case nir_intrinsic_load_local_invocation_id:
47 case nir_intrinsic_load_work_group_id:
48 case nir_intrinsic_load_num_work_groups:
49 shader->info.system_values_read |=
50 (1 << nir_system_value_from_intrinsic(instr->intrinsic));
51 break;
52
53 case nir_intrinsic_end_primitive:
54 case nir_intrinsic_end_primitive_with_counter:
55 assert(shader->stage == MESA_SHADER_GEOMETRY);
56 shader->info.gs.uses_end_primitive = 1;
57 break;
58
59 case nir_intrinsic_interp_var_at_offset:
60 shader->info.uses_interp_var_at_offset = 1;
61 break;
62
63 default:
64 break;
65 }
66 }
67
68 static void
69 gather_tex_info(nir_tex_instr *instr, nir_shader *shader)
70 {
71 if (instr->op == nir_texop_tg4)
72 shader->info.uses_texture_gather = true;
73 }
74
75 static void
76 gather_info_block(nir_block *block, nir_shader *shader)
77 {
78 nir_foreach_instr(instr, block) {
79 switch (instr->type) {
80 case nir_instr_type_intrinsic:
81 gather_intrinsic_info(nir_instr_as_intrinsic(instr), shader);
82 break;
83 case nir_instr_type_tex:
84 gather_tex_info(nir_instr_as_tex(instr), shader);
85 break;
86 case nir_instr_type_call:
87 assert(!"nir_shader_gather_info only works if functions are inlined");
88 break;
89 default:
90 break;
91 }
92 }
93 }
94
95 /**
96 * Returns the bits in the inputs_read, outputs_written, or
97 * system_values_read bitfield corresponding to this variable.
98 */
99 static inline uint64_t
100 get_io_mask(nir_variable *var, gl_shader_stage stage)
101 {
102 assert(var->data.mode == nir_var_shader_in ||
103 var->data.mode == nir_var_shader_out ||
104 var->data.mode == nir_var_system_value);
105 assert(var->data.location >= 0);
106
107 const struct glsl_type *var_type = var->type;
108 if (stage == MESA_SHADER_GEOMETRY && var->data.mode == nir_var_shader_in) {
109 /* Most geometry shader inputs are per-vertex arrays */
110 if (var->data.location >= VARYING_SLOT_VAR0)
111 assert(glsl_type_is_array(var_type));
112
113 if (glsl_type_is_array(var_type))
114 var_type = glsl_get_array_element(var_type);
115 }
116
117 bool is_vertex_input = (var->data.mode == nir_var_shader_in &&
118 stage == MESA_SHADER_VERTEX);
119 unsigned slots = glsl_count_attribute_slots(var_type, is_vertex_input);
120 return ((1ull << slots) - 1) << var->data.location;
121 }
122
123 void
124 nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
125 {
126 /* This pass does not yet support tessellation shaders */
127 assert(shader->stage == MESA_SHADER_VERTEX ||
128 shader->stage == MESA_SHADER_GEOMETRY ||
129 shader->stage == MESA_SHADER_FRAGMENT ||
130 shader->stage == MESA_SHADER_COMPUTE);
131
132 bool uses_sample_qualifier = false;
133 shader->info.inputs_read = 0;
134 foreach_list_typed(nir_variable, var, node, &shader->inputs) {
135 shader->info.inputs_read |= get_io_mask(var, shader->stage);
136 uses_sample_qualifier |= var->data.sample;
137 }
138
139 if (shader->stage == MESA_SHADER_FRAGMENT)
140 shader->info.fs.uses_sample_qualifier = uses_sample_qualifier;
141
142 /* TODO: Some day we may need to add stream support to NIR */
143 shader->info.outputs_written = 0;
144 foreach_list_typed(nir_variable, var, node, &shader->outputs)
145 shader->info.outputs_written |= get_io_mask(var, shader->stage);
146
147 shader->info.system_values_read = 0;
148 foreach_list_typed(nir_variable, var, node, &shader->system_values)
149 shader->info.system_values_read |= get_io_mask(var, shader->stage);
150
151 shader->info.num_textures = 0;
152 shader->info.num_images = 0;
153 nir_foreach_variable(var, &shader->uniforms) {
154 const struct glsl_type *type = var->type;
155 unsigned count = 1;
156 if (glsl_type_is_array(type)) {
157 count = glsl_get_length(type);
158 type = glsl_get_array_element(type);
159 }
160
161 if (glsl_type_is_image(type)) {
162 shader->info.num_images += count;
163 } else if (glsl_type_is_sampler(type)) {
164 shader->info.num_textures += count;
165 }
166 }
167
168 nir_foreach_block(block, entrypoint) {
169 gather_info_block(block, shader);
170 }
171 }