f85e53ac75839053470c58a33898e3869cea9a75
[mesa.git] / src / compiler / nir / nir_lower_io_to_vector.c
1 /*
2 * Copyright © 2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "nir.h"
25 #include "nir_builder.h"
26 #include "nir_deref.h"
27
28 /** @file nir_lower_io_to_vector.c
29 *
30 * Merges compatible input/output variables residing in different components
31 * of the same location. It's expected that further passes such as
32 * nir_lower_io_to_temporaries will combine loads and stores of the merged
33 * variables, producing vector nir_load_input/nir_store_output instructions
34 * when all is said and done.
35 */
36
37 /* FRAG_RESULT_MAX+1 instead of just FRAG_RESULT_MAX because of how this pass
38 * handles dual source blending */
39 #define MAX_SLOTS MAX2(VARYING_SLOT_TESS_MAX, FRAG_RESULT_MAX+1)
40
41 static unsigned
42 get_slot(const nir_variable *var)
43 {
44 /* This handling of dual-source blending might not be correct when more than
45 * one render target is supported, but it seems no driver supports more than
46 * one. */
47 return var->data.location + var->data.index;
48 }
49
50 static const struct glsl_type *
51 get_per_vertex_type(const nir_shader *shader, const nir_variable *var,
52 unsigned *num_vertices)
53 {
54 if (nir_is_per_vertex_io(var, shader->info.stage)) {
55 assert(glsl_type_is_array(var->type));
56 if (num_vertices)
57 *num_vertices = glsl_get_length(var->type);
58 return glsl_get_array_element(var->type);
59 } else {
60 if (num_vertices)
61 *num_vertices = 0;
62 return var->type;
63 }
64 }
65
66 static const struct glsl_type *
67 resize_array_vec_type(const struct glsl_type *type, unsigned num_components)
68 {
69 if (glsl_type_is_array(type)) {
70 const struct glsl_type *arr_elem =
71 resize_array_vec_type(glsl_get_array_element(type), num_components);
72 return glsl_array_type(arr_elem, glsl_get_length(type), 0);
73 } else {
74 assert(glsl_type_is_vector_or_scalar(type));
75 return glsl_vector_type(glsl_get_base_type(type), num_components);
76 }
77 }
78
79 static bool
80 variables_can_merge(const nir_shader *shader,
81 const nir_variable *a, const nir_variable *b,
82 bool same_array_structure)
83 {
84 if (a->data.compact || b->data.compact)
85 return false;
86
87 if (a->data.per_view || b->data.per_view)
88 return false;
89
90 const struct glsl_type *a_type_tail = a->type;
91 const struct glsl_type *b_type_tail = b->type;
92
93 if (nir_is_per_vertex_io(a, shader->info.stage) !=
94 nir_is_per_vertex_io(b, shader->info.stage))
95 return false;
96
97 /* They must have the same array structure */
98 if (same_array_structure) {
99 while (glsl_type_is_array(a_type_tail)) {
100 if (!glsl_type_is_array(b_type_tail))
101 return false;
102
103 if (glsl_get_length(a_type_tail) != glsl_get_length(b_type_tail))
104 return false;
105
106 a_type_tail = glsl_get_array_element(a_type_tail);
107 b_type_tail = glsl_get_array_element(b_type_tail);
108 }
109 if (glsl_type_is_array(b_type_tail))
110 return false;
111 } else {
112 a_type_tail = glsl_without_array(a_type_tail);
113 b_type_tail = glsl_without_array(b_type_tail);
114 }
115
116 if (!glsl_type_is_vector_or_scalar(a_type_tail) ||
117 !glsl_type_is_vector_or_scalar(b_type_tail))
118 return false;
119
120 if (glsl_get_base_type(a_type_tail) != glsl_get_base_type(b_type_tail))
121 return false;
122
123 /* TODO: add 64/16bit support ? */
124 if (glsl_get_bit_size(a_type_tail) != 32)
125 return false;
126
127 assert(a->data.mode == b->data.mode);
128 if (shader->info.stage == MESA_SHADER_FRAGMENT &&
129 a->data.mode == nir_var_shader_in &&
130 a->data.interpolation != b->data.interpolation)
131 return false;
132
133 if (shader->info.stage == MESA_SHADER_FRAGMENT &&
134 a->data.mode == nir_var_shader_out &&
135 a->data.index != b->data.index)
136 return false;
137
138 return true;
139 }
140
141 static const struct glsl_type *
142 get_flat_type(const nir_shader *shader, nir_variable *old_vars[MAX_SLOTS][4],
143 unsigned *loc, nir_variable **first_var, unsigned *num_vertices)
144 {
145 unsigned todo = 1;
146 unsigned slots = 0;
147 unsigned num_vars = 0;
148 enum glsl_base_type base;
149 *num_vertices = 0;
150 *first_var = NULL;
151
152 while (todo) {
153 assert(*loc < MAX_SLOTS);
154 for (unsigned frac = 0; frac < 4; frac++) {
155 nir_variable *var = old_vars[*loc][frac];
156 if (!var)
157 continue;
158 if ((*first_var &&
159 !variables_can_merge(shader, var, *first_var, false)) ||
160 var->data.compact) {
161 (*loc)++;
162 return NULL;
163 }
164
165 if (!*first_var) {
166 if (!glsl_type_is_vector_or_scalar(glsl_without_array(var->type))) {
167 (*loc)++;
168 return NULL;
169 }
170 *first_var = var;
171 base = glsl_get_base_type(
172 glsl_without_array(get_per_vertex_type(shader, var, NULL)));
173 }
174
175 bool vs_in = shader->info.stage == MESA_SHADER_VERTEX &&
176 var->data.mode == nir_var_shader_in;
177 unsigned var_slots = glsl_count_attribute_slots(
178 get_per_vertex_type(shader, var, num_vertices), vs_in);
179 todo = MAX2(todo, var_slots);
180 num_vars++;
181 }
182 todo--;
183 slots++;
184 (*loc)++;
185 }
186
187 if (num_vars <= 1)
188 return NULL;
189
190 if (slots == 1)
191 return glsl_vector_type(base, 4);
192 else
193 return glsl_array_type(glsl_vector_type(base, 4), slots, 0);
194 }
195
196 static bool
197 create_new_io_vars(nir_shader *shader, struct exec_list *io_list,
198 nir_variable *new_vars[MAX_SLOTS][4],
199 bool flat_vars[MAX_SLOTS])
200 {
201 if (exec_list_is_empty(io_list))
202 return false;
203
204 nir_variable *old_vars[MAX_SLOTS][4] = {{0}};
205
206 nir_foreach_variable(var, io_list) {
207 unsigned frac = var->data.location_frac;
208 old_vars[get_slot(var)][frac] = var;
209 }
210
211 bool merged_any_vars = false;
212
213 for (unsigned loc = 0; loc < MAX_SLOTS; loc++) {
214 unsigned frac = 0;
215 while (frac < 4) {
216 nir_variable *first_var = old_vars[loc][frac];
217 if (!first_var) {
218 frac++;
219 continue;
220 }
221
222 int first = frac;
223 bool found_merge = false;
224
225 while (frac < 4) {
226 nir_variable *var = old_vars[loc][frac];
227 if (!var)
228 break;
229
230 if (var != first_var) {
231 if (!variables_can_merge(shader, first_var, var, true))
232 break;
233
234 found_merge = true;
235 }
236
237 const unsigned num_components =
238 glsl_get_components(glsl_without_array(var->type));
239 if (!num_components) {
240 assert(frac == 0);
241 frac++;
242 break; /* The type was a struct. */
243 }
244
245 /* We had better not have any overlapping vars */
246 for (unsigned i = 1; i < num_components; i++)
247 assert(old_vars[loc][frac + i] == NULL);
248
249 frac += num_components;
250 }
251
252 if (!found_merge)
253 continue;
254
255 merged_any_vars = true;
256
257 nir_variable *var = nir_variable_clone(old_vars[loc][first], shader);
258 var->data.location_frac = first;
259 var->type = resize_array_vec_type(var->type, frac - first);
260
261 nir_shader_add_variable(shader, var);
262 for (unsigned i = first; i < frac; i++) {
263 new_vars[loc][i] = var;
264 old_vars[loc][i] = NULL;
265 }
266
267 old_vars[loc][first] = var;
268 }
269 }
270
271 /* "flat" mode: tries to ensure there is at most one variable per slot by
272 * merging variables into vec4s
273 */
274 for (unsigned loc = 0; loc < MAX_SLOTS;) {
275 nir_variable *first_var;
276 unsigned num_vertices;
277 unsigned new_loc = loc;
278 const struct glsl_type *flat_type =
279 get_flat_type(shader, old_vars, &new_loc, &first_var, &num_vertices);
280 if (flat_type) {
281 merged_any_vars = true;
282
283 nir_variable *var = nir_variable_clone(first_var, shader);
284 var->data.location_frac = 0;
285 if (num_vertices)
286 var->type = glsl_array_type(flat_type, num_vertices, 0);
287 else
288 var->type = flat_type;
289
290 nir_shader_add_variable(shader, var);
291 for (unsigned i = 0; i < glsl_get_length(flat_type); i++) {
292 for (unsigned j = 0; j < 4; j++)
293 new_vars[loc + i][j] = var;
294 flat_vars[loc + i] = true;
295 }
296 }
297 loc = new_loc;
298 }
299
300 return merged_any_vars;
301 }
302
303 static nir_deref_instr *
304 build_array_deref_of_new_var(nir_builder *b, nir_variable *new_var,
305 nir_deref_instr *leader)
306 {
307 if (leader->deref_type == nir_deref_type_var)
308 return nir_build_deref_var(b, new_var);
309
310 nir_deref_instr *parent =
311 build_array_deref_of_new_var(b, new_var, nir_deref_instr_parent(leader));
312
313 return nir_build_deref_follower(b, parent, leader);
314 }
315
316 static nir_ssa_def *
317 build_array_index(nir_builder *b, nir_deref_instr *deref, nir_ssa_def *base,
318 bool vs_in)
319 {
320 switch (deref->deref_type) {
321 case nir_deref_type_var:
322 return base;
323 case nir_deref_type_array: {
324 nir_ssa_def *index = nir_i2i(b, deref->arr.index.ssa,
325 deref->dest.ssa.bit_size);
326 return nir_iadd(
327 b, build_array_index(b, nir_deref_instr_parent(deref), base, vs_in),
328 nir_amul_imm(b, index, glsl_count_attribute_slots(deref->type, vs_in)));
329 }
330 default:
331 unreachable("Invalid deref instruction type");
332 }
333 }
334
335 static nir_deref_instr *
336 build_array_deref_of_new_var_flat(nir_shader *shader,
337 nir_builder *b, nir_variable *new_var,
338 nir_deref_instr *leader, unsigned base)
339 {
340 nir_deref_instr *deref = nir_build_deref_var(b, new_var);
341
342 if (nir_is_per_vertex_io(new_var, shader->info.stage)) {
343 assert(leader->deref_type == nir_deref_type_array);
344 nir_ssa_def *index = leader->arr.index.ssa;
345 leader = nir_deref_instr_parent(leader);
346 deref = nir_build_deref_array(b, deref, index);
347 }
348
349 if (!glsl_type_is_array(deref->type))
350 return deref;
351
352 bool vs_in = shader->info.stage == MESA_SHADER_VERTEX &&
353 new_var->data.mode == nir_var_shader_in;
354 return nir_build_deref_array(
355 b, deref, build_array_index(b, leader, nir_imm_int(b, base), vs_in));
356 }
357
358 static bool
359 nir_lower_io_to_vector_impl(nir_function_impl *impl, nir_variable_mode modes)
360 {
361 assert(!(modes & ~(nir_var_shader_in | nir_var_shader_out)));
362
363 nir_builder b;
364 nir_builder_init(&b, impl);
365
366 nir_metadata_require(impl, nir_metadata_dominance);
367
368 nir_shader *shader = impl->function->shader;
369 nir_variable *new_inputs[MAX_SLOTS][4] = {{0}};
370 nir_variable *new_outputs[MAX_SLOTS][4] = {{0}};
371 bool flat_inputs[MAX_SLOTS] = {0};
372 bool flat_outputs[MAX_SLOTS] = {0};
373
374 if (modes & nir_var_shader_in) {
375 /* Vertex shaders support overlapping inputs. We don't do those */
376 assert(b.shader->info.stage != MESA_SHADER_VERTEX);
377
378 /* If we don't actually merge any variables, remove that bit from modes
379 * so we don't bother doing extra non-work.
380 */
381 if (!create_new_io_vars(shader, &shader->inputs,
382 new_inputs, flat_inputs))
383 modes &= ~nir_var_shader_in;
384 }
385
386 if (modes & nir_var_shader_out) {
387 /* If we don't actually merge any variables, remove that bit from modes
388 * so we don't bother doing extra non-work.
389 */
390 if (!create_new_io_vars(shader, &shader->outputs,
391 new_outputs, flat_outputs))
392 modes &= ~nir_var_shader_out;
393 }
394
395 if (!modes)
396 return false;
397
398 bool progress = false;
399
400 /* Actually lower all the IO load/store intrinsics. Load instructions are
401 * lowered to a vector load and an ALU instruction to grab the channels we
402 * want. Outputs are lowered to a write-masked store of the vector output.
403 * For non-TCS outputs, we then run nir_lower_io_to_temporaries at the end
404 * to clean up the partial writes.
405 */
406 nir_foreach_block(block, impl) {
407 nir_foreach_instr_safe(instr, block) {
408 if (instr->type != nir_instr_type_intrinsic)
409 continue;
410
411 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
412
413 switch (intrin->intrinsic) {
414 case nir_intrinsic_load_deref:
415 case nir_intrinsic_interp_deref_at_centroid:
416 case nir_intrinsic_interp_deref_at_sample:
417 case nir_intrinsic_interp_deref_at_offset:
418 case nir_intrinsic_interp_deref_at_vertex: {
419 nir_deref_instr *old_deref = nir_src_as_deref(intrin->src[0]);
420 if (!(old_deref->mode & modes))
421 break;
422
423 if (old_deref->mode == nir_var_shader_out)
424 assert(b.shader->info.stage == MESA_SHADER_TESS_CTRL ||
425 b.shader->info.stage == MESA_SHADER_FRAGMENT);
426
427 nir_variable *old_var = nir_deref_instr_get_variable(old_deref);
428
429 const unsigned loc = get_slot(old_var);
430 const unsigned old_frac = old_var->data.location_frac;
431 nir_variable *new_var = old_deref->mode == nir_var_shader_in ?
432 new_inputs[loc][old_frac] :
433 new_outputs[loc][old_frac];
434 bool flat = old_deref->mode == nir_var_shader_in ?
435 flat_inputs[loc] : flat_outputs[loc];
436 if (!new_var)
437 break;
438
439 const unsigned new_frac = new_var->data.location_frac;
440
441 nir_component_mask_t vec4_comp_mask =
442 ((1 << intrin->num_components) - 1) << old_frac;
443
444 b.cursor = nir_before_instr(&intrin->instr);
445
446 /* Rewrite the load to use the new variable and only select a
447 * portion of the result.
448 */
449 nir_deref_instr *new_deref;
450 if (flat) {
451 new_deref = build_array_deref_of_new_var_flat(
452 shader, &b, new_var, old_deref, loc - get_slot(new_var));
453 } else {
454 assert(get_slot(new_var) == loc);
455 new_deref = build_array_deref_of_new_var(&b, new_var, old_deref);
456 assert(glsl_type_is_vector(new_deref->type));
457 }
458 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
459 nir_src_for_ssa(&new_deref->dest.ssa));
460
461 intrin->num_components =
462 glsl_get_components(new_deref->type);
463 intrin->dest.ssa.num_components = intrin->num_components;
464
465 b.cursor = nir_after_instr(&intrin->instr);
466
467 nir_ssa_def *new_vec = nir_channels(&b, &intrin->dest.ssa,
468 vec4_comp_mask >> new_frac);
469 nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa,
470 nir_src_for_ssa(new_vec),
471 new_vec->parent_instr);
472
473 progress = true;
474 break;
475 }
476
477 case nir_intrinsic_store_deref: {
478 nir_deref_instr *old_deref = nir_src_as_deref(intrin->src[0]);
479 if (old_deref->mode != nir_var_shader_out)
480 break;
481
482 nir_variable *old_var = nir_deref_instr_get_variable(old_deref);
483
484 const unsigned loc = get_slot(old_var);
485 const unsigned old_frac = old_var->data.location_frac;
486 nir_variable *new_var = new_outputs[loc][old_frac];
487 bool flat = flat_outputs[loc];
488 if (!new_var)
489 break;
490
491 const unsigned new_frac = new_var->data.location_frac;
492
493 b.cursor = nir_before_instr(&intrin->instr);
494
495 /* Rewrite the store to be a masked store to the new variable */
496 nir_deref_instr *new_deref;
497 if (flat) {
498 new_deref = build_array_deref_of_new_var_flat(
499 shader, &b, new_var, old_deref, loc - get_slot(new_var));
500 } else {
501 assert(get_slot(new_var) == loc);
502 new_deref = build_array_deref_of_new_var(&b, new_var, old_deref);
503 assert(glsl_type_is_vector(new_deref->type));
504 }
505 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
506 nir_src_for_ssa(&new_deref->dest.ssa));
507
508 intrin->num_components =
509 glsl_get_components(new_deref->type);
510
511 nir_component_mask_t old_wrmask = nir_intrinsic_write_mask(intrin);
512
513 assert(intrin->src[1].is_ssa);
514 nir_ssa_def *old_value = intrin->src[1].ssa;
515 nir_ssa_def *comps[4];
516 for (unsigned c = 0; c < intrin->num_components; c++) {
517 if (new_frac + c >= old_frac &&
518 (old_wrmask & 1 << (new_frac + c - old_frac))) {
519 comps[c] = nir_channel(&b, old_value,
520 new_frac + c - old_frac);
521 } else {
522 comps[c] = nir_ssa_undef(&b, old_value->num_components,
523 old_value->bit_size);
524 }
525 }
526 nir_ssa_def *new_value = nir_vec(&b, comps, intrin->num_components);
527 nir_instr_rewrite_src(&intrin->instr, &intrin->src[1],
528 nir_src_for_ssa(new_value));
529
530 nir_intrinsic_set_write_mask(intrin,
531 old_wrmask << (old_frac - new_frac));
532
533 progress = true;
534 break;
535 }
536
537 default:
538 break;
539 }
540 }
541 }
542
543 if (progress) {
544 nir_metadata_preserve(impl, nir_metadata_block_index |
545 nir_metadata_dominance);
546 }
547
548 return progress;
549 }
550
551 bool
552 nir_lower_io_to_vector(nir_shader *shader, nir_variable_mode modes)
553 {
554 bool progress = false;
555
556 nir_foreach_function(function, shader) {
557 if (function->impl)
558 progress |= nir_lower_io_to_vector_impl(function->impl, modes);
559 }
560
561 return progress;
562 }