src/freedreno/fdl/fd6_layout.c

   1 /*
   2  * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018-2019 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include <stdio.h>
  29
  30 #include "freedreno_layout.h"
  31
  32 /* indexed by cpp, including msaa 2x and 4x:
  33  * TODO:
  34  * cpp=1 UBWC needs testing at larger texture sizes
  35  * missing UBWC blockwidth/blockheight for npot+64 cpp
  36  * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
  37  */
  38 static const struct {
  39         unsigned basealign;
  40         unsigned pitchalign;
  41         unsigned heightalign;
  42         uint8_t ubwc_blockwidth;
  43         uint8_t ubwc_blockheight;
  44 } tile_alignment[] = {
  45         [1]  = {  64, 128, 32, 16, 4 },
  46         [2]  = { 128, 128, 16, 16, 4 },
  47         [3]  = { 256,  64, 32 },
  48         [4]  = { 256,  64, 16, 16, 4 },
  49         [6]  = { 256,  64, 16 },
  50         [8]  = { 256,  64, 16, 8, 4, },
  51         [12] = { 256,  64, 16 },
  52         [16] = { 256,  64, 16, 4, 4, },
  53         [24] = { 256,  64, 16 },
  54         [32] = { 256,  64, 16, 4, 2 },
  55         [48] = { 256,  64, 16 },
  56         [64] = { 256,  64, 16 },
  57
  58         /* special cases for r8g8: */
  59         [0]  = { 256, 64, 32, 16, 4 },
  60 };
  61
  62 #define RGB_TILE_WIDTH_ALIGNMENT 64
  63 #define RGB_TILE_HEIGHT_ALIGNMENT 16
  64 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
  65
  66 /* NOTE: good way to test this is:  (for example)
  67  *  piglit/bin/texelFetch fs sampler3D 100x100x8
  68  */
  69 void
  70 fdl6_layout(struct fdl_layout *layout,
  71                 enum pipe_format format, uint32_t nr_samples,
  72                 uint32_t width0, uint32_t height0, uint32_t depth0,
  73                 uint32_t mip_levels, uint32_t array_size, bool is_3d)
  74 {
  75         assert(nr_samples > 0);
  76         layout->width0 = width0;
  77         layout->height0 = height0;
  78         layout->depth0 = depth0;
  79
  80         layout->cpp = util_format_get_blocksize(format);
  81         layout->cpp *= nr_samples;
  82         layout->format = format;
  83         layout->nr_samples = nr_samples;
  84
  85         if (depth0 > 1)
  86                 layout->ubwc = false;
  87         if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
  88                 layout->ubwc = false;
  89
  90         const struct util_format_description *format_desc =
  91                 util_format_description(format);
  92         int ta = layout->cpp;
  93
  94         /* The z16/r16 formats seem to not play by the normal tiling rules: */
  95         if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
  96                 ta = 0;
  97
  98         uint32_t alignment;
  99         if (is_3d) {
 100                 layout->layer_first = false;
 101                 alignment = 4096;
 102         } else {
 103                 layout->layer_first = true;
 104                 alignment = 1;
 105         }
 106         /* in layer_first layout, the level (slice) contains just one
 107          * layer (since in fact the layer contains the slices)
 108          */
 109         uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
 110
 111         debug_assert(ta < ARRAY_SIZE(tile_alignment));
 112         debug_assert(tile_alignment[ta].pitchalign);
 113
 114         if (layout->tile_mode) {
 115                 layout->base_align = tile_alignment[ta].basealign;
 116         } else {
 117                 layout->base_align = 64;
 118         }
 119
 120         for (uint32_t level = 0; level < mip_levels; level++) {
 121                 uint32_t depth = u_minify(depth0, level);
 122                 struct fdl_slice *slice = &layout->slices[level];
 123                 struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
 124                 uint32_t tile_mode = fdl_tile_mode(layout, level);
 125                 uint32_t width, height;
 126
 127                 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
 128                 if (is_3d && tile_mode) {
 129                         width = u_minify(util_next_power_of_two(width0), level);
 130                         height = u_minify(util_next_power_of_two(height0), level);
 131                 } else {
 132                         width = u_minify(width0, level);
 133                         height = u_minify(height0, level);
 134                 }
 135                 uint32_t aligned_height = height;
 136                 uint32_t pitchalign;
 137
 138                 if (tile_mode) {
 139                         pitchalign = tile_alignment[ta].pitchalign;
 140                         aligned_height = align(aligned_height,
 141                                         tile_alignment[ta].heightalign);
 142                 } else {
 143                         pitchalign = 64;
 144                 }
 145
 146                 /* The blits used for mem<->gmem work at a granularity of
 147                  * 32x32, which can cause faults due to over-fetch on the
 148                  * last level.  The simple solution is to over-allocate a
 149                  * bit the last level to ensure any over-fetch is harmless.
 150                  * The pitch is already sufficiently aligned, but height
 151                  * may not be:
 152                  */
 153                 if (level == mip_levels - 1)
 154                         aligned_height = align(aligned_height, 32);
 155
 156                 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC)
 157                         slice->pitch =
 158                                 util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
 159                 else
 160                         slice->pitch = align(width, pitchalign);
 161
 162                 slice->offset = layout->size;
 163                 uint32_t blocks = util_format_get_nblocks(format,
 164                                 slice->pitch, aligned_height);
 165
 166                 /* 1d array and 2d array textures must all have the same layer size
 167                  * for each miplevel on a6xx. 3d textures can have different layer
 168                  * sizes for high levels, but the hw auto-sizer is buggy (or at least
 169                  * different than what this code does), so as soon as the layer size
 170                  * range gets into range, we stop reducing it.
 171                  */
 172                 if (is_3d) {
 173                         if (level < 1 || layout->slices[level - 1].size0 > 0xf000) {
 174                                 slice->size0 = align(blocks * layout->cpp, alignment);
 175                         } else {
 176                                 slice->size0 = layout->slices[level - 1].size0;
 177                         }
 178                 } else {
 179                         slice->size0 = align(blocks * layout->cpp, alignment);
 180                 }
 181
 182                 layout->size += slice->size0 * depth * layers_in_level;
 183
 184                 if (layout->ubwc) {
 185                         /* with UBWC every level is aligned to 4K */
 186                         layout->size = align(layout->size, 4096);
 187
 188                         uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
 189                         uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
 190                         uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
 191                                         RGB_TILE_WIDTH_ALIGNMENT);
 192                         uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
 193                                         RGB_TILE_HEIGHT_ALIGNMENT);
 194
 195                         /* it looks like mipmaps need alignment to power of two
 196                          * TODO: needs testing with large npot textures
 197                          * (needed for the first level?)
 198                          */
 199                         if (mip_levels > 1) {
 200                                 meta_pitch = util_next_power_of_two(meta_pitch);
 201                                 meta_height = util_next_power_of_two(meta_height);
 202                         }
 203
 204                         ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
 205                         ubwc_slice->pitch = meta_pitch;
 206                         ubwc_slice->offset = layout->ubwc_layer_size;
 207                         layout->ubwc_layer_size += ubwc_slice->size0;
 208                 }
 209         }
 210
 211         if (layout->layer_first) {
 212                 layout->layer_size = align(layout->size, 4096);
 213                 layout->size = layout->layer_size * array_size;
 214         }
 215
 216         /* Place the UBWC slices before the uncompressed slices, because the
 217          * kernel expects UBWC to be at the start of the buffer.  In the HW, we
 218          * get to program the UBWC and non-UBWC offset/strides
 219          * independently.
 220          */
 221         if (layout->ubwc) {
 222                 for (uint32_t level = 0; level < mip_levels; level++)
 223                         layout->slices[level].offset += layout->ubwc_layer_size * array_size;
 224                 layout->size += layout->ubwc_layer_size * array_size;
 225         }
 226 }
 227
 228 void
 229 fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
 230                 uint32_t *blockwidth, uint32_t *blockheight)
 231 {
 232         *blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
 233         *blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
 234 }