src/freedreno/fdl/fd6_layout.c

   1 /*
   2  * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018-2019 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include <stdio.h>
  29
  30 #include "freedreno_layout.h"
  31
  32 /* indexed by cpp, including msaa 2x and 4x:
  33  * TODO:
  34  * cpp=1 UBWC needs testing at larger texture sizes
  35  * missing UBWC blockwidth/blockheight for npot+64 cpp
  36  * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
  37  */
  38 static const struct {
  39         unsigned pitchalign;
  40         unsigned heightalign;
  41         uint8_t ubwc_blockwidth;
  42         uint8_t ubwc_blockheight;
  43 } tile_alignment[] = {
  44         [1]  = { 128, 32, 16, 4 },
  45         [2]  = { 128, 16, 16, 4 },
  46         [3]  = {  64, 32 },
  47         [4]  = {  64, 16, 16, 4 },
  48         [6]  = {  64, 16 },
  49         [8]  = {  64, 16, 8, 4, },
  50         [12] = {  64, 16 },
  51         [16] = {  64, 16, 4, 4, },
  52         [24] = {  64, 16 },
  53         [32] = {  64, 16, 4, 2 },
  54         [48] = {  64, 16 },
  55         [64] = {  64, 16 },
  56
  57         /* special cases for r8g8: */
  58         [0]  = {  64, 32, 16, 4 },
  59 };
  60
  61 #define RGB_TILE_WIDTH_ALIGNMENT 64
  62 #define RGB_TILE_HEIGHT_ALIGNMENT 16
  63 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
  64
  65 /* NOTE: good way to test this is:  (for example)
  66  *  piglit/bin/texelFetch fs sampler3D 100x100x8
  67  */
  68 void
  69 fdl6_layout(struct fdl_layout *layout,
  70                 enum pipe_format format, uint32_t nr_samples,
  71                 uint32_t width0, uint32_t height0, uint32_t depth0,
  72                 uint32_t mip_levels, uint32_t array_size, bool is_3d)
  73 {
  74         assert(nr_samples > 0);
  75         layout->width0 = width0;
  76         layout->height0 = height0;
  77         layout->depth0 = depth0;
  78
  79         layout->cpp = util_format_get_blocksize(format);
  80         layout->cpp *= nr_samples;
  81         layout->format = format;
  82         layout->nr_samples = nr_samples;
  83
  84         if (depth0 > 1)
  85                 layout->ubwc = false;
  86         if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
  87                 layout->ubwc = false;
  88
  89         const struct util_format_description *format_desc =
  90                 util_format_description(format);
  91         uint32_t depth = depth0;
  92         /* linear dimensions: */
  93         uint32_t lwidth = width0;
  94         uint32_t lheight = height0;
  95         /* tile_mode dimensions: */
  96         uint32_t twidth = util_next_power_of_two(lwidth);
  97         uint32_t theight = util_next_power_of_two(lheight);
  98         int ta = layout->cpp;
  99
 100         /* The z16/r16 formats seem to not play by the normal tiling rules: */
 101         if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
 102                 ta = 0;
 103
 104         uint32_t alignment;
 105         if (is_3d) {
 106                 layout->layer_first = false;
 107                 alignment = 4096;
 108         } else {
 109                 layout->layer_first = true;
 110                 alignment = 1;
 111         }
 112         /* in layer_first layout, the level (slice) contains just one
 113          * layer (since in fact the layer contains the slices)
 114          */
 115         uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
 116
 117         debug_assert(ta < ARRAY_SIZE(tile_alignment));
 118         debug_assert(tile_alignment[ta].pitchalign);
 119
 120         for (uint32_t level = 0; level < mip_levels; level++) {
 121                 struct fdl_slice *slice = &layout->slices[level];
 122                 struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
 123                 uint32_t tile_mode = fdl_tile_mode(layout, level);
 124                 uint32_t width, height;
 125
 126                 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
 127                 if (is_3d && tile_mode) {
 128                         width = twidth;
 129                         height = theight;
 130                 } else {
 131                         width = lwidth;
 132                         height = lheight;
 133                 }
 134                 uint32_t aligned_height = height;
 135                 uint32_t pitchalign;
 136
 137                 if (tile_mode) {
 138                         pitchalign = tile_alignment[ta].pitchalign;
 139                         aligned_height = align(aligned_height,
 140                                         tile_alignment[ta].heightalign);
 141                 } else {
 142                         pitchalign = 64;
 143                 }
 144
 145                 /* The blits used for mem<->gmem work at a granularity of
 146                  * 32x32, which can cause faults due to over-fetch on the
 147                  * last level.  The simple solution is to over-allocate a
 148                  * bit the last level to ensure any over-fetch is harmless.
 149                  * The pitch is already sufficiently aligned, but height
 150                  * may not be:
 151                  */
 152                 if (level == mip_levels - 1)
 153                         aligned_height = align(aligned_height, 32);
 154
 155                 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC)
 156                         slice->pitch =
 157                                 util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
 158                 else
 159                         slice->pitch = align(width, pitchalign);
 160
 161                 slice->offset = layout->size;
 162                 uint32_t blocks = util_format_get_nblocks(format,
 163                                 slice->pitch, aligned_height);
 164
 165                 /* 1d array and 2d array textures must all have the same layer size
 166                  * for each miplevel on a6xx. 3d textures can have different layer
 167                  * sizes for high levels, but the hw auto-sizer is buggy (or at least
 168                  * different than what this code does), so as soon as the layer size
 169                  * range gets into range, we stop reducing it.
 170                  */
 171                 if (is_3d) {
 172                         if (level < 1 || layout->slices[level - 1].size0 > 0xf000) {
 173                                 slice->size0 = align(blocks * layout->cpp, alignment);
 174                         } else {
 175                                 slice->size0 = layout->slices[level - 1].size0;
 176                         }
 177                 } else {
 178                         slice->size0 = align(blocks * layout->cpp, alignment);
 179                 }
 180
 181                 layout->size += slice->size0 * depth * layers_in_level;
 182
 183                 if (layout->ubwc) {
 184                         /* with UBWC every level is aligned to 4K */
 185                         layout->size = align(layout->size, 4096);
 186
 187                         uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
 188                         uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
 189                         uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
 190                                         RGB_TILE_WIDTH_ALIGNMENT);
 191                         uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
 192                                         RGB_TILE_HEIGHT_ALIGNMENT);
 193
 194                         /* it looks like mipmaps need alignment to power of two
 195                          * TODO: needs testing with large npot textures
 196                          * (needed for the first level?)
 197                          */
 198                         if (mip_levels > 1) {
 199                                 meta_pitch = util_next_power_of_two(meta_pitch);
 200                                 meta_height = util_next_power_of_two(meta_height);
 201                         }
 202
 203                         ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
 204                         ubwc_slice->pitch = meta_pitch;
 205                         ubwc_slice->offset = layout->ubwc_layer_size;
 206                         layout->ubwc_layer_size += ubwc_slice->size0;
 207                 }
 208
 209                 depth = u_minify(depth, 1);
 210                 lwidth = u_minify(lwidth, 1);
 211                 lheight = u_minify(lheight, 1);
 212                 twidth = u_minify(twidth, 1);
 213                 theight = u_minify(theight, 1);
 214         }
 215
 216         if (layout->layer_first) {
 217                 layout->layer_size = align(layout->size, 4096);
 218                 layout->size = layout->layer_size * array_size;
 219         }
 220
 221         /* Place the UBWC slices before the uncompressed slices, because the
 222          * kernel expects UBWC to be at the start of the buffer.  In the HW, we
 223          * get to program the UBWC and non-UBWC offset/strides
 224          * independently.
 225          */
 226         if (layout->ubwc) {
 227                 for (uint32_t level = 0; level < mip_levels; level++)
 228                         layout->slices[level].offset += layout->ubwc_layer_size * array_size;
 229                 layout->size += layout->ubwc_layer_size * array_size;
 230         }
 231 }
 232
 233 void
 234 fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
 235                 uint32_t *blockwidth, uint32_t *blockheight)
 236 {
 237         *blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
 238         *blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
 239 }