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turnip: Move tu_bo functions to tu_drm.c
[mesa.git] / src / freedreno / ir3 / disasm-a3xx.c
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <assert.h>
30
31 #include <util/u_debug.h>
32
33 #include "disasm.h"
34 #include "instr-a3xx.h"
35 #include "regmask.h"
36
37 static enum debug_t debug;
38
39 #define printf debug_printf
40
41 static const char *levels[] = {
42 "",
43 "\t",
44 "\t\t",
45 "\t\t\t",
46 "\t\t\t\t",
47 "\t\t\t\t\t",
48 "\t\t\t\t\t\t",
49 "\t\t\t\t\t\t\t",
50 "\t\t\t\t\t\t\t\t",
51 "\t\t\t\t\t\t\t\t\t",
52 "x",
53 "x",
54 "x",
55 "x",
56 "x",
57 "x",
58 };
59
60 static const char *component = "xyzw";
61
62 static const char *type[] = {
63 [TYPE_F16] = "f16",
64 [TYPE_F32] = "f32",
65 [TYPE_U16] = "u16",
66 [TYPE_U32] = "u32",
67 [TYPE_S16] = "s16",
68 [TYPE_S32] = "s32",
69 [TYPE_U8] = "u8",
70 [TYPE_S8] = "s8",
71 };
72
73 struct disasm_ctx {
74 FILE *out;
75 int level;
76 unsigned gpu_id;
77
78 struct shader_stats *stats;
79
80 /* we have to process the dst register after src to avoid tripping up
81 * the read-before-write detection
82 */
83 unsigned last_dst;
84 bool last_dst_full;
85 bool last_dst_valid;
86
87 /* current instruction repeat flag: */
88 unsigned repeat;
89 /* current instruction repeat indx/offset (for --expand): */
90 unsigned repeatidx;
91
92 /* tracking for register usage */
93 struct {
94 regmask_t used;
95 regmask_t used_merged;
96 regmask_t rbw; /* read before write */
97 regmask_t war; /* write after read */
98 unsigned max_const;
99 } regs;
100 };
101
102 static const char *float_imms[] = {
103 "0.0",
104 "0.5",
105 "1.0",
106 "2.0",
107 "e",
108 "pi",
109 "1/pi",
110 "1/log2(e)",
111 "log2(e)",
112 "1/log2(10)",
113 "log2(10)",
114 "4.0",
115 };
116
117 static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
118 bool is_float, bool r,
119 bool c, bool im, bool neg, bool abs, bool addr_rel)
120 {
121 const char type = c ? 'c' : 'r';
122
123 // XXX I prefer - and || for neg/abs, but preserving format used
124 // by libllvm-a3xx for easy diffing..
125
126 if (abs && neg)
127 fprintf(ctx->out, "(absneg)");
128 else if (neg)
129 fprintf(ctx->out, "(neg)");
130 else if (abs)
131 fprintf(ctx->out, "(abs)");
132
133 if (r)
134 fprintf(ctx->out, "(r)");
135
136 if (im) {
137 if (is_float && full && reg.iim_val < ARRAY_SIZE(float_imms)) {
138 fprintf(ctx->out, "(%s)", float_imms[reg.iim_val]);
139 } else {
140 fprintf(ctx->out, "%d", reg.iim_val);
141 }
142 } else if (addr_rel) {
143 /* I would just use %+d but trying to make it diff'able with
144 * libllvm-a3xx...
145 */
146 if (reg.iim_val < 0)
147 fprintf(ctx->out, "%s%c<a0.x - %d>", full ? "" : "h", type, -reg.iim_val);
148 else if (reg.iim_val > 0)
149 fprintf(ctx->out, "%s%c<a0.x + %d>", full ? "" : "h", type, reg.iim_val);
150 else
151 fprintf(ctx->out, "%s%c<a0.x>", full ? "" : "h", type);
152 } else if ((reg.num == REG_A0) && !c) {
153 /* This matches libllvm output, the second (scalar) address register
154 * seems to be called a1.x instead of a0.y.
155 */
156 fprintf(ctx->out, "a%d.x", reg.comp);
157 } else if ((reg.num == REG_P0) && !c) {
158 fprintf(ctx->out, "p0.%c", component[reg.comp]);
159 } else {
160 fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
161 if (0 && full && !c) {
162 reg_t hr0 = reg;
163 hr0.iim_val *= 2;
164 reg_t hr1 = hr0;
165 hr1.iim_val += 1;
166 fprintf(ctx->out, " (hr%d.%c,hr%d.%c)", hr0.num, component[hr0.comp], hr1.num, component[hr1.comp]);
167 }
168 }
169 }
170
171 static void regmask_set(regmask_t *regmask, unsigned num, bool full)
172 {
173 ir3_assert(num < MAX_REG);
174 __regmask_set(regmask, !full, num);
175 }
176
177 static void regmask_clear(regmask_t *regmask, unsigned num, bool full)
178 {
179 ir3_assert(num < MAX_REG);
180 __regmask_clear(regmask, !full, num);
181 }
182
183 static unsigned regmask_get(regmask_t *regmask, unsigned num, bool full)
184 {
185 ir3_assert(num < MAX_REG);
186 return __regmask_get(regmask, !full, num);
187 }
188
189 static unsigned regidx(reg_t reg)
190 {
191 return (4 * reg.num) + reg.comp;
192 }
193
194 static reg_t idxreg(unsigned idx)
195 {
196 return (reg_t){
197 .comp = idx & 0x3,
198 .num = idx >> 2,
199 };
200 }
201
202 static void print_sequence(struct disasm_ctx *ctx, int first, int last)
203 {
204 if (first != MAX_REG) {
205 if (first == last) {
206 fprintf(ctx->out, " %d", first);
207 } else {
208 fprintf(ctx->out, " %d-%d", first, last);
209 }
210 }
211 }
212
213 static int print_regs(struct disasm_ctx *ctx, regmask_t *regmask, bool full)
214 {
215 int num, max = 0, cnt = 0;
216 int first, last;
217
218 first = last = MAX_REG;
219
220 for (num = 0; num < MAX_REG; num++) {
221 if (regmask_get(regmask, num, full)) {
222 if (num != (last + 1)) {
223 print_sequence(ctx, first, last);
224 first = num;
225 }
226 last = num;
227 if (num < (48*4))
228 max = num;
229 cnt++;
230 }
231 }
232
233 print_sequence(ctx, first, last);
234
235 fprintf(ctx->out, " (cnt=%d, max=%d)", cnt, max);
236
237 return max;
238 }
239
240 static void print_reg_stats(struct disasm_ctx *ctx)
241 {
242 int fullreg, halfreg;
243
244 fprintf(ctx->out, "%sRegister Stats:\n", levels[ctx->level]);
245 fprintf(ctx->out, "%s- used (half):", levels[ctx->level]);
246 halfreg = print_regs(ctx, &ctx->regs.used, false);
247 fprintf(ctx->out, "\n");
248 fprintf(ctx->out, "%s- used (full):", levels[ctx->level]);
249 fullreg = print_regs(ctx, &ctx->regs.used, true);
250 fprintf(ctx->out, "\n");
251 if (ctx->gpu_id >= 600) {
252 fprintf(ctx->out, "%s- used (merged):", levels[ctx->level]);
253 print_regs(ctx, &ctx->regs.used_merged, false);
254 fprintf(ctx->out, "\n");
255 }
256 fprintf(ctx->out, "%s- input (half):", levels[ctx->level]);
257 print_regs(ctx, &ctx->regs.rbw, false);
258 fprintf(ctx->out, "\n");
259 fprintf(ctx->out, "%s- input (full):", levels[ctx->level]);
260 print_regs(ctx, &ctx->regs.rbw, true);
261 fprintf(ctx->out, "\n");
262 fprintf(ctx->out, "%s- max const: %u\n", levels[ctx->level], ctx->regs.max_const);
263 fprintf(ctx->out, "\n");
264 fprintf(ctx->out, "%s- output (half):", levels[ctx->level]);
265 print_regs(ctx, &ctx->regs.war, false);
266 fprintf(ctx->out, " (estimated)\n");
267 fprintf(ctx->out, "%s- output (full):", levels[ctx->level]);
268 print_regs(ctx, &ctx->regs.war, true);
269 fprintf(ctx->out, " (estimated)\n");
270
271 /* convert to vec4, which is the granularity that registers are
272 * assigned to shader:
273 */
274 fullreg = (fullreg + 3) / 4;
275 halfreg = (halfreg + 3) / 4;
276
277 // Note this count of instructions includes rptN, which matches
278 // up to how mesa prints this:
279 fprintf(ctx->out, "%s- shaderdb: %d instructions, %d nops, %d non-nops, "
280 "(%d instlen), %d half, %d full\n",
281 levels[ctx->level], ctx->stats->instructions, ctx->stats->nops,
282 ctx->stats->instructions - ctx->stats->nops, ctx->stats->instlen,
283 halfreg, fullreg);
284 fprintf(ctx->out, "%s- shaderdb: %d (ss), %d (sy)\n", levels[ctx->level],
285 ctx->stats->ss, ctx->stats->sy);
286 }
287
288 static void process_reg_dst(struct disasm_ctx *ctx)
289 {
290 if (!ctx->last_dst_valid)
291 return;
292
293 /* ignore dummy writes (ie. r63.x): */
294 if (!VALIDREG(ctx->last_dst))
295 return;
296
297 for (unsigned i = 0; i <= ctx->repeat; i++) {
298 unsigned dst = ctx->last_dst + i;
299
300 regmask_set(&ctx->regs.war, dst, ctx->last_dst_full);
301 regmask_set(&ctx->regs.used, dst, ctx->last_dst_full);
302
303 if (ctx->gpu_id >= 600) {
304 if (ctx->last_dst_full) {
305 regmask_set(&ctx->regs.used_merged, (dst*2)+0, false);
306 regmask_set(&ctx->regs.used_merged, (dst*2)+1, false);
307 } else {
308 regmask_set(&ctx->regs.used_merged, dst, false);
309 }
310 }
311 }
312
313 ctx->last_dst_valid = false;
314 }
315 static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
316 {
317 /* presumably the special registers a0.c and p0.c don't count.. */
318 if (!(addr_rel || (reg.num == REG_A0) || (reg.num == REG_P0))) {
319 ctx->last_dst = regidx(reg);
320 ctx->last_dst_full = full;
321 ctx->last_dst_valid = true;
322 }
323 reg = idxreg(regidx(reg) + ctx->repeatidx);
324 print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel);
325 }
326
327 /* TODO switch to using reginfo struct everywhere, since more readable
328 * than passing a bunch of bools to print_reg_src
329 */
330
331 struct reginfo {
332 reg_t reg;
333 bool full;
334 bool r;
335 bool c;
336 bool f; /* src reg is interpreted as float, used for printing immediates */
337 bool im;
338 bool neg;
339 bool abs;
340 bool addr_rel;
341 };
342
343 static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
344 {
345 reg_t reg = info->reg;
346
347 /* presumably the special registers a0.c and p0.c don't count.. */
348 if (!(info->addr_rel || info->c || info->im ||
349 (reg.num == REG_A0) || (reg.num == REG_P0))) {
350 int i, num = regidx(reg);
351 for (i = 0; i <= ctx->repeat; i++) {
352 unsigned src = num + i;
353
354 if (!regmask_get(&ctx->regs.used, src, info->full))
355 regmask_set(&ctx->regs.rbw, src, info->full);
356
357 regmask_clear(&ctx->regs.war, src, info->full);
358 regmask_set(&ctx->regs.used, src, info->full);
359
360 if (info->full) {
361 regmask_set(&ctx->regs.used_merged, (src*2)+0, false);
362 regmask_set(&ctx->regs.used_merged, (src*2)+1, false);
363 } else {
364 regmask_set(&ctx->regs.used_merged, src, false);
365 }
366
367 if (!info->r)
368 break;
369 }
370 } else if (info->c) {
371 int i, num = regidx(reg);
372 for (i = 0; i <= ctx->repeat; i++) {
373 unsigned src = num + i;
374
375 ctx->regs.max_const = MAX2(ctx->regs.max_const, src);
376
377 if (!info->r)
378 break;
379 }
380
381 unsigned max = (num + ctx->repeat + 1 + 3) / 4;
382 if (max > ctx->stats->constlen)
383 ctx->stats->constlen = max;
384 }
385
386 if (info->r)
387 reg = idxreg(regidx(info->reg) + ctx->repeatidx);
388
389 print_reg(ctx, reg, info->full, info->f, info->r, info->c, info->im,
390 info->neg, info->abs, info->addr_rel);
391 }
392
393 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
394 //{
395 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
396 //}
397
398 static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
399 {
400 static const struct {
401 const char *suffix;
402 int nsrc;
403 bool idx;
404 } brinfo[7] = {
405 [BRANCH_PLAIN] = { "r", 1, false },
406 [BRANCH_OR] = { "rao", 2, false },
407 [BRANCH_AND] = { "raa", 2, false },
408 [BRANCH_CONST] = { "rac", 0, true },
409 [BRANCH_ANY] = { "any", 1, false },
410 [BRANCH_ALL] = { "all", 1, false },
411 [BRANCH_X] = { "rax", 0, false },
412 };
413 instr_cat0_t *cat0 = &instr->cat0;
414
415 switch (instr_opc(instr, ctx->gpu_id)) {
416 case OPC_KILL:
417 case OPC_PREDT:
418 case OPC_PREDF:
419 fprintf(ctx->out, " %sp0.%c", cat0->inv0 ? "!" : "",
420 component[cat0->comp0]);
421 break;
422 case OPC_B:
423 fprintf(ctx->out, "%s", brinfo[cat0->brtype].suffix);
424 if (brinfo[cat0->brtype].idx) {
425 fprintf(ctx->out, ".%u", cat0->idx);
426 }
427 if (brinfo[cat0->brtype].nsrc >= 1) {
428 fprintf(ctx->out, " %sp0.%c,", cat0->inv0 ? "!" : "",
429 component[cat0->comp0]);
430 }
431 if (brinfo[cat0->brtype].nsrc >= 2) {
432 fprintf(ctx->out, " %sp0.%c,", cat0->inv1 ? "!" : "",
433 component[cat0->comp1]);
434 }
435 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
436 break;
437 case OPC_JUMP:
438 case OPC_CALL:
439 case OPC_BKT:
440 case OPC_GETONE:
441 case OPC_SHPS:
442 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
443 break;
444 }
445
446 if ((debug & PRINT_VERBOSE) && (cat0->dummy3|cat0->dummy4))
447 fprintf(ctx->out, "\t{0: %x,%x}", cat0->dummy3, cat0->dummy4);
448 }
449
450 static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr)
451 {
452 instr_cat1_t *cat1 = &instr->cat1;
453
454 if (cat1->ul)
455 fprintf(ctx->out, "(ul)");
456
457 if (cat1->src_type == cat1->dst_type) {
458 if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) {
459 /* special case (nmemonic?): */
460 fprintf(ctx->out, "mova");
461 } else {
462 fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
463 }
464 } else {
465 fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
466 }
467
468 fprintf(ctx->out, " ");
469
470 if (cat1->even)
471 fprintf(ctx->out, "(even)");
472
473 if (cat1->pos_inf)
474 fprintf(ctx->out, "(pos_infinity)");
475
476 print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32,
477 cat1->dst_rel);
478
479 fprintf(ctx->out, ", ");
480
481 /* ugg, have to special case this.. vs print_reg().. */
482 if (cat1->src_im) {
483 if (type_float(cat1->src_type))
484 fprintf(ctx->out, "(%f)", cat1->fim_val);
485 else if (type_uint(cat1->src_type))
486 fprintf(ctx->out, "0x%08x", cat1->uim_val);
487 else
488 fprintf(ctx->out, "%d", cat1->iim_val);
489 } else if (cat1->src_rel && !cat1->src_c) {
490 /* I would just use %+d but trying to make it diff'able with
491 * libllvm-a3xx...
492 */
493 char type = cat1->src_rel_c ? 'c' : 'r';
494 const char *full = (type_size(cat1->src_type) == 32) ? "" : "h";
495 if (cat1->off < 0)
496 fprintf(ctx->out, "%s%c<a0.x - %d>", full, type, -cat1->off);
497 else if (cat1->off > 0)
498 fprintf(ctx->out, "%s%c<a0.x + %d>", full, type, cat1->off);
499 else
500 fprintf(ctx->out, "%s%c<a0.x>", full, type);
501 } else {
502 struct reginfo src = {
503 .reg = (reg_t)cat1->src,
504 .full = type_size(cat1->src_type) == 32,
505 .r = cat1->src_r,
506 .c = cat1->src_c,
507 .im = cat1->src_im,
508 };
509 print_src(ctx, &src);
510 }
511
512 if ((debug & PRINT_VERBOSE) && (cat1->must_be_0))
513 fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0);
514 }
515
516 static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr)
517 {
518 instr_cat2_t *cat2 = &instr->cat2;
519 int opc = _OPC(2, cat2->opc);
520 static const char *cond[] = {
521 "lt",
522 "le",
523 "gt",
524 "ge",
525 "eq",
526 "ne",
527 "?6?",
528 };
529
530 switch (opc) {
531 case OPC_CMPS_F:
532 case OPC_CMPS_U:
533 case OPC_CMPS_S:
534 case OPC_CMPV_F:
535 case OPC_CMPV_U:
536 case OPC_CMPV_S:
537 fprintf(ctx->out, ".%s", cond[cat2->cond]);
538 break;
539 }
540
541 fprintf(ctx->out, " ");
542 if (cat2->ei)
543 fprintf(ctx->out, "(ei)");
544 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
545 fprintf(ctx->out, ", ");
546
547 struct reginfo src1 = {
548 .full = cat2->full,
549 .r = cat2->repeat ? cat2->src1_r : 0,
550 .f = is_cat2_float(opc),
551 .im = cat2->src1_im,
552 .abs = cat2->src1_abs,
553 .neg = cat2->src1_neg,
554 };
555
556 if (cat2->c1.src1_c) {
557 src1.reg = (reg_t)(cat2->c1.src1);
558 src1.c = true;
559 } else if (cat2->rel1.src1_rel) {
560 src1.reg = (reg_t)(cat2->rel1.src1);
561 src1.c = cat2->rel1.src1_c;
562 src1.addr_rel = true;
563 } else {
564 src1.reg = (reg_t)(cat2->src1);
565 }
566 print_src(ctx, &src1);
567
568 struct reginfo src2 = {
569 .r = cat2->repeat ? cat2->src2_r : 0,
570 .full = cat2->full,
571 .f = is_cat2_float(opc),
572 .abs = cat2->src2_abs,
573 .neg = cat2->src2_neg,
574 .im = cat2->src2_im,
575 };
576 switch (opc) {
577 case OPC_ABSNEG_F:
578 case OPC_ABSNEG_S:
579 case OPC_CLZ_B:
580 case OPC_CLZ_S:
581 case OPC_SIGN_F:
582 case OPC_FLOOR_F:
583 case OPC_CEIL_F:
584 case OPC_RNDNE_F:
585 case OPC_RNDAZ_F:
586 case OPC_TRUNC_F:
587 case OPC_NOT_B:
588 case OPC_BFREV_B:
589 case OPC_SETRM:
590 case OPC_CBITS_B:
591 /* these only have one src reg */
592 break;
593 default:
594 fprintf(ctx->out, ", ");
595 if (cat2->c2.src2_c) {
596 src2.reg = (reg_t)(cat2->c2.src2);
597 src2.c = true;
598 } else if (cat2->rel2.src2_rel) {
599 src2.reg = (reg_t)(cat2->rel2.src2);
600 src2.c = cat2->rel2.src2_c;
601 src2.addr_rel = true;
602 } else {
603 src2.reg = (reg_t)(cat2->src2);
604 }
605 print_src(ctx, &src2);
606 break;
607 }
608 }
609
610 static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr)
611 {
612 instr_cat3_t *cat3 = &instr->cat3;
613 bool full = instr_cat3_full(cat3);
614
615 fprintf(ctx->out, " ");
616 print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false);
617 fprintf(ctx->out, ", ");
618
619 struct reginfo src1 = {
620 .r = cat3->repeat ? cat3->src1_r : 0,
621 .full = full,
622 .neg = cat3->src1_neg,
623 };
624 if (cat3->c1.src1_c) {
625 src1.reg = (reg_t)(cat3->c1.src1);
626 src1.c = true;
627 } else if (cat3->rel1.src1_rel) {
628 src1.reg = (reg_t)(cat3->rel1.src1);
629 src1.c = cat3->rel1.src1_c;
630 src1.addr_rel = true;
631 } else {
632 src1.reg = (reg_t)(cat3->src1);
633 }
634 print_src(ctx, &src1);
635
636 fprintf(ctx->out, ", ");
637 struct reginfo src2 = {
638 .reg = (reg_t)cat3->src2,
639 .full = full,
640 .r = cat3->repeat ? cat3->src2_r : 0,
641 .c = cat3->src2_c,
642 .neg = cat3->src2_neg,
643 };
644 print_src(ctx, &src2);
645
646 fprintf(ctx->out, ", ");
647 struct reginfo src3 = {
648 .r = cat3->src3_r,
649 .full = full,
650 .neg = cat3->src3_neg,
651 };
652 if (cat3->c2.src3_c) {
653 src3.reg = (reg_t)(cat3->c2.src3);
654 src3.c = true;
655 } else if (cat3->rel2.src3_rel) {
656 src3.reg = (reg_t)(cat3->rel2.src3);
657 src3.c = cat3->rel2.src3_c;
658 src3.addr_rel = true;
659 } else {
660 src3.reg = (reg_t)(cat3->src3);
661 }
662 print_src(ctx, &src3);
663 }
664
665 static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr)
666 {
667 instr_cat4_t *cat4 = &instr->cat4;
668
669 fprintf(ctx->out, " ");
670 print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false);
671 fprintf(ctx->out, ", ");
672
673 struct reginfo src = {
674 .r = cat4->src_r,
675 .im = cat4->src_im,
676 .full = cat4->full,
677 .neg = cat4->src_neg,
678 .abs = cat4->src_abs,
679 };
680 if (cat4->c.src_c) {
681 src.reg = (reg_t)(cat4->c.src);
682 src.c = true;
683 } else if (cat4->rel.src_rel) {
684 src.reg = (reg_t)(cat4->rel.src);
685 src.c = cat4->rel.src_c;
686 src.addr_rel = true;
687 } else {
688 src.reg = (reg_t)(cat4->src);
689 }
690 print_src(ctx, &src);
691
692 if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2))
693 fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2);
694 }
695
696 static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr)
697 {
698 static const struct {
699 bool src1, src2, samp, tex;
700 } info[0x1f] = {
701 [opc_op(OPC_ISAM)] = { true, false, true, true, },
702 [opc_op(OPC_ISAML)] = { true, true, true, true, },
703 [opc_op(OPC_ISAMM)] = { true, false, true, true, },
704 [opc_op(OPC_SAM)] = { true, false, true, true, },
705 [opc_op(OPC_SAMB)] = { true, true, true, true, },
706 [opc_op(OPC_SAML)] = { true, true, true, true, },
707 [opc_op(OPC_SAMGQ)] = { true, false, true, true, },
708 [opc_op(OPC_GETLOD)] = { true, false, true, true, },
709 [opc_op(OPC_CONV)] = { true, true, true, true, },
710 [opc_op(OPC_CONVM)] = { true, true, true, true, },
711 [opc_op(OPC_GETSIZE)] = { true, false, false, true, },
712 [opc_op(OPC_GETBUF)] = { false, false, false, true, },
713 [opc_op(OPC_GETPOS)] = { true, false, false, true, },
714 [opc_op(OPC_GETINFO)] = { false, false, false, true, },
715 [opc_op(OPC_DSX)] = { true, false, false, false, },
716 [opc_op(OPC_DSY)] = { true, false, false, false, },
717 [opc_op(OPC_GATHER4R)] = { true, false, true, true, },
718 [opc_op(OPC_GATHER4G)] = { true, false, true, true, },
719 [opc_op(OPC_GATHER4B)] = { true, false, true, true, },
720 [opc_op(OPC_GATHER4A)] = { true, false, true, true, },
721 [opc_op(OPC_SAMGP0)] = { true, false, true, true, },
722 [opc_op(OPC_SAMGP1)] = { true, false, true, true, },
723 [opc_op(OPC_SAMGP2)] = { true, false, true, true, },
724 [opc_op(OPC_SAMGP3)] = { true, false, true, true, },
725 [opc_op(OPC_DSXPP_1)] = { true, false, false, false, },
726 [opc_op(OPC_DSYPP_1)] = { true, false, false, false, },
727 [opc_op(OPC_RGETPOS)] = { true, false, false, false, },
728 [opc_op(OPC_RGETINFO)] = { false, false, false, false, },
729 };
730
731 static const struct {
732 bool indirect;
733 bool bindless;
734 bool use_a1;
735 bool uniform;
736 } desc_features[8] = {
737 [CAT5_NONUNIFORM] = { .indirect = true, },
738 [CAT5_UNIFORM] = { .indirect = true, .uniform = true, },
739 [CAT5_BINDLESS_IMM] = { .bindless = true, },
740 [CAT5_BINDLESS_UNIFORM] = {
741 .bindless = true,
742 .indirect = true,
743 .uniform = true,
744 },
745 [CAT5_BINDLESS_NONUNIFORM] = {
746 .bindless = true,
747 .indirect = true,
748 },
749 [CAT5_BINDLESS_A1_IMM] = {
750 .bindless = true,
751 .use_a1 = true,
752 },
753 [CAT5_BINDLESS_A1_UNIFORM] = {
754 .bindless = true,
755 .indirect = true,
756 .uniform = true,
757 .use_a1 = true,
758 },
759 [CAT5_BINDLESS_A1_NONUNIFORM] = {
760 .bindless = true,
761 .indirect = true,
762 .use_a1 = true,
763 },
764 };
765
766 instr_cat5_t *cat5 = &instr->cat5;
767 int i;
768
769 bool desc_indirect =
770 cat5->is_s2en_bindless &&
771 desc_features[cat5->s2en_bindless.desc_mode].indirect;
772 bool bindless =
773 cat5->is_s2en_bindless &&
774 desc_features[cat5->s2en_bindless.desc_mode].bindless;
775 bool use_a1 =
776 cat5->is_s2en_bindless &&
777 desc_features[cat5->s2en_bindless.desc_mode].use_a1;
778 bool uniform =
779 cat5->is_s2en_bindless &&
780 desc_features[cat5->s2en_bindless.desc_mode].uniform;
781
782 if (cat5->is_3d) fprintf(ctx->out, ".3d");
783 if (cat5->is_a) fprintf(ctx->out, ".a");
784 if (cat5->is_o) fprintf(ctx->out, ".o");
785 if (cat5->is_p) fprintf(ctx->out, ".p");
786 if (cat5->is_s) fprintf(ctx->out, ".s");
787 if (desc_indirect) fprintf(ctx->out, ".s2en");
788 if (uniform) fprintf(ctx->out, ".uniform");
789
790 if (bindless) {
791 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo;
792 fprintf(ctx->out, ".base%d", base);
793 }
794
795 fprintf(ctx->out, " ");
796
797 switch (_OPC(5, cat5->opc)) {
798 case OPC_DSXPP_1:
799 case OPC_DSYPP_1:
800 break;
801 default:
802 fprintf(ctx->out, "(%s)", type[cat5->type]);
803 break;
804 }
805
806 fprintf(ctx->out, "(");
807 for (i = 0; i < 4; i++)
808 if (cat5->wrmask & (1 << i))
809 fprintf(ctx->out, "%c", "xyzw"[i]);
810 fprintf(ctx->out, ")");
811
812 print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false);
813
814 if (info[cat5->opc].src1) {
815 fprintf(ctx->out, ", ");
816 struct reginfo src = { .reg = (reg_t)(cat5->src1), .full = cat5->full };
817 print_src(ctx, &src);
818 }
819
820 if (cat5->is_o || info[cat5->opc].src2) {
821 fprintf(ctx->out, ", ");
822 struct reginfo src = { .reg = (reg_t)(cat5->src2), .full = cat5->full };
823 print_src(ctx, &src);
824 }
825 if (cat5->is_s2en_bindless) {
826 if (!desc_indirect) {
827 if (info[cat5->opc].samp) {
828 if (use_a1)
829 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3);
830 else
831 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf);
832 }
833
834 if (info[cat5->opc].tex && !use_a1) {
835 fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4);
836 }
837 }
838 } else {
839 if (info[cat5->opc].samp)
840 fprintf(ctx->out, ", s#%d", cat5->norm.samp);
841 if (info[cat5->opc].tex)
842 fprintf(ctx->out, ", t#%d", cat5->norm.tex);
843 }
844
845 if (desc_indirect) {
846 fprintf(ctx->out, ", ");
847 struct reginfo src = { .reg = (reg_t)(cat5->s2en_bindless.src3), .full = bindless };
848 print_src(ctx, &src);
849 }
850
851 if (use_a1)
852 fprintf(ctx->out, ", a1.x");
853
854 if (debug & PRINT_VERBOSE) {
855 if (cat5->is_s2en_bindless) {
856 if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1)
857 fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1);
858 } else {
859 if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1)
860 fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1);
861 }
862 }
863 }
864
865 static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
866 {
867 instr_cat6_t *cat6 = &instr->cat6;
868 char sd = 0, ss = 0; /* dst/src address space */
869 bool nodst = false;
870 struct reginfo dst, src1, src2, ssbo;
871 int src1off = 0;
872
873 memset(&dst, 0, sizeof(dst));
874 memset(&src1, 0, sizeof(src1));
875 memset(&src2, 0, sizeof(src2));
876 memset(&ssbo, 0, sizeof(ssbo));
877
878 switch (_OPC(6, cat6->opc)) {
879 case OPC_RESINFO:
880 case OPC_RESFMT:
881 dst.full = type_size(cat6->type) == 32;
882 src1.full = type_size(cat6->type) == 32;
883 src2.full = type_size(cat6->type) == 32;
884 break;
885 case OPC_L2G:
886 case OPC_G2L:
887 dst.full = true;
888 src1.full = true;
889 src2.full = true;
890 break;
891 case OPC_STG:
892 case OPC_STL:
893 case OPC_STP:
894 case OPC_STLW:
895 case OPC_STIB:
896 dst.full = type_size(cat6->type) == 32;
897 src1.full = type_size(cat6->type) == 32;
898 src2.full = type_size(cat6->type) == 32;
899 break;
900 default:
901 dst.full = type_size(cat6->type) == 32;
902 src1.full = true;
903 src2.full = true;
904 break;
905 }
906
907 switch (_OPC(6, cat6->opc)) {
908 case OPC_PREFETCH:
909 break;
910 case OPC_RESINFO:
911 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
912 break;
913 case OPC_LDGB:
914 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
915 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
916 fprintf(ctx->out, ".%s", type[cat6->type]);
917 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
918 break;
919 case OPC_STGB:
920 case OPC_STIB:
921 fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped");
922 fprintf(ctx->out, ".%dd", cat6->stgb.d + 1);
923 fprintf(ctx->out, ".%s", type[cat6->type]);
924 fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1);
925 break;
926 case OPC_ATOMIC_ADD:
927 case OPC_ATOMIC_SUB:
928 case OPC_ATOMIC_XCHG:
929 case OPC_ATOMIC_INC:
930 case OPC_ATOMIC_DEC:
931 case OPC_ATOMIC_CMPXCHG:
932 case OPC_ATOMIC_MIN:
933 case OPC_ATOMIC_MAX:
934 case OPC_ATOMIC_AND:
935 case OPC_ATOMIC_OR:
936 case OPC_ATOMIC_XOR:
937 ss = cat6->g ? 'g' : 'l';
938 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
939 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
940 fprintf(ctx->out, ".%s", type[cat6->type]);
941 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
942 fprintf(ctx->out, ".%c", ss);
943 break;
944 default:
945 dst.im = cat6->g && !cat6->dst_off;
946 fprintf(ctx->out, ".%s", type[cat6->type]);
947 break;
948 }
949 fprintf(ctx->out, " ");
950
951 switch (_OPC(6, cat6->opc)) {
952 case OPC_STG:
953 sd = 'g';
954 break;
955 case OPC_STP:
956 sd = 'p';
957 break;
958 case OPC_STL:
959 case OPC_STLW:
960 sd = 'l';
961 break;
962
963 case OPC_LDG:
964 case OPC_LDC:
965 ss = 'g';
966 break;
967 case OPC_LDP:
968 ss = 'p';
969 break;
970 case OPC_LDL:
971 case OPC_LDLW:
972 case OPC_LDLV:
973 ss = 'l';
974 break;
975
976 case OPC_L2G:
977 ss = 'l';
978 sd = 'g';
979 break;
980
981 case OPC_G2L:
982 ss = 'g';
983 sd = 'l';
984 break;
985
986 case OPC_PREFETCH:
987 ss = 'g';
988 nodst = true;
989 break;
990 }
991
992 if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) {
993 struct reginfo src3;
994
995 memset(&src3, 0, sizeof(src3));
996
997 src1.reg = (reg_t)(cat6->stgb.src1);
998 src2.reg = (reg_t)(cat6->stgb.src2);
999 src2.im = cat6->stgb.src2_im;
1000 src3.reg = (reg_t)(cat6->stgb.src3);
1001 src3.im = cat6->stgb.src3_im;
1002 src3.full = true;
1003
1004 fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo);
1005 print_src(ctx, &src1);
1006 fprintf(ctx->out, ", ");
1007 print_src(ctx, &src2);
1008 fprintf(ctx->out, ", ");
1009 print_src(ctx, &src3);
1010
1011 if (debug & PRINT_VERBOSE)
1012 fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3);
1013
1014 return;
1015 }
1016
1017 if (is_atomic(_OPC(6, cat6->opc))) {
1018
1019 src1.reg = (reg_t)(cat6->ldgb.src1);
1020 src1.im = cat6->ldgb.src1_im;
1021 src2.reg = (reg_t)(cat6->ldgb.src2);
1022 src2.im = cat6->ldgb.src2_im;
1023 dst.reg = (reg_t)(cat6->ldgb.dst);
1024
1025 print_src(ctx, &dst);
1026 fprintf(ctx->out, ", ");
1027 if (ss == 'g') {
1028 struct reginfo src3;
1029 memset(&src3, 0, sizeof(src3));
1030
1031 src3.reg = (reg_t)(cat6->ldgb.src3);
1032 src3.full = true;
1033
1034 /* For images, the ".typed" variant is used and src2 is
1035 * the ivecN coordinates, ie ivec2 for 2d.
1036 *
1037 * For SSBOs, the ".untyped" variant is used and src2 is
1038 * a simple dword offset.. src3 appears to be
1039 * uvec2(offset * 4, 0). Not sure the point of that.
1040 */
1041
1042 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
1043 print_src(ctx, &src1); /* value */
1044 fprintf(ctx->out, ", ");
1045 print_src(ctx, &src2); /* offset/coords */
1046 fprintf(ctx->out, ", ");
1047 print_src(ctx, &src3); /* 64b byte offset.. */
1048
1049 if (debug & PRINT_VERBOSE) {
1050 fprintf(ctx->out, " (pad0=%x, mustbe0=%x)", cat6->ldgb.pad0,
1051 cat6->ldgb.mustbe0);
1052 }
1053 } else { /* ss == 'l' */
1054 fprintf(ctx->out, "l[");
1055 print_src(ctx, &src1); /* simple byte offset */
1056 fprintf(ctx->out, "], ");
1057 print_src(ctx, &src2); /* value */
1058
1059 if (debug & PRINT_VERBOSE) {
1060 fprintf(ctx->out, " (src3=%x, pad0=%x, src_ssbo_im=%x, mustbe0=%x)",
1061 cat6->ldgb.src3, cat6->ldgb.pad0,
1062 cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
1063 }
1064 }
1065
1066 return;
1067 } else if (_OPC(6, cat6->opc) == OPC_RESINFO) {
1068 dst.reg = (reg_t)(cat6->ldgb.dst);
1069 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
1070 ssbo.im = cat6->ldgb.src_ssbo_im;
1071
1072 print_src(ctx, &dst);
1073 fprintf(ctx->out, ", ");
1074
1075 fprintf(ctx->out, "g[");
1076 print_src(ctx, &ssbo);
1077 fprintf(ctx->out, "]");
1078
1079 return;
1080 } else if (_OPC(6, cat6->opc) == OPC_LDGB) {
1081
1082 src1.reg = (reg_t)(cat6->ldgb.src1);
1083 src1.im = cat6->ldgb.src1_im;
1084 src2.reg = (reg_t)(cat6->ldgb.src2);
1085 src2.im = cat6->ldgb.src2_im;
1086 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
1087 ssbo.im = cat6->ldgb.src_ssbo_im;
1088 dst.reg = (reg_t)(cat6->ldgb.dst);
1089
1090 print_src(ctx, &dst);
1091 fprintf(ctx->out, ", ");
1092
1093 fprintf(ctx->out, "g[");
1094 print_src(ctx, &ssbo);
1095 fprintf(ctx->out, "], ");
1096
1097 print_src(ctx, &src1);
1098 fprintf(ctx->out, ", ");
1099 print_src(ctx, &src2);
1100
1101 if (debug & PRINT_VERBOSE)
1102 fprintf(ctx->out, " (pad0=%x, ssbo_im=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
1103
1104 return;
1105 } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) {
1106 struct reginfo src3;
1107
1108 memset(&src3, 0, sizeof(src3));
1109 src1.reg = (reg_t)(cat6->a.src1);
1110 src2.reg = (reg_t)(cat6->a.src2);
1111 src2.im = cat6->a.src2_im;
1112 src3.reg = (reg_t)(cat6->a.off);
1113 src3.full = true;
1114 dst.reg = (reg_t)(cat6->d.dst);
1115
1116 print_src(ctx, &dst);
1117 fprintf(ctx->out, ", g[");
1118 print_src(ctx, &src1);
1119 fprintf(ctx->out, "+");
1120 print_src(ctx, &src3);
1121 fprintf(ctx->out, "], ");
1122 print_src(ctx, &src2);
1123
1124 return;
1125 }
1126
1127 if (cat6->src_off) {
1128 src1.reg = (reg_t)(cat6->a.src1);
1129 src1.im = cat6->a.src1_im;
1130 src2.reg = (reg_t)(cat6->a.src2);
1131 src2.im = cat6->a.src2_im;
1132 src1off = cat6->a.off;
1133 } else {
1134 src1.reg = (reg_t)(cat6->b.src1);
1135 src1.im = cat6->b.src1_im;
1136 src2.reg = (reg_t)(cat6->b.src2);
1137 src2.im = cat6->b.src2_im;
1138 }
1139
1140 if (!nodst) {
1141 if (sd)
1142 fprintf(ctx->out, "%c[", sd);
1143 /* note: dst might actually be a src (ie. address to store to) */
1144 if (cat6->dst_off) {
1145 dst.reg = (reg_t)(cat6->c.dst);
1146 print_src(ctx, &dst);
1147 if (cat6->g) {
1148 struct reginfo dstoff_reg = {
1149 .reg = (reg_t) cat6->c.off,
1150 .full = true
1151 };
1152 fprintf(ctx->out, "+");
1153 print_src(ctx, &dstoff_reg);
1154 } else if (cat6->c.off || cat6->c.off_high) {
1155 fprintf(ctx->out, "%+d", ((uint32_t)cat6->c.off_high << 8) | cat6->c.off);
1156 }
1157 } else {
1158 dst.reg = (reg_t)(cat6->d.dst);
1159 print_src(ctx, &dst);
1160 }
1161 if (sd)
1162 fprintf(ctx->out, "]");
1163 fprintf(ctx->out, ", ");
1164 }
1165
1166 if (ss)
1167 fprintf(ctx->out, "%c[", ss);
1168
1169 /* can have a larger than normal immed, so hack: */
1170 if (src1.im) {
1171 fprintf(ctx->out, "%u", src1.reg.dummy13);
1172 } else {
1173 print_src(ctx, &src1);
1174 }
1175
1176 if (cat6->src_off && cat6->g)
1177 print_src(ctx, &src2);
1178 else if (src1off)
1179 fprintf(ctx->out, "%+d", src1off);
1180 if (ss)
1181 fprintf(ctx->out, "]");
1182
1183 switch (_OPC(6, cat6->opc)) {
1184 case OPC_RESINFO:
1185 case OPC_RESFMT:
1186 break;
1187 default:
1188 fprintf(ctx->out, ", ");
1189 print_src(ctx, &src2);
1190 break;
1191 }
1192 }
1193
1194 static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr)
1195 {
1196 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
1197 struct reginfo src1, src2, ssbo;
1198 uint32_t opc = _OPC(6, cat6->opc);
1199 bool uses_type = opc != OPC_LDC;
1200
1201 static const struct {
1202 bool indirect;
1203 bool bindless;
1204 const char *name;
1205 } desc_features[8] = {
1206 [CAT6_IMM] = {
1207 .name = "imm"
1208 },
1209 [CAT6_UNIFORM] = {
1210 .indirect = true,
1211 .name = "uniform"
1212 },
1213 [CAT6_NONUNIFORM] = {
1214 .indirect = true,
1215 .name = "nonuniform"
1216 },
1217 [CAT6_BINDLESS_IMM] = {
1218 .bindless = true,
1219 .name = "imm"
1220 },
1221 [CAT6_BINDLESS_UNIFORM] = {
1222 .bindless = true,
1223 .indirect = true,
1224 .name = "uniform"
1225 },
1226 [CAT6_BINDLESS_NONUNIFORM] = {
1227 .bindless = true,
1228 .indirect = true,
1229 .name = "nonuniform"
1230 },
1231 };
1232
1233 bool indirect_ssbo = desc_features[cat6->desc_mode].indirect;
1234 bool bindless = desc_features[cat6->desc_mode].bindless;
1235 bool type_full = cat6->type != TYPE_U16;
1236
1237
1238 memset(&src1, 0, sizeof(src1));
1239 memset(&src2, 0, sizeof(src2));
1240 memset(&ssbo, 0, sizeof(ssbo));
1241
1242 if (uses_type) {
1243 fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped");
1244 fprintf(ctx->out, ".%dd", cat6->d + 1);
1245 fprintf(ctx->out, ".%s", type[cat6->type]);
1246 } else {
1247 fprintf(ctx->out, ".offset%d", cat6->d);
1248 }
1249 fprintf(ctx->out, ".%u", cat6->type_size + 1);
1250
1251 fprintf(ctx->out, ".%s", desc_features[cat6->desc_mode].name);
1252 if (bindless)
1253 fprintf(ctx->out, ".base%d", cat6->base);
1254 fprintf(ctx->out, " ");
1255
1256 src2.reg = (reg_t)(cat6->src2);
1257 src2.full = type_full;
1258 print_src(ctx, &src2);
1259 fprintf(ctx->out, ", ");
1260
1261 if (opc != OPC_RESINFO) {
1262 src1.reg = (reg_t)(cat6->src1);
1263 src1.full = true; // XXX
1264 print_src(ctx, &src1);
1265 fprintf(ctx->out, ", ");
1266 }
1267
1268 ssbo.reg = (reg_t)(cat6->ssbo);
1269 ssbo.im = !indirect_ssbo;
1270 ssbo.full = true;
1271 print_src(ctx, &ssbo);
1272
1273 if (debug & PRINT_VERBOSE) {
1274 fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1275 cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5);
1276 }
1277 }
1278
1279 static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr)
1280 {
1281 if (!is_cat6_legacy(instr, ctx->gpu_id)) {
1282 print_instr_cat6_a6xx(ctx, instr);
1283 if (debug & PRINT_VERBOSE)
1284 fprintf(ctx->out, " NEW");
1285 } else {
1286 print_instr_cat6_a3xx(ctx, instr);
1287 if (debug & PRINT_VERBOSE)
1288 fprintf(ctx->out, " LEGACY");
1289 }
1290 }
1291 static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr)
1292 {
1293 instr_cat7_t *cat7 = &instr->cat7;
1294
1295 if (cat7->g)
1296 fprintf(ctx->out, ".g");
1297 if (cat7->l)
1298 fprintf(ctx->out, ".l");
1299
1300 if (_OPC(7, cat7->opc) == OPC_FENCE) {
1301 if (cat7->r)
1302 fprintf(ctx->out, ".r");
1303 if (cat7->w)
1304 fprintf(ctx->out, ".w");
1305 }
1306 }
1307
1308 /* size of largest OPC field of all the instruction categories: */
1309 #define NOPC_BITS 6
1310
1311 static const struct opc_info {
1312 uint16_t cat;
1313 uint16_t opc;
1314 const char *name;
1315 void (*print)(struct disasm_ctx *ctx, instr_t *instr);
1316 } opcs[1 << (3+NOPC_BITS)] = {
1317 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1318 /* category 0: */
1319 OPC(0, OPC_NOP, nop),
1320 OPC(0, OPC_B, b),
1321 OPC(0, OPC_JUMP, jump),
1322 OPC(0, OPC_CALL, call),
1323 OPC(0, OPC_RET, ret),
1324 OPC(0, OPC_KILL, kill),
1325 OPC(0, OPC_END, end),
1326 OPC(0, OPC_EMIT, emit),
1327 OPC(0, OPC_CUT, cut),
1328 OPC(0, OPC_CHMASK, chmask),
1329 OPC(0, OPC_CHSH, chsh),
1330 OPC(0, OPC_FLOW_REV, flow_rev),
1331 OPC(0, OPC_PREDT, predt),
1332 OPC(0, OPC_PREDF, predf),
1333 OPC(0, OPC_PREDE, prede),
1334 OPC(0, OPC_BKT, bkt),
1335 OPC(0, OPC_STKS, stks),
1336 OPC(0, OPC_STKR, stkr),
1337 OPC(0, OPC_XSET, xset),
1338 OPC(0, OPC_XCLR, xclr),
1339 OPC(0, OPC_GETONE, getone),
1340 OPC(0, OPC_DBG, dbg),
1341 OPC(0, OPC_SHPS, shps),
1342 OPC(0, OPC_SHPE, shpe),
1343
1344 /* category 1: */
1345 OPC(1, OPC_MOV, ),
1346
1347 /* category 2: */
1348 OPC(2, OPC_ADD_F, add.f),
1349 OPC(2, OPC_MIN_F, min.f),
1350 OPC(2, OPC_MAX_F, max.f),
1351 OPC(2, OPC_MUL_F, mul.f),
1352 OPC(2, OPC_SIGN_F, sign.f),
1353 OPC(2, OPC_CMPS_F, cmps.f),
1354 OPC(2, OPC_ABSNEG_F, absneg.f),
1355 OPC(2, OPC_CMPV_F, cmpv.f),
1356 OPC(2, OPC_FLOOR_F, floor.f),
1357 OPC(2, OPC_CEIL_F, ceil.f),
1358 OPC(2, OPC_RNDNE_F, rndne.f),
1359 OPC(2, OPC_RNDAZ_F, rndaz.f),
1360 OPC(2, OPC_TRUNC_F, trunc.f),
1361 OPC(2, OPC_ADD_U, add.u),
1362 OPC(2, OPC_ADD_S, add.s),
1363 OPC(2, OPC_SUB_U, sub.u),
1364 OPC(2, OPC_SUB_S, sub.s),
1365 OPC(2, OPC_CMPS_U, cmps.u),
1366 OPC(2, OPC_CMPS_S, cmps.s),
1367 OPC(2, OPC_MIN_U, min.u),
1368 OPC(2, OPC_MIN_S, min.s),
1369 OPC(2, OPC_MAX_U, max.u),
1370 OPC(2, OPC_MAX_S, max.s),
1371 OPC(2, OPC_ABSNEG_S, absneg.s),
1372 OPC(2, OPC_AND_B, and.b),
1373 OPC(2, OPC_OR_B, or.b),
1374 OPC(2, OPC_NOT_B, not.b),
1375 OPC(2, OPC_XOR_B, xor.b),
1376 OPC(2, OPC_CMPV_U, cmpv.u),
1377 OPC(2, OPC_CMPV_S, cmpv.s),
1378 OPC(2, OPC_MUL_U24, mul.u24),
1379 OPC(2, OPC_MUL_S24, mul.s24),
1380 OPC(2, OPC_MULL_U, mull.u),
1381 OPC(2, OPC_BFREV_B, bfrev.b),
1382 OPC(2, OPC_CLZ_S, clz.s),
1383 OPC(2, OPC_CLZ_B, clz.b),
1384 OPC(2, OPC_SHL_B, shl.b),
1385 OPC(2, OPC_SHR_B, shr.b),
1386 OPC(2, OPC_ASHR_B, ashr.b),
1387 OPC(2, OPC_BARY_F, bary.f),
1388 OPC(2, OPC_MGEN_B, mgen.b),
1389 OPC(2, OPC_GETBIT_B, getbit.b),
1390 OPC(2, OPC_SETRM, setrm),
1391 OPC(2, OPC_CBITS_B, cbits.b),
1392 OPC(2, OPC_SHB, shb),
1393 OPC(2, OPC_MSAD, msad),
1394
1395 /* category 3: */
1396 OPC(3, OPC_MAD_U16, mad.u16),
1397 OPC(3, OPC_MADSH_U16, madsh.u16),
1398 OPC(3, OPC_MAD_S16, mad.s16),
1399 OPC(3, OPC_MADSH_M16, madsh.m16),
1400 OPC(3, OPC_MAD_U24, mad.u24),
1401 OPC(3, OPC_MAD_S24, mad.s24),
1402 OPC(3, OPC_MAD_F16, mad.f16),
1403 OPC(3, OPC_MAD_F32, mad.f32),
1404 OPC(3, OPC_SEL_B16, sel.b16),
1405 OPC(3, OPC_SEL_B32, sel.b32),
1406 OPC(3, OPC_SEL_S16, sel.s16),
1407 OPC(3, OPC_SEL_S32, sel.s32),
1408 OPC(3, OPC_SEL_F16, sel.f16),
1409 OPC(3, OPC_SEL_F32, sel.f32),
1410 OPC(3, OPC_SAD_S16, sad.s16),
1411 OPC(3, OPC_SAD_S32, sad.s32),
1412
1413 /* category 4: */
1414 OPC(4, OPC_RCP, rcp),
1415 OPC(4, OPC_RSQ, rsq),
1416 OPC(4, OPC_LOG2, log2),
1417 OPC(4, OPC_EXP2, exp2),
1418 OPC(4, OPC_SIN, sin),
1419 OPC(4, OPC_COS, cos),
1420 OPC(4, OPC_SQRT, sqrt),
1421 OPC(4, OPC_HRSQ, hrsq),
1422 OPC(4, OPC_HLOG2, hlog2),
1423 OPC(4, OPC_HEXP2, hexp2),
1424
1425 /* category 5: */
1426 OPC(5, OPC_ISAM, isam),
1427 OPC(5, OPC_ISAML, isaml),
1428 OPC(5, OPC_ISAMM, isamm),
1429 OPC(5, OPC_SAM, sam),
1430 OPC(5, OPC_SAMB, samb),
1431 OPC(5, OPC_SAML, saml),
1432 OPC(5, OPC_SAMGQ, samgq),
1433 OPC(5, OPC_GETLOD, getlod),
1434 OPC(5, OPC_CONV, conv),
1435 OPC(5, OPC_CONVM, convm),
1436 OPC(5, OPC_GETSIZE, getsize),
1437 OPC(5, OPC_GETBUF, getbuf),
1438 OPC(5, OPC_GETPOS, getpos),
1439 OPC(5, OPC_GETINFO, getinfo),
1440 OPC(5, OPC_DSX, dsx),
1441 OPC(5, OPC_DSY, dsy),
1442 OPC(5, OPC_GATHER4R, gather4r),
1443 OPC(5, OPC_GATHER4G, gather4g),
1444 OPC(5, OPC_GATHER4B, gather4b),
1445 OPC(5, OPC_GATHER4A, gather4a),
1446 OPC(5, OPC_SAMGP0, samgp0),
1447 OPC(5, OPC_SAMGP1, samgp1),
1448 OPC(5, OPC_SAMGP2, samgp2),
1449 OPC(5, OPC_SAMGP3, samgp3),
1450 OPC(5, OPC_DSXPP_1, dsxpp.1),
1451 OPC(5, OPC_DSYPP_1, dsypp.1),
1452 OPC(5, OPC_RGETPOS, rgetpos),
1453 OPC(5, OPC_RGETINFO, rgetinfo),
1454 /* macros are needed here for ir3_print */
1455 OPC(5, OPC_DSXPP_MACRO, dsxpp.macro),
1456 OPC(5, OPC_DSYPP_MACRO, dsypp.macro),
1457
1458
1459 /* category 6: */
1460 OPC(6, OPC_LDG, ldg),
1461 OPC(6, OPC_LDL, ldl),
1462 OPC(6, OPC_LDP, ldp),
1463 OPC(6, OPC_STG, stg),
1464 OPC(6, OPC_STL, stl),
1465 OPC(6, OPC_STP, stp),
1466 OPC(6, OPC_LDIB, ldib),
1467 OPC(6, OPC_G2L, g2l),
1468 OPC(6, OPC_L2G, l2g),
1469 OPC(6, OPC_PREFETCH, prefetch),
1470 OPC(6, OPC_LDLW, ldlw),
1471 OPC(6, OPC_STLW, stlw),
1472 OPC(6, OPC_RESFMT, resfmt),
1473 OPC(6, OPC_RESINFO, resinfo),
1474 OPC(6, OPC_ATOMIC_ADD, atomic.add),
1475 OPC(6, OPC_ATOMIC_SUB, atomic.sub),
1476 OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
1477 OPC(6, OPC_ATOMIC_INC, atomic.inc),
1478 OPC(6, OPC_ATOMIC_DEC, atomic.dec),
1479 OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
1480 OPC(6, OPC_ATOMIC_MIN, atomic.min),
1481 OPC(6, OPC_ATOMIC_MAX, atomic.max),
1482 OPC(6, OPC_ATOMIC_AND, atomic.and),
1483 OPC(6, OPC_ATOMIC_OR, atomic.or),
1484 OPC(6, OPC_ATOMIC_XOR, atomic.xor),
1485 OPC(6, OPC_LDGB, ldgb),
1486 OPC(6, OPC_STGB, stgb),
1487 OPC(6, OPC_STIB, stib),
1488 OPC(6, OPC_LDC, ldc),
1489 OPC(6, OPC_LDLV, ldlv),
1490
1491 OPC(7, OPC_BAR, bar),
1492 OPC(7, OPC_FENCE, fence),
1493
1494 #undef OPC
1495 };
1496
1497 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1498
1499 const char *disasm_a3xx_instr_name(opc_t opc)
1500 {
1501 if (opc_cat(opc) == -1) return "??meta??";
1502 return opcs[opc].name;
1503 }
1504
1505 static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
1506 {
1507 const char *name = GETINFO(instr)->name;
1508 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1509
1510 if (name) {
1511 fprintf(ctx->out, "%s", name);
1512 GETINFO(instr)->print(ctx, instr);
1513 } else {
1514 fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
1515
1516 switch (instr->opc_cat) {
1517 case 0: print_instr_cat0(ctx, instr); break;
1518 case 1: print_instr_cat1(ctx, instr); break;
1519 case 2: print_instr_cat2(ctx, instr); break;
1520 case 3: print_instr_cat3(ctx, instr); break;
1521 case 4: print_instr_cat4(ctx, instr); break;
1522 case 5: print_instr_cat5(ctx, instr); break;
1523 case 6: print_instr_cat6(ctx, instr); break;
1524 case 7: print_instr_cat7(ctx, instr); break;
1525 }
1526 }
1527 }
1528
1529 static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
1530 {
1531 instr_t *instr = (instr_t *)dwords;
1532 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1533 unsigned nop = 0;
1534 unsigned cycles = ctx->stats->instructions;
1535
1536 if (debug & PRINT_RAW) {
1537 fprintf(ctx->out, "%s:%d:%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
1538 instr->opc_cat, n, cycles++, dwords[1], dwords[0]);
1539 }
1540
1541 /* NOTE: order flags are printed is a bit fugly.. but for now I
1542 * try to match the order in llvm-a3xx disassembler for easy
1543 * diff'ing..
1544 */
1545
1546 ctx->repeat = instr_repeat(instr);
1547 ctx->stats->instructions += 1 + ctx->repeat;
1548 ctx->stats->instlen++;
1549
1550 if (instr->sync) {
1551 fprintf(ctx->out, "(sy)");
1552 ctx->stats->sy++;
1553 }
1554 if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
1555 fprintf(ctx->out, "(ss)");
1556 ctx->stats->ss++;
1557 }
1558 if (instr->jmp_tgt)
1559 fprintf(ctx->out, "(jp)");
1560 if ((instr->opc_cat == 0) && instr->cat0.eq)
1561 fprintf(ctx->out, "(eq)");
1562 if (instr_sat(instr))
1563 fprintf(ctx->out, "(sat)");
1564 if (ctx->repeat)
1565 fprintf(ctx->out, "(rpt%d)", ctx->repeat);
1566 else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
1567 nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
1568 else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
1569 nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
1570 ctx->stats->instructions += nop;
1571 ctx->stats->nops += nop;
1572 if (opc == OPC_NOP)
1573 ctx->stats->nops += 1 + ctx->repeat;
1574 if (nop)
1575 fprintf(ctx->out, "(nop%d) ", nop);
1576
1577 if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
1578 fprintf(ctx->out, "(ul)");
1579
1580 print_single_instr(ctx, instr);
1581 fprintf(ctx->out, "\n");
1582
1583 process_reg_dst(ctx);
1584
1585 if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
1586 int i;
1587 for (i = 0; i < nop; i++) {
1588 if (debug & PRINT_VERBOSE) {
1589 fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
1590 levels[ctx->level], instr->opc_cat, n, cycles++);
1591 }
1592 fprintf(ctx->out, "nop\n");
1593 }
1594 for (i = 0; i < ctx->repeat; i++) {
1595 ctx->repeatidx = i + 1;
1596 if (debug & PRINT_VERBOSE) {
1597 fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
1598 levels[ctx->level], instr->opc_cat, n, cycles++);
1599 }
1600 print_single_instr(ctx, instr);
1601 fprintf(ctx->out, "\n");
1602 }
1603 ctx->repeatidx = 0;
1604 }
1605
1606 return (instr->opc_cat == 0) &&
1607 ((opc == OPC_END) || (opc == OPC_CHSH));
1608 }
1609
1610 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
1611 {
1612 struct shader_stats stats;
1613 return disasm_a3xx_stat(dwords, sizedwords, level, out, gpu_id, &stats);
1614 }
1615
1616 int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
1617 unsigned gpu_id, struct shader_stats *stats)
1618 {
1619 struct disasm_ctx ctx;
1620 int i;
1621 int nop_count = 0;
1622 bool has_end = false;
1623
1624 ir3_assert((sizedwords % 2) == 0);
1625
1626 memset(&ctx, 0, sizeof(ctx));
1627 ctx.out = out;
1628 ctx.level = level;
1629 ctx.gpu_id = gpu_id;
1630 ctx.stats = stats;
1631 memset(ctx.stats, 0, sizeof(*ctx.stats));
1632
1633 for (i = 0; i < sizedwords; i += 2) {
1634 has_end |= print_instr(&ctx, &dwords[i], i/2);
1635 if (!has_end)
1636 continue;
1637 if (dwords[i] == 0 && dwords[i + 1] == 0)
1638 nop_count++;
1639 else
1640 nop_count = 0;
1641 if (nop_count > 3)
1642 break;
1643 }
1644
1645 if (debug & PRINT_STATS)
1646 print_reg_stats(&ctx);
1647
1648 return 0;
1649 }
1650
1651 void disasm_a3xx_set_debug(enum debug_t d)
1652 {
1653 debug = d;
1654 }