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freedreno/ir3: Print a space after nop counts, like qcom's disasm.
[mesa.git] / src / freedreno / ir3 / disasm-a3xx.c
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <assert.h>
30
31 #include <util/u_debug.h>
32
33 #include "instr-a3xx.h"
34
35 /* bitmask of debug flags */
36 enum debug_t {
37 PRINT_RAW = 0x1, /* dump raw hexdump */
38 PRINT_VERBOSE = 0x2,
39 EXPAND_REPEAT = 0x4,
40 };
41
42 static enum debug_t debug;
43
44 #define printf debug_printf
45
46 static const char *levels[] = {
47 "",
48 "\t",
49 "\t\t",
50 "\t\t\t",
51 "\t\t\t\t",
52 "\t\t\t\t\t",
53 "\t\t\t\t\t\t",
54 "\t\t\t\t\t\t\t",
55 "\t\t\t\t\t\t\t\t",
56 "\t\t\t\t\t\t\t\t\t",
57 "x",
58 "x",
59 "x",
60 "x",
61 "x",
62 "x",
63 };
64
65 static const char *component = "xyzw";
66
67 static const char *type[] = {
68 [TYPE_F16] = "f16",
69 [TYPE_F32] = "f32",
70 [TYPE_U16] = "u16",
71 [TYPE_U32] = "u32",
72 [TYPE_S16] = "s16",
73 [TYPE_S32] = "s32",
74 [TYPE_U8] = "u8",
75 [TYPE_S8] = "s8",
76 };
77
78 struct disasm_ctx {
79 FILE *out;
80 int level;
81 unsigned gpu_id;
82
83 /* current instruction repeat flag: */
84 unsigned repeat;
85 /* current instruction repeat indx/offset (for --expand): */
86 unsigned repeatidx;
87
88 unsigned instructions;
89 };
90
91 static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full, bool r,
92 bool c, bool im, bool neg, bool abs, bool addr_rel)
93 {
94 const char type = c ? 'c' : 'r';
95
96 // XXX I prefer - and || for neg/abs, but preserving format used
97 // by libllvm-a3xx for easy diffing..
98
99 if (abs && neg)
100 fprintf(ctx->out, "(absneg)");
101 else if (neg)
102 fprintf(ctx->out, "(neg)");
103 else if (abs)
104 fprintf(ctx->out, "(abs)");
105
106 if (r)
107 fprintf(ctx->out, "(r)");
108
109 if (im) {
110 fprintf(ctx->out, "%d", reg.iim_val);
111 } else if (addr_rel) {
112 /* I would just use %+d but trying to make it diff'able with
113 * libllvm-a3xx...
114 */
115 if (reg.iim_val < 0)
116 fprintf(ctx->out, "%s%c<a0.x - %d>", full ? "" : "h", type, -reg.iim_val);
117 else if (reg.iim_val > 0)
118 fprintf(ctx->out, "%s%c<a0.x + %d>", full ? "" : "h", type, reg.iim_val);
119 else
120 fprintf(ctx->out, "%s%c<a0.x>", full ? "" : "h", type);
121 } else if ((reg.num == REG_A0) && !c) {
122 /* This matches libllvm output, the second (scalar) address register
123 * seems to be called a1.x instead of a0.y.
124 */
125 fprintf(ctx->out, "a%d.x", reg.comp);
126 } else if ((reg.num == REG_P0) && !c) {
127 fprintf(ctx->out, "p0.%c", component[reg.comp]);
128 } else {
129 fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
130 }
131 }
132
133 static unsigned regidx(reg_t reg)
134 {
135 return (4 * reg.num) + reg.comp;
136 }
137
138 static reg_t idxreg(unsigned idx)
139 {
140 return (reg_t){
141 .comp = idx & 0x3,
142 .num = idx >> 2,
143 };
144 }
145
146 static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
147 {
148 reg = idxreg(regidx(reg) + ctx->repeatidx);
149 print_reg(ctx, reg, full, false, false, false, false, false, addr_rel);
150 }
151
152 static void print_reg_src(struct disasm_ctx *ctx, reg_t reg, bool full, bool r,
153 bool c, bool im, bool neg, bool abs, bool addr_rel)
154 {
155 if (r)
156 reg = idxreg(regidx(reg) + ctx->repeatidx);
157
158 print_reg(ctx, reg, full, r, c, im, neg, abs, addr_rel);
159 }
160
161 /* TODO switch to using reginfo struct everywhere, since more readable
162 * than passing a bunch of bools to print_reg_src
163 */
164
165 struct reginfo {
166 reg_t reg;
167 bool full;
168 bool r;
169 bool c;
170 bool im;
171 bool neg;
172 bool abs;
173 bool addr_rel;
174 };
175
176 static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
177 {
178 print_reg_src(ctx, info->reg, info->full, info->r, info->c, info->im,
179 info->neg, info->abs, info->addr_rel);
180 }
181
182 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
183 //{
184 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
185 //}
186
187 static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
188 {
189 instr_cat0_t *cat0 = &instr->cat0;
190
191 switch (cat0->opc) {
192 case OPC_KILL:
193 case OPC_IF:
194 fprintf(ctx->out, " %sp0.%c", cat0->inv ? "!" : "",
195 component[cat0->comp]);
196 break;
197 case OPC_BR:
198 fprintf(ctx->out, " %sp0.%c, #%d", cat0->inv ? "!" : "",
199 component[cat0->comp], cat0->a3xx.immed);
200 break;
201 case OPC_JUMP:
202 case OPC_CALL:
203 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
204 break;
205 }
206
207 if ((debug & PRINT_VERBOSE) && (cat0->dummy2|cat0->dummy3|cat0->dummy4))
208 fprintf(ctx->out, "\t{0: %x,%x,%x}", cat0->dummy2, cat0->dummy3, cat0->dummy4);
209 }
210
211 static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr)
212 {
213 instr_cat1_t *cat1 = &instr->cat1;
214
215 if (cat1->ul)
216 fprintf(ctx->out, "(ul)");
217
218 if (cat1->src_type == cat1->dst_type) {
219 if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) {
220 /* special case (nmemonic?): */
221 fprintf(ctx->out, "mova");
222 } else {
223 fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
224 }
225 } else {
226 fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
227 }
228
229 fprintf(ctx->out, " ");
230
231 if (cat1->even)
232 fprintf(ctx->out, "(even)");
233
234 if (cat1->pos_inf)
235 fprintf(ctx->out, "(pos_infinity)");
236
237 print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32,
238 cat1->dst_rel);
239
240 fprintf(ctx->out, ", ");
241
242 /* ugg, have to special case this.. vs print_reg().. */
243 if (cat1->src_im) {
244 if (type_float(cat1->src_type))
245 fprintf(ctx->out, "(%f)", cat1->fim_val);
246 else if (type_uint(cat1->src_type))
247 fprintf(ctx->out, "0x%08x", cat1->uim_val);
248 else
249 fprintf(ctx->out, "%d", cat1->iim_val);
250 } else if (cat1->src_rel && !cat1->src_c) {
251 /* I would just use %+d but trying to make it diff'able with
252 * libllvm-a3xx...
253 */
254 char type = cat1->src_rel_c ? 'c' : 'r';
255 const char *full = (type_size(cat1->src_type) == 32) ? "" : "h";
256 if (cat1->off < 0)
257 fprintf(ctx->out, "%s%c<a0.x - %d>", full, type, -cat1->off);
258 else if (cat1->off > 0)
259 fprintf(ctx->out, "%s%c<a0.x + %d>", full, type, cat1->off);
260 else
261 fprintf(ctx->out, "%s%c<a0.x>", full, type);
262 } else {
263 print_reg_src(ctx, (reg_t)(cat1->src), type_size(cat1->src_type) == 32,
264 cat1->src_r, cat1->src_c, cat1->src_im, false, false, false);
265 }
266
267 if ((debug & PRINT_VERBOSE) && (cat1->must_be_0))
268 fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0);
269 }
270
271 static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr)
272 {
273 instr_cat2_t *cat2 = &instr->cat2;
274 static const char *cond[] = {
275 "lt",
276 "le",
277 "gt",
278 "ge",
279 "eq",
280 "ne",
281 "?6?",
282 };
283
284 switch (_OPC(2, cat2->opc)) {
285 case OPC_CMPS_F:
286 case OPC_CMPS_U:
287 case OPC_CMPS_S:
288 case OPC_CMPV_F:
289 case OPC_CMPV_U:
290 case OPC_CMPV_S:
291 fprintf(ctx->out, ".%s", cond[cat2->cond]);
292 break;
293 }
294
295 fprintf(ctx->out, " ");
296 if (cat2->ei)
297 fprintf(ctx->out, "(ei)");
298 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
299 fprintf(ctx->out, ", ");
300
301 unsigned src1_r = cat2->repeat ? cat2->src1_r : 0;
302 if (cat2->c1.src1_c) {
303 print_reg_src(ctx, (reg_t)(cat2->c1.src1), cat2->full, src1_r,
304 cat2->c1.src1_c, cat2->src1_im, cat2->src1_neg,
305 cat2->src1_abs, false);
306 } else if (cat2->rel1.src1_rel) {
307 print_reg_src(ctx, (reg_t)(cat2->rel1.src1), cat2->full, src1_r,
308 cat2->rel1.src1_c, cat2->src1_im, cat2->src1_neg,
309 cat2->src1_abs, cat2->rel1.src1_rel);
310 } else {
311 print_reg_src(ctx, (reg_t)(cat2->src1), cat2->full, src1_r,
312 false, cat2->src1_im, cat2->src1_neg,
313 cat2->src1_abs, false);
314 }
315
316 unsigned src2_r = cat2->repeat ? cat2->src2_r : 0;
317 switch (_OPC(2, cat2->opc)) {
318 case OPC_ABSNEG_F:
319 case OPC_ABSNEG_S:
320 case OPC_CLZ_B:
321 case OPC_CLZ_S:
322 case OPC_SIGN_F:
323 case OPC_FLOOR_F:
324 case OPC_CEIL_F:
325 case OPC_RNDNE_F:
326 case OPC_RNDAZ_F:
327 case OPC_TRUNC_F:
328 case OPC_NOT_B:
329 case OPC_BFREV_B:
330 case OPC_SETRM:
331 case OPC_CBITS_B:
332 /* these only have one src reg */
333 break;
334 default:
335 fprintf(ctx->out, ", ");
336 if (cat2->c2.src2_c) {
337 print_reg_src(ctx, (reg_t)(cat2->c2.src2), cat2->full, src2_r,
338 cat2->c2.src2_c, cat2->src2_im, cat2->src2_neg,
339 cat2->src2_abs, false);
340 } else if (cat2->rel2.src2_rel) {
341 print_reg_src(ctx, (reg_t)(cat2->rel2.src2), cat2->full, src2_r,
342 cat2->rel2.src2_c, cat2->src2_im, cat2->src2_neg,
343 cat2->src2_abs, cat2->rel2.src2_rel);
344 } else {
345 print_reg_src(ctx, (reg_t)(cat2->src2), cat2->full, src2_r,
346 false, cat2->src2_im, cat2->src2_neg,
347 cat2->src2_abs, false);
348 }
349 break;
350 }
351 }
352
353 static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr)
354 {
355 instr_cat3_t *cat3 = &instr->cat3;
356 bool full = instr_cat3_full(cat3);
357
358 fprintf(ctx->out, " ");
359 print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false);
360 fprintf(ctx->out, ", ");
361 unsigned src1_r = cat3->repeat ? cat3->src1_r : 0;
362 if (cat3->c1.src1_c) {
363 print_reg_src(ctx, (reg_t)(cat3->c1.src1), full,
364 src1_r, cat3->c1.src1_c, false, cat3->src1_neg,
365 false, false);
366 } else if (cat3->rel1.src1_rel) {
367 print_reg_src(ctx, (reg_t)(cat3->rel1.src1), full,
368 src1_r, cat3->rel1.src1_c, false, cat3->src1_neg,
369 false, cat3->rel1.src1_rel);
370 } else {
371 print_reg_src(ctx, (reg_t)(cat3->src1), full,
372 src1_r, false, false, cat3->src1_neg,
373 false, false);
374 }
375 fprintf(ctx->out, ", ");
376 unsigned src2_r = cat3->repeat ? cat3->src2_r : 0;
377 print_reg_src(ctx, (reg_t)cat3->src2, full,
378 src2_r, cat3->src2_c, false, cat3->src2_neg,
379 false, false);
380 fprintf(ctx->out, ", ");
381 if (cat3->c2.src3_c) {
382 print_reg_src(ctx, (reg_t)(cat3->c2.src3), full,
383 cat3->src3_r, cat3->c2.src3_c, false, cat3->src3_neg,
384 false, false);
385 } else if (cat3->rel2.src3_rel) {
386 print_reg_src(ctx, (reg_t)(cat3->rel2.src3), full,
387 cat3->src3_r, cat3->rel2.src3_c, false, cat3->src3_neg,
388 false, cat3->rel2.src3_rel);
389 } else {
390 print_reg_src(ctx, (reg_t)(cat3->src3), full,
391 cat3->src3_r, false, false, cat3->src3_neg,
392 false, false);
393 }
394 }
395
396 static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr)
397 {
398 instr_cat4_t *cat4 = &instr->cat4;
399
400 fprintf(ctx->out, " ");
401 print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false);
402 fprintf(ctx->out, ", ");
403
404 if (cat4->c.src_c) {
405 print_reg_src(ctx, (reg_t)(cat4->c.src), cat4->full,
406 cat4->src_r, cat4->c.src_c, cat4->src_im,
407 cat4->src_neg, cat4->src_abs, false);
408 } else if (cat4->rel.src_rel) {
409 print_reg_src(ctx, (reg_t)(cat4->rel.src), cat4->full,
410 cat4->src_r, cat4->rel.src_c, cat4->src_im,
411 cat4->src_neg, cat4->src_abs, cat4->rel.src_rel);
412 } else {
413 print_reg_src(ctx, (reg_t)(cat4->src), cat4->full,
414 cat4->src_r, false, cat4->src_im,
415 cat4->src_neg, cat4->src_abs, false);
416 }
417
418 if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2))
419 fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2);
420 }
421
422 static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr)
423 {
424 static const struct {
425 bool src1, src2, samp, tex;
426 } info[0x1f] = {
427 [opc_op(OPC_ISAM)] = { true, false, true, true, },
428 [opc_op(OPC_ISAML)] = { true, true, true, true, },
429 [opc_op(OPC_ISAMM)] = { true, false, true, true, },
430 [opc_op(OPC_SAM)] = { true, false, true, true, },
431 [opc_op(OPC_SAMB)] = { true, true, true, true, },
432 [opc_op(OPC_SAML)] = { true, true, true, true, },
433 [opc_op(OPC_SAMGQ)] = { true, false, true, true, },
434 [opc_op(OPC_GETLOD)] = { true, false, true, true, },
435 [opc_op(OPC_CONV)] = { true, true, true, true, },
436 [opc_op(OPC_CONVM)] = { true, true, true, true, },
437 [opc_op(OPC_GETSIZE)] = { true, false, false, true, },
438 [opc_op(OPC_GETBUF)] = { false, false, false, true, },
439 [opc_op(OPC_GETPOS)] = { true, false, false, true, },
440 [opc_op(OPC_GETINFO)] = { false, false, false, true, },
441 [opc_op(OPC_DSX)] = { true, false, false, false, },
442 [opc_op(OPC_DSY)] = { true, false, false, false, },
443 [opc_op(OPC_GATHER4R)] = { true, false, true, true, },
444 [opc_op(OPC_GATHER4G)] = { true, false, true, true, },
445 [opc_op(OPC_GATHER4B)] = { true, false, true, true, },
446 [opc_op(OPC_GATHER4A)] = { true, false, true, true, },
447 [opc_op(OPC_SAMGP0)] = { true, false, true, true, },
448 [opc_op(OPC_SAMGP1)] = { true, false, true, true, },
449 [opc_op(OPC_SAMGP2)] = { true, false, true, true, },
450 [opc_op(OPC_SAMGP3)] = { true, false, true, true, },
451 [opc_op(OPC_DSXPP_1)] = { true, false, false, false, },
452 [opc_op(OPC_DSYPP_1)] = { true, false, false, false, },
453 [opc_op(OPC_RGETPOS)] = { true, false, false, false, },
454 [opc_op(OPC_RGETINFO)] = { false, false, false, false, },
455 };
456
457 static const struct {
458 bool indirect;
459 bool bindless;
460 bool use_a1;
461 bool uniform;
462 } desc_features[8] = {
463 [CAT5_NONUNIFORM] = { .indirect = true, },
464 [CAT5_UNIFORM] = { .indirect = true, .uniform = true, },
465 [CAT5_BINDLESS_IMM] = { .bindless = true, },
466 [CAT5_BINDLESS_UNIFORM] = {
467 .bindless = true,
468 .indirect = true,
469 .uniform = true,
470 },
471 [CAT5_BINDLESS_NONUNIFORM] = {
472 .bindless = true,
473 .indirect = true,
474 },
475 [CAT5_BINDLESS_A1_IMM] = {
476 .bindless = true,
477 .use_a1 = true,
478 },
479 [CAT5_BINDLESS_A1_UNIFORM] = {
480 .bindless = true,
481 .indirect = true,
482 .uniform = true,
483 .use_a1 = true,
484 },
485 [CAT5_BINDLESS_A1_NONUNIFORM] = {
486 .bindless = true,
487 .indirect = true,
488 .use_a1 = true,
489 },
490 };
491
492 instr_cat5_t *cat5 = &instr->cat5;
493 int i;
494
495 bool desc_indirect =
496 cat5->is_s2en_bindless &&
497 desc_features[cat5->s2en_bindless.desc_mode].indirect;
498 bool bindless =
499 cat5->is_s2en_bindless &&
500 desc_features[cat5->s2en_bindless.desc_mode].bindless;
501 bool use_a1 =
502 cat5->is_s2en_bindless &&
503 desc_features[cat5->s2en_bindless.desc_mode].use_a1;
504 bool uniform =
505 cat5->is_s2en_bindless &&
506 desc_features[cat5->s2en_bindless.desc_mode].uniform;
507
508 if (cat5->is_3d) fprintf(ctx->out, ".3d");
509 if (cat5->is_a) fprintf(ctx->out, ".a");
510 if (cat5->is_o) fprintf(ctx->out, ".o");
511 if (cat5->is_p) fprintf(ctx->out, ".p");
512 if (cat5->is_s) fprintf(ctx->out, ".s");
513 if (desc_indirect) fprintf(ctx->out, ".s2en");
514 if (uniform) fprintf(ctx->out, ".uniform");
515
516 if (bindless) {
517 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo;
518 fprintf(ctx->out, ".base%d", base);
519 }
520
521 fprintf(ctx->out, " ");
522
523 switch (_OPC(5, cat5->opc)) {
524 case OPC_DSXPP_1:
525 case OPC_DSYPP_1:
526 break;
527 default:
528 fprintf(ctx->out, "(%s)", type[cat5->type]);
529 break;
530 }
531
532 fprintf(ctx->out, "(");
533 for (i = 0; i < 4; i++)
534 if (cat5->wrmask & (1 << i))
535 fprintf(ctx->out, "%c", "xyzw"[i]);
536 fprintf(ctx->out, ")");
537
538 print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false);
539
540 if (info[cat5->opc].src1) {
541 fprintf(ctx->out, ", ");
542 print_reg_src(ctx, (reg_t)(cat5->src1), cat5->full, false, false, false,
543 false, false, false);
544 }
545
546 if (cat5->is_o || info[cat5->opc].src2) {
547 fprintf(ctx->out, ", ");
548 print_reg_src(ctx, (reg_t)(cat5->src2), cat5->full,
549 false, false, false, false, false, false);
550 }
551 if (cat5->is_s2en_bindless) {
552 if (!desc_indirect) {
553 if (info[cat5->opc].samp) {
554 if (use_a1)
555 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3);
556 else
557 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf);
558 }
559
560 if (info[cat5->opc].tex && !use_a1) {
561 fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4);
562 }
563 }
564 } else {
565 if (info[cat5->opc].samp)
566 fprintf(ctx->out, ", s#%d", cat5->norm.samp);
567 if (info[cat5->opc].tex)
568 fprintf(ctx->out, ", t#%d", cat5->norm.tex);
569 }
570
571 if (desc_indirect) {
572 fprintf(ctx->out, ", ");
573 print_reg_src(ctx, (reg_t)(cat5->s2en_bindless.src3), bindless,
574 false, false, false, false, false, false);
575 }
576
577 if (use_a1)
578 fprintf(ctx->out, ", a1.x");
579
580 if (debug & PRINT_VERBOSE) {
581 if (cat5->is_s2en_bindless) {
582 if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1)
583 fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1);
584 } else {
585 if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1)
586 fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1);
587 }
588 }
589 }
590
591 static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
592 {
593 instr_cat6_t *cat6 = &instr->cat6;
594 char sd = 0, ss = 0; /* dst/src address space */
595 bool nodst = false;
596 struct reginfo dst, src1, src2;
597 int src1off = 0, dstoff = 0;
598
599 memset(&dst, 0, sizeof(dst));
600 memset(&src1, 0, sizeof(src1));
601 memset(&src2, 0, sizeof(src2));
602
603 switch (_OPC(6, cat6->opc)) {
604 case OPC_RESINFO:
605 case OPC_RESFMT:
606 dst.full = type_size(cat6->type) == 32;
607 src1.full = type_size(cat6->type) == 32;
608 src2.full = type_size(cat6->type) == 32;
609 break;
610 case OPC_L2G:
611 case OPC_G2L:
612 dst.full = true;
613 src1.full = true;
614 src2.full = true;
615 break;
616 case OPC_STG:
617 case OPC_STL:
618 case OPC_STP:
619 case OPC_STLW:
620 case OPC_STIB:
621 dst.full = type_size(cat6->type) == 32;
622 src1.full = type_size(cat6->type) == 32;
623 src2.full = type_size(cat6->type) == 32;
624 break;
625 default:
626 dst.full = type_size(cat6->type) == 32;
627 src1.full = true;
628 src2.full = true;
629 break;
630 }
631
632 switch (_OPC(6, cat6->opc)) {
633 case OPC_PREFETCH:
634 break;
635 case OPC_RESINFO:
636 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
637 break;
638 case OPC_LDGB:
639 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
640 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
641 fprintf(ctx->out, ".%s", type[cat6->type]);
642 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
643 break;
644 case OPC_STGB:
645 case OPC_STIB:
646 fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped");
647 fprintf(ctx->out, ".%dd", cat6->stgb.d + 1);
648 fprintf(ctx->out, ".%s", type[cat6->type]);
649 fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1);
650 break;
651 case OPC_ATOMIC_ADD:
652 case OPC_ATOMIC_SUB:
653 case OPC_ATOMIC_XCHG:
654 case OPC_ATOMIC_INC:
655 case OPC_ATOMIC_DEC:
656 case OPC_ATOMIC_CMPXCHG:
657 case OPC_ATOMIC_MIN:
658 case OPC_ATOMIC_MAX:
659 case OPC_ATOMIC_AND:
660 case OPC_ATOMIC_OR:
661 case OPC_ATOMIC_XOR:
662 ss = cat6->g ? 'g' : 'l';
663 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
664 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
665 fprintf(ctx->out, ".%s", type[cat6->type]);
666 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
667 fprintf(ctx->out, ".%c", ss);
668 break;
669 default:
670 dst.im = cat6->g && !cat6->dst_off;
671 fprintf(ctx->out, ".%s", type[cat6->type]);
672 break;
673 }
674 fprintf(ctx->out, " ");
675
676 switch (_OPC(6, cat6->opc)) {
677 case OPC_STG:
678 sd = 'g';
679 break;
680 case OPC_STP:
681 sd = 'p';
682 break;
683 case OPC_STL:
684 case OPC_STLW:
685 sd = 'l';
686 break;
687
688 case OPC_LDG:
689 case OPC_LDC:
690 ss = 'g';
691 break;
692 case OPC_LDP:
693 ss = 'p';
694 break;
695 case OPC_LDL:
696 case OPC_LDLW:
697 case OPC_LDLV:
698 ss = 'l';
699 break;
700
701 case OPC_L2G:
702 ss = 'l';
703 sd = 'g';
704 break;
705
706 case OPC_G2L:
707 ss = 'g';
708 sd = 'l';
709 break;
710
711 case OPC_PREFETCH:
712 ss = 'g';
713 nodst = true;
714 break;
715 }
716
717 if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) {
718 struct reginfo src3;
719
720 memset(&src3, 0, sizeof(src3));
721
722 src1.reg = (reg_t)(cat6->stgb.src1);
723 src2.reg = (reg_t)(cat6->stgb.src2);
724 src2.im = cat6->stgb.src2_im;
725 src3.reg = (reg_t)(cat6->stgb.src3);
726 src3.im = cat6->stgb.src3_im;
727 src3.full = true;
728
729 fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo);
730 print_src(ctx, &src1);
731 fprintf(ctx->out, ", ");
732 print_src(ctx, &src2);
733 fprintf(ctx->out, ", ");
734 print_src(ctx, &src3);
735
736 if (debug & PRINT_VERBOSE)
737 fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3);
738
739 return;
740 }
741
742 if (is_atomic(_OPC(6, cat6->opc))) {
743
744 src1.reg = (reg_t)(cat6->ldgb.src1);
745 src1.im = cat6->ldgb.src1_im;
746 src2.reg = (reg_t)(cat6->ldgb.src2);
747 src2.im = cat6->ldgb.src2_im;
748 dst.reg = (reg_t)(cat6->ldgb.dst);
749
750 print_src(ctx, &dst);
751 fprintf(ctx->out, ", ");
752 if (ss == 'g') {
753 struct reginfo src3;
754 memset(&src3, 0, sizeof(src3));
755
756 src3.reg = (reg_t)(cat6->ldgb.src3);
757 src3.full = true;
758
759 /* For images, the ".typed" variant is used and src2 is
760 * the ivecN coordinates, ie ivec2 for 2d.
761 *
762 * For SSBOs, the ".untyped" variant is used and src2 is
763 * a simple dword offset.. src3 appears to be
764 * uvec2(offset * 4, 0). Not sure the point of that.
765 */
766
767 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
768 print_src(ctx, &src1); /* value */
769 fprintf(ctx->out, ", ");
770 print_src(ctx, &src2); /* offset/coords */
771 fprintf(ctx->out, ", ");
772 print_src(ctx, &src3); /* 64b byte offset.. */
773
774 if (debug & PRINT_VERBOSE) {
775 fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0,
776 cat6->ldgb.pad3, cat6->ldgb.mustbe0);
777 }
778 } else { /* ss == 'l' */
779 fprintf(ctx->out, "l[");
780 print_src(ctx, &src1); /* simple byte offset */
781 fprintf(ctx->out, "], ");
782 print_src(ctx, &src2); /* value */
783
784 if (debug & PRINT_VERBOSE) {
785 fprintf(ctx->out, " (src3=%x, pad0=%x, pad3=%x, mustbe0=%x)",
786 cat6->ldgb.src3, cat6->ldgb.pad0,
787 cat6->ldgb.pad3, cat6->ldgb.mustbe0);
788 }
789 }
790
791 return;
792 } else if (_OPC(6, cat6->opc) == OPC_RESINFO) {
793 dst.reg = (reg_t)(cat6->ldgb.dst);
794
795 print_src(ctx, &dst);
796 fprintf(ctx->out, ", ");
797 fprintf(ctx->out, "g[%u]", cat6->ldgb.src_ssbo);
798
799 return;
800 } else if (_OPC(6, cat6->opc) == OPC_LDGB) {
801
802 src1.reg = (reg_t)(cat6->ldgb.src1);
803 src1.im = cat6->ldgb.src1_im;
804 src2.reg = (reg_t)(cat6->ldgb.src2);
805 src2.im = cat6->ldgb.src2_im;
806 dst.reg = (reg_t)(cat6->ldgb.dst);
807
808 print_src(ctx, &dst);
809 fprintf(ctx->out, ", ");
810 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
811 print_src(ctx, &src1);
812 fprintf(ctx->out, ", ");
813 print_src(ctx, &src2);
814
815 if (debug & PRINT_VERBOSE)
816 fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.pad3, cat6->ldgb.mustbe0);
817
818 return;
819 } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) {
820 struct reginfo src3;
821
822 memset(&src3, 0, sizeof(src3));
823 src1.reg = (reg_t)(cat6->a.src1);
824 src2.reg = (reg_t)(cat6->a.src2);
825 src2.im = cat6->a.src2_im;
826 src3.reg = (reg_t)(cat6->a.off);
827 src3.full = true;
828 dst.reg = (reg_t)(cat6->d.dst);
829
830 print_src(ctx, &dst);
831 fprintf(ctx->out, ", g[");
832 print_src(ctx, &src1);
833 fprintf(ctx->out, "+");
834 print_src(ctx, &src3);
835 fprintf(ctx->out, "], ");
836 print_src(ctx, &src2);
837
838 return;
839 }
840 if (cat6->dst_off) {
841 dst.reg = (reg_t)(cat6->c.dst);
842 dstoff = cat6->c.off;
843 } else {
844 dst.reg = (reg_t)(cat6->d.dst);
845 }
846
847 if (cat6->src_off) {
848 src1.reg = (reg_t)(cat6->a.src1);
849 src1.im = cat6->a.src1_im;
850 src2.reg = (reg_t)(cat6->a.src2);
851 src2.im = cat6->a.src2_im;
852 src1off = cat6->a.off;
853 } else {
854 src1.reg = (reg_t)(cat6->b.src1);
855 src1.im = cat6->b.src1_im;
856 src2.reg = (reg_t)(cat6->b.src2);
857 src2.im = cat6->b.src2_im;
858 }
859
860 if (!nodst) {
861 if (sd)
862 fprintf(ctx->out, "%c[", sd);
863 /* note: dst might actually be a src (ie. address to store to) */
864 print_src(ctx, &dst);
865 if (cat6->dst_off && cat6->g) {
866 struct reginfo dstoff_reg = {0};
867 dstoff_reg.reg = (reg_t) cat6->c.off;
868 dstoff_reg.full = true;
869 fprintf(ctx->out, "+");
870 print_src(ctx, &dstoff_reg);
871 } else if (dstoff)
872 fprintf(ctx->out, "%+d", dstoff);
873 if (sd)
874 fprintf(ctx->out, "]");
875 fprintf(ctx->out, ", ");
876 }
877
878 if (ss)
879 fprintf(ctx->out, "%c[", ss);
880
881 /* can have a larger than normal immed, so hack: */
882 if (src1.im) {
883 fprintf(ctx->out, "%u", src1.reg.dummy13);
884 } else {
885 print_src(ctx, &src1);
886 }
887
888 if (cat6->src_off && cat6->g)
889 print_src(ctx, &src2);
890 else if (src1off)
891 fprintf(ctx->out, "%+d", src1off);
892 if (ss)
893 fprintf(ctx->out, "]");
894
895 switch (_OPC(6, cat6->opc)) {
896 case OPC_RESINFO:
897 case OPC_RESFMT:
898 break;
899 default:
900 fprintf(ctx->out, ", ");
901 print_src(ctx, &src2);
902 break;
903 }
904 }
905
906 static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr)
907 {
908 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
909 struct reginfo src1, src2, ssbo;
910 bool uses_type = _OPC(6, cat6->opc) != OPC_LDC;
911
912 static const struct {
913 bool indirect;
914 bool bindless;
915 bool uniform;
916 } desc_features[8] = {
917 [CAT6_IMM] = { false },
918 [CAT6_BINDLESS_IMM] = { .bindless = true, },
919 [CAT6_BINDLESS_UNIFORM] = {
920 .bindless = true,
921 .indirect = true,
922 .uniform = true,
923 },
924 [CAT6_BINDLESS_NONUNIFORM] = {
925 .bindless = true,
926 .indirect = true,
927 },
928 };
929
930 bool indirect_ssbo = desc_features[cat6->desc_mode].indirect;
931 bool bindless = desc_features[cat6->desc_mode].bindless;
932 bool uniform = desc_features[cat6->desc_mode].uniform;
933 bool type_full = cat6->type != TYPE_U16;
934
935
936 memset(&src1, 0, sizeof(src1));
937 memset(&src2, 0, sizeof(src2));
938 memset(&ssbo, 0, sizeof(ssbo));
939
940 if (uses_type) {
941 fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped");
942 fprintf(ctx->out, ".%dd", cat6->d + 1);
943 fprintf(ctx->out, ".%s", type[cat6->type]);
944 } else {
945 fprintf(ctx->out, ".offset%d", cat6->d);
946 }
947 fprintf(ctx->out, ".%u", cat6->type_size + 1);
948
949 if (bindless)
950 fprintf(ctx->out, ".base%d", cat6->base);
951 if (uniform)
952 fprintf(ctx->out, ".uniform");
953 fprintf(ctx->out, " ");
954
955 src2.reg = (reg_t)(cat6->src2);
956 src2.full = type_full;
957 print_src(ctx, &src2);
958 fprintf(ctx->out, ", ");
959
960 src1.reg = (reg_t)(cat6->src1);
961 src1.full = true; // XXX
962 print_src(ctx, &src1);
963 fprintf(ctx->out, ", ");
964 ssbo.reg = (reg_t)(cat6->ssbo);
965 ssbo.im = !indirect_ssbo;
966 ssbo.full = true;
967 print_src(ctx, &ssbo);
968
969 if (debug & PRINT_VERBOSE) {
970 fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
971 cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5);
972 }
973 }
974
975 static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr)
976 {
977 if (!is_cat6_legacy(instr, ctx->gpu_id)) {
978 print_instr_cat6_a6xx(ctx, instr);
979 if (debug & PRINT_VERBOSE)
980 fprintf(ctx->out, " NEW");
981 } else {
982 print_instr_cat6_a3xx(ctx, instr);
983 if (debug & PRINT_VERBOSE)
984 fprintf(ctx->out, " LEGACY");
985 }
986 }
987 static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr)
988 {
989 instr_cat7_t *cat7 = &instr->cat7;
990
991 if (cat7->g)
992 fprintf(ctx->out, ".g");
993 if (cat7->l)
994 fprintf(ctx->out, ".l");
995
996 if (_OPC(7, cat7->opc) == OPC_FENCE) {
997 if (cat7->r)
998 fprintf(ctx->out, ".r");
999 if (cat7->w)
1000 fprintf(ctx->out, ".w");
1001 }
1002 }
1003
1004 /* size of largest OPC field of all the instruction categories: */
1005 #define NOPC_BITS 6
1006
1007 static const struct opc_info {
1008 uint16_t cat;
1009 uint16_t opc;
1010 const char *name;
1011 void (*print)(struct disasm_ctx *ctx, instr_t *instr);
1012 } opcs[1 << (3+NOPC_BITS)] = {
1013 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1014 /* category 0: */
1015 OPC(0, OPC_NOP, nop),
1016 OPC(0, OPC_BR, br),
1017 OPC(0, OPC_JUMP, jump),
1018 OPC(0, OPC_CALL, call),
1019 OPC(0, OPC_RET, ret),
1020 OPC(0, OPC_KILL, kill),
1021 OPC(0, OPC_END, end),
1022 OPC(0, OPC_EMIT, emit),
1023 OPC(0, OPC_CUT, cut),
1024 OPC(0, OPC_CHMASK, chmask),
1025 OPC(0, OPC_CHSH, chsh),
1026 OPC(0, OPC_FLOW_REV, flow_rev),
1027 OPC(0, OPC_IF, if),
1028 OPC(0, OPC_ELSE, else),
1029 OPC(0, OPC_ENDIF, endif),
1030
1031 /* category 1: */
1032 OPC(1, OPC_MOV, ),
1033
1034 /* category 2: */
1035 OPC(2, OPC_ADD_F, add.f),
1036 OPC(2, OPC_MIN_F, min.f),
1037 OPC(2, OPC_MAX_F, max.f),
1038 OPC(2, OPC_MUL_F, mul.f),
1039 OPC(2, OPC_SIGN_F, sign.f),
1040 OPC(2, OPC_CMPS_F, cmps.f),
1041 OPC(2, OPC_ABSNEG_F, absneg.f),
1042 OPC(2, OPC_CMPV_F, cmpv.f),
1043 OPC(2, OPC_FLOOR_F, floor.f),
1044 OPC(2, OPC_CEIL_F, ceil.f),
1045 OPC(2, OPC_RNDNE_F, rndne.f),
1046 OPC(2, OPC_RNDAZ_F, rndaz.f),
1047 OPC(2, OPC_TRUNC_F, trunc.f),
1048 OPC(2, OPC_ADD_U, add.u),
1049 OPC(2, OPC_ADD_S, add.s),
1050 OPC(2, OPC_SUB_U, sub.u),
1051 OPC(2, OPC_SUB_S, sub.s),
1052 OPC(2, OPC_CMPS_U, cmps.u),
1053 OPC(2, OPC_CMPS_S, cmps.s),
1054 OPC(2, OPC_MIN_U, min.u),
1055 OPC(2, OPC_MIN_S, min.s),
1056 OPC(2, OPC_MAX_U, max.u),
1057 OPC(2, OPC_MAX_S, max.s),
1058 OPC(2, OPC_ABSNEG_S, absneg.s),
1059 OPC(2, OPC_AND_B, and.b),
1060 OPC(2, OPC_OR_B, or.b),
1061 OPC(2, OPC_NOT_B, not.b),
1062 OPC(2, OPC_XOR_B, xor.b),
1063 OPC(2, OPC_CMPV_U, cmpv.u),
1064 OPC(2, OPC_CMPV_S, cmpv.s),
1065 OPC(2, OPC_MUL_U24, mul.u24),
1066 OPC(2, OPC_MUL_S24, mul.s24),
1067 OPC(2, OPC_MULL_U, mull.u),
1068 OPC(2, OPC_BFREV_B, bfrev.b),
1069 OPC(2, OPC_CLZ_S, clz.s),
1070 OPC(2, OPC_CLZ_B, clz.b),
1071 OPC(2, OPC_SHL_B, shl.b),
1072 OPC(2, OPC_SHR_B, shr.b),
1073 OPC(2, OPC_ASHR_B, ashr.b),
1074 OPC(2, OPC_BARY_F, bary.f),
1075 OPC(2, OPC_MGEN_B, mgen.b),
1076 OPC(2, OPC_GETBIT_B, getbit.b),
1077 OPC(2, OPC_SETRM, setrm),
1078 OPC(2, OPC_CBITS_B, cbits.b),
1079 OPC(2, OPC_SHB, shb),
1080 OPC(2, OPC_MSAD, msad),
1081
1082 /* category 3: */
1083 OPC(3, OPC_MAD_U16, mad.u16),
1084 OPC(3, OPC_MADSH_U16, madsh.u16),
1085 OPC(3, OPC_MAD_S16, mad.s16),
1086 OPC(3, OPC_MADSH_M16, madsh.m16),
1087 OPC(3, OPC_MAD_U24, mad.u24),
1088 OPC(3, OPC_MAD_S24, mad.s24),
1089 OPC(3, OPC_MAD_F16, mad.f16),
1090 OPC(3, OPC_MAD_F32, mad.f32),
1091 OPC(3, OPC_SEL_B16, sel.b16),
1092 OPC(3, OPC_SEL_B32, sel.b32),
1093 OPC(3, OPC_SEL_S16, sel.s16),
1094 OPC(3, OPC_SEL_S32, sel.s32),
1095 OPC(3, OPC_SEL_F16, sel.f16),
1096 OPC(3, OPC_SEL_F32, sel.f32),
1097 OPC(3, OPC_SAD_S16, sad.s16),
1098 OPC(3, OPC_SAD_S32, sad.s32),
1099
1100 /* category 4: */
1101 OPC(4, OPC_RCP, rcp),
1102 OPC(4, OPC_RSQ, rsq),
1103 OPC(4, OPC_LOG2, log2),
1104 OPC(4, OPC_EXP2, exp2),
1105 OPC(4, OPC_SIN, sin),
1106 OPC(4, OPC_COS, cos),
1107 OPC(4, OPC_SQRT, sqrt),
1108 OPC(4, OPC_HRSQ, hrsq),
1109 OPC(4, OPC_HLOG2, hlog2),
1110 OPC(4, OPC_HEXP2, hexp2),
1111
1112 /* category 5: */
1113 OPC(5, OPC_ISAM, isam),
1114 OPC(5, OPC_ISAML, isaml),
1115 OPC(5, OPC_ISAMM, isamm),
1116 OPC(5, OPC_SAM, sam),
1117 OPC(5, OPC_SAMB, samb),
1118 OPC(5, OPC_SAML, saml),
1119 OPC(5, OPC_SAMGQ, samgq),
1120 OPC(5, OPC_GETLOD, getlod),
1121 OPC(5, OPC_CONV, conv),
1122 OPC(5, OPC_CONVM, convm),
1123 OPC(5, OPC_GETSIZE, getsize),
1124 OPC(5, OPC_GETBUF, getbuf),
1125 OPC(5, OPC_GETPOS, getpos),
1126 OPC(5, OPC_GETINFO, getinfo),
1127 OPC(5, OPC_DSX, dsx),
1128 OPC(5, OPC_DSY, dsy),
1129 OPC(5, OPC_GATHER4R, gather4r),
1130 OPC(5, OPC_GATHER4G, gather4g),
1131 OPC(5, OPC_GATHER4B, gather4b),
1132 OPC(5, OPC_GATHER4A, gather4a),
1133 OPC(5, OPC_SAMGP0, samgp0),
1134 OPC(5, OPC_SAMGP1, samgp1),
1135 OPC(5, OPC_SAMGP2, samgp2),
1136 OPC(5, OPC_SAMGP3, samgp3),
1137 OPC(5, OPC_DSXPP_1, dsxpp.1),
1138 OPC(5, OPC_DSYPP_1, dsypp.1),
1139 OPC(5, OPC_RGETPOS, rgetpos),
1140 OPC(5, OPC_RGETINFO, rgetinfo),
1141
1142
1143 /* category 6: */
1144 OPC(6, OPC_LDG, ldg),
1145 OPC(6, OPC_LDL, ldl),
1146 OPC(6, OPC_LDP, ldp),
1147 OPC(6, OPC_STG, stg),
1148 OPC(6, OPC_STL, stl),
1149 OPC(6, OPC_STP, stp),
1150 OPC(6, OPC_LDIB, ldib),
1151 OPC(6, OPC_G2L, g2l),
1152 OPC(6, OPC_L2G, l2g),
1153 OPC(6, OPC_PREFETCH, prefetch),
1154 OPC(6, OPC_LDLW, ldlw),
1155 OPC(6, OPC_STLW, stlw),
1156 OPC(6, OPC_RESFMT, resfmt),
1157 OPC(6, OPC_RESINFO, resinfo),
1158 OPC(6, OPC_ATOMIC_ADD, atomic.add),
1159 OPC(6, OPC_ATOMIC_SUB, atomic.sub),
1160 OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
1161 OPC(6, OPC_ATOMIC_INC, atomic.inc),
1162 OPC(6, OPC_ATOMIC_DEC, atomic.dec),
1163 OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
1164 OPC(6, OPC_ATOMIC_MIN, atomic.min),
1165 OPC(6, OPC_ATOMIC_MAX, atomic.max),
1166 OPC(6, OPC_ATOMIC_AND, atomic.and),
1167 OPC(6, OPC_ATOMIC_OR, atomic.or),
1168 OPC(6, OPC_ATOMIC_XOR, atomic.xor),
1169 OPC(6, OPC_LDGB, ldgb),
1170 OPC(6, OPC_STGB, stgb),
1171 OPC(6, OPC_STIB, stib),
1172 OPC(6, OPC_LDC, ldc),
1173 OPC(6, OPC_LDLV, ldlv),
1174
1175 OPC(7, OPC_BAR, bar),
1176 OPC(7, OPC_FENCE, fence),
1177
1178 #undef OPC
1179 };
1180
1181 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1182
1183 // XXX hack.. probably should move this table somewhere common:
1184 #include "ir3.h"
1185 const char *ir3_instr_name(struct ir3_instruction *instr)
1186 {
1187 if (opc_cat(instr->opc) == -1) return "??meta??";
1188 return opcs[instr->opc].name;
1189 }
1190
1191 static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
1192 {
1193 const char *name = GETINFO(instr)->name;
1194 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1195
1196 if (name) {
1197 fprintf(ctx->out, "%s", name);
1198 GETINFO(instr)->print(ctx, instr);
1199 } else {
1200 fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
1201
1202 switch (instr->opc_cat) {
1203 case 0: print_instr_cat0(ctx, instr); break;
1204 case 1: print_instr_cat1(ctx, instr); break;
1205 case 2: print_instr_cat2(ctx, instr); break;
1206 case 3: print_instr_cat3(ctx, instr); break;
1207 case 4: print_instr_cat4(ctx, instr); break;
1208 case 5: print_instr_cat5(ctx, instr); break;
1209 case 6: print_instr_cat6(ctx, instr); break;
1210 case 7: print_instr_cat7(ctx, instr); break;
1211 }
1212 }
1213 }
1214
1215 static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
1216 {
1217 instr_t *instr = (instr_t *)dwords;
1218 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1219 unsigned nop = 0;
1220 unsigned cycles = ctx->instructions;
1221
1222 if (debug & PRINT_VERBOSE) {
1223 fprintf(ctx->out, "%s%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
1224 n, cycles++, dwords[1], dwords[0]);
1225 }
1226
1227 /* NOTE: order flags are printed is a bit fugly.. but for now I
1228 * try to match the order in llvm-a3xx disassembler for easy
1229 * diff'ing..
1230 */
1231
1232 ctx->repeat = instr_repeat(instr);
1233 ctx->instructions += 1 + ctx->repeat;
1234
1235 if (instr->sync) {
1236 fprintf(ctx->out, "(sy)");
1237 }
1238 if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
1239 fprintf(ctx->out, "(ss)");
1240 }
1241 if (instr->jmp_tgt)
1242 fprintf(ctx->out, "(jp)");
1243 if (instr_sat(instr))
1244 fprintf(ctx->out, "(sat)");
1245 if (ctx->repeat)
1246 fprintf(ctx->out, "(rpt%d)", ctx->repeat);
1247 else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
1248 nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
1249 else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
1250 nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
1251 ctx->instructions += nop;
1252 if (nop)
1253 fprintf(ctx->out, "(nop%d) ", nop);
1254
1255 if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
1256 fprintf(ctx->out, "(ul)");
1257
1258 print_single_instr(ctx, instr);
1259 fprintf(ctx->out, "\n");
1260
1261 if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
1262 int i;
1263 for (i = 0; i < nop; i++) {
1264 if (debug & PRINT_VERBOSE) {
1265 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1266 levels[ctx->level], n, cycles++);
1267 }
1268 fprintf(ctx->out, "nop\n");
1269 }
1270 for (i = 0; i < ctx->repeat; i++) {
1271 ctx->repeatidx = i + 1;
1272 if (debug & PRINT_VERBOSE) {
1273 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1274 levels[ctx->level], n, cycles++);
1275 }
1276 print_single_instr(ctx, instr);
1277 fprintf(ctx->out, "\n");
1278 }
1279 ctx->repeatidx = 0;
1280 }
1281
1282 return (instr->opc_cat == 0) && (opc == OPC_END);
1283 }
1284
1285 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
1286 {
1287 struct disasm_ctx ctx;
1288 int i;
1289 int nop_count = 0;
1290
1291 assert((sizedwords % 2) == 0);
1292
1293 memset(&ctx, 0, sizeof(ctx));
1294 ctx.out = out;
1295 ctx.level = level;
1296 ctx.gpu_id = gpu_id;
1297
1298 for (i = 0; i < sizedwords; i += 2) {
1299 print_instr(&ctx, &dwords[i], i/2);
1300 if (dwords[i] == 0 && dwords[i + 1] == 0)
1301 nop_count++;
1302 else
1303 nop_count = 0;
1304 if (nop_count > 3)
1305 break;
1306 }
1307
1308 return 0;
1309 }