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freedreno/ir3: add generic get_barycentric()
[mesa.git] / src / freedreno / ir3 / instr-a3xx.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef INSTR_A3XX_H_
25 #define INSTR_A3XX_H_
26
27 #define PACKED __attribute__((__packed__))
28
29 #include <stdint.h>
30 #include <stdio.h>
31 #include <stdbool.h>
32 #include <assert.h>
33
34 /* size of largest OPC field of all the instruction categories: */
35 #define NOPC_BITS 6
36
37 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc)
38
39 typedef enum {
40 /* category 0: */
41 OPC_NOP = _OPC(0, 0),
42 OPC_B = _OPC(0, 1),
43 OPC_JUMP = _OPC(0, 2),
44 OPC_CALL = _OPC(0, 3),
45 OPC_RET = _OPC(0, 4),
46 OPC_KILL = _OPC(0, 5),
47 OPC_END = _OPC(0, 6),
48 OPC_EMIT = _OPC(0, 7),
49 OPC_CUT = _OPC(0, 8),
50 OPC_CHMASK = _OPC(0, 9),
51 OPC_CHSH = _OPC(0, 10),
52 OPC_FLOW_REV = _OPC(0, 11),
53
54 OPC_BKT = _OPC(0, 16),
55 OPC_STKS = _OPC(0, 17),
56 OPC_STKR = _OPC(0, 18),
57 OPC_XSET = _OPC(0, 19),
58 OPC_XCLR = _OPC(0, 20),
59 OPC_GETONE = _OPC(0, 21),
60 OPC_DBG = _OPC(0, 22),
61 OPC_SHPS = _OPC(0, 23), /* shader prologue start */
62 OPC_SHPE = _OPC(0, 24), /* shader prologue end */
63
64 OPC_PREDT = _OPC(0, 29), /* predicated true */
65 OPC_PREDF = _OPC(0, 30), /* predicated false */
66 OPC_PREDE = _OPC(0, 31), /* predicated end */
67
68 /* category 1: */
69 OPC_MOV = _OPC(1, 0),
70
71 /* category 2: */
72 OPC_ADD_F = _OPC(2, 0),
73 OPC_MIN_F = _OPC(2, 1),
74 OPC_MAX_F = _OPC(2, 2),
75 OPC_MUL_F = _OPC(2, 3),
76 OPC_SIGN_F = _OPC(2, 4),
77 OPC_CMPS_F = _OPC(2, 5),
78 OPC_ABSNEG_F = _OPC(2, 6),
79 OPC_CMPV_F = _OPC(2, 7),
80 /* 8 - invalid */
81 OPC_FLOOR_F = _OPC(2, 9),
82 OPC_CEIL_F = _OPC(2, 10),
83 OPC_RNDNE_F = _OPC(2, 11),
84 OPC_RNDAZ_F = _OPC(2, 12),
85 OPC_TRUNC_F = _OPC(2, 13),
86 /* 14-15 - invalid */
87 OPC_ADD_U = _OPC(2, 16),
88 OPC_ADD_S = _OPC(2, 17),
89 OPC_SUB_U = _OPC(2, 18),
90 OPC_SUB_S = _OPC(2, 19),
91 OPC_CMPS_U = _OPC(2, 20),
92 OPC_CMPS_S = _OPC(2, 21),
93 OPC_MIN_U = _OPC(2, 22),
94 OPC_MIN_S = _OPC(2, 23),
95 OPC_MAX_U = _OPC(2, 24),
96 OPC_MAX_S = _OPC(2, 25),
97 OPC_ABSNEG_S = _OPC(2, 26),
98 /* 27 - invalid */
99 OPC_AND_B = _OPC(2, 28),
100 OPC_OR_B = _OPC(2, 29),
101 OPC_NOT_B = _OPC(2, 30),
102 OPC_XOR_B = _OPC(2, 31),
103 /* 32 - invalid */
104 OPC_CMPV_U = _OPC(2, 33),
105 OPC_CMPV_S = _OPC(2, 34),
106 /* 35-47 - invalid */
107 OPC_MUL_U24 = _OPC(2, 48), /* 24b mul into 32b result */
108 OPC_MUL_S24 = _OPC(2, 49), /* 24b mul into 32b result with sign extension */
109 OPC_MULL_U = _OPC(2, 50),
110 OPC_BFREV_B = _OPC(2, 51),
111 OPC_CLZ_S = _OPC(2, 52),
112 OPC_CLZ_B = _OPC(2, 53),
113 OPC_SHL_B = _OPC(2, 54),
114 OPC_SHR_B = _OPC(2, 55),
115 OPC_ASHR_B = _OPC(2, 56),
116 OPC_BARY_F = _OPC(2, 57),
117 OPC_MGEN_B = _OPC(2, 58),
118 OPC_GETBIT_B = _OPC(2, 59),
119 OPC_SETRM = _OPC(2, 60),
120 OPC_CBITS_B = _OPC(2, 61),
121 OPC_SHB = _OPC(2, 62),
122 OPC_MSAD = _OPC(2, 63),
123
124 /* category 3: */
125 OPC_MAD_U16 = _OPC(3, 0),
126 OPC_MADSH_U16 = _OPC(3, 1),
127 OPC_MAD_S16 = _OPC(3, 2),
128 OPC_MADSH_M16 = _OPC(3, 3), /* should this be .s16? */
129 OPC_MAD_U24 = _OPC(3, 4),
130 OPC_MAD_S24 = _OPC(3, 5),
131 OPC_MAD_F16 = _OPC(3, 6),
132 OPC_MAD_F32 = _OPC(3, 7),
133 OPC_SEL_B16 = _OPC(3, 8),
134 OPC_SEL_B32 = _OPC(3, 9),
135 OPC_SEL_S16 = _OPC(3, 10),
136 OPC_SEL_S32 = _OPC(3, 11),
137 OPC_SEL_F16 = _OPC(3, 12),
138 OPC_SEL_F32 = _OPC(3, 13),
139 OPC_SAD_S16 = _OPC(3, 14),
140 OPC_SAD_S32 = _OPC(3, 15),
141
142 /* category 4: */
143 OPC_RCP = _OPC(4, 0),
144 OPC_RSQ = _OPC(4, 1),
145 OPC_LOG2 = _OPC(4, 2),
146 OPC_EXP2 = _OPC(4, 3),
147 OPC_SIN = _OPC(4, 4),
148 OPC_COS = _OPC(4, 5),
149 OPC_SQRT = _OPC(4, 6),
150 /* NOTE that these are 8+opc from their highp equivs, so it's possible
151 * that the high order bit in the opc field has been repurposed for
152 * half-precision use? But note that other ops (rcp/lsin/cos/sqrt)
153 * still use the same opc as highp
154 */
155 OPC_HRSQ = _OPC(4, 9),
156 OPC_HLOG2 = _OPC(4, 10),
157 OPC_HEXP2 = _OPC(4, 11),
158
159 /* category 5: */
160 OPC_ISAM = _OPC(5, 0),
161 OPC_ISAML = _OPC(5, 1),
162 OPC_ISAMM = _OPC(5, 2),
163 OPC_SAM = _OPC(5, 3),
164 OPC_SAMB = _OPC(5, 4),
165 OPC_SAML = _OPC(5, 5),
166 OPC_SAMGQ = _OPC(5, 6),
167 OPC_GETLOD = _OPC(5, 7),
168 OPC_CONV = _OPC(5, 8),
169 OPC_CONVM = _OPC(5, 9),
170 OPC_GETSIZE = _OPC(5, 10),
171 OPC_GETBUF = _OPC(5, 11),
172 OPC_GETPOS = _OPC(5, 12),
173 OPC_GETINFO = _OPC(5, 13),
174 OPC_DSX = _OPC(5, 14),
175 OPC_DSY = _OPC(5, 15),
176 OPC_GATHER4R = _OPC(5, 16),
177 OPC_GATHER4G = _OPC(5, 17),
178 OPC_GATHER4B = _OPC(5, 18),
179 OPC_GATHER4A = _OPC(5, 19),
180 OPC_SAMGP0 = _OPC(5, 20),
181 OPC_SAMGP1 = _OPC(5, 21),
182 OPC_SAMGP2 = _OPC(5, 22),
183 OPC_SAMGP3 = _OPC(5, 23),
184 OPC_DSXPP_1 = _OPC(5, 24),
185 OPC_DSYPP_1 = _OPC(5, 25),
186 OPC_RGETPOS = _OPC(5, 26),
187 OPC_RGETINFO = _OPC(5, 27),
188
189 /* category 6: */
190 OPC_LDG = _OPC(6, 0), /* load-global */
191 OPC_LDL = _OPC(6, 1),
192 OPC_LDP = _OPC(6, 2),
193 OPC_STG = _OPC(6, 3), /* store-global */
194 OPC_STL = _OPC(6, 4),
195 OPC_STP = _OPC(6, 5),
196 OPC_LDIB = _OPC(6, 6),
197 OPC_G2L = _OPC(6, 7),
198 OPC_L2G = _OPC(6, 8),
199 OPC_PREFETCH = _OPC(6, 9),
200 OPC_LDLW = _OPC(6, 10),
201 OPC_STLW = _OPC(6, 11),
202 OPC_RESFMT = _OPC(6, 14),
203 OPC_RESINFO = _OPC(6, 15),
204 OPC_ATOMIC_ADD = _OPC(6, 16),
205 OPC_ATOMIC_SUB = _OPC(6, 17),
206 OPC_ATOMIC_XCHG = _OPC(6, 18),
207 OPC_ATOMIC_INC = _OPC(6, 19),
208 OPC_ATOMIC_DEC = _OPC(6, 20),
209 OPC_ATOMIC_CMPXCHG = _OPC(6, 21),
210 OPC_ATOMIC_MIN = _OPC(6, 22),
211 OPC_ATOMIC_MAX = _OPC(6, 23),
212 OPC_ATOMIC_AND = _OPC(6, 24),
213 OPC_ATOMIC_OR = _OPC(6, 25),
214 OPC_ATOMIC_XOR = _OPC(6, 26),
215 OPC_LDGB = _OPC(6, 27),
216 OPC_STGB = _OPC(6, 28),
217 OPC_STIB = _OPC(6, 29),
218 OPC_LDC = _OPC(6, 30),
219 OPC_LDLV = _OPC(6, 31),
220
221 /* category 7: */
222 OPC_BAR = _OPC(7, 0),
223 OPC_FENCE = _OPC(7, 1),
224
225 /* meta instructions (category -1): */
226 /* placeholder instr to mark shader inputs: */
227 OPC_META_INPUT = _OPC(-1, 0),
228 /* The "collect" and "split" instructions are used for keeping
229 * track of instructions that write to multiple dst registers
230 * (split) like texture sample instructions, or read multiple
231 * consecutive scalar registers (collect) (bary.f, texture samp)
232 *
233 * A "split" extracts a scalar component from a vecN, and a
234 * "collect" gathers multiple scalar components into a vecN
235 */
236 OPC_META_SPLIT = _OPC(-1, 2),
237 OPC_META_COLLECT = _OPC(-1, 3),
238
239 /* placeholder for texture fetches that run before FS invocation
240 * starts:
241 */
242 OPC_META_TEX_PREFETCH = _OPC(-1, 4),
243
244 } opc_t;
245
246 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS))
247 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1)))
248
249 typedef enum {
250 TYPE_F16 = 0,
251 TYPE_F32 = 1,
252 TYPE_U16 = 2,
253 TYPE_U32 = 3,
254 TYPE_S16 = 4,
255 TYPE_S32 = 5,
256 TYPE_U8 = 6,
257 TYPE_S8 = 7, // XXX I assume?
258 } type_t;
259
260 static inline uint32_t type_size(type_t type)
261 {
262 switch (type) {
263 case TYPE_F32:
264 case TYPE_U32:
265 case TYPE_S32:
266 return 32;
267 case TYPE_F16:
268 case TYPE_U16:
269 case TYPE_S16:
270 return 16;
271 case TYPE_U8:
272 case TYPE_S8:
273 return 8;
274 default:
275 assert(0); /* invalid type */
276 return 0;
277 }
278 }
279
280 static inline int type_float(type_t type)
281 {
282 return (type == TYPE_F32) || (type == TYPE_F16);
283 }
284
285 static inline int type_uint(type_t type)
286 {
287 return (type == TYPE_U32) || (type == TYPE_U16) || (type == TYPE_U8);
288 }
289
290 static inline int type_sint(type_t type)
291 {
292 return (type == TYPE_S32) || (type == TYPE_S16) || (type == TYPE_S8);
293 }
294
295 typedef union PACKED {
296 /* normal gpr or const src register: */
297 struct PACKED {
298 uint32_t comp : 2;
299 uint32_t num : 10;
300 };
301 /* for immediate val: */
302 int32_t iim_val : 11;
303 /* to make compiler happy: */
304 uint32_t dummy32;
305 uint32_t dummy10 : 10;
306 int32_t idummy10 : 10;
307 uint32_t dummy11 : 11;
308 uint32_t dummy12 : 12;
309 uint32_t dummy13 : 13;
310 uint32_t dummy8 : 8;
311 int32_t idummy13 : 13;
312 int32_t idummy8 : 8;
313 } reg_t;
314
315 /* special registers: */
316 #define REG_A0 61 /* address register */
317 #define REG_P0 62 /* predicate register */
318
319 static inline int reg_special(reg_t reg)
320 {
321 return (reg.num == REG_A0) || (reg.num == REG_P0);
322 }
323
324 typedef enum {
325 BRANCH_PLAIN = 0, /* br */
326 BRANCH_OR = 1, /* brao */
327 BRANCH_AND = 2, /* braa */
328 BRANCH_CONST = 3, /* brac */
329 BRANCH_ANY = 4, /* bany */
330 BRANCH_ALL = 5, /* ball */
331 BRANCH_X = 6, /* brax ??? */
332 } brtype_t;
333
334 typedef struct PACKED {
335 /* dword0: */
336 union PACKED {
337 struct PACKED {
338 int16_t immed : 16;
339 uint32_t dummy1 : 16;
340 } a3xx;
341 struct PACKED {
342 int32_t immed : 20;
343 uint32_t dummy1 : 12;
344 } a4xx;
345 struct PACKED {
346 int32_t immed : 32;
347 } a5xx;
348 };
349
350 /* dword1: */
351 uint32_t idx : 5; /* brac.N index */
352 uint32_t brtype : 3; /* branch type, see brtype_t */
353 uint32_t repeat : 3;
354 uint32_t dummy3 : 1;
355 uint32_t ss : 1;
356 uint32_t inv1 : 1;
357 uint32_t comp1 : 2;
358 uint32_t eq : 1;
359 uint32_t opc_hi : 1; /* at least one bit */
360 uint32_t dummy4 : 2;
361 uint32_t inv0 : 1;
362 uint32_t comp0 : 2; /* component for first src */
363 uint32_t opc : 4;
364 uint32_t jmp_tgt : 1;
365 uint32_t sync : 1;
366 uint32_t opc_cat : 3;
367 } instr_cat0_t;
368
369 typedef struct PACKED {
370 /* dword0: */
371 union PACKED {
372 /* for normal src register: */
373 struct PACKED {
374 uint32_t src : 11;
375 /* at least low bit of pad must be zero or it will
376 * look like a address relative src
377 */
378 uint32_t pad : 21;
379 };
380 /* for address relative: */
381 struct PACKED {
382 int32_t off : 10;
383 uint32_t src_rel_c : 1;
384 uint32_t src_rel : 1;
385 uint32_t unknown : 20;
386 };
387 /* for immediate: */
388 int32_t iim_val;
389 uint32_t uim_val;
390 float fim_val;
391 };
392
393 /* dword1: */
394 uint32_t dst : 8;
395 uint32_t repeat : 3;
396 uint32_t src_r : 1;
397 uint32_t ss : 1;
398 uint32_t ul : 1;
399 uint32_t dst_type : 3;
400 uint32_t dst_rel : 1;
401 uint32_t src_type : 3;
402 uint32_t src_c : 1;
403 uint32_t src_im : 1;
404 uint32_t even : 1;
405 uint32_t pos_inf : 1;
406 uint32_t must_be_0 : 2;
407 uint32_t jmp_tgt : 1;
408 uint32_t sync : 1;
409 uint32_t opc_cat : 3;
410 } instr_cat1_t;
411
412 typedef struct PACKED {
413 /* dword0: */
414 union PACKED {
415 struct PACKED {
416 uint32_t src1 : 11;
417 uint32_t must_be_zero1: 2;
418 uint32_t src1_im : 1; /* immediate */
419 uint32_t src1_neg : 1; /* negate */
420 uint32_t src1_abs : 1; /* absolute value */
421 };
422 struct PACKED {
423 uint32_t src1 : 10;
424 uint32_t src1_c : 1; /* relative-const */
425 uint32_t src1_rel : 1; /* relative address */
426 uint32_t must_be_zero : 1;
427 uint32_t dummy : 3;
428 } rel1;
429 struct PACKED {
430 uint32_t src1 : 12;
431 uint32_t src1_c : 1; /* const */
432 uint32_t dummy : 3;
433 } c1;
434 };
435
436 union PACKED {
437 struct PACKED {
438 uint32_t src2 : 11;
439 uint32_t must_be_zero2: 2;
440 uint32_t src2_im : 1; /* immediate */
441 uint32_t src2_neg : 1; /* negate */
442 uint32_t src2_abs : 1; /* absolute value */
443 };
444 struct PACKED {
445 uint32_t src2 : 10;
446 uint32_t src2_c : 1; /* relative-const */
447 uint32_t src2_rel : 1; /* relative address */
448 uint32_t must_be_zero : 1;
449 uint32_t dummy : 3;
450 } rel2;
451 struct PACKED {
452 uint32_t src2 : 12;
453 uint32_t src2_c : 1; /* const */
454 uint32_t dummy : 3;
455 } c2;
456 };
457
458 /* dword1: */
459 uint32_t dst : 8;
460 uint32_t repeat : 2;
461 uint32_t sat : 1;
462 uint32_t src1_r : 1; /* doubles as nop0 if repeat==0 */
463 uint32_t ss : 1;
464 uint32_t ul : 1; /* dunno */
465 uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */
466 uint32_t ei : 1;
467 uint32_t cond : 3;
468 uint32_t src2_r : 1; /* doubles as nop1 if repeat==0 */
469 uint32_t full : 1; /* not half */
470 uint32_t opc : 6;
471 uint32_t jmp_tgt : 1;
472 uint32_t sync : 1;
473 uint32_t opc_cat : 3;
474 } instr_cat2_t;
475
476 typedef struct PACKED {
477 /* dword0: */
478 union PACKED {
479 struct PACKED {
480 uint32_t src1 : 11;
481 uint32_t must_be_zero1: 2;
482 uint32_t src2_c : 1;
483 uint32_t src1_neg : 1;
484 uint32_t src2_r : 1; /* doubles as nop1 if repeat==0 */
485 };
486 struct PACKED {
487 uint32_t src1 : 10;
488 uint32_t src1_c : 1;
489 uint32_t src1_rel : 1;
490 uint32_t must_be_zero : 1;
491 uint32_t dummy : 3;
492 } rel1;
493 struct PACKED {
494 uint32_t src1 : 12;
495 uint32_t src1_c : 1;
496 uint32_t dummy : 3;
497 } c1;
498 };
499
500 union PACKED {
501 struct PACKED {
502 uint32_t src3 : 11;
503 uint32_t must_be_zero2: 2;
504 uint32_t src3_r : 1;
505 uint32_t src2_neg : 1;
506 uint32_t src3_neg : 1;
507 };
508 struct PACKED {
509 uint32_t src3 : 10;
510 uint32_t src3_c : 1;
511 uint32_t src3_rel : 1;
512 uint32_t must_be_zero : 1;
513 uint32_t dummy : 3;
514 } rel2;
515 struct PACKED {
516 uint32_t src3 : 12;
517 uint32_t src3_c : 1;
518 uint32_t dummy : 3;
519 } c2;
520 };
521
522 /* dword1: */
523 uint32_t dst : 8;
524 uint32_t repeat : 2;
525 uint32_t sat : 1;
526 uint32_t src1_r : 1; /* doubles as nop0 if repeat==0 */
527 uint32_t ss : 1;
528 uint32_t ul : 1;
529 uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */
530 uint32_t src2 : 8;
531 uint32_t opc : 4;
532 uint32_t jmp_tgt : 1;
533 uint32_t sync : 1;
534 uint32_t opc_cat : 3;
535 } instr_cat3_t;
536
537 static inline bool instr_cat3_full(instr_cat3_t *cat3)
538 {
539 switch (_OPC(3, cat3->opc)) {
540 case OPC_MAD_F16:
541 case OPC_MAD_U16:
542 case OPC_MAD_S16:
543 case OPC_SEL_B16:
544 case OPC_SEL_S16:
545 case OPC_SEL_F16:
546 case OPC_SAD_S16:
547 case OPC_SAD_S32: // really??
548 return false;
549 default:
550 return true;
551 }
552 }
553
554 typedef struct PACKED {
555 /* dword0: */
556 union PACKED {
557 struct PACKED {
558 uint32_t src : 11;
559 uint32_t must_be_zero1: 2;
560 uint32_t src_im : 1; /* immediate */
561 uint32_t src_neg : 1; /* negate */
562 uint32_t src_abs : 1; /* absolute value */
563 };
564 struct PACKED {
565 uint32_t src : 10;
566 uint32_t src_c : 1; /* relative-const */
567 uint32_t src_rel : 1; /* relative address */
568 uint32_t must_be_zero : 1;
569 uint32_t dummy : 3;
570 } rel;
571 struct PACKED {
572 uint32_t src : 12;
573 uint32_t src_c : 1; /* const */
574 uint32_t dummy : 3;
575 } c;
576 };
577 uint32_t dummy1 : 16; /* seem to be ignored */
578
579 /* dword1: */
580 uint32_t dst : 8;
581 uint32_t repeat : 2;
582 uint32_t sat : 1;
583 uint32_t src_r : 1;
584 uint32_t ss : 1;
585 uint32_t ul : 1;
586 uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */
587 uint32_t dummy2 : 5; /* seem to be ignored */
588 uint32_t full : 1; /* not half */
589 uint32_t opc : 6;
590 uint32_t jmp_tgt : 1;
591 uint32_t sync : 1;
592 uint32_t opc_cat : 3;
593 } instr_cat4_t;
594
595 /* With is_bindless_s2en = 1, this determines whether bindless is enabled and
596 * if so, how to get the (base, index) pair for both sampler and texture.
597 * There is a single base embedded in the instruction, which is always used
598 * for the texture.
599 */
600 typedef enum {
601 /* Use traditional GL binding model, get texture and sampler index
602 * from src3 which is not presumed to be uniform. This is
603 * backwards-compatible with earlier generations, where this field was
604 * always 0 and nonuniform-indexed sampling always worked.
605 */
606 CAT5_NONUNIFORM = 0,
607
608 /* The sampler base comes from the low 3 bits of a1.x, and the sampler
609 * and texture index come from src3 which is presumed to be uniform.
610 */
611 CAT5_BINDLESS_A1_UNIFORM = 1,
612
613 /* The texture and sampler share the same base, and the sampler and
614 * texture index come from src3 which is *not* presumed to be uniform.
615 */
616 CAT5_BINDLESS_NONUNIFORM = 2,
617
618 /* The sampler base comes from the low 3 bits of a1.x, and the sampler
619 * and texture index come from src3 which is *not* presumed to be
620 * uniform.
621 */
622 CAT5_BINDLESS_A1_NONUNIFORM = 3,
623
624 /* Use traditional GL binding model, get texture and sampler index
625 * from src3 which is presumed to be uniform.
626 */
627 CAT5_UNIFORM = 4,
628
629 /* The texture and sampler share the same base, and the sampler and
630 * texture index come from src3 which is presumed to be uniform.
631 */
632 CAT5_BINDLESS_UNIFORM = 5,
633
634 /* The texture and sampler share the same base, get sampler index from low
635 * 4 bits of src3 and texture index from high 4 bits.
636 */
637 CAT5_BINDLESS_IMM = 6,
638
639 /* The sampler base comes from the low 3 bits of a1.x, and the texture
640 * index comes from the next 8 bits of a1.x. The sampler index is an
641 * immediate in src3.
642 */
643 CAT5_BINDLESS_A1_IMM = 7,
644 } cat5_desc_mode_t;
645
646 typedef struct PACKED {
647 /* dword0: */
648 union PACKED {
649 /* normal case: */
650 struct PACKED {
651 uint32_t full : 1; /* not half */
652 uint32_t src1 : 8;
653 uint32_t src2 : 8;
654 uint32_t dummy1 : 4; /* seem to be ignored */
655 uint32_t samp : 4;
656 uint32_t tex : 7;
657 } norm;
658 /* s2en case: */
659 struct PACKED {
660 uint32_t full : 1; /* not half */
661 uint32_t src1 : 8;
662 uint32_t src2 : 8;
663 uint32_t dummy1 : 2;
664 uint32_t base_hi : 2;
665 uint32_t src3 : 8;
666 uint32_t desc_mode : 3;
667 } s2en_bindless;
668 /* same in either case: */
669 // XXX I think, confirm this
670 struct PACKED {
671 uint32_t full : 1; /* not half */
672 uint32_t src1 : 8;
673 uint32_t src2 : 8;
674 uint32_t pad : 15;
675 };
676 };
677
678 /* dword1: */
679 uint32_t dst : 8;
680 uint32_t wrmask : 4; /* write-mask */
681 uint32_t type : 3;
682 uint32_t base_lo : 1; /* used with bindless */
683 uint32_t is_3d : 1;
684
685 uint32_t is_a : 1;
686 uint32_t is_s : 1;
687 uint32_t is_s2en_bindless : 1;
688 uint32_t is_o : 1;
689 uint32_t is_p : 1;
690
691 uint32_t opc : 5;
692 uint32_t jmp_tgt : 1;
693 uint32_t sync : 1;
694 uint32_t opc_cat : 3;
695 } instr_cat5_t;
696
697 /* dword0 encoding for src_off: [src1 + off], src2: */
698 typedef struct PACKED {
699 /* dword0: */
700 uint32_t mustbe1 : 1;
701 int32_t off : 13;
702 uint32_t src1 : 8;
703 uint32_t src1_im : 1;
704 uint32_t src2_im : 1;
705 uint32_t src2 : 8;
706
707 /* dword1: */
708 uint32_t dword1;
709 } instr_cat6a_t;
710
711 /* dword0 encoding for !src_off: [src1], src2 */
712 typedef struct PACKED {
713 /* dword0: */
714 uint32_t mustbe0 : 1;
715 uint32_t src1 : 13;
716 uint32_t ignore0 : 8;
717 uint32_t src1_im : 1;
718 uint32_t src2_im : 1;
719 uint32_t src2 : 8;
720
721 /* dword1: */
722 uint32_t dword1;
723 } instr_cat6b_t;
724
725 /* dword1 encoding for dst_off: */
726 typedef struct PACKED {
727 /* dword0: */
728 uint32_t dword0;
729
730 /* note: there is some weird stuff going on where sometimes
731 * cat6->a.off is involved.. but that seems like a bug in
732 * the blob, since it is used even if !cat6->src_off
733 * It would make sense for there to be some more bits to
734 * bring us to 11 bits worth of offset, but not sure..
735 */
736 int32_t off : 8;
737 uint32_t mustbe1 : 1;
738 uint32_t dst : 8;
739 uint32_t pad1 : 15;
740 } instr_cat6c_t;
741
742 /* dword1 encoding for !dst_off: */
743 typedef struct PACKED {
744 /* dword0: */
745 uint32_t dword0;
746
747 uint32_t dst : 8;
748 uint32_t mustbe0 : 1;
749 uint32_t idx : 8;
750 uint32_t pad0 : 15;
751 } instr_cat6d_t;
752
753 /* ldgb and atomics..
754 *
755 * ldgb: pad0=0, pad3=1
756 * atomic .g: pad0=1, pad3=1
757 * .l: pad0=1, pad3=0
758 */
759 typedef struct PACKED {
760 /* dword0: */
761 uint32_t pad0 : 1;
762 uint32_t src3 : 8;
763 uint32_t d : 2;
764 uint32_t typed : 1;
765 uint32_t type_size : 2;
766 uint32_t src1 : 8;
767 uint32_t src1_im : 1;
768 uint32_t src2_im : 1;
769 uint32_t src2 : 8;
770
771 /* dword1: */
772 uint32_t dst : 8;
773 uint32_t mustbe0 : 1;
774 uint32_t src_ssbo : 8;
775 uint32_t pad2 : 3; // type
776 uint32_t g : 1;
777 uint32_t src_ssbo_im : 1;
778 uint32_t pad4 : 10; // opc/jmp_tgt/sync/opc_cat
779 } instr_cat6ldgb_t;
780
781 /* stgb, pad0=0, pad3=2
782 */
783 typedef struct PACKED {
784 /* dword0: */
785 uint32_t mustbe1 : 1; // ???
786 uint32_t src1 : 8;
787 uint32_t d : 2;
788 uint32_t typed : 1;
789 uint32_t type_size : 2;
790 uint32_t pad0 : 9;
791 uint32_t src2_im : 1;
792 uint32_t src2 : 8;
793
794 /* dword1: */
795 uint32_t src3 : 8;
796 uint32_t src3_im : 1;
797 uint32_t dst_ssbo : 8;
798 uint32_t pad2 : 3; // type
799 uint32_t pad3 : 2;
800 uint32_t pad4 : 10; // opc/jmp_tgt/sync/opc_cat
801 } instr_cat6stgb_t;
802
803 typedef union PACKED {
804 instr_cat6a_t a;
805 instr_cat6b_t b;
806 instr_cat6c_t c;
807 instr_cat6d_t d;
808 instr_cat6ldgb_t ldgb;
809 instr_cat6stgb_t stgb;
810 struct PACKED {
811 /* dword0: */
812 uint32_t src_off : 1;
813 uint32_t pad1 : 31;
814
815 /* dword1: */
816 uint32_t pad2 : 8;
817 uint32_t dst_off : 1;
818 uint32_t pad3 : 8;
819 uint32_t type : 3;
820 uint32_t g : 1; /* or in some cases it means dst immed */
821 uint32_t pad4 : 1;
822 uint32_t opc : 5;
823 uint32_t jmp_tgt : 1;
824 uint32_t sync : 1;
825 uint32_t opc_cat : 3;
826 };
827 } instr_cat6_t;
828
829 /* Similar to cat5_desc_mode_t, describes how the descriptor is loaded.
830 */
831 typedef enum {
832 /* Use old GL binding model with an immediate index. */
833 CAT6_IMM = 0,
834
835 CAT6_UNIFORM = 1,
836
837 CAT6_NONUNIFORM = 2,
838
839 /* Use the bindless model, with an immediate index.
840 */
841 CAT6_BINDLESS_IMM = 4,
842
843 /* Use the bindless model, with a uniform register index.
844 */
845 CAT6_BINDLESS_UNIFORM = 5,
846
847 /* Use the bindless model, with a register index that isn't guaranteed
848 * to be uniform. This presumably checks if the indices are equal and
849 * splits up the load/store, because it works the way you would
850 * expect.
851 */
852 CAT6_BINDLESS_NONUNIFORM = 6,
853 } cat6_desc_mode_t;
854
855 /**
856 * For atomic ops (which return a value):
857 *
858 * pad1=1, pad3=c, pad5=3
859 * src1 - vecN offset/coords
860 * src2.x - is actually dest register
861 * src2.y - is 'data' except for cmpxchg where src2.y is 'compare'
862 * and src2.z is 'data'
863 *
864 * For stib (which does not return a value):
865 * pad1=0, pad3=c, pad5=2
866 * src1 - vecN offset/coords
867 * src2 - value to store
868 *
869 * For ldib:
870 * pad1=1, pad3=c, pad5=2
871 * src1 - vecN offset/coords
872 *
873 * for ldc (load from UBO using descriptor):
874 * pad1=0, pad3=8, pad5=2
875 *
876 * pad2 and pad5 are only observed to be 0.
877 */
878 typedef struct PACKED {
879 /* dword0: */
880 uint32_t pad1 : 1;
881 uint32_t base : 3;
882 uint32_t pad2 : 2;
883 uint32_t desc_mode : 3;
884 uint32_t d : 2;
885 uint32_t typed : 1;
886 uint32_t type_size : 2;
887 uint32_t opc : 5;
888 uint32_t pad3 : 5;
889 uint32_t src1 : 8; /* coordinate/offset */
890
891 /* dword1: */
892 uint32_t src2 : 8; /* or the dst for load instructions */
893 uint32_t pad4 : 1; //mustbe0 ??
894 uint32_t ssbo : 8; /* ssbo/image binding point */
895 uint32_t type : 3;
896 uint32_t pad5 : 7;
897 uint32_t jmp_tgt : 1;
898 uint32_t sync : 1;
899 uint32_t opc_cat : 3;
900 } instr_cat6_a6xx_t;
901
902 typedef struct PACKED {
903 /* dword0: */
904 uint32_t pad1 : 32;
905
906 /* dword1: */
907 uint32_t pad2 : 12;
908 uint32_t ss : 1; /* maybe in the encoding, but blob only uses (sy) */
909 uint32_t pad3 : 6;
910 uint32_t w : 1; /* write */
911 uint32_t r : 1; /* read */
912 uint32_t l : 1; /* local */
913 uint32_t g : 1; /* global */
914 uint32_t opc : 4; /* presumed, but only a couple known OPCs */
915 uint32_t jmp_tgt : 1; /* (jp) */
916 uint32_t sync : 1; /* (sy) */
917 uint32_t opc_cat : 3;
918 } instr_cat7_t;
919
920 typedef union PACKED {
921 instr_cat0_t cat0;
922 instr_cat1_t cat1;
923 instr_cat2_t cat2;
924 instr_cat3_t cat3;
925 instr_cat4_t cat4;
926 instr_cat5_t cat5;
927 instr_cat6_t cat6;
928 instr_cat6_a6xx_t cat6_a6xx;
929 instr_cat7_t cat7;
930 struct PACKED {
931 /* dword0: */
932 uint32_t pad1 : 32;
933
934 /* dword1: */
935 uint32_t pad2 : 12;
936 uint32_t ss : 1; /* cat1-cat4 (cat0??) and cat7 (?) */
937 uint32_t ul : 1; /* cat2-cat4 (and cat1 in blob.. which may be bug??) */
938 uint32_t pad3 : 13;
939 uint32_t jmp_tgt : 1;
940 uint32_t sync : 1;
941 uint32_t opc_cat : 3;
942
943 };
944 } instr_t;
945
946 static inline uint32_t instr_repeat(instr_t *instr)
947 {
948 switch (instr->opc_cat) {
949 case 0: return instr->cat0.repeat;
950 case 1: return instr->cat1.repeat;
951 case 2: return instr->cat2.repeat;
952 case 3: return instr->cat3.repeat;
953 case 4: return instr->cat4.repeat;
954 default: return 0;
955 }
956 }
957
958 static inline bool instr_sat(instr_t *instr)
959 {
960 switch (instr->opc_cat) {
961 case 2: return instr->cat2.sat;
962 case 3: return instr->cat3.sat;
963 case 4: return instr->cat4.sat;
964 default: return false;
965 }
966 }
967
968 /* We can probably drop the gpu_id arg, but keeping it for now so we can
969 * assert if we see something we think should be new encoding on an older
970 * gpu.
971 */
972 static inline bool is_cat6_legacy(instr_t *instr, unsigned gpu_id)
973 {
974 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
975
976 /* At least one of these two bits is pad in all the possible
977 * "legacy" cat6 encodings, and a analysis of all the pre-a6xx
978 * cmdstream traces I have indicates that the pad bit is zero
979 * in all cases. So we can use this to detect new encoding:
980 */
981 if ((cat6->pad3 & 0x8) && (cat6->pad5 & 0x2)) {
982 assert(gpu_id >= 600);
983 assert(instr->cat6.opc == 0);
984 return false;
985 }
986
987 return true;
988 }
989
990 static inline uint32_t instr_opc(instr_t *instr, unsigned gpu_id)
991 {
992 switch (instr->opc_cat) {
993 case 0: return instr->cat0.opc | instr->cat0.opc_hi << 4;
994 case 1: return 0;
995 case 2: return instr->cat2.opc;
996 case 3: return instr->cat3.opc;
997 case 4: return instr->cat4.opc;
998 case 5: return instr->cat5.opc;
999 case 6:
1000 if (!is_cat6_legacy(instr, gpu_id))
1001 return instr->cat6_a6xx.opc;
1002 return instr->cat6.opc;
1003 case 7: return instr->cat7.opc;
1004 default: return 0;
1005 }
1006 }
1007
1008 static inline bool is_mad(opc_t opc)
1009 {
1010 switch (opc) {
1011 case OPC_MAD_U16:
1012 case OPC_MAD_S16:
1013 case OPC_MAD_U24:
1014 case OPC_MAD_S24:
1015 case OPC_MAD_F16:
1016 case OPC_MAD_F32:
1017 return true;
1018 default:
1019 return false;
1020 }
1021 }
1022
1023 static inline bool is_madsh(opc_t opc)
1024 {
1025 switch (opc) {
1026 case OPC_MADSH_U16:
1027 case OPC_MADSH_M16:
1028 return true;
1029 default:
1030 return false;
1031 }
1032 }
1033
1034 static inline bool is_atomic(opc_t opc)
1035 {
1036 switch (opc) {
1037 case OPC_ATOMIC_ADD:
1038 case OPC_ATOMIC_SUB:
1039 case OPC_ATOMIC_XCHG:
1040 case OPC_ATOMIC_INC:
1041 case OPC_ATOMIC_DEC:
1042 case OPC_ATOMIC_CMPXCHG:
1043 case OPC_ATOMIC_MIN:
1044 case OPC_ATOMIC_MAX:
1045 case OPC_ATOMIC_AND:
1046 case OPC_ATOMIC_OR:
1047 case OPC_ATOMIC_XOR:
1048 return true;
1049 default:
1050 return false;
1051 }
1052 }
1053
1054 static inline bool is_ssbo(opc_t opc)
1055 {
1056 switch (opc) {
1057 case OPC_RESFMT:
1058 case OPC_RESINFO:
1059 case OPC_LDGB:
1060 case OPC_STGB:
1061 case OPC_STIB:
1062 return true;
1063 default:
1064 return false;
1065 }
1066 }
1067
1068 static inline bool is_isam(opc_t opc)
1069 {
1070 switch (opc) {
1071 case OPC_ISAM:
1072 case OPC_ISAML:
1073 case OPC_ISAMM:
1074 return true;
1075 default:
1076 return false;
1077 }
1078 }
1079
1080
1081 static inline bool is_cat2_float(opc_t opc)
1082 {
1083 switch (opc) {
1084 case OPC_ADD_F:
1085 case OPC_MIN_F:
1086 case OPC_MAX_F:
1087 case OPC_MUL_F:
1088 case OPC_SIGN_F:
1089 case OPC_CMPS_F:
1090 case OPC_ABSNEG_F:
1091 case OPC_CMPV_F:
1092 case OPC_FLOOR_F:
1093 case OPC_CEIL_F:
1094 case OPC_RNDNE_F:
1095 case OPC_RNDAZ_F:
1096 case OPC_TRUNC_F:
1097 return true;
1098
1099 default:
1100 return false;
1101 }
1102 }
1103
1104 static inline bool is_cat3_float(opc_t opc)
1105 {
1106 switch (opc) {
1107 case OPC_MAD_F16:
1108 case OPC_MAD_F32:
1109 case OPC_SEL_F16:
1110 case OPC_SEL_F32:
1111 return true;
1112 default:
1113 return false;
1114 }
1115 }
1116
1117 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
1118
1119 #endif /* INSTR_A3XX_H_ */