2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
62 uint16_t last_baryf
; /* instruction # of last varying fetch */
67 IR3_REG_CONST
= 0x001,
68 IR3_REG_IMMED
= 0x002,
70 /* high registers are used for some things in compute shaders,
71 * for example. Seems to be for things that are global to all
72 * threads in a wave, so possibly these are global/shared by
73 * all the threads in the wave?
76 IR3_REG_RELATIV
= 0x010,
78 /* Most instructions, it seems, can do float abs/neg but not
79 * integer. The CP pass needs to know what is intended (int or
80 * float) in order to do the right thing. For this reason the
81 * abs/neg flags are split out into float and int variants. In
82 * addition, .b (bitwise) operations, the negate is actually a
83 * bitwise not, so split that out into a new flag to make it
92 IR3_REG_POS_INF
= 0x1000,
93 /* (ei) flag, end-input? Set on last bary, presumably to signal
94 * that the shader needs no more input:
97 /* meta-flags, for intermediate stages of IR, ie.
98 * before register assignment is done:
100 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
101 IR3_REG_ARRAY
= 0x8000,
105 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
108 * the component is in the low two bits of the reg #, so
109 * rN.x becomes: (N << 2) | x
124 /* For IR3_REG_SSA, src registers contain ptr back to assigning
127 * For IR3_REG_ARRAY, the pointer is back to the last dependent
128 * array access (although the net effect is the same, it points
129 * back to a previous instruction that we depend on).
131 struct ir3_instruction
*instr
;
134 /* used for cat5 instructions, but also for internal/IR level
135 * tracking of what registers are read/written by an instruction.
136 * wrmask may be a bad name since it is used to represent both
137 * src and dst that touch multiple adjacent registers.
140 /* for relative addressing, 32bits for array size is too small,
141 * but otoh we don't need to deal with disjoint sets, so instead
142 * use a simple size field (number of scalar components).
149 * Stupid/simple growable array implementation:
151 #define DECLARE_ARRAY(type, name) \
152 unsigned name ## _count, name ## _sz; \
155 #define array_insert(ctx, arr, val) do { \
156 if (arr ## _count == arr ## _sz) { \
157 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
158 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
160 arr[arr ##_count++] = val; \
163 struct ir3_instruction
{
164 struct ir3_block
*block
;
167 /* (sy) flag is set on first instruction, and after sample
168 * instructions (probably just on RAW hazard).
170 IR3_INSTR_SY
= 0x001,
171 /* (ss) flag is set on first instruction, and first instruction
172 * to depend on the result of "long" instructions (RAW hazard):
174 * rcp, rsq, log2, exp2, sin, cos, sqrt
176 * It seems to synchronize until all in-flight instructions are
177 * completed, for example:
180 * add.f hr2.z, (neg)hr2.z, hc0.y
181 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
184 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
186 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
187 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
188 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
190 * The last mul.f does not have (ss) set, presumably because the
191 * (ss) on the previous instruction does the job.
193 * The blob driver also seems to set it on WAR hazards, although
194 * not really clear if this is needed or just blob compiler being
195 * sloppy. So far I haven't found a case where removing the (ss)
196 * causes problems for WAR hazard, but I could just be getting
200 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
203 IR3_INSTR_SS
= 0x002,
204 /* (jp) flag is set on jump targets:
206 IR3_INSTR_JP
= 0x004,
207 IR3_INSTR_UL
= 0x008,
208 IR3_INSTR_3D
= 0x010,
213 IR3_INSTR_S2EN
= 0x200,
215 IR3_INSTR_SAT
= 0x800,
216 /* meta-flags, for intermediate stages of IR, ie.
217 * before register assignment is done:
219 IR3_INSTR_MARK
= 0x1000,
220 IR3_INSTR_UNUSED
= 0x2000,
228 struct ir3_register
**regs
;
234 struct ir3_block
*target
;
237 type_t src_type
, dst_type
;
257 int iim_val
: 3; /* for ldgb/stgb, # of components */
262 unsigned w
: 1; /* write */
263 unsigned r
: 1; /* read */
264 unsigned l
: 1; /* local */
265 unsigned g
: 1; /* global */
267 /* for meta-instructions, just used to hold extra data
268 * before instruction scheduling, etc
271 int off
; /* component/offset */
274 /* for output collects, this maps back to the entry in the
275 * ir3_shader_variant::outputs table.
281 unsigned input_offset
;
284 /* maps back to entry in ir3_shader_variant::inputs table: */
286 /* for sysvals, identifies the sysval type. Mostly so we can
287 * identify the special cases where a sysval should not be DCE'd
288 * (currently, just pre-fs texture fetch)
290 gl_system_value sysval
;
294 /* transient values used during various algorithms: */
296 /* The instruction depth is the max dependency distance to output.
298 * You can also think of it as the "cost", if we did any sort of
299 * optimization for register footprint. Ie. a value that is just
300 * result of moving a const to a reg would have a low cost, so to
301 * it could make sense to duplicate the instruction at various
302 * points where the result is needed to reduce register footprint.
305 /* When we get to the RA stage, we no longer need depth, but
306 * we do need instruction's position/name:
314 /* used for per-pass extra instruction data.
316 * TODO we should remove the per-pass data like this and 'use_count'
317 * and do something similar to what RA does w/ ir3_ra_instr_data..
318 * ie. use the ir3_count_instructions pass, and then use instr->ip
319 * to index into a table of pass-private data.
323 int sun
; /* Sethi–Ullman number, used by sched */
324 int use_count
; /* currently just updated/used by cp */
326 /* Used during CP and RA stages. For collect and shader inputs/
327 * outputs where we need a sequence of consecutive registers,
328 * keep track of each src instructions left (ie 'n-1') and right
329 * (ie 'n+1') neighbor. The front-end must insert enough mov's
330 * to ensure that each instruction has at most one left and at
331 * most one right neighbor. During the copy-propagation pass,
332 * we only remove mov's when we can preserve this constraint.
333 * And during the RA stage, we use the neighbor information to
334 * allocate a block of registers in one shot.
336 * TODO: maybe just add something like:
337 * struct ir3_instruction_ref {
338 * struct ir3_instruction *instr;
342 * Or can we get away without the refcnt stuff? It seems like
343 * it should be overkill.. the problem is if, potentially after
344 * already eliminating some mov's, if you have a single mov that
345 * needs to be grouped with it's neighbors in two different
346 * places (ex. shader output and a collect).
349 struct ir3_instruction
*left
, *right
;
350 uint16_t left_cnt
, right_cnt
;
353 /* an instruction can reference at most one address register amongst
354 * it's src/dst registers. Beyond that, you need to insert mov's.
356 * NOTE: do not write this directly, use ir3_instr_set_address()
358 struct ir3_instruction
*address
;
360 /* Tracking for additional dependent instructions. Used to handle
361 * barriers, WAR hazards for arrays/SSBOs/etc.
363 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
366 * From PoV of instruction scheduling, not execution (ie. ignores global/
367 * local distinction):
368 * shared image atomic SSBO everything
369 * barrier()/ - R/W R/W R/W R/W X
370 * groupMemoryBarrier()
371 * memoryBarrier() - R/W R/W
372 * (but only images declared coherent?)
373 * memoryBarrierAtomic() - R/W
374 * memoryBarrierBuffer() - R/W
375 * memoryBarrierImage() - R/W
376 * memoryBarrierShared() - R/W
378 * TODO I think for SSBO/image/shared, in cases where we can determine
379 * which variable is accessed, we don't need to care about accesses to
380 * different variables (unless declared coherent??)
383 IR3_BARRIER_EVERYTHING
= 1 << 0,
384 IR3_BARRIER_SHARED_R
= 1 << 1,
385 IR3_BARRIER_SHARED_W
= 1 << 2,
386 IR3_BARRIER_IMAGE_R
= 1 << 3,
387 IR3_BARRIER_IMAGE_W
= 1 << 4,
388 IR3_BARRIER_BUFFER_R
= 1 << 5,
389 IR3_BARRIER_BUFFER_W
= 1 << 6,
390 IR3_BARRIER_ARRAY_R
= 1 << 7,
391 IR3_BARRIER_ARRAY_W
= 1 << 8,
392 } barrier_class
, barrier_conflict
;
394 /* Entry in ir3_block's instruction list: */
395 struct list_head node
;
402 static inline struct ir3_instruction
*
403 ir3_neighbor_first(struct ir3_instruction
*instr
)
406 while (instr
->cp
.left
) {
407 instr
= instr
->cp
.left
;
408 if (++cnt
> 0xffff) {
416 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
420 debug_assert(!instr
->cp
.left
);
422 while (instr
->cp
.right
) {
424 instr
= instr
->cp
.right
;
435 struct ir3_compiler
*compiler
;
436 gl_shader_stage type
;
438 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
439 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
441 /* Track bary.f (and ldlv) instructions.. this is needed in
442 * scheduling to ensure that all varying fetches happen before
443 * any potential kill instructions. The hw gets grumpy if all
444 * threads in a group are killed before the last bary.f gets
445 * a chance to signal end of input (ei).
447 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
449 /* Track all indirect instructions (read and write). To avoid
450 * deadlock scenario where an address register gets scheduled,
451 * but other dependent src instructions cannot be scheduled due
452 * to dependency on a *different* address register value, the
453 * scheduler needs to ensure that all dependencies other than
454 * the instruction other than the address register are scheduled
455 * before the one that writes the address register. Having a
456 * convenient list of instructions that reference some address
457 * register simplifies this.
459 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
461 /* and same for instructions that consume predicate register: */
462 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
464 /* Track texture sample instructions which need texture state
465 * patched in (for astc-srgb workaround):
467 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
469 /* List of blocks: */
470 struct list_head block_list
;
472 /* List of ir3_array's: */
473 struct list_head array_list
;
475 unsigned max_sun
; /* max Sethi–Ullman number */
478 unsigned block_count
, instr_count
;
483 struct list_head node
;
487 struct nir_register
*r
;
489 /* To avoid array write's from getting DCE'd, keep track of the
490 * most recent write. Any array access depends on the most
491 * recent write. This way, nothing depends on writes after the
492 * last read. But all the writes that happen before that have
493 * something depending on them
495 struct ir3_instruction
*last_write
;
497 /* extra stuff used in RA pass: */
498 unsigned base
; /* base vreg name */
499 unsigned reg
; /* base physical reg */
500 uint16_t start_ip
, end_ip
;
503 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
506 struct list_head node
;
509 const struct nir_block
*nblock
;
511 struct list_head instr_list
; /* list of ir3_instruction */
513 /* each block has either one or two successors.. in case of
514 * two successors, 'condition' decides which one to follow.
515 * A block preceding an if/else has two successors.
517 struct ir3_instruction
*condition
;
518 struct ir3_block
*successors
[2];
520 struct set
*predecessors
; /* set of ir3_block */
522 uint16_t start_ip
, end_ip
;
524 /* Track instructions which do not write a register but other-
525 * wise must not be discarded (such as kill, stg, etc)
527 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
529 /* used for per-pass extra block data. Mainly used right
530 * now in RA step to track livein/liveout.
539 static inline uint32_t
540 block_id(struct ir3_block
*block
)
543 return block
->serialno
;
545 return (uint32_t)(unsigned long)block
;
549 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
550 void ir3_destroy(struct ir3
*shader
);
551 void * ir3_assemble(struct ir3
*shader
,
552 struct ir3_info
*info
, uint32_t gpu_id
);
553 void * ir3_alloc(struct ir3
*shader
, int sz
);
555 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
557 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
558 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
559 opc_t opc
, int nreg
);
560 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
561 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
562 const char *ir3_instr_name(struct ir3_instruction
*instr
);
564 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
566 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
567 struct ir3_register
*reg
);
569 void ir3_instr_set_address(struct ir3_instruction
*instr
,
570 struct ir3_instruction
*addr
);
572 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
574 if (instr
->flags
& IR3_INSTR_MARK
)
575 return true; /* already visited */
576 instr
->flags
|= IR3_INSTR_MARK
;
580 void ir3_block_clear_mark(struct ir3_block
*block
);
581 void ir3_clear_mark(struct ir3
*shader
);
583 unsigned ir3_count_instructions(struct ir3
*ir
);
585 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
586 struct ir3_register
*reg
)
589 for (i
= 0; i
< instr
->regs_count
; i
++)
590 if (reg
== instr
->regs
[i
])
596 #define MAX_ARRAYS 16
604 static inline uint32_t regid(int num
, int comp
)
606 return (num
<< 2) | (comp
& 0x3);
609 static inline uint32_t reg_num(struct ir3_register
*reg
)
611 return reg
->num
>> 2;
614 static inline uint32_t reg_comp(struct ir3_register
*reg
)
616 return reg
->num
& 0x3;
619 #define INVALID_REG regid(63, 0)
620 #define VALIDREG(r) ((r) != INVALID_REG)
621 #define CONDREG(r, val) COND(VALIDREG(r), (val))
623 static inline bool is_flow(struct ir3_instruction
*instr
)
625 return (opc_cat(instr
->opc
) == 0);
628 static inline bool is_kill(struct ir3_instruction
*instr
)
630 return instr
->opc
== OPC_KILL
|| instr
->opc
== OPC_CONDEND
;
633 static inline bool is_nop(struct ir3_instruction
*instr
)
635 return instr
->opc
== OPC_NOP
;
638 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
639 struct ir3_register
*reg2
)
641 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
642 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
644 if (type_reg1
^ type_reg2
)
650 /* Is it a non-transformative (ie. not type changing) mov? This can
651 * also include absneg.s/absneg.f, which for the most part can be
652 * treated as a mov (single src argument).
654 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
656 struct ir3_register
*dst
;
658 switch (instr
->opc
) {
660 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
662 /* If the type of dest reg and src reg are different,
663 * it shouldn't be considered as same type mov
665 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
670 if (instr
->flags
& IR3_INSTR_SAT
)
672 /* If the type of dest reg and src reg are different,
673 * it shouldn't be considered as same type mov
675 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
682 dst
= instr
->regs
[0];
684 /* mov's that write to a0.x or p0.x are special: */
685 if (dst
->num
== regid(REG_P0
, 0))
687 if (dst
->num
== regid(REG_A0
, 0))
690 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
696 static inline bool is_alu(struct ir3_instruction
*instr
)
698 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
701 static inline bool is_sfu(struct ir3_instruction
*instr
)
703 return (opc_cat(instr
->opc
) == 4);
706 static inline bool is_tex(struct ir3_instruction
*instr
)
708 return (opc_cat(instr
->opc
) == 5);
711 static inline bool is_mem(struct ir3_instruction
*instr
)
713 return (opc_cat(instr
->opc
) == 6);
716 static inline bool is_barrier(struct ir3_instruction
*instr
)
718 return (opc_cat(instr
->opc
) == 7);
722 is_store(struct ir3_instruction
*instr
)
724 /* these instructions, the "destination" register is
725 * actually a source, the address to store to.
727 switch (instr
->opc
) {
742 static inline bool is_load(struct ir3_instruction
*instr
)
744 switch (instr
->opc
) {
754 /* probably some others too.. */
761 static inline bool is_input(struct ir3_instruction
*instr
)
763 /* in some cases, ldlv is used to fetch varying without
764 * interpolation.. fortunately inloc is the first src
765 * register in either case
767 switch (instr
->opc
) {
776 static inline bool is_bool(struct ir3_instruction
*instr
)
778 switch (instr
->opc
) {
788 static inline bool is_meta(struct ir3_instruction
*instr
)
790 return (opc_cat(instr
->opc
) == -1);
793 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
795 if ((instr
->regs_count
== 0) || is_store(instr
))
798 return util_last_bit(instr
->regs
[0]->wrmask
);
801 static inline bool writes_addr(struct ir3_instruction
*instr
)
803 if (instr
->regs_count
> 0) {
804 struct ir3_register
*dst
= instr
->regs
[0];
805 return reg_num(dst
) == REG_A0
;
810 static inline bool writes_pred(struct ir3_instruction
*instr
)
812 if (instr
->regs_count
> 0) {
813 struct ir3_register
*dst
= instr
->regs
[0];
814 return reg_num(dst
) == REG_P0
;
819 /* returns defining instruction for reg */
820 /* TODO better name */
821 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
823 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
829 static inline bool conflicts(struct ir3_instruction
*a
,
830 struct ir3_instruction
*b
)
832 return (a
&& b
) && (a
!= b
);
835 static inline bool reg_gpr(struct ir3_register
*r
)
837 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
839 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
844 static inline type_t
half_type(type_t type
)
847 case TYPE_F32
: return TYPE_F16
;
848 case TYPE_U32
: return TYPE_U16
;
849 case TYPE_S32
: return TYPE_S16
;
860 /* some cat2 instructions (ie. those which are not float) can embed an
863 static inline bool ir3_cat2_int(opc_t opc
)
903 static inline bool ir3_cat2_float(opc_t opc
)
926 static inline bool ir3_cat3_float(opc_t opc
)
939 /* map cat2 instruction to valid abs/neg flags: */
940 static inline unsigned ir3_cat2_absneg(opc_t opc
)
957 return IR3_REG_FABS
| IR3_REG_FNEG
;
978 return IR3_REG_SABS
| IR3_REG_SNEG
;
999 /* map cat3 instructions to valid abs/neg flags: */
1000 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1007 return IR3_REG_FNEG
;
1019 /* neg *may* work on 3rd src.. */
1029 #define MASK(n) ((1 << (n)) - 1)
1031 /* iterator for an instructions's sources (reg), also returns src #: */
1032 #define foreach_src_n(__srcreg, __n, __instr) \
1033 if ((__instr)->regs_count) \
1034 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1035 if ((__srcreg = (__instr)->regs[__n + 1]))
1037 /* iterator for an instructions's sources (reg): */
1038 #define foreach_src(__srcreg, __instr) \
1039 foreach_src_n(__srcreg, __i, __instr)
1041 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1043 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1049 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1051 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1052 return instr
->address
;
1053 if (n
>= instr
->regs_count
)
1054 return instr
->deps
[n
- instr
->regs_count
];
1055 return ssa(instr
->regs
[n
]);
1058 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1060 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1062 if (n
>= instr
->regs_count
)
1067 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1069 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1070 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1071 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1072 if ((__srcinst = __ssa_src_n(__instr, __n)))
1074 /* iterator for an instruction's SSA sources (instr): */
1075 #define foreach_ssa_src(__srcinst, __instr) \
1076 foreach_ssa_src_n(__srcinst, __i, __instr)
1078 /* iterators for shader inputs: */
1079 #define foreach_input_n(__ininstr, __cnt, __ir) \
1080 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1081 if ((__ininstr = (__ir)->inputs[__cnt]))
1082 #define foreach_input(__ininstr, __ir) \
1083 foreach_input_n(__ininstr, __i, __ir)
1085 /* iterators for shader outputs: */
1086 #define foreach_output_n(__outinstr, __cnt, __ir) \
1087 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1088 if ((__outinstr = (__ir)->outputs[__cnt]))
1089 #define foreach_output(__outinstr, __ir) \
1090 foreach_output_n(__outinstr, __i, __ir)
1092 /* iterators for instructions: */
1093 #define foreach_instr(__instr, __list) \
1094 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1095 #define foreach_instr_rev(__instr, __list) \
1096 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1097 #define foreach_instr_safe(__instr, __list) \
1098 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1100 /* iterators for blocks: */
1101 #define foreach_block(__block, __list) \
1102 list_for_each_entry(struct ir3_block, __block, __list, node)
1103 #define foreach_block_safe(__block, __list) \
1104 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1106 /* iterators for arrays: */
1107 #define foreach_array(__array, __list) \
1108 list_for_each_entry(struct ir3_array, __array, __list, node)
1111 void ir3_print(struct ir3
*ir
);
1112 void ir3_print_instr(struct ir3_instruction
*instr
);
1114 /* depth calculation: */
1115 struct ir3_shader_variant
;
1116 int ir3_delayslots(struct ir3_instruction
*assigner
,
1117 struct ir3_instruction
*consumer
, unsigned n
);
1118 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1119 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1121 /* copy-propagate: */
1122 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1124 /* group neighbors and insert mov's to resolve conflicts: */
1125 void ir3_group(struct ir3
*ir
);
1127 /* Sethi–Ullman numbering: */
1128 void ir3_sun(struct ir3
*ir
);
1131 void ir3_sched_add_deps(struct ir3
*ir
);
1132 int ir3_sched(struct ir3
*ir
);
1134 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1136 /* register assignment: */
1137 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1138 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1141 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1143 /* ************************************************************************* */
1144 /* instruction helpers */
1146 /* creates SSA src of correct type (ie. half vs full precision) */
1147 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1148 struct ir3_instruction
*src
, unsigned flags
)
1150 struct ir3_register
*reg
;
1151 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1152 flags
|= IR3_REG_HALF
;
1153 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1155 reg
->wrmask
= src
->regs
[0]->wrmask
;
1159 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1161 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1162 reg
->flags
|= IR3_REG_SSA
;
1166 static inline struct ir3_instruction
*
1167 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1169 struct ir3_instruction
*mov
;
1170 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1172 mov
= ir3_instr_create(block
, OPC_MOV
);
1173 mov
->cat1
.src_type
= type
;
1174 mov
->cat1
.dst_type
= type
;
1175 __ssa_dst(mov
)->flags
|= flags
;
1176 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1181 static inline struct ir3_instruction
*
1182 create_immed(struct ir3_block
*block
, uint32_t val
)
1184 return create_immed_typed(block
, val
, TYPE_U32
);
1187 static inline struct ir3_instruction
*
1188 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1190 struct ir3_instruction
*mov
;
1191 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1193 mov
= ir3_instr_create(block
, OPC_MOV
);
1194 mov
->cat1
.src_type
= type
;
1195 mov
->cat1
.dst_type
= type
;
1196 __ssa_dst(mov
)->flags
|= flags
;
1197 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1202 static inline struct ir3_instruction
*
1203 create_uniform(struct ir3_block
*block
, unsigned n
)
1205 return create_uniform_typed(block
, n
, TYPE_F32
);
1208 static inline struct ir3_instruction
*
1209 create_uniform_indirect(struct ir3_block
*block
, int n
,
1210 struct ir3_instruction
*address
)
1212 struct ir3_instruction
*mov
;
1214 mov
= ir3_instr_create(block
, OPC_MOV
);
1215 mov
->cat1
.src_type
= TYPE_U32
;
1216 mov
->cat1
.dst_type
= TYPE_U32
;
1218 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1220 ir3_instr_set_address(mov
, address
);
1225 static inline struct ir3_instruction
*
1226 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1228 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1230 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1231 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1232 src_reg
->array
= src
->regs
[0]->array
;
1234 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1236 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1237 instr
->cat1
.src_type
= type
;
1238 instr
->cat1
.dst_type
= type
;
1242 static inline struct ir3_instruction
*
1243 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1244 type_t src_type
, type_t dst_type
)
1246 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1247 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1248 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1250 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1252 __ssa_dst(instr
)->flags
|= dst_flags
;
1253 __ssa_src(instr
, src
, 0);
1254 instr
->cat1
.src_type
= src_type
;
1255 instr
->cat1
.dst_type
= dst_type
;
1256 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1260 static inline struct ir3_instruction
*
1261 ir3_NOP(struct ir3_block
*block
)
1263 return ir3_instr_create(block
, OPC_NOP
);
1266 #define IR3_INSTR_0 0
1268 #define __INSTR0(flag, name, opc) \
1269 static inline struct ir3_instruction * \
1270 ir3_##name(struct ir3_block *block) \
1272 struct ir3_instruction *instr = \
1273 ir3_instr_create(block, opc); \
1274 instr->flags |= flag; \
1277 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1278 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1280 #define __INSTR1(flag, name, opc) \
1281 static inline struct ir3_instruction * \
1282 ir3_##name(struct ir3_block *block, \
1283 struct ir3_instruction *a, unsigned aflags) \
1285 struct ir3_instruction *instr = \
1286 ir3_instr_create(block, opc); \
1288 __ssa_src(instr, a, aflags); \
1289 instr->flags |= flag; \
1292 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1293 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1295 #define __INSTR2(flag, name, opc) \
1296 static inline struct ir3_instruction * \
1297 ir3_##name(struct ir3_block *block, \
1298 struct ir3_instruction *a, unsigned aflags, \
1299 struct ir3_instruction *b, unsigned bflags) \
1301 struct ir3_instruction *instr = \
1302 ir3_instr_create(block, opc); \
1304 __ssa_src(instr, a, aflags); \
1305 __ssa_src(instr, b, bflags); \
1306 instr->flags |= flag; \
1309 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1310 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1312 #define __INSTR3(flag, name, opc) \
1313 static inline struct ir3_instruction * \
1314 ir3_##name(struct ir3_block *block, \
1315 struct ir3_instruction *a, unsigned aflags, \
1316 struct ir3_instruction *b, unsigned bflags, \
1317 struct ir3_instruction *c, unsigned cflags) \
1319 struct ir3_instruction *instr = \
1320 ir3_instr_create2(block, opc, 4); \
1322 __ssa_src(instr, a, aflags); \
1323 __ssa_src(instr, b, bflags); \
1324 __ssa_src(instr, c, cflags); \
1325 instr->flags |= flag; \
1328 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1329 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1331 #define __INSTR4(flag, name, opc) \
1332 static inline struct ir3_instruction * \
1333 ir3_##name(struct ir3_block *block, \
1334 struct ir3_instruction *a, unsigned aflags, \
1335 struct ir3_instruction *b, unsigned bflags, \
1336 struct ir3_instruction *c, unsigned cflags, \
1337 struct ir3_instruction *d, unsigned dflags) \
1339 struct ir3_instruction *instr = \
1340 ir3_instr_create2(block, opc, 5); \
1342 __ssa_src(instr, a, aflags); \
1343 __ssa_src(instr, b, bflags); \
1344 __ssa_src(instr, c, cflags); \
1345 __ssa_src(instr, d, dflags); \
1346 instr->flags |= flag; \
1349 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1350 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1352 /* cat0 instructions: */
1362 /* cat2 instructions, most 2 src but some 1 src: */
1410 /* cat3 instructions: */
1428 /* cat4 instructions: */
1437 /* cat5 instructions: */
1444 static inline struct ir3_instruction
*
1445 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1446 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1447 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1449 struct ir3_instruction
*sam
;
1451 sam
= ir3_instr_create(block
, opc
);
1452 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1453 __ssa_dst(sam
)->wrmask
= wrmask
;
1454 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1456 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1459 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1461 sam
->cat5
.type
= type
;
1466 /* cat6 instructions: */
1481 INSTR2(ATOMIC_CMPXCHG
)
1490 INSTR3F(G
, ATOMIC_ADD
)
1491 INSTR3F(G
, ATOMIC_SUB
)
1492 INSTR3F(G
, ATOMIC_XCHG
)
1493 INSTR3F(G
, ATOMIC_INC
)
1494 INSTR3F(G
, ATOMIC_DEC
)
1495 INSTR3F(G
, ATOMIC_CMPXCHG
)
1496 INSTR3F(G
, ATOMIC_MIN
)
1497 INSTR3F(G
, ATOMIC_MAX
)
1498 INSTR3F(G
, ATOMIC_AND
)
1499 INSTR3F(G
, ATOMIC_OR
)
1500 INSTR3F(G
, ATOMIC_XOR
)
1505 INSTR4F(G
, ATOMIC_ADD
)
1506 INSTR4F(G
, ATOMIC_SUB
)
1507 INSTR4F(G
, ATOMIC_XCHG
)
1508 INSTR4F(G
, ATOMIC_INC
)
1509 INSTR4F(G
, ATOMIC_DEC
)
1510 INSTR4F(G
, ATOMIC_CMPXCHG
)
1511 INSTR4F(G
, ATOMIC_MIN
)
1512 INSTR4F(G
, ATOMIC_MAX
)
1513 INSTR4F(G
, ATOMIC_AND
)
1514 INSTR4F(G
, ATOMIC_OR
)
1515 INSTR4F(G
, ATOMIC_XOR
)
1520 /* cat7 instructions: */
1524 /* meta instructions: */
1525 INSTR0(META_TEX_PREFETCH
);
1527 /* ************************************************************************* */
1528 /* split this out or find some helper to use.. like main/bitset.h.. */
1534 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1536 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1538 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1539 debug_assert(num
< MAX_REG
);
1540 if (reg
->flags
& IR3_REG_HALF
) {
1550 static inline void regmask_init(regmask_t
*regmask
)
1552 memset(regmask
, 0, sizeof(*regmask
));
1555 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1557 unsigned idx
= regmask_idx(reg
);
1558 if (reg
->flags
& IR3_REG_RELATIV
) {
1560 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1561 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1564 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1566 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1570 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1573 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1574 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1577 /* set bits in a if not set in b, conceptually:
1580 static inline void regmask_set_if_not(regmask_t
*a
,
1581 struct ir3_register
*reg
, regmask_t
*b
)
1583 unsigned idx
= regmask_idx(reg
);
1584 if (reg
->flags
& IR3_REG_RELATIV
) {
1586 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1587 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1588 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1591 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1593 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1594 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1598 static inline bool regmask_get(regmask_t
*regmask
,
1599 struct ir3_register
*reg
)
1601 unsigned idx
= regmask_idx(reg
);
1602 if (reg
->flags
& IR3_REG_RELATIV
) {
1604 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1605 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1609 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1611 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1617 /* ************************************************************************* */