src/freedreno/ir3/ir3_compiler.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28
  29 #include "ir3_compiler.h"
  30
  31 static const struct debug_named_value shader_debug_options[] = {
  32         {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
  33         {"tcs",        IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
  34         {"tes",        IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
  35         {"gs",         IR3_DBG_SHADER_GS,  "Print shader disasm for geometry shaders"},
  36         {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
  37         {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
  38         {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
  39         {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
  40         {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
  41         {"nouboopt",   IR3_DBG_NOUBOOPT,   "Disable lowering UBO to uniform"},
  42         {"nofp16",     IR3_DBG_NOFP16,     "Don't lower mediump to fp16"},
  43 #ifdef DEBUG
  44         /* DEBUG-only options: */
  45         {"schedmsgs",  IR3_DBG_SCHEDMSGS,  "Enable scheduler debug messages"},
  46         {"ramsgs",     IR3_DBG_RAMSGS,     "Enable register-allocation debug messages"},
  47 #endif
  48         DEBUG_NAMED_VALUE_END
  49 };
  50
  51 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
  52
  53 enum ir3_shader_debug ir3_shader_debug = 0;
  54
  55 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
  56 {
  57         struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
  58
  59         ir3_shader_debug = debug_get_option_ir3_shader_debug();
  60
  61         compiler->dev = dev;
  62         compiler->gpu_id = gpu_id;
  63         compiler->set = ir3_ra_alloc_reg_set(compiler, false);
  64
  65         if (compiler->gpu_id >= 600) {
  66                 compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
  67                 compiler->samgq_workaround = true;
  68                 /* a6xx split the pipeline state into geometry and fragment state, in
  69                  * order to let the VS run ahead of the FS. As a result there are now
  70                  * separate const files for the the fragment shader and everything
  71                  * else, and separate limits. There seems to be a shared limit, but
  72                  * it's higher than the vert or frag limits.
  73                  *
  74                  * TODO: The shared limit seems to be different on different on
  75                  * different models.
  76                  */
  77                 compiler->max_const_pipeline = 640;
  78                 compiler->max_const_frag = 512;
  79                 compiler->max_const_geom = 512;
  80                 compiler->max_const_safe = 128;
  81
  82                 /* Compute shaders don't share a const file with the FS. Instead they
  83                  * have their own file, which is smaller than the FS one.
  84                  *
  85                  * TODO: is this true on earlier gen's?
  86                  */
  87                 compiler->max_const_compute = 256;
  88         } else {
  89                 compiler->max_const_pipeline = 512;
  90                 compiler->max_const_geom = 512;
  91                 compiler->max_const_frag = 512;
  92                 compiler->max_const_compute = 512;
  93
  94                 /* Note: this will have to change if/when we support tess+GS on
  95                  * earlier gen's.
  96                  */
  97                 compiler->max_const_safe = 256;
  98         }
  99
 100         if (compiler->gpu_id >= 400) {
 101                 /* need special handling for "flat" */
 102                 compiler->flat_bypass = true;
 103                 compiler->levels_add_one = false;
 104                 compiler->unminify_coords = false;
 105                 compiler->txf_ms_with_isaml = false;
 106                 compiler->array_index_add_half = true;
 107                 compiler->const_upload_unit = 4;
 108         } else {
 109                 /* no special handling for "flat" */
 110                 compiler->flat_bypass = false;
 111                 compiler->levels_add_one = true;
 112                 compiler->unminify_coords = true;
 113                 compiler->txf_ms_with_isaml = true;
 114                 compiler->array_index_add_half = false;
 115                 compiler->const_upload_unit = 8;
 116         }
 117
 118         return compiler;
 119 }