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freedreno/ir3: add assert
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
633
634 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
635 cond->regs[0]->flags |= IR3_REG_HALF;
636
637 compile_assert(ctx, bs[1] == bs[2]);
638 /* Make sure the boolean condition has the same bit size as the other
639 * two arguments, adding a conversion if necessary.
640 */
641 if (bs[1] < bs[0])
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 else if (bs[1] > bs[0])
644 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
645
646 if (bs[1] > 16)
647 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
648 else
649 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
650 break;
651 }
652 case nir_op_bit_count: {
653 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
654 // double check on earlier gen's. Once half-precision support is
655 // in place, this should probably move to a NIR lowering pass:
656 struct ir3_instruction *hi, *lo;
657
658 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
659 TYPE_U32, TYPE_U16);
660 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
661
662 hi = ir3_CBITS_B(b, hi, 0);
663 lo = ir3_CBITS_B(b, lo, 0);
664
665 // TODO maybe the builders should default to making dst half-precision
666 // if the src's were half precision, to make this less awkward.. otoh
667 // we should probably just do this lowering in NIR.
668 hi->regs[0]->flags |= IR3_REG_HALF;
669 lo->regs[0]->flags |= IR3_REG_HALF;
670
671 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
672 dst[0]->regs[0]->flags |= IR3_REG_HALF;
673 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
674 break;
675 }
676 case nir_op_ifind_msb: {
677 struct ir3_instruction *cmp;
678 dst[0] = ir3_CLZ_S(b, src[0], 0);
679 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
680 cmp->cat2.condition = IR3_COND_GE;
681 dst[0] = ir3_SEL_B32(b,
682 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
683 cmp, 0, dst[0], 0);
684 break;
685 }
686 case nir_op_ufind_msb:
687 dst[0] = ir3_CLZ_B(b, src[0], 0);
688 dst[0] = ir3_SEL_B32(b,
689 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
690 src[0], 0, dst[0], 0);
691 break;
692 case nir_op_find_lsb:
693 dst[0] = ir3_BFREV_B(b, src[0], 0);
694 dst[0] = ir3_CLZ_B(b, dst[0], 0);
695 break;
696 case nir_op_bitfield_reverse:
697 dst[0] = ir3_BFREV_B(b, src[0], 0);
698 break;
699
700 default:
701 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
702 nir_op_infos[alu->op].name);
703 break;
704 }
705
706 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
707 assert(dst_sz == 1);
708
709 if (nir_dest_bit_size(alu->dest.dest) < 32)
710 dst[0]->regs[0]->flags |= IR3_REG_HALF;
711
712 dst[0] = ir3_n2b(b, dst[0]);
713 }
714
715 if (nir_dest_bit_size(alu->dest.dest) < 32) {
716 for (unsigned i = 0; i < dst_sz; i++) {
717 dst[i]->regs[0]->flags |= IR3_REG_HALF;
718 }
719 }
720
721 ir3_put_dst(ctx, &alu->dest.dest);
722 }
723
724 /* handles direct/indirect UBO reads: */
725 static void
726 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
727 struct ir3_instruction **dst)
728 {
729 struct ir3_block *b = ctx->block;
730 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
731 /* UBO addresses are the first driver params, but subtract 2 here to
732 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
733 * is the uniforms: */
734 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
735 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
736 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
737
738 int off = 0;
739
740 /* First src is ubo index, which could either be an immed or not: */
741 src0 = ir3_get_src(ctx, &intr->src[0])[0];
742 if (is_same_type_mov(src0) &&
743 (src0->regs[1]->flags & IR3_REG_IMMED)) {
744 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
745 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
746 } else {
747 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
748 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
749
750 /* NOTE: since relative addressing is used, make sure constlen is
751 * at least big enough to cover all the UBO addresses, since the
752 * assembler won't know what the max address reg is.
753 */
754 ctx->so->constlen = MAX2(ctx->so->constlen,
755 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
756 }
757
758 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
759 addr = base_lo;
760
761 if (nir_src_is_const(intr->src[1])) {
762 off += nir_src_as_uint(intr->src[1]);
763 } else {
764 /* For load_ubo_indirect, second src is indirect offset: */
765 src1 = ir3_get_src(ctx, &intr->src[1])[0];
766
767 /* and add offset to addr: */
768 addr = ir3_ADD_S(b, addr, 0, src1, 0);
769 }
770
771 /* if offset is to large to encode in the ldg, split it out: */
772 if ((off + (intr->num_components * 4)) > 1024) {
773 /* split out the minimal amount to improve the odds that
774 * cp can fit the immediate in the add.s instruction:
775 */
776 unsigned off2 = off + (intr->num_components * 4) - 1024;
777 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
778 off -= off2;
779 }
780
781 if (ptrsz == 2) {
782 struct ir3_instruction *carry;
783
784 /* handle 32b rollover, ie:
785 * if (addr < base_lo)
786 * base_hi++
787 */
788 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
789 carry->cat2.condition = IR3_COND_LT;
790 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
791
792 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
793 }
794
795 for (int i = 0; i < intr->num_components; i++) {
796 struct ir3_instruction *load =
797 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
798 create_immed(b, off + i * 4), 0);
799 load->cat6.type = TYPE_U32;
800 dst[i] = load;
801 }
802 }
803
804 /* src[] = { block_index } */
805 static void
806 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
807 struct ir3_instruction **dst)
808 {
809 /* SSBO size stored as a const starting at ssbo_sizes: */
810 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
811 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
812 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
813 const_state->ssbo_size.off[blk_idx];
814
815 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
816
817 dst[0] = create_uniform(ctx->block, idx);
818 }
819
820 /* src[] = { offset }. const_index[] = { base } */
821 static void
822 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
823 struct ir3_instruction **dst)
824 {
825 struct ir3_block *b = ctx->block;
826 struct ir3_instruction *ldl, *offset;
827 unsigned base;
828
829 offset = ir3_get_src(ctx, &intr->src[0])[0];
830 base = nir_intrinsic_base(intr);
831
832 ldl = ir3_LDL(b, offset, 0,
833 create_immed(b, intr->num_components), 0,
834 create_immed(b, base), 0);
835
836 ldl->cat6.type = utype_dst(intr->dest);
837 ldl->regs[0]->wrmask = MASK(intr->num_components);
838
839 ldl->barrier_class = IR3_BARRIER_SHARED_R;
840 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
841
842 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
843 }
844
845 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
846 static void
847 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
848 {
849 struct ir3_block *b = ctx->block;
850 struct ir3_instruction *stl, *offset;
851 struct ir3_instruction * const *value;
852 unsigned base, wrmask;
853
854 value = ir3_get_src(ctx, &intr->src[0]);
855 offset = ir3_get_src(ctx, &intr->src[1])[0];
856
857 base = nir_intrinsic_base(intr);
858 wrmask = nir_intrinsic_write_mask(intr);
859
860 /* Combine groups of consecutive enabled channels in one write
861 * message. We use ffs to find the first enabled channel and then ffs on
862 * the bit-inverse, down-shifted writemask to determine the length of
863 * the block of enabled bits.
864 *
865 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
866 */
867 while (wrmask) {
868 unsigned first_component = ffs(wrmask) - 1;
869 unsigned length = ffs(~(wrmask >> first_component)) - 1;
870
871 stl = ir3_STL(b, offset, 0,
872 ir3_create_collect(ctx, &value[first_component], length), 0,
873 create_immed(b, length), 0);
874 stl->cat6.dst_offset = first_component + base;
875 stl->cat6.type = utype_src(intr->src[0]);
876 stl->barrier_class = IR3_BARRIER_SHARED_W;
877 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
878
879 array_insert(b, b->keeps, stl);
880
881 /* Clear the bits in the writemask that we just wrote, then try
882 * again to see if more channels are left.
883 */
884 wrmask &= (15 << (first_component + length));
885 }
886 }
887
888 /* src[] = { offset }. const_index[] = { base } */
889 static void
890 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
891 struct ir3_instruction **dst)
892 {
893 struct ir3_block *b = ctx->block;
894 struct ir3_instruction *load, *offset;
895 unsigned base;
896
897 offset = ir3_get_src(ctx, &intr->src[0])[0];
898 base = nir_intrinsic_base(intr);
899
900 load = ir3_LDLW(b, offset, 0,
901 create_immed(b, intr->num_components), 0,
902 create_immed(b, base), 0);
903
904 load->cat6.type = utype_dst(intr->dest);
905 load->regs[0]->wrmask = MASK(intr->num_components);
906
907 load->barrier_class = IR3_BARRIER_SHARED_R;
908 load->barrier_conflict = IR3_BARRIER_SHARED_W;
909
910 ir3_split_dest(b, dst, load, 0, intr->num_components);
911 }
912
913 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
914 static void
915 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
916 {
917 struct ir3_block *b = ctx->block;
918 struct ir3_instruction *store, *offset;
919 struct ir3_instruction * const *value;
920 unsigned base, wrmask;
921
922 value = ir3_get_src(ctx, &intr->src[0]);
923 offset = ir3_get_src(ctx, &intr->src[1])[0];
924
925 base = nir_intrinsic_base(intr);
926 wrmask = nir_intrinsic_write_mask(intr);
927
928 /* Combine groups of consecutive enabled channels in one write
929 * message. We use ffs to find the first enabled channel and then ffs on
930 * the bit-inverse, down-shifted writemask to determine the length of
931 * the block of enabled bits.
932 *
933 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
934 */
935 while (wrmask) {
936 unsigned first_component = ffs(wrmask) - 1;
937 unsigned length = ffs(~(wrmask >> first_component)) - 1;
938
939 store = ir3_STLW(b, offset, 0,
940 ir3_create_collect(ctx, &value[first_component], length), 0,
941 create_immed(b, length), 0);
942
943 store->cat6.dst_offset = first_component + base;
944 store->cat6.type = utype_src(intr->src[0]);
945 store->barrier_class = IR3_BARRIER_SHARED_W;
946 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
947
948 array_insert(b, b->keeps, store);
949
950 /* Clear the bits in the writemask that we just wrote, then try
951 * again to see if more channels are left.
952 */
953 wrmask &= (15 << (first_component + length));
954 }
955 }
956
957 /*
958 * CS shared variable atomic intrinsics
959 *
960 * All of the shared variable atomic memory operations read a value from
961 * memory, compute a new value using one of the operations below, write the
962 * new value to memory, and return the original value read.
963 *
964 * All operations take 2 sources except CompSwap that takes 3. These
965 * sources represent:
966 *
967 * 0: The offset into the shared variable storage region that the atomic
968 * operation will operate on.
969 * 1: The data parameter to the atomic function (i.e. the value to add
970 * in shared_atomic_add, etc).
971 * 2: For CompSwap only: the second data parameter.
972 */
973 static struct ir3_instruction *
974 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
975 {
976 struct ir3_block *b = ctx->block;
977 struct ir3_instruction *atomic, *src0, *src1;
978 type_t type = TYPE_U32;
979
980 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
981 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
982
983 switch (intr->intrinsic) {
984 case nir_intrinsic_shared_atomic_add:
985 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
986 break;
987 case nir_intrinsic_shared_atomic_imin:
988 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
989 type = TYPE_S32;
990 break;
991 case nir_intrinsic_shared_atomic_umin:
992 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
993 break;
994 case nir_intrinsic_shared_atomic_imax:
995 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
996 type = TYPE_S32;
997 break;
998 case nir_intrinsic_shared_atomic_umax:
999 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1000 break;
1001 case nir_intrinsic_shared_atomic_and:
1002 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1003 break;
1004 case nir_intrinsic_shared_atomic_or:
1005 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_xor:
1008 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_exchange:
1011 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1012 break;
1013 case nir_intrinsic_shared_atomic_comp_swap:
1014 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1015 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1016 ir3_get_src(ctx, &intr->src[2])[0],
1017 src1,
1018 }, 2);
1019 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1020 break;
1021 default:
1022 unreachable("boo");
1023 }
1024
1025 atomic->cat6.iim_val = 1;
1026 atomic->cat6.d = 1;
1027 atomic->cat6.type = type;
1028 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1029 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1030
1031 /* even if nothing consume the result, we can't DCE the instruction: */
1032 array_insert(b, b->keeps, atomic);
1033
1034 return atomic;
1035 }
1036
1037 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1038 * to handle with the image_mapping table..
1039 */
1040 static struct ir3_instruction *
1041 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1042 {
1043 unsigned slot = nir_src_as_uint(intr->src[0]);
1044 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1045 struct ir3_instruction *texture, *sampler;
1046
1047 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1048 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1049
1050 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1051 sampler,
1052 texture,
1053 }, 2);
1054 }
1055
1056 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1057 static void
1058 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1059 struct ir3_instruction **dst)
1060 {
1061 struct ir3_block *b = ctx->block;
1062 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1063 struct ir3_instruction *sam;
1064 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1065 struct ir3_instruction *coords[4];
1066 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1067 type_t type = ir3_get_type_for_image_intrinsic(intr);
1068
1069 /* hmm, this seems a bit odd, but it is what blob does and (at least
1070 * a5xx) just faults on bogus addresses otherwise:
1071 */
1072 if (flags & IR3_INSTR_3D) {
1073 flags &= ~IR3_INSTR_3D;
1074 flags |= IR3_INSTR_A;
1075 }
1076
1077 for (unsigned i = 0; i < ncoords; i++)
1078 coords[i] = src0[i];
1079
1080 if (ncoords == 1)
1081 coords[ncoords++] = create_immed(b, 0);
1082
1083 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1084 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1085
1086 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1087 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1088
1089 ir3_split_dest(b, dst, sam, 0, 4);
1090 }
1091
1092 static void
1093 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1094 struct ir3_instruction **dst)
1095 {
1096 struct ir3_block *b = ctx->block;
1097 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1098 struct ir3_instruction *sam, *lod;
1099 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1100 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1101 TYPE_U16 : TYPE_U32;
1102
1103 lod = create_immed(b, 0);
1104 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1105 samp_tex, lod, NULL);
1106
1107 /* Array size actually ends up in .w rather than .z. This doesn't
1108 * matter for miplevel 0, but for higher mips the value in z is
1109 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1110 * returned, which means that we have to add 1 to it for arrays for
1111 * a3xx.
1112 *
1113 * Note use a temporary dst and then copy, since the size of the dst
1114 * array that is passed in is based on nir's understanding of the
1115 * result size, not the hardware's
1116 */
1117 struct ir3_instruction *tmp[4];
1118
1119 ir3_split_dest(b, tmp, sam, 0, 4);
1120
1121 /* get_size instruction returns size in bytes instead of texels
1122 * for imageBuffer, so we need to divide it by the pixel size
1123 * of the image format.
1124 *
1125 * TODO: This is at least true on a5xx. Check other gens.
1126 */
1127 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1128 /* Since all the possible values the divisor can take are
1129 * power-of-two (4, 8, or 16), the division is implemented
1130 * as a shift-right.
1131 * During shader setup, the log2 of the image format's
1132 * bytes-per-pixel should have been emitted in 2nd slot of
1133 * image_dims. See ir3_shader::emit_image_dims().
1134 */
1135 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1136 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1137 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1138 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1139
1140 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1141 }
1142
1143 for (unsigned i = 0; i < ncoords; i++)
1144 dst[i] = tmp[i];
1145
1146 if (flags & IR3_INSTR_A) {
1147 if (ctx->compiler->levels_add_one) {
1148 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1149 } else {
1150 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1151 }
1152 }
1153 }
1154
1155 static void
1156 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1157 {
1158 struct ir3_block *b = ctx->block;
1159 struct ir3_instruction *barrier;
1160
1161 switch (intr->intrinsic) {
1162 case nir_intrinsic_control_barrier:
1163 barrier = ir3_BAR(b);
1164 barrier->cat7.g = true;
1165 barrier->cat7.l = true;
1166 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1167 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1168 break;
1169 case nir_intrinsic_memory_barrier:
1170 barrier = ir3_FENCE(b);
1171 barrier->cat7.g = true;
1172 barrier->cat7.r = true;
1173 barrier->cat7.w = true;
1174 barrier->cat7.l = true;
1175 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1176 IR3_BARRIER_BUFFER_W;
1177 barrier->barrier_conflict =
1178 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1179 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1180 break;
1181 case nir_intrinsic_memory_barrier_buffer:
1182 barrier = ir3_FENCE(b);
1183 barrier->cat7.g = true;
1184 barrier->cat7.r = true;
1185 barrier->cat7.w = true;
1186 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1187 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1188 IR3_BARRIER_BUFFER_W;
1189 break;
1190 case nir_intrinsic_memory_barrier_image:
1191 // TODO double check if this should have .g set
1192 barrier = ir3_FENCE(b);
1193 barrier->cat7.g = true;
1194 barrier->cat7.r = true;
1195 barrier->cat7.w = true;
1196 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1197 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1198 IR3_BARRIER_IMAGE_W;
1199 break;
1200 case nir_intrinsic_memory_barrier_shared:
1201 barrier = ir3_FENCE(b);
1202 barrier->cat7.g = true;
1203 barrier->cat7.l = true;
1204 barrier->cat7.r = true;
1205 barrier->cat7.w = true;
1206 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1207 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1208 IR3_BARRIER_SHARED_W;
1209 break;
1210 case nir_intrinsic_group_memory_barrier:
1211 barrier = ir3_FENCE(b);
1212 barrier->cat7.g = true;
1213 barrier->cat7.l = true;
1214 barrier->cat7.r = true;
1215 barrier->cat7.w = true;
1216 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1217 IR3_BARRIER_IMAGE_W |
1218 IR3_BARRIER_BUFFER_W;
1219 barrier->barrier_conflict =
1220 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1221 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1222 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1223 break;
1224 default:
1225 unreachable("boo");
1226 }
1227
1228 /* make sure barrier doesn't get DCE'd */
1229 array_insert(b, b->keeps, barrier);
1230 }
1231
1232 static void add_sysval_input_compmask(struct ir3_context *ctx,
1233 gl_system_value slot, unsigned compmask,
1234 struct ir3_instruction *instr)
1235 {
1236 struct ir3_shader_variant *so = ctx->so;
1237 unsigned n = so->inputs_count++;
1238
1239 assert(instr->opc == OPC_META_INPUT);
1240 instr->input.inidx = n;
1241 instr->input.sysval = slot;
1242
1243 so->inputs[n].sysval = true;
1244 so->inputs[n].slot = slot;
1245 so->inputs[n].compmask = compmask;
1246 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1247 so->total_in++;
1248 }
1249
1250 static struct ir3_instruction *
1251 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1252 unsigned compmask)
1253 {
1254 assert(compmask);
1255 struct ir3_instruction *sysval = create_input(ctx, compmask);
1256 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1257 return sysval;
1258 }
1259
1260 static struct ir3_instruction *
1261 get_barycentric_centroid(struct ir3_context *ctx)
1262 {
1263 if (!ctx->ij_centroid) {
1264 struct ir3_instruction *xy[2];
1265 struct ir3_instruction *ij;
1266
1267 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1268 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1269
1270 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1271 }
1272
1273 return ctx->ij_centroid;
1274 }
1275
1276 static struct ir3_instruction *
1277 get_barycentric_sample(struct ir3_context *ctx)
1278 {
1279 if (!ctx->ij_sample) {
1280 struct ir3_instruction *xy[2];
1281 struct ir3_instruction *ij;
1282
1283 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1284 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1285
1286 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1287 }
1288
1289 return ctx->ij_sample;
1290 }
1291
1292 static struct ir3_instruction *
1293 get_barycentric_pixel(struct ir3_context *ctx)
1294 {
1295 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1296 * this to create ij_pixel only on demand:
1297 */
1298 return ctx->ij_pixel;
1299 }
1300
1301 static struct ir3_instruction *
1302 get_frag_coord(struct ir3_context *ctx)
1303 {
1304 if (!ctx->frag_coord) {
1305 struct ir3_block *b = ctx->in_block;
1306 struct ir3_instruction *xyzw[4];
1307 struct ir3_instruction *hw_frag_coord;
1308
1309 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1310 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1311
1312 /* for frag_coord.xy, we get unsigned values.. we need
1313 * to subtract (integer) 8 and divide by 16 (right-
1314 * shift by 4) then convert to float:
1315 *
1316 * sub.s tmp, src, 8
1317 * shr.b tmp, tmp, 4
1318 * mov.u32f32 dst, tmp
1319 *
1320 */
1321 for (int i = 0; i < 2; i++) {
1322 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1323 create_immed(b, 8), 0);
1324 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1325 create_immed(b, 4), 0);
1326 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1327 }
1328
1329 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1330 ctx->so->frag_coord = true;
1331 }
1332
1333 return ctx->frag_coord;
1334 }
1335
1336 static void
1337 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1338 {
1339 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1340 struct ir3_instruction **dst;
1341 struct ir3_instruction * const *src;
1342 struct ir3_block *b = ctx->block;
1343 int idx, comp;
1344
1345 if (info->has_dest) {
1346 unsigned n = nir_intrinsic_dest_components(intr);
1347 dst = ir3_get_dst(ctx, &intr->dest, n);
1348 } else {
1349 dst = NULL;
1350 }
1351
1352 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1353 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1354
1355 switch (intr->intrinsic) {
1356 case nir_intrinsic_load_uniform:
1357 idx = nir_intrinsic_base(intr);
1358 if (nir_src_is_const(intr->src[0])) {
1359 idx += nir_src_as_uint(intr->src[0]);
1360 for (int i = 0; i < intr->num_components; i++) {
1361 dst[i] = create_uniform_typed(b, idx + i,
1362 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1363 }
1364 } else {
1365 src = ir3_get_src(ctx, &intr->src[0]);
1366 for (int i = 0; i < intr->num_components; i++) {
1367 dst[i] = create_uniform_indirect(b, idx + i,
1368 ir3_get_addr(ctx, src[0], 1));
1369 }
1370 /* NOTE: if relative addressing is used, we set
1371 * constlen in the compiler (to worst-case value)
1372 * since we don't know in the assembler what the max
1373 * addr reg value can be:
1374 */
1375 ctx->so->constlen = MAX2(ctx->so->constlen,
1376 ctx->so->shader->ubo_state.size / 16);
1377 }
1378 break;
1379
1380 case nir_intrinsic_load_vs_primitive_stride_ir3:
1381 dst[0] = create_uniform(b, primitive_param + 0);
1382 break;
1383 case nir_intrinsic_load_vs_vertex_stride_ir3:
1384 dst[0] = create_uniform(b, primitive_param + 1);
1385 break;
1386 case nir_intrinsic_load_hs_patch_stride_ir3:
1387 dst[0] = create_uniform(b, primitive_param + 2);
1388 break;
1389 case nir_intrinsic_load_patch_vertices_in:
1390 dst[0] = create_uniform(b, primitive_param + 3);
1391 break;
1392 case nir_intrinsic_load_tess_param_base_ir3:
1393 dst[0] = create_uniform(b, primitive_param + 4);
1394 dst[1] = create_uniform(b, primitive_param + 5);
1395 break;
1396 case nir_intrinsic_load_tess_factor_base_ir3:
1397 dst[0] = create_uniform(b, primitive_param + 6);
1398 dst[1] = create_uniform(b, primitive_param + 7);
1399 break;
1400
1401 case nir_intrinsic_load_primitive_location_ir3:
1402 idx = nir_intrinsic_driver_location(intr);
1403 dst[0] = create_uniform(b, primitive_map + idx);
1404 break;
1405
1406 case nir_intrinsic_load_gs_header_ir3:
1407 dst[0] = ctx->gs_header;
1408 break;
1409 case nir_intrinsic_load_tcs_header_ir3:
1410 dst[0] = ctx->tcs_header;
1411 break;
1412
1413 case nir_intrinsic_load_primitive_id:
1414 dst[0] = ctx->primitive_id;
1415 break;
1416
1417 case nir_intrinsic_load_tess_coord:
1418 if (!ctx->tess_coord) {
1419 ctx->tess_coord =
1420 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1421 }
1422 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1423
1424 /* Unused, but ir3_put_dst() below wants to free something */
1425 dst[2] = create_immed(b, 0);
1426 break;
1427
1428 case nir_intrinsic_end_patch_ir3:
1429 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1430 struct ir3_instruction *end = ir3_ENDIF(b);
1431 array_insert(b, b->keeps, end);
1432
1433 end->barrier_class = IR3_BARRIER_EVERYTHING;
1434 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1435 break;
1436
1437 case nir_intrinsic_store_global_ir3: {
1438 struct ir3_instruction *value, *addr, *offset;
1439
1440 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1441 ir3_get_src(ctx, &intr->src[1])[0],
1442 ir3_get_src(ctx, &intr->src[1])[1]
1443 }, 2);
1444
1445 offset = ir3_get_src(ctx, &intr->src[2])[0];
1446
1447 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1448 intr->num_components);
1449
1450 struct ir3_instruction *stg =
1451 ir3_STG_G(ctx->block, addr, 0, value, 0,
1452 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1453 stg->cat6.type = TYPE_U32;
1454 stg->cat6.iim_val = 1;
1455
1456 array_insert(b, b->keeps, stg);
1457
1458 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1459 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1460 break;
1461 }
1462
1463 case nir_intrinsic_load_global_ir3: {
1464 struct ir3_instruction *addr, *offset;
1465
1466 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1467 ir3_get_src(ctx, &intr->src[0])[0],
1468 ir3_get_src(ctx, &intr->src[0])[1]
1469 }, 2);
1470
1471 offset = ir3_get_src(ctx, &intr->src[1])[0];
1472
1473 struct ir3_instruction *load =
1474 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1475 0, offset, 0);
1476 load->cat6.type = TYPE_U32;
1477 load->regs[0]->wrmask = MASK(intr->num_components);
1478
1479 load->barrier_class = IR3_BARRIER_BUFFER_R;
1480 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1481
1482 ir3_split_dest(b, dst, load, 0, intr->num_components);
1483 break;
1484 }
1485
1486 case nir_intrinsic_load_ubo:
1487 emit_intrinsic_load_ubo(ctx, intr, dst);
1488 break;
1489 case nir_intrinsic_load_frag_coord:
1490 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1491 break;
1492 case nir_intrinsic_load_sample_pos_from_id: {
1493 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1494 * but that doesn't seem necessary.
1495 */
1496 struct ir3_instruction *offset =
1497 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1498 offset->regs[0]->wrmask = 0x3;
1499 offset->cat5.type = TYPE_F32;
1500
1501 ir3_split_dest(b, dst, offset, 0, 2);
1502
1503 break;
1504 }
1505 case nir_intrinsic_load_size_ir3:
1506 if (!ctx->ij_size) {
1507 ctx->ij_size =
1508 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1509 }
1510 dst[0] = ctx->ij_size;
1511 break;
1512 case nir_intrinsic_load_barycentric_centroid:
1513 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1514 break;
1515 case nir_intrinsic_load_barycentric_sample:
1516 if (ctx->so->key.msaa) {
1517 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1518 } else {
1519 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1520 }
1521 break;
1522 case nir_intrinsic_load_barycentric_pixel:
1523 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1524 break;
1525 case nir_intrinsic_load_interpolated_input:
1526 idx = nir_intrinsic_base(intr);
1527 comp = nir_intrinsic_component(intr);
1528 src = ir3_get_src(ctx, &intr->src[0]);
1529 if (nir_src_is_const(intr->src[1])) {
1530 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1531 idx += nir_src_as_uint(intr->src[1]);
1532 for (int i = 0; i < intr->num_components; i++) {
1533 unsigned inloc = idx * 4 + i + comp;
1534 if (ctx->so->inputs[idx].bary &&
1535 !ctx->so->inputs[idx].use_ldlv) {
1536 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1537 } else {
1538 /* for non-varyings use the pre-setup input, since
1539 * that is easier than mapping things back to a
1540 * nir_variable to figure out what it is.
1541 */
1542 dst[i] = ctx->inputs[inloc];
1543 compile_assert(ctx, dst[i]);
1544 }
1545 }
1546 } else {
1547 ir3_context_error(ctx, "unhandled");
1548 }
1549 break;
1550 case nir_intrinsic_load_input:
1551 idx = nir_intrinsic_base(intr);
1552 comp = nir_intrinsic_component(intr);
1553 if (nir_src_is_const(intr->src[0])) {
1554 idx += nir_src_as_uint(intr->src[0]);
1555 for (int i = 0; i < intr->num_components; i++) {
1556 unsigned n = idx * 4 + i + comp;
1557 dst[i] = ctx->inputs[n];
1558 compile_assert(ctx, ctx->inputs[n]);
1559 }
1560 } else {
1561 src = ir3_get_src(ctx, &intr->src[0]);
1562 struct ir3_instruction *collect =
1563 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1564 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1565 for (int i = 0; i < intr->num_components; i++) {
1566 unsigned n = idx * 4 + i + comp;
1567 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1568 n, addr, collect);
1569 }
1570 }
1571 break;
1572 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1573 * pass and replaced by an ir3-specifc version that adds the
1574 * dword-offset in the last source.
1575 */
1576 case nir_intrinsic_load_ssbo_ir3:
1577 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1578 break;
1579 case nir_intrinsic_store_ssbo_ir3:
1580 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1581 !ctx->s->info.fs.early_fragment_tests)
1582 ctx->so->no_earlyz = true;
1583 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1584 break;
1585 case nir_intrinsic_get_buffer_size:
1586 emit_intrinsic_ssbo_size(ctx, intr, dst);
1587 break;
1588 case nir_intrinsic_ssbo_atomic_add_ir3:
1589 case nir_intrinsic_ssbo_atomic_imin_ir3:
1590 case nir_intrinsic_ssbo_atomic_umin_ir3:
1591 case nir_intrinsic_ssbo_atomic_imax_ir3:
1592 case nir_intrinsic_ssbo_atomic_umax_ir3:
1593 case nir_intrinsic_ssbo_atomic_and_ir3:
1594 case nir_intrinsic_ssbo_atomic_or_ir3:
1595 case nir_intrinsic_ssbo_atomic_xor_ir3:
1596 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1597 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1598 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1599 !ctx->s->info.fs.early_fragment_tests)
1600 ctx->so->no_earlyz = true;
1601 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1602 break;
1603 case nir_intrinsic_load_shared:
1604 emit_intrinsic_load_shared(ctx, intr, dst);
1605 break;
1606 case nir_intrinsic_store_shared:
1607 emit_intrinsic_store_shared(ctx, intr);
1608 break;
1609 case nir_intrinsic_shared_atomic_add:
1610 case nir_intrinsic_shared_atomic_imin:
1611 case nir_intrinsic_shared_atomic_umin:
1612 case nir_intrinsic_shared_atomic_imax:
1613 case nir_intrinsic_shared_atomic_umax:
1614 case nir_intrinsic_shared_atomic_and:
1615 case nir_intrinsic_shared_atomic_or:
1616 case nir_intrinsic_shared_atomic_xor:
1617 case nir_intrinsic_shared_atomic_exchange:
1618 case nir_intrinsic_shared_atomic_comp_swap:
1619 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1620 break;
1621 case nir_intrinsic_image_load:
1622 emit_intrinsic_load_image(ctx, intr, dst);
1623 break;
1624 case nir_intrinsic_image_store:
1625 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1626 !ctx->s->info.fs.early_fragment_tests)
1627 ctx->so->no_earlyz = true;
1628 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1629 break;
1630 case nir_intrinsic_image_size:
1631 emit_intrinsic_image_size(ctx, intr, dst);
1632 break;
1633 case nir_intrinsic_image_atomic_add:
1634 case nir_intrinsic_image_atomic_imin:
1635 case nir_intrinsic_image_atomic_umin:
1636 case nir_intrinsic_image_atomic_imax:
1637 case nir_intrinsic_image_atomic_umax:
1638 case nir_intrinsic_image_atomic_and:
1639 case nir_intrinsic_image_atomic_or:
1640 case nir_intrinsic_image_atomic_xor:
1641 case nir_intrinsic_image_atomic_exchange:
1642 case nir_intrinsic_image_atomic_comp_swap:
1643 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1644 !ctx->s->info.fs.early_fragment_tests)
1645 ctx->so->no_earlyz = true;
1646 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1647 break;
1648 case nir_intrinsic_control_barrier:
1649 case nir_intrinsic_memory_barrier:
1650 case nir_intrinsic_group_memory_barrier:
1651 case nir_intrinsic_memory_barrier_buffer:
1652 case nir_intrinsic_memory_barrier_image:
1653 case nir_intrinsic_memory_barrier_shared:
1654 emit_intrinsic_barrier(ctx, intr);
1655 /* note that blk ptr no longer valid, make that obvious: */
1656 b = NULL;
1657 break;
1658 case nir_intrinsic_store_output:
1659 idx = nir_intrinsic_base(intr);
1660 comp = nir_intrinsic_component(intr);
1661 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1662 idx += nir_src_as_uint(intr->src[1]);
1663
1664 src = ir3_get_src(ctx, &intr->src[0]);
1665 for (int i = 0; i < intr->num_components; i++) {
1666 unsigned n = idx * 4 + i + comp;
1667 ctx->outputs[n] = src[i];
1668 }
1669 break;
1670 case nir_intrinsic_load_base_vertex:
1671 case nir_intrinsic_load_first_vertex:
1672 if (!ctx->basevertex) {
1673 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1674 }
1675 dst[0] = ctx->basevertex;
1676 break;
1677 case nir_intrinsic_load_base_instance:
1678 if (!ctx->base_instance) {
1679 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1680 }
1681 dst[0] = ctx->base_instance;
1682 break;
1683 case nir_intrinsic_load_vertex_id_zero_base:
1684 case nir_intrinsic_load_vertex_id:
1685 if (!ctx->vertex_id) {
1686 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1687 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1688 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1689 }
1690 dst[0] = ctx->vertex_id;
1691 break;
1692 case nir_intrinsic_load_instance_id:
1693 if (!ctx->instance_id) {
1694 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1695 }
1696 dst[0] = ctx->instance_id;
1697 break;
1698 case nir_intrinsic_load_sample_id:
1699 ctx->so->per_samp = true;
1700 /* fall-thru */
1701 case nir_intrinsic_load_sample_id_no_per_sample:
1702 if (!ctx->samp_id) {
1703 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1704 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1705 }
1706 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1707 break;
1708 case nir_intrinsic_load_sample_mask_in:
1709 if (!ctx->samp_mask_in) {
1710 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1711 }
1712 dst[0] = ctx->samp_mask_in;
1713 break;
1714 case nir_intrinsic_load_user_clip_plane:
1715 idx = nir_intrinsic_ucp_id(intr);
1716 for (int i = 0; i < intr->num_components; i++) {
1717 unsigned n = idx * 4 + i;
1718 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1719 }
1720 break;
1721 case nir_intrinsic_load_front_face:
1722 if (!ctx->frag_face) {
1723 ctx->so->frag_face = true;
1724 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1725 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1726 }
1727 /* for fragface, we get -1 for back and 0 for front. However this is
1728 * the inverse of what nir expects (where ~0 is true).
1729 */
1730 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1731 dst[0] = ir3_NOT_B(b, dst[0], 0);
1732 break;
1733 case nir_intrinsic_load_local_invocation_id:
1734 if (!ctx->local_invocation_id) {
1735 ctx->local_invocation_id =
1736 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1737 }
1738 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1739 break;
1740 case nir_intrinsic_load_work_group_id:
1741 if (!ctx->work_group_id) {
1742 ctx->work_group_id =
1743 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1744 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1745 }
1746 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1747 break;
1748 case nir_intrinsic_load_num_work_groups:
1749 for (int i = 0; i < intr->num_components; i++) {
1750 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1751 }
1752 break;
1753 case nir_intrinsic_load_local_group_size:
1754 for (int i = 0; i < intr->num_components; i++) {
1755 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1756 }
1757 break;
1758 case nir_intrinsic_discard_if:
1759 case nir_intrinsic_discard: {
1760 struct ir3_instruction *cond, *kill;
1761
1762 if (intr->intrinsic == nir_intrinsic_discard_if) {
1763 /* conditional discard: */
1764 src = ir3_get_src(ctx, &intr->src[0]);
1765 cond = ir3_b2n(b, src[0]);
1766 } else {
1767 /* unconditional discard: */
1768 cond = create_immed(b, 1);
1769 }
1770
1771 /* NOTE: only cmps.*.* can write p0.x: */
1772 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1773 cond->cat2.condition = IR3_COND_NE;
1774
1775 /* condition always goes in predicate register: */
1776 cond->regs[0]->num = regid(REG_P0, 0);
1777 cond->regs[0]->flags &= ~IR3_REG_SSA;
1778
1779 kill = ir3_KILL(b, cond, 0);
1780 kill->regs[1]->num = regid(REG_P0, 0);
1781 array_insert(ctx->ir, ctx->ir->predicates, kill);
1782
1783 array_insert(b, b->keeps, kill);
1784 ctx->so->no_earlyz = true;
1785
1786 break;
1787 }
1788
1789 case nir_intrinsic_cond_end_ir3: {
1790 struct ir3_instruction *cond, *kill;
1791
1792 src = ir3_get_src(ctx, &intr->src[0]);
1793 cond = ir3_b2n(b, src[0]);
1794
1795 /* NOTE: only cmps.*.* can write p0.x: */
1796 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1797 cond->cat2.condition = IR3_COND_NE;
1798
1799 /* condition always goes in predicate register: */
1800 cond->regs[0]->num = regid(REG_P0, 0);
1801
1802 kill = ir3_IF(b, cond, 0);
1803
1804 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1805 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1806
1807 array_insert(ctx->ir, ctx->ir->predicates, kill);
1808 array_insert(b, b->keeps, kill);
1809 break;
1810 }
1811
1812 case nir_intrinsic_load_shared_ir3:
1813 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1814 break;
1815 case nir_intrinsic_store_shared_ir3:
1816 emit_intrinsic_store_shared_ir3(ctx, intr);
1817 break;
1818 default:
1819 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1820 nir_intrinsic_infos[intr->intrinsic].name);
1821 break;
1822 }
1823
1824 if (info->has_dest)
1825 ir3_put_dst(ctx, &intr->dest);
1826 }
1827
1828 static void
1829 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1830 {
1831 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1832 instr->def.num_components);
1833
1834 if (instr->def.bit_size < 32) {
1835 for (int i = 0; i < instr->def.num_components; i++)
1836 dst[i] = create_immed_typed(ctx->block,
1837 instr->value[i].u16,
1838 TYPE_U16);
1839 } else {
1840 for (int i = 0; i < instr->def.num_components; i++)
1841 dst[i] = create_immed_typed(ctx->block,
1842 instr->value[i].u32,
1843 TYPE_U32);
1844 }
1845
1846 }
1847
1848 static void
1849 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1850 {
1851 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1852 undef->def.num_components);
1853 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1854
1855 /* backend doesn't want undefined instructions, so just plug
1856 * in 0.0..
1857 */
1858 for (int i = 0; i < undef->def.num_components; i++)
1859 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1860 }
1861
1862 /*
1863 * texture fetch/sample instructions:
1864 */
1865
1866 static type_t
1867 get_tex_dest_type(nir_tex_instr *tex)
1868 {
1869 type_t type;
1870
1871 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1872 case nir_type_invalid:
1873 case nir_type_float:
1874 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1875 break;
1876 case nir_type_int:
1877 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1878 break;
1879 case nir_type_uint:
1880 case nir_type_bool:
1881 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1882 break;
1883 default:
1884 unreachable("bad dest_type");
1885 }
1886
1887 return type;
1888 }
1889
1890 static void
1891 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1892 {
1893 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
1894 unsigned flags = 0;
1895
1896 /* note: would use tex->coord_components.. except txs.. also,
1897 * since array index goes after shadow ref, we don't want to
1898 * count it:
1899 */
1900 if (coords == 3)
1901 flags |= IR3_INSTR_3D;
1902
1903 if (tex->is_shadow && tex->op != nir_texop_lod)
1904 flags |= IR3_INSTR_S;
1905
1906 if (tex->is_array && tex->op != nir_texop_lod)
1907 flags |= IR3_INSTR_A;
1908
1909 *flagsp = flags;
1910 *coordsp = coords;
1911 }
1912
1913 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1914 * or immediate (in which case it will get lowered later to a non .s2en
1915 * version of the tex instruction which encode tex/samp as immediates:
1916 */
1917 static struct ir3_instruction *
1918 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1919 {
1920 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1921 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1922 struct ir3_instruction *texture, *sampler;
1923
1924 if (texture_idx >= 0) {
1925 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1926 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1927 } else {
1928 /* TODO what to do for dynamic case? I guess we only need the
1929 * max index for astc srgb workaround so maybe not a problem
1930 * to worry about if we don't enable indirect samplers for
1931 * a4xx?
1932 */
1933 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1934 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1935 }
1936
1937 if (sampler_idx >= 0) {
1938 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1939 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1940 } else {
1941 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1942 }
1943
1944 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1945 sampler,
1946 texture,
1947 }, 2);
1948 }
1949
1950 static void
1951 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1952 {
1953 struct ir3_block *b = ctx->block;
1954 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1955 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1956 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1957 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1958 unsigned i, coords, flags, ncomp;
1959 unsigned nsrc0 = 0, nsrc1 = 0;
1960 type_t type;
1961 opc_t opc = 0;
1962
1963 ncomp = nir_dest_num_components(tex->dest);
1964
1965 coord = off = ddx = ddy = NULL;
1966 lod = proj = compare = sample_index = NULL;
1967
1968 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1969
1970 for (unsigned i = 0; i < tex->num_srcs; i++) {
1971 switch (tex->src[i].src_type) {
1972 case nir_tex_src_coord:
1973 coord = ir3_get_src(ctx, &tex->src[i].src);
1974 break;
1975 case nir_tex_src_bias:
1976 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1977 has_bias = true;
1978 break;
1979 case nir_tex_src_lod:
1980 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1981 has_lod = true;
1982 break;
1983 case nir_tex_src_comparator: /* shadow comparator */
1984 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1985 break;
1986 case nir_tex_src_projector:
1987 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1988 has_proj = true;
1989 break;
1990 case nir_tex_src_offset:
1991 off = ir3_get_src(ctx, &tex->src[i].src);
1992 has_off = true;
1993 break;
1994 case nir_tex_src_ddx:
1995 ddx = ir3_get_src(ctx, &tex->src[i].src);
1996 break;
1997 case nir_tex_src_ddy:
1998 ddy = ir3_get_src(ctx, &tex->src[i].src);
1999 break;
2000 case nir_tex_src_ms_index:
2001 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2002 break;
2003 case nir_tex_src_texture_offset:
2004 case nir_tex_src_sampler_offset:
2005 /* handled in get_tex_samp_src() */
2006 break;
2007 default:
2008 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2009 tex->src[i].src_type);
2010 return;
2011 }
2012 }
2013
2014 switch (tex->op) {
2015 case nir_texop_tex_prefetch:
2016 compile_assert(ctx, !has_bias);
2017 compile_assert(ctx, !has_lod);
2018 compile_assert(ctx, !compare);
2019 compile_assert(ctx, !has_proj);
2020 compile_assert(ctx, !has_off);
2021 compile_assert(ctx, !ddx);
2022 compile_assert(ctx, !ddy);
2023 compile_assert(ctx, !sample_index);
2024 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2025 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2026
2027 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2028 opc = OPC_META_TEX_PREFETCH;
2029 ctx->so->num_sampler_prefetch++;
2030 break;
2031 }
2032 /* fallthru */
2033 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2034 case nir_texop_txb: opc = OPC_SAMB; break;
2035 case nir_texop_txl: opc = OPC_SAML; break;
2036 case nir_texop_txd: opc = OPC_SAMGQ; break;
2037 case nir_texop_txf: opc = OPC_ISAML; break;
2038 case nir_texop_lod: opc = OPC_GETLOD; break;
2039 case nir_texop_tg4:
2040 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2041 * what blob does, seems gather is broken?), and a3xx did
2042 * not support it (but probably could also emulate).
2043 */
2044 switch (tex->component) {
2045 case 0: opc = OPC_GATHER4R; break;
2046 case 1: opc = OPC_GATHER4G; break;
2047 case 2: opc = OPC_GATHER4B; break;
2048 case 3: opc = OPC_GATHER4A; break;
2049 }
2050 break;
2051 case nir_texop_txf_ms_fb:
2052 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2053 default:
2054 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2055 return;
2056 }
2057
2058 tex_info(tex, &flags, &coords);
2059
2060 /*
2061 * lay out the first argument in the proper order:
2062 * - actual coordinates first
2063 * - shadow reference
2064 * - array index
2065 * - projection w
2066 * - starting at offset 4, dpdx.xy, dpdy.xy
2067 *
2068 * bias/lod go into the second arg
2069 */
2070
2071 /* insert tex coords: */
2072 for (i = 0; i < coords; i++)
2073 src0[i] = coord[i];
2074
2075 nsrc0 = i;
2076
2077 /* scale up integer coords for TXF based on the LOD */
2078 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2079 assert(has_lod);
2080 for (i = 0; i < coords; i++)
2081 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2082 }
2083
2084 if (coords == 1) {
2085 /* hw doesn't do 1d, so we treat it as 2d with
2086 * height of 1, and patch up the y coord.
2087 */
2088 if (is_isam(opc)) {
2089 src0[nsrc0++] = create_immed(b, 0);
2090 } else {
2091 src0[nsrc0++] = create_immed(b, fui(0.5));
2092 }
2093 }
2094
2095 if (tex->is_shadow && tex->op != nir_texop_lod)
2096 src0[nsrc0++] = compare;
2097
2098 if (tex->is_array && tex->op != nir_texop_lod) {
2099 struct ir3_instruction *idx = coord[coords];
2100
2101 /* the array coord for cube arrays needs 0.5 added to it */
2102 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2103 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2104
2105 src0[nsrc0++] = idx;
2106 }
2107
2108 if (has_proj) {
2109 src0[nsrc0++] = proj;
2110 flags |= IR3_INSTR_P;
2111 }
2112
2113 /* pad to 4, then ddx/ddy: */
2114 if (tex->op == nir_texop_txd) {
2115 while (nsrc0 < 4)
2116 src0[nsrc0++] = create_immed(b, fui(0.0));
2117 for (i = 0; i < coords; i++)
2118 src0[nsrc0++] = ddx[i];
2119 if (coords < 2)
2120 src0[nsrc0++] = create_immed(b, fui(0.0));
2121 for (i = 0; i < coords; i++)
2122 src0[nsrc0++] = ddy[i];
2123 if (coords < 2)
2124 src0[nsrc0++] = create_immed(b, fui(0.0));
2125 }
2126
2127 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2128 * with scaled x coord according to requested sample:
2129 */
2130 if (opc == OPC_ISAMM) {
2131 if (ctx->compiler->txf_ms_with_isaml) {
2132 /* the samples are laid out in x dimension as
2133 * 0 1 2 3
2134 * x_ms = (x << ms) + sample_index;
2135 */
2136 struct ir3_instruction *ms;
2137 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2138
2139 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2140 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2141
2142 opc = OPC_ISAML;
2143 } else {
2144 src0[nsrc0++] = sample_index;
2145 }
2146 }
2147
2148 /*
2149 * second argument (if applicable):
2150 * - offsets
2151 * - lod
2152 * - bias
2153 */
2154 if (has_off | has_lod | has_bias) {
2155 if (has_off) {
2156 unsigned off_coords = coords;
2157 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2158 off_coords--;
2159 for (i = 0; i < off_coords; i++)
2160 src1[nsrc1++] = off[i];
2161 if (off_coords < 2)
2162 src1[nsrc1++] = create_immed(b, fui(0.0));
2163 flags |= IR3_INSTR_O;
2164 }
2165
2166 if (has_lod | has_bias)
2167 src1[nsrc1++] = lod;
2168 }
2169
2170 type = get_tex_dest_type(tex);
2171
2172 if (opc == OPC_GETLOD)
2173 type = TYPE_S32;
2174
2175 struct ir3_instruction *samp_tex;
2176
2177 if (tex->op == nir_texop_txf_ms_fb) {
2178 /* only expect a single txf_ms_fb per shader: */
2179 compile_assert(ctx, !ctx->so->fb_read);
2180 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2181
2182 ctx->so->fb_read = true;
2183 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2184 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2185 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2186 }, 2);
2187
2188 ctx->so->num_samp++;
2189 } else {
2190 samp_tex = get_tex_samp_tex_src(ctx, tex);
2191 }
2192
2193 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2194 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2195
2196 if (opc == OPC_META_TEX_PREFETCH) {
2197 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2198
2199 compile_assert(ctx, tex->src[idx].src.is_ssa);
2200
2201 sam = ir3_META_TEX_PREFETCH(b);
2202 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2203 sam->prefetch.input_offset =
2204 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2205 sam->prefetch.tex = tex->texture_index;
2206 sam->prefetch.samp = tex->sampler_index;
2207 } else {
2208 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2209 samp_tex, col0, col1);
2210 }
2211
2212 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2213 assert(opc != OPC_META_TEX_PREFETCH);
2214
2215 /* only need first 3 components: */
2216 sam->regs[0]->wrmask = 0x7;
2217 ir3_split_dest(b, dst, sam, 0, 3);
2218
2219 /* we need to sample the alpha separately with a non-ASTC
2220 * texture state:
2221 */
2222 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2223 samp_tex, col0, col1);
2224
2225 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2226
2227 /* fixup .w component: */
2228 ir3_split_dest(b, &dst[3], sam, 3, 1);
2229 } else {
2230 /* normal (non-workaround) case: */
2231 ir3_split_dest(b, dst, sam, 0, ncomp);
2232 }
2233
2234 /* GETLOD returns results in 4.8 fixed point */
2235 if (opc == OPC_GETLOD) {
2236 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2237
2238 compile_assert(ctx, tex->dest_type == nir_type_float);
2239 for (i = 0; i < 2; i++) {
2240 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2241 factor, 0);
2242 }
2243 }
2244
2245 ir3_put_dst(ctx, &tex->dest);
2246 }
2247
2248 static void
2249 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2250 {
2251 struct ir3_block *b = ctx->block;
2252 struct ir3_instruction **dst, *sam;
2253 type_t dst_type = get_tex_dest_type(tex);
2254
2255 dst = ir3_get_dst(ctx, &tex->dest, 1);
2256
2257 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2258 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2259
2260 /* even though there is only one component, since it ends
2261 * up in .y/.z/.w rather than .x, we need a split_dest()
2262 */
2263 if (idx)
2264 ir3_split_dest(b, dst, sam, 0, idx + 1);
2265
2266 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2267 * the value in TEX_CONST_0 is zero-based.
2268 */
2269 if (ctx->compiler->levels_add_one)
2270 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2271
2272 ir3_put_dst(ctx, &tex->dest);
2273 }
2274
2275 static void
2276 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2277 {
2278 struct ir3_block *b = ctx->block;
2279 struct ir3_instruction **dst, *sam;
2280 struct ir3_instruction *lod;
2281 unsigned flags, coords;
2282 type_t dst_type = get_tex_dest_type(tex);
2283
2284 tex_info(tex, &flags, &coords);
2285
2286 /* Actually we want the number of dimensions, not coordinates. This
2287 * distinction only matters for cubes.
2288 */
2289 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2290 coords = 2;
2291
2292 dst = ir3_get_dst(ctx, &tex->dest, 4);
2293
2294 compile_assert(ctx, tex->num_srcs == 1);
2295 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2296
2297 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2298
2299 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2300 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2301
2302 ir3_split_dest(b, dst, sam, 0, 4);
2303
2304 /* Array size actually ends up in .w rather than .z. This doesn't
2305 * matter for miplevel 0, but for higher mips the value in z is
2306 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2307 * returned, which means that we have to add 1 to it for arrays.
2308 */
2309 if (tex->is_array) {
2310 if (ctx->compiler->levels_add_one) {
2311 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2312 } else {
2313 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2314 }
2315 }
2316
2317 ir3_put_dst(ctx, &tex->dest);
2318 }
2319
2320 static void
2321 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2322 {
2323 switch (jump->type) {
2324 case nir_jump_break:
2325 case nir_jump_continue:
2326 case nir_jump_return:
2327 /* I *think* we can simply just ignore this, and use the
2328 * successor block link to figure out where we need to
2329 * jump to for break/continue
2330 */
2331 break;
2332 default:
2333 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2334 break;
2335 }
2336 }
2337
2338 static void
2339 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2340 {
2341 switch (instr->type) {
2342 case nir_instr_type_alu:
2343 emit_alu(ctx, nir_instr_as_alu(instr));
2344 break;
2345 case nir_instr_type_deref:
2346 /* ignored, handled as part of the intrinsic they are src to */
2347 break;
2348 case nir_instr_type_intrinsic:
2349 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2350 break;
2351 case nir_instr_type_load_const:
2352 emit_load_const(ctx, nir_instr_as_load_const(instr));
2353 break;
2354 case nir_instr_type_ssa_undef:
2355 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2356 break;
2357 case nir_instr_type_tex: {
2358 nir_tex_instr *tex = nir_instr_as_tex(instr);
2359 /* couple tex instructions get special-cased:
2360 */
2361 switch (tex->op) {
2362 case nir_texop_txs:
2363 emit_tex_txs(ctx, tex);
2364 break;
2365 case nir_texop_query_levels:
2366 emit_tex_info(ctx, tex, 2);
2367 break;
2368 case nir_texop_texture_samples:
2369 emit_tex_info(ctx, tex, 3);
2370 break;
2371 default:
2372 emit_tex(ctx, tex);
2373 break;
2374 }
2375 break;
2376 }
2377 case nir_instr_type_jump:
2378 emit_jump(ctx, nir_instr_as_jump(instr));
2379 break;
2380 case nir_instr_type_phi:
2381 /* we have converted phi webs to regs in NIR by now */
2382 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2383 break;
2384 case nir_instr_type_call:
2385 case nir_instr_type_parallel_copy:
2386 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2387 break;
2388 }
2389 }
2390
2391 static struct ir3_block *
2392 get_block(struct ir3_context *ctx, const nir_block *nblock)
2393 {
2394 struct ir3_block *block;
2395 struct hash_entry *hentry;
2396
2397 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2398 if (hentry)
2399 return hentry->data;
2400
2401 block = ir3_block_create(ctx->ir);
2402 block->nblock = nblock;
2403 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2404
2405 block->predecessors = _mesa_pointer_set_create(block);
2406 set_foreach(nblock->predecessors, sentry) {
2407 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2408 }
2409
2410 return block;
2411 }
2412
2413 static void
2414 emit_block(struct ir3_context *ctx, nir_block *nblock)
2415 {
2416 struct ir3_block *block = get_block(ctx, nblock);
2417
2418 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2419 if (nblock->successors[i]) {
2420 block->successors[i] =
2421 get_block(ctx, nblock->successors[i]);
2422 }
2423 }
2424
2425 ctx->block = block;
2426 list_addtail(&block->node, &ctx->ir->block_list);
2427
2428 /* re-emit addr register in each block if needed: */
2429 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2430 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2431 ctx->addr_ht[i] = NULL;
2432 }
2433
2434 nir_foreach_instr(instr, nblock) {
2435 ctx->cur_instr = instr;
2436 emit_instr(ctx, instr);
2437 ctx->cur_instr = NULL;
2438 if (ctx->error)
2439 return;
2440 }
2441 }
2442
2443 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2444
2445 static void
2446 emit_if(struct ir3_context *ctx, nir_if *nif)
2447 {
2448 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2449
2450 ctx->block->condition =
2451 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2452
2453 emit_cf_list(ctx, &nif->then_list);
2454 emit_cf_list(ctx, &nif->else_list);
2455 }
2456
2457 static void
2458 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2459 {
2460 emit_cf_list(ctx, &nloop->body);
2461 ctx->so->loops++;
2462 }
2463
2464 static void
2465 stack_push(struct ir3_context *ctx)
2466 {
2467 ctx->stack++;
2468 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2469 }
2470
2471 static void
2472 stack_pop(struct ir3_context *ctx)
2473 {
2474 compile_assert(ctx, ctx->stack > 0);
2475 ctx->stack--;
2476 }
2477
2478 static void
2479 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2480 {
2481 foreach_list_typed(nir_cf_node, node, node, list) {
2482 switch (node->type) {
2483 case nir_cf_node_block:
2484 emit_block(ctx, nir_cf_node_as_block(node));
2485 break;
2486 case nir_cf_node_if:
2487 stack_push(ctx);
2488 emit_if(ctx, nir_cf_node_as_if(node));
2489 stack_pop(ctx);
2490 break;
2491 case nir_cf_node_loop:
2492 stack_push(ctx);
2493 emit_loop(ctx, nir_cf_node_as_loop(node));
2494 stack_pop(ctx);
2495 break;
2496 case nir_cf_node_function:
2497 ir3_context_error(ctx, "TODO\n");
2498 break;
2499 }
2500 }
2501 }
2502
2503 /* emit stream-out code. At this point, the current block is the original
2504 * (nir) end block, and nir ensures that all flow control paths terminate
2505 * into the end block. We re-purpose the original end block to generate
2506 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2507 * block holding stream-out write instructions, followed by the new end
2508 * block:
2509 *
2510 * blockOrigEnd {
2511 * p0.x = (vtxcnt < maxvtxcnt)
2512 * // succs: blockStreamOut, blockNewEnd
2513 * }
2514 * blockStreamOut {
2515 * ... stream-out instructions ...
2516 * // succs: blockNewEnd
2517 * }
2518 * blockNewEnd {
2519 * }
2520 */
2521 static void
2522 emit_stream_out(struct ir3_context *ctx)
2523 {
2524 struct ir3 *ir = ctx->ir;
2525 struct ir3_stream_output_info *strmout =
2526 &ctx->so->shader->stream_output;
2527 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2528 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2529 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2530
2531 /* create vtxcnt input in input block at top of shader,
2532 * so that it is seen as live over the entire duration
2533 * of the shader:
2534 */
2535 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2536 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2537
2538 /* at this point, we are at the original 'end' block,
2539 * re-purpose this block to stream-out condition, then
2540 * append stream-out block and new-end block
2541 */
2542 orig_end_block = ctx->block;
2543
2544 // TODO these blocks need to update predecessors..
2545 // maybe w/ store_global intrinsic, we could do this
2546 // stuff in nir->nir pass
2547
2548 stream_out_block = ir3_block_create(ir);
2549 list_addtail(&stream_out_block->node, &ir->block_list);
2550
2551 new_end_block = ir3_block_create(ir);
2552 list_addtail(&new_end_block->node, &ir->block_list);
2553
2554 orig_end_block->successors[0] = stream_out_block;
2555 orig_end_block->successors[1] = new_end_block;
2556 stream_out_block->successors[0] = new_end_block;
2557
2558 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2559 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2560 cond->regs[0]->num = regid(REG_P0, 0);
2561 cond->regs[0]->flags &= ~IR3_REG_SSA;
2562 cond->cat2.condition = IR3_COND_LT;
2563
2564 /* condition goes on previous block to the conditional,
2565 * since it is used to pick which of the two successor
2566 * paths to take:
2567 */
2568 orig_end_block->condition = cond;
2569
2570 /* switch to stream_out_block to generate the stream-out
2571 * instructions:
2572 */
2573 ctx->block = stream_out_block;
2574
2575 /* Calculate base addresses based on vtxcnt. Instructions
2576 * generated for bases not used in following loop will be
2577 * stripped out in the backend.
2578 */
2579 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2580 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2581 unsigned stride = strmout->stride[i];
2582 struct ir3_instruction *base, *off;
2583
2584 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2585
2586 /* 24-bit should be enough: */
2587 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2588 create_immed(ctx->block, stride * 4), 0);
2589
2590 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2591 }
2592
2593 /* Generate the per-output store instructions: */
2594 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2595 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2596 unsigned c = j + strmout->output[i].start_component;
2597 struct ir3_instruction *base, *out, *stg;
2598
2599 base = bases[strmout->output[i].output_buffer];
2600 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2601
2602 stg = ir3_STG(ctx->block, base, 0, out, 0,
2603 create_immed(ctx->block, 1), 0);
2604 stg->cat6.type = TYPE_U32;
2605 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2606
2607 array_insert(ctx->block, ctx->block->keeps, stg);
2608 }
2609 }
2610
2611 /* and finally switch to the new_end_block: */
2612 ctx->block = new_end_block;
2613 }
2614
2615 static void
2616 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2617 {
2618 nir_metadata_require(impl, nir_metadata_block_index);
2619
2620 compile_assert(ctx, ctx->stack == 0);
2621
2622 emit_cf_list(ctx, &impl->body);
2623 emit_block(ctx, impl->end_block);
2624
2625 compile_assert(ctx, ctx->stack == 0);
2626
2627 /* at this point, we should have a single empty block,
2628 * into which we emit the 'end' instruction.
2629 */
2630 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2631
2632 /* If stream-out (aka transform-feedback) enabled, emit the
2633 * stream-out instructions, followed by a new empty block (into
2634 * which the 'end' instruction lands).
2635 *
2636 * NOTE: it is done in this order, rather than inserting before
2637 * we emit end_block, because NIR guarantees that all blocks
2638 * flow into end_block, and that end_block has no successors.
2639 * So by re-purposing end_block as the first block of stream-
2640 * out, we guarantee that all exit paths flow into the stream-
2641 * out instructions.
2642 */
2643 if ((ctx->compiler->gpu_id < 500) &&
2644 (ctx->so->shader->stream_output.num_outputs > 0) &&
2645 !ctx->so->binning_pass) {
2646 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2647 emit_stream_out(ctx);
2648 }
2649
2650 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2651 * NOP and has an epilogue that writes the VS outputs to local storage, to
2652 * be read by the HS. Then it resets execution mask (chmask) and chains
2653 * to the next shader (chsh).
2654 */
2655 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2656 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2657 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2658 struct ir3_instruction *chmask =
2659 ir3_CHMASK(ctx->block);
2660 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2661 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2662
2663 struct ir3_instruction *chsh =
2664 ir3_CHSH(ctx->block);
2665 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2666 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2667 } else {
2668 ir3_END(ctx->block);
2669 }
2670 }
2671
2672 static void
2673 setup_input(struct ir3_context *ctx, nir_variable *in)
2674 {
2675 struct ir3_shader_variant *so = ctx->so;
2676 unsigned ncomp = glsl_get_components(in->type);
2677 unsigned n = in->data.driver_location;
2678 unsigned frac = in->data.location_frac;
2679 unsigned slot = in->data.location;
2680
2681 /* Inputs are loaded using ldlw or ldg for these stages. */
2682 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2683 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2684 ctx->so->type == MESA_SHADER_GEOMETRY)
2685 return;
2686
2687 /* skip unread inputs, we could end up with (for example), unsplit
2688 * matrix/etc inputs in the case they are not read, so just silently
2689 * skip these.
2690 */
2691 if (ncomp > 4)
2692 return;
2693
2694 so->inputs[n].slot = slot;
2695 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2696 so->inputs_count = MAX2(so->inputs_count, n + 1);
2697 so->inputs[n].interpolate = in->data.interpolation;
2698
2699 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2700
2701 /* if any varyings have 'sample' qualifer, that triggers us
2702 * to run in per-sample mode:
2703 */
2704 so->per_samp |= in->data.sample;
2705
2706 for (int i = 0; i < ncomp; i++) {
2707 struct ir3_instruction *instr = NULL;
2708 unsigned idx = (n * 4) + i + frac;
2709
2710 if (slot == VARYING_SLOT_POS) {
2711 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2712 } else if (slot == VARYING_SLOT_PNTC) {
2713 /* see for example st_nir_fixup_varying_slots().. this is
2714 * maybe a bit mesa/st specific. But we need things to line
2715 * up for this in fdN_program:
2716 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2717 * if (emit->sprite_coord_enable & texmask) {
2718 * ...
2719 * }
2720 */
2721 so->inputs[n].slot = VARYING_SLOT_VAR8;
2722 so->inputs[n].bary = true;
2723 instr = create_frag_input(ctx, false, idx);
2724 } else {
2725 /* detect the special case for front/back colors where
2726 * we need to do flat vs smooth shading depending on
2727 * rast state:
2728 */
2729 if (in->data.interpolation == INTERP_MODE_NONE) {
2730 switch (slot) {
2731 case VARYING_SLOT_COL0:
2732 case VARYING_SLOT_COL1:
2733 case VARYING_SLOT_BFC0:
2734 case VARYING_SLOT_BFC1:
2735 so->inputs[n].rasterflat = true;
2736 break;
2737 default:
2738 break;
2739 }
2740 }
2741
2742 if (ctx->compiler->flat_bypass) {
2743 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2744 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2745 so->inputs[n].use_ldlv = true;
2746 }
2747
2748 so->inputs[n].bary = true;
2749
2750 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2751 }
2752
2753 compile_assert(ctx, idx < ctx->ninputs);
2754
2755 ctx->inputs[idx] = instr;
2756 }
2757 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2758 struct ir3_instruction *input = NULL, *in;
2759 struct ir3_instruction *components[4];
2760 unsigned mask = (1 << (ncomp + frac)) - 1;
2761
2762 foreach_input(in, ctx->ir) {
2763 if (in->input.inidx == n) {
2764 input = in;
2765 break;
2766 }
2767 }
2768
2769 if (!input) {
2770 input = create_input(ctx, mask);
2771 input->input.inidx = n;
2772 } else {
2773 input->regs[0]->wrmask |= mask;
2774 }
2775
2776 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2777
2778 for (int i = 0; i < ncomp; i++) {
2779 unsigned idx = (n * 4) + i + frac;
2780 compile_assert(ctx, idx < ctx->ninputs);
2781 ctx->inputs[idx] = components[i];
2782 }
2783 } else {
2784 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2785 }
2786
2787 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2788 so->total_in += ncomp;
2789 }
2790 }
2791
2792 /* Initially we assign non-packed inloc's for varyings, as we don't really
2793 * know up-front which components will be unused. After all the compilation
2794 * stages we scan the shader to see which components are actually used, and
2795 * re-pack the inlocs to eliminate unneeded varyings.
2796 */
2797 static void
2798 pack_inlocs(struct ir3_context *ctx)
2799 {
2800 struct ir3_shader_variant *so = ctx->so;
2801 uint8_t used_components[so->inputs_count];
2802
2803 memset(used_components, 0, sizeof(used_components));
2804
2805 /*
2806 * First Step: scan shader to find which bary.f/ldlv remain:
2807 */
2808
2809 foreach_block (block, &ctx->ir->block_list) {
2810 foreach_instr (instr, &block->instr_list) {
2811 if (is_input(instr)) {
2812 unsigned inloc = instr->regs[1]->iim_val;
2813 unsigned i = inloc / 4;
2814 unsigned j = inloc % 4;
2815
2816 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2817 compile_assert(ctx, i < so->inputs_count);
2818
2819 used_components[i] |= 1 << j;
2820 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2821 for (int n = 0; n < 2; n++) {
2822 unsigned inloc = instr->prefetch.input_offset + n;
2823 unsigned i = inloc / 4;
2824 unsigned j = inloc % 4;
2825
2826 compile_assert(ctx, i < so->inputs_count);
2827
2828 used_components[i] |= 1 << j;
2829 }
2830 }
2831 }
2832 }
2833
2834 /*
2835 * Second Step: reassign varying inloc/slots:
2836 */
2837
2838 unsigned actual_in = 0;
2839 unsigned inloc = 0;
2840
2841 for (unsigned i = 0; i < so->inputs_count; i++) {
2842 unsigned compmask = 0, maxcomp = 0;
2843
2844 so->inputs[i].inloc = inloc;
2845 so->inputs[i].bary = false;
2846
2847 for (unsigned j = 0; j < 4; j++) {
2848 if (!(used_components[i] & (1 << j)))
2849 continue;
2850
2851 compmask |= (1 << j);
2852 actual_in++;
2853 maxcomp = j + 1;
2854
2855 /* at this point, since used_components[i] mask is only
2856 * considering varyings (ie. not sysvals) we know this
2857 * is a varying:
2858 */
2859 so->inputs[i].bary = true;
2860 }
2861
2862 if (so->inputs[i].bary) {
2863 so->varying_in++;
2864 so->inputs[i].compmask = (1 << maxcomp) - 1;
2865 inloc += maxcomp;
2866 }
2867 }
2868
2869 /*
2870 * Third Step: reassign packed inloc's:
2871 */
2872
2873 foreach_block (block, &ctx->ir->block_list) {
2874 foreach_instr (instr, &block->instr_list) {
2875 if (is_input(instr)) {
2876 unsigned inloc = instr->regs[1]->iim_val;
2877 unsigned i = inloc / 4;
2878 unsigned j = inloc % 4;
2879
2880 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2881 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2882 unsigned i = instr->prefetch.input_offset / 4;
2883 unsigned j = instr->prefetch.input_offset % 4;
2884 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2885 }
2886 }
2887 }
2888 }
2889
2890 static void
2891 setup_output(struct ir3_context *ctx, nir_variable *out)
2892 {
2893 struct ir3_shader_variant *so = ctx->so;
2894 unsigned ncomp = glsl_get_components(out->type);
2895 unsigned n = out->data.driver_location;
2896 unsigned frac = out->data.location_frac;
2897 unsigned slot = out->data.location;
2898 unsigned comp = 0;
2899
2900 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2901 switch (slot) {
2902 case FRAG_RESULT_DEPTH:
2903 comp = 2; /* tgsi will write to .z component */
2904 so->writes_pos = true;
2905 break;
2906 case FRAG_RESULT_COLOR:
2907 so->color0_mrt = 1;
2908 break;
2909 case FRAG_RESULT_SAMPLE_MASK:
2910 so->writes_smask = true;
2911 break;
2912 default:
2913 if (slot >= FRAG_RESULT_DATA0)
2914 break;
2915 ir3_context_error(ctx, "unknown FS output name: %s\n",
2916 gl_frag_result_name(slot));
2917 }
2918 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2919 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2920 ctx->so->type == MESA_SHADER_GEOMETRY) {
2921 switch (slot) {
2922 case VARYING_SLOT_POS:
2923 so->writes_pos = true;
2924 break;
2925 case VARYING_SLOT_PSIZ:
2926 so->writes_psize = true;
2927 break;
2928 case VARYING_SLOT_PRIMITIVE_ID:
2929 case VARYING_SLOT_LAYER:
2930 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2931 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2932 /* fall through */
2933 case VARYING_SLOT_COL0:
2934 case VARYING_SLOT_COL1:
2935 case VARYING_SLOT_BFC0:
2936 case VARYING_SLOT_BFC1:
2937 case VARYING_SLOT_FOGC:
2938 case VARYING_SLOT_CLIP_DIST0:
2939 case VARYING_SLOT_CLIP_DIST1:
2940 case VARYING_SLOT_CLIP_VERTEX:
2941 break;
2942 default:
2943 if (slot >= VARYING_SLOT_VAR0)
2944 break;
2945 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2946 break;
2947 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2948 _mesa_shader_stage_to_string(ctx->so->type),
2949 gl_varying_slot_name(slot));
2950 }
2951 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2952 /* output lowered to buffer writes. */
2953 return;
2954 } else {
2955 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2956 }
2957
2958 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2959
2960 so->outputs[n].slot = slot;
2961 so->outputs[n].regid = regid(n, comp);
2962 so->outputs_count = MAX2(so->outputs_count, n + 1);
2963
2964 for (int i = 0; i < ncomp; i++) {
2965 unsigned idx = (n * 4) + i + frac;
2966 compile_assert(ctx, idx < ctx->noutputs);
2967 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2968 }
2969
2970 /* if varying packing doesn't happen, we could end up in a situation
2971 * with "holes" in the output, and since the per-generation code that
2972 * sets up varying linkage registers doesn't expect to have more than
2973 * one varying per vec4 slot, pad the holes.
2974 *
2975 * Note that this should probably generate a performance warning of
2976 * some sort.
2977 */
2978 for (int i = 0; i < frac; i++) {
2979 unsigned idx = (n * 4) + i;
2980 if (!ctx->outputs[idx]) {
2981 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2982 }
2983 }
2984 }
2985
2986 static int
2987 max_drvloc(struct exec_list *vars)
2988 {
2989 int drvloc = -1;
2990 nir_foreach_variable(var, vars) {
2991 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2992 }
2993 return drvloc;
2994 }
2995
2996 static void
2997 emit_instructions(struct ir3_context *ctx)
2998 {
2999 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3000
3001 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3002 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3003
3004 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3005 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3006
3007 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3008
3009 /* Create inputs in first block: */
3010 ctx->block = get_block(ctx, nir_start_block(fxn));
3011 ctx->in_block = ctx->block;
3012 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3013
3014 /* for fragment shader, the vcoord input register is used as the
3015 * base for bary.f varying fetch instrs:
3016 *
3017 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3018 * until emit_intrinsic when we know they are actually needed.
3019 * For now, we defer creating ctx->ij_centroid, etc, since we
3020 * only need ij_pixel for "old style" varying inputs (ie.
3021 * tgsi_to_nir)
3022 */
3023 struct ir3_instruction *vcoord = NULL;
3024 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3025 struct ir3_instruction *xy[2];
3026
3027 vcoord = create_input(ctx, 0x3);
3028 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3029
3030 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3031 }
3032
3033 /* Setup inputs: */
3034 nir_foreach_variable(var, &ctx->s->inputs) {
3035 setup_input(ctx, var);
3036 }
3037
3038 /* Defer add_sysval_input() stuff until after setup_inputs(),
3039 * because sysvals need to be appended after varyings:
3040 */
3041 if (vcoord) {
3042 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3043 0x3, vcoord);
3044 }
3045
3046
3047 /* Tesselation shaders always need primitive ID for indexing the
3048 * BO. Geometry shaders don't always need it but when they do it has be
3049 * delivered and unclobbered in the VS. To make things easy, we always
3050 * make room for it in VS/DS.
3051 */
3052 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3053 bool has_gs = ctx->so->key.has_gs;
3054 switch (ctx->so->type) {
3055 case MESA_SHADER_VERTEX:
3056 if (has_tess) {
3057 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3058 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3059 } else if (has_gs) {
3060 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3061 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3062 }
3063 break;
3064 case MESA_SHADER_TESS_CTRL:
3065 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3066 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3067 break;
3068 case MESA_SHADER_TESS_EVAL:
3069 if (has_gs)
3070 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3071 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3072 break;
3073 case MESA_SHADER_GEOMETRY:
3074 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3075 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3076 break;
3077 default:
3078 break;
3079 }
3080
3081 /* Setup outputs: */
3082 nir_foreach_variable(var, &ctx->s->outputs) {
3083 setup_output(ctx, var);
3084 }
3085
3086 /* Find # of samplers: */
3087 nir_foreach_variable(var, &ctx->s->uniforms) {
3088 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3089 /* just assume that we'll be reading from images.. if it
3090 * is write-only we don't have to count it, but not sure
3091 * if there is a good way to know?
3092 */
3093 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3094 }
3095
3096 /* NOTE: need to do something more clever when we support >1 fxn */
3097 nir_foreach_register(reg, &fxn->registers) {
3098 ir3_declare_array(ctx, reg);
3099 }
3100 /* And emit the body: */
3101 ctx->impl = fxn;
3102 emit_function(ctx, fxn);
3103 }
3104
3105 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3106 * need to assign the tex state indexes for these after we know the
3107 * max tex index.
3108 */
3109 static void
3110 fixup_astc_srgb(struct ir3_context *ctx)
3111 {
3112 struct ir3_shader_variant *so = ctx->so;
3113 /* indexed by original tex idx, value is newly assigned alpha sampler
3114 * state tex idx. Zero is invalid since there is at least one sampler
3115 * if we get here.
3116 */
3117 unsigned alt_tex_state[16] = {0};
3118 unsigned tex_idx = ctx->max_texture_index + 1;
3119 unsigned idx = 0;
3120
3121 so->astc_srgb.base = tex_idx;
3122
3123 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3124 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3125
3126 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3127
3128 if (alt_tex_state[sam->cat5.tex] == 0) {
3129 /* assign new alternate/alpha tex state slot: */
3130 alt_tex_state[sam->cat5.tex] = tex_idx++;
3131 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3132 so->astc_srgb.count++;
3133 }
3134
3135 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3136 }
3137 }
3138
3139 static void
3140 fixup_binning_pass(struct ir3_context *ctx)
3141 {
3142 struct ir3_shader_variant *so = ctx->so;
3143 struct ir3 *ir = ctx->ir;
3144 unsigned i, j;
3145
3146 /* first pass, remove unused outputs from the IR level outputs: */
3147 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3148 struct ir3_instruction *out = ir->outputs[i];
3149 assert(out->opc == OPC_META_COLLECT);
3150 unsigned outidx = out->collect.outidx;
3151 unsigned slot = so->outputs[outidx].slot;
3152
3153 /* throw away everything but first position/psize */
3154 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3155 ir->outputs[j] = ir->outputs[i];
3156 j++;
3157 }
3158 }
3159 ir->outputs_count = j;
3160
3161 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3162 * table:
3163 */
3164 for (i = 0, j = 0; i < so->outputs_count; i++) {
3165 unsigned slot = so->outputs[i].slot;
3166
3167 /* throw away everything but first position/psize */
3168 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3169 so->outputs[j] = so->outputs[i];
3170
3171 /* fixup outidx to point to new output table entry: */
3172 struct ir3_instruction *out;
3173 foreach_output(out, ir) {
3174 if (out->collect.outidx == i) {
3175 out->collect.outidx = j;
3176 break;
3177 }
3178 }
3179
3180 j++;
3181 }
3182 }
3183 so->outputs_count = j;
3184 }
3185
3186 static void
3187 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3188 {
3189 unsigned idx = 0;
3190
3191 /* Collect sampling instructions eligible for pre-dispatch. */
3192 foreach_block (block, &ir->block_list) {
3193 foreach_instr_safe (instr, &block->instr_list) {
3194 if (instr->opc == OPC_META_TEX_PREFETCH) {
3195 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3196 struct ir3_sampler_prefetch *fetch =
3197 &ctx->so->sampler_prefetch[idx];
3198 idx++;
3199
3200 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3201 fetch->wrmask = instr->regs[0]->wrmask;
3202 fetch->tex_id = instr->prefetch.tex;
3203 fetch->samp_id = instr->prefetch.samp;
3204 fetch->dst = instr->regs[0]->num;
3205 fetch->src = instr->prefetch.input_offset;
3206
3207 ctx->so->total_in =
3208 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3209
3210 /* Disable half precision until supported. */
3211 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3212
3213 /* Remove the prefetch placeholder instruction: */
3214 list_delinit(&instr->node);
3215 }
3216 }
3217 }
3218 }
3219
3220 int
3221 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3222 struct ir3_shader_variant *so)
3223 {
3224 struct ir3_context *ctx;
3225 struct ir3 *ir;
3226 int ret = 0, max_bary;
3227
3228 assert(!so->ir);
3229
3230 ctx = ir3_context_init(compiler, so);
3231 if (!ctx) {
3232 DBG("INIT failed!");
3233 ret = -1;
3234 goto out;
3235 }
3236
3237 emit_instructions(ctx);
3238
3239 if (ctx->error) {
3240 DBG("EMIT failed!");
3241 ret = -1;
3242 goto out;
3243 }
3244
3245 ir = so->ir = ctx->ir;
3246
3247 assert((ctx->noutputs % 4) == 0);
3248
3249 /* Setup IR level outputs, which are "collects" that gather
3250 * the scalar components of outputs.
3251 */
3252 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3253 unsigned ncomp = 0;
3254 /* figure out the # of components written:
3255 *
3256 * TODO do we need to handle holes, ie. if .x and .z
3257 * components written, but .y component not written?
3258 */
3259 for (unsigned j = 0; j < 4; j++) {
3260 if (!ctx->outputs[i + j])
3261 break;
3262 ncomp++;
3263 }
3264
3265 /* Note that in some stages, like TCS, store_output is
3266 * lowered to memory writes, so no components of the
3267 * are "written" from the PoV of traditional store-
3268 * output instructions:
3269 */
3270 if (!ncomp)
3271 continue;
3272
3273 struct ir3_instruction *out =
3274 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3275
3276 int outidx = i / 4;
3277 assert(outidx < so->outputs_count);
3278
3279 /* stash index into so->outputs[] so we can map the
3280 * output back to slot/etc later:
3281 */
3282 out->collect.outidx = outidx;
3283
3284 array_insert(ir, ir->outputs, out);
3285 }
3286
3287 /* Set up the gs header as an output for the vertex shader so it won't
3288 * clobber it for the tess ctrl shader.
3289 *
3290 * TODO this could probably be done more cleanly in a nir pass.
3291 */
3292 if (ctx->so->type == MESA_SHADER_VERTEX ||
3293 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3294 if (ctx->primitive_id) {
3295 unsigned n = so->outputs_count++;
3296 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3297
3298 struct ir3_instruction *out =
3299 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3300 out->collect.outidx = n;
3301 array_insert(ir, ir->outputs, out);
3302 }
3303
3304 if (ctx->gs_header) {
3305 unsigned n = so->outputs_count++;
3306 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3307 struct ir3_instruction *out =
3308 ir3_create_collect(ctx, &ctx->gs_header, 1);
3309 out->collect.outidx = n;
3310 array_insert(ir, ir->outputs, out);
3311 }
3312
3313 if (ctx->tcs_header) {
3314 unsigned n = so->outputs_count++;
3315 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3316 struct ir3_instruction *out =
3317 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3318 out->collect.outidx = n;
3319 array_insert(ir, ir->outputs, out);
3320 }
3321 }
3322
3323 /* at this point, for binning pass, throw away unneeded outputs: */
3324 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3325 fixup_binning_pass(ctx);
3326
3327 ir3_debug_print(ir, "BEFORE CF");
3328
3329 ir3_cf(ir);
3330
3331 ir3_debug_print(ir, "BEFORE CP");
3332
3333 ir3_cp(ir, so);
3334
3335 /* at this point, for binning pass, throw away unneeded outputs:
3336 * Note that for a6xx and later, we do this after ir3_cp to ensure
3337 * that the uniform/constant layout for BS and VS matches, so that
3338 * we can re-use same VS_CONST state group.
3339 */
3340 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3341 fixup_binning_pass(ctx);
3342
3343 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3344 * need to make sure not to remove any inputs that are used by
3345 * the nonbinning VS.
3346 */
3347 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3348 so->type == MESA_SHADER_VERTEX) {
3349 for (int i = 0; i < ctx->ninputs; i++) {
3350 struct ir3_instruction *in = ctx->inputs[i];
3351
3352 if (!in)
3353 continue;
3354
3355 unsigned n = i / 4;
3356 unsigned c = i % 4;
3357
3358 debug_assert(n < so->nonbinning->inputs_count);
3359
3360 if (so->nonbinning->inputs[n].sysval)
3361 continue;
3362
3363 /* be sure to keep inputs, even if only used in VS */
3364 if (so->nonbinning->inputs[n].compmask & (1 << c))
3365 array_insert(in->block, in->block->keeps, in);
3366 }
3367 }
3368
3369 ir3_debug_print(ir, "BEFORE GROUPING");
3370
3371 ir3_sched_add_deps(ir);
3372
3373 /* Group left/right neighbors, inserting mov's where needed to
3374 * solve conflicts:
3375 */
3376 ir3_group(ir);
3377
3378 ir3_debug_print(ir, "AFTER GROUPING");
3379
3380 ir3_depth(ir, so);
3381
3382 ir3_debug_print(ir, "AFTER DEPTH");
3383
3384 /* do Sethi–Ullman numbering before scheduling: */
3385 ir3_sun(ir);
3386
3387 ret = ir3_sched(ir);
3388 if (ret) {
3389 DBG("SCHED failed!");
3390 goto out;
3391 }
3392
3393 ir3_debug_print(ir, "AFTER SCHED");
3394
3395 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3396 * with draw pass VS, so binning and draw pass can both use the
3397 * same VBO state.
3398 *
3399 * Note that VS inputs are expected to be full precision.
3400 */
3401 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3402 (ir->type == MESA_SHADER_VERTEX) &&
3403 so->binning_pass;
3404
3405 if (pre_assign_inputs) {
3406 for (unsigned i = 0; i < ctx->ninputs; i++) {
3407 struct ir3_instruction *instr = ctx->inputs[i];
3408
3409 if (!instr)
3410 continue;
3411
3412 unsigned n = i / 4;
3413 unsigned c = i % 4;
3414 unsigned regid = so->nonbinning->inputs[n].regid + c;
3415
3416 instr->regs[0]->num = regid;
3417 }
3418
3419 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3420 } else if (ctx->tcs_header) {
3421 /* We need to have these values in the same registers between VS and TCS
3422 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3423 */
3424
3425 ctx->tcs_header->regs[0]->num = regid(0, 0);
3426 ctx->primitive_id->regs[0]->num = regid(0, 1);
3427 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3428 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3429 } else if (ctx->gs_header) {
3430 /* We need to have these values in the same registers between producer
3431 * (VS or DS) and GS since the producer chains to GS and doesn't get
3432 * the sysvals redelivered.
3433 */
3434
3435 ctx->gs_header->regs[0]->num = regid(0, 0);
3436 ctx->primitive_id->regs[0]->num = regid(0, 1);
3437 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3438 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3439 } else if (so->num_sampler_prefetch) {
3440 assert(so->type == MESA_SHADER_FRAGMENT);
3441 struct ir3_instruction *instr, *precolor[2];
3442 int idx = 0;
3443
3444 foreach_input(instr, ir) {
3445 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3446 continue;
3447
3448 assert(idx < ARRAY_SIZE(precolor));
3449
3450 precolor[idx] = instr;
3451 instr->regs[0]->num = idx;
3452
3453 idx++;
3454 }
3455 ret = ir3_ra(so, precolor, idx);
3456 } else {
3457 ret = ir3_ra(so, NULL, 0);
3458 }
3459
3460 if (ret) {
3461 DBG("RA failed!");
3462 goto out;
3463 }
3464
3465 ir3_postsched(ctx);
3466 ir3_debug_print(ir, "AFTER POSTSCHED");
3467
3468 if (compiler->gpu_id >= 600) {
3469 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3470 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3471 }
3472 }
3473
3474 if (so->type == MESA_SHADER_FRAGMENT)
3475 pack_inlocs(ctx);
3476
3477 /*
3478 * Fixup inputs/outputs to point to the actual registers assigned:
3479 *
3480 * 1) initialize to r63.x (invalid/unused)
3481 * 2) iterate IR level inputs/outputs and update the variants
3482 * inputs/outputs table based on the assigned registers for
3483 * the remaining inputs/outputs.
3484 */
3485
3486 for (unsigned i = 0; i < so->inputs_count; i++)
3487 so->inputs[i].regid = INVALID_REG;
3488 for (unsigned i = 0; i < so->outputs_count; i++)
3489 so->outputs[i].regid = INVALID_REG;
3490
3491 struct ir3_instruction *out;
3492 foreach_output(out, ir) {
3493 assert(out->opc == OPC_META_COLLECT);
3494 unsigned outidx = out->collect.outidx;
3495
3496 so->outputs[outidx].regid = out->regs[0]->num;
3497 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3498 }
3499
3500 struct ir3_instruction *in;
3501 foreach_input(in, ir) {
3502 assert(in->opc == OPC_META_INPUT);
3503 unsigned inidx = in->input.inidx;
3504
3505 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3506 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3507 compile_assert(ctx, in->regs[0]->num ==
3508 so->nonbinning->inputs[inidx].regid);
3509 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3510 so->nonbinning->inputs[inidx].half);
3511 }
3512 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3513 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3514 } else {
3515 so->inputs[inidx].regid = in->regs[0]->num;
3516 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3517 }
3518 }
3519
3520 if (ctx->astc_srgb)
3521 fixup_astc_srgb(ctx);
3522
3523 /* We need to do legalize after (for frag shader's) the "bary.f"
3524 * offsets (inloc) have been assigned.
3525 */
3526 ir3_legalize(ir, so, &max_bary);
3527
3528 ir3_debug_print(ir, "AFTER LEGALIZE");
3529
3530 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3531 * know what we might have to wait on when coming in from VS chsh.
3532 */
3533 if (so->type == MESA_SHADER_TESS_CTRL ||
3534 so->type == MESA_SHADER_GEOMETRY ) {
3535 foreach_block (block, &ir->block_list) {
3536 foreach_instr (instr, &block->instr_list) {
3537 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3538 break;
3539 }
3540 }
3541 }
3542
3543 so->branchstack = ctx->max_stack;
3544
3545 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3546 if (so->type == MESA_SHADER_FRAGMENT)
3547 so->total_in = max_bary + 1;
3548
3549 so->max_sun = ir->max_sun;
3550
3551 /* Collect sampling instructions eligible for pre-dispatch. */
3552 collect_tex_prefetches(ctx, ir);
3553
3554 out:
3555 if (ret) {
3556 if (so->ir)
3557 ir3_destroy(so->ir);
3558 so->ir = NULL;
3559 }
3560 ir3_context_free(ctx);
3561
3562 return ret;
3563 }