2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
55 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
57 src
->array
.offset
= n
;
59 ir3_instr_set_address(mov
, address
);
64 static struct ir3_instruction
*
65 create_input(struct ir3_context
*ctx
, unsigned compmask
)
67 struct ir3_instruction
*in
;
69 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
70 in
->input
.sysval
= ~0;
71 __ssa_dst(in
)->wrmask
= compmask
;
73 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
78 static struct ir3_instruction
*
79 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
81 struct ir3_block
*block
= ctx
->block
;
82 struct ir3_instruction
*instr
;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction
*inloc
= create_immed(block
, n
);
87 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
88 instr
->cat6
.type
= TYPE_U32
;
89 instr
->cat6
.iim_val
= 1;
91 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
92 instr
->regs
[2]->wrmask
= 0x3;
98 static struct ir3_instruction
*
99 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
104 unsigned n
= const_state
->offsets
.driver_param
;
105 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
106 return create_uniform(ctx
->block
, r
);
110 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
111 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
112 * trust that we will only see and/or/xor on those 1-bit values, so we can
113 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
118 * alu/sfu instructions:
121 static struct ir3_instruction
*
122 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
123 unsigned src_bitsize
, nir_op op
)
125 type_t src_type
, dst_type
;
129 case nir_op_f2f16_rtne
:
130 case nir_op_f2f16_rtz
:
138 switch (src_bitsize
) {
146 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
155 switch (src_bitsize
) {
166 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
175 switch (src_bitsize
) {
186 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
199 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
210 case nir_op_f2f16_rtne
:
211 case nir_op_f2f16_rtz
:
253 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
256 if (src_type
== dst_type
)
259 struct ir3_instruction
*cov
=
260 ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
262 if (op
== nir_op_f2f16_rtne
)
263 cov
->regs
[0]->flags
|= IR3_REG_EVEN
;
269 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
271 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
272 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
273 unsigned bs
[info
->num_inputs
]; /* bit size */
274 struct ir3_block
*b
= ctx
->block
;
275 unsigned dst_sz
, wrmask
;
276 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) == 16 ?
279 if (alu
->dest
.dest
.is_ssa
) {
280 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
281 wrmask
= (1 << dst_sz
) - 1;
283 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
284 wrmask
= alu
->dest
.write_mask
;
287 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
289 /* Vectors are special in that they have non-scalarized writemasks,
290 * and just take the first swizzle channel for each argument in
291 * order into each writemask channel.
293 if ((alu
->op
== nir_op_vec2
) ||
294 (alu
->op
== nir_op_vec3
) ||
295 (alu
->op
== nir_op_vec4
)) {
297 for (int i
= 0; i
< info
->num_inputs
; i
++) {
298 nir_alu_src
*asrc
= &alu
->src
[i
];
300 compile_assert(ctx
, !asrc
->abs
);
301 compile_assert(ctx
, !asrc
->negate
);
303 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
305 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
306 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
309 ir3_put_dst(ctx
, &alu
->dest
.dest
);
313 /* We also get mov's with more than one component for mov's so
314 * handle those specially:
316 if (alu
->op
== nir_op_mov
) {
317 nir_alu_src
*asrc
= &alu
->src
[0];
318 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
320 for (unsigned i
= 0; i
< dst_sz
; i
++) {
321 if (wrmask
& (1 << i
)) {
322 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
328 ir3_put_dst(ctx
, &alu
->dest
.dest
);
332 /* General case: We can just grab the one used channel per src. */
333 for (int i
= 0; i
< info
->num_inputs
; i
++) {
334 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
335 nir_alu_src
*asrc
= &alu
->src
[i
];
337 compile_assert(ctx
, !asrc
->abs
);
338 compile_assert(ctx
, !asrc
->negate
);
340 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
341 bs
[i
] = nir_src_bit_size(asrc
->src
);
343 compile_assert(ctx
, src
[i
]);
348 case nir_op_f2f16_rtne
:
349 case nir_op_f2f16_rtz
:
372 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
375 case nir_op_fquantize2f16
:
376 dst
[0] = create_cov(ctx
,
377 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
381 dst
[0] = ir3_CMPS_F(b
,
383 create_immed_typed(b
, 0, bs
[0] == 16 ? TYPE_F16
: TYPE_F32
), 0);
384 dst
[0]->cat2
.condition
= IR3_COND_NE
;
388 /* i2b1 will appear when translating from nir_load_ubo or
389 * nir_intrinsic_load_ssbo, where any non-zero value is true.
391 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
392 dst
[0]->cat2
.condition
= IR3_COND_NE
;
396 /* b2b1 will appear when translating from
398 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
399 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
401 * A negate can turn those into a 1 or 0 for us.
403 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
407 /* b2b32 will appear when converting our 1-bit bools to a store_shared
410 * A negate can turn those into a ~0 for us.
412 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
416 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
419 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
422 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
425 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
428 /* if there is just a single use of the src, and it supports
429 * (sat) bit, we can just fold the (sat) flag back to the
430 * src instruction and create a mov. This is easier for cp
433 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
434 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
437 * TODO probably opc_cat==4 is ok too
439 if (alu
->src
[0].src
.is_ssa
&&
440 src
[0]->opc
!= OPC_BARY_F
&&
441 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
442 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
443 src
[0]->flags
|= IR3_INSTR_SAT
;
444 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
449 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
450 dst
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
460 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
463 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
466 case nir_op_fddx_coarse
:
467 dst
[0] = ir3_DSX(b
, src
[0], 0);
468 dst
[0]->cat5
.type
= TYPE_F32
;
470 case nir_op_fddx_fine
:
471 dst
[0] = ir3_DSXPP_1(b
, src
[0], 0);
472 dst
[0]->cat5
.type
= TYPE_F32
;
475 case nir_op_fddy_coarse
:
476 dst
[0] = ir3_DSY(b
, src
[0], 0);
477 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddy_fine
:
481 dst
[0] = ir3_DSYPP_1(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
485 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
486 dst
[0]->cat2
.condition
= IR3_COND_LT
;
489 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
490 dst
[0]->cat2
.condition
= IR3_COND_GE
;
493 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
494 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
497 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
498 dst
[0]->cat2
.condition
= IR3_COND_NE
;
501 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
504 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
507 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
509 case nir_op_fround_even
:
510 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
513 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
517 dst
[0] = ir3_SIN(b
, src
[0], 0);
520 dst
[0] = ir3_COS(b
, src
[0], 0);
523 dst
[0] = ir3_RSQ(b
, src
[0], 0);
526 dst
[0] = ir3_RCP(b
, src
[0], 0);
529 dst
[0] = ir3_LOG2(b
, src
[0], 0);
532 dst
[0] = ir3_EXP2(b
, src
[0], 0);
535 dst
[0] = ir3_SQRT(b
, src
[0], 0);
539 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
542 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
545 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
548 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
551 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
554 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
557 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
559 case nir_op_umul_low
:
560 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
562 case nir_op_imadsh_mix16
:
563 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
565 case nir_op_imad24_ir3
:
566 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
569 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
572 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
576 dst
[0] = ir3_SUB_U(b
, create_immed(ctx
->block
, 1), 0, src
[0], 0);
578 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
582 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
585 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
588 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
591 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
594 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
597 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
600 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
601 dst
[0]->cat2
.condition
= IR3_COND_LT
;
604 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
605 dst
[0]->cat2
.condition
= IR3_COND_GE
;
608 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
609 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
612 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
613 dst
[0]->cat2
.condition
= IR3_COND_NE
;
616 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
617 dst
[0]->cat2
.condition
= IR3_COND_LT
;
620 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
621 dst
[0]->cat2
.condition
= IR3_COND_GE
;
625 struct ir3_instruction
*cond
= src
[0];
627 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
628 * we can ignore that and use original cond, since the nonzero-ness of
629 * cond stays the same.
631 if (cond
->opc
== OPC_ABSNEG_S
&&
633 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
634 cond
= cond
->regs
[1]->instr
;
637 compile_assert(ctx
, bs
[1] == bs
[2]);
638 /* The condition's size has to match the other two arguments' size, so
639 * convert down if necessary.
642 struct hash_entry
*prev_entry
=
643 _mesa_hash_table_search(ctx
->sel_cond_conversions
, src
[0]);
645 cond
= prev_entry
->data
;
647 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
648 _mesa_hash_table_insert(ctx
->sel_cond_conversions
, src
[0], cond
);
653 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
655 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
658 case nir_op_bit_count
: {
659 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
660 // double check on earlier gen's. Once half-precision support is
661 // in place, this should probably move to a NIR lowering pass:
662 struct ir3_instruction
*hi
, *lo
;
664 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
666 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
668 hi
= ir3_CBITS_B(b
, hi
, 0);
669 lo
= ir3_CBITS_B(b
, lo
, 0);
671 // TODO maybe the builders should default to making dst half-precision
672 // if the src's were half precision, to make this less awkward.. otoh
673 // we should probably just do this lowering in NIR.
674 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
675 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
677 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
678 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
679 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
682 case nir_op_ifind_msb
: {
683 struct ir3_instruction
*cmp
;
684 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
685 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
686 cmp
->cat2
.condition
= IR3_COND_GE
;
687 dst
[0] = ir3_SEL_B32(b
,
688 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
692 case nir_op_ufind_msb
:
693 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
694 dst
[0] = ir3_SEL_B32(b
,
695 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
696 src
[0], 0, dst
[0], 0);
698 case nir_op_find_lsb
:
699 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
700 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
702 case nir_op_bitfield_reverse
:
703 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
707 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
708 nir_op_infos
[alu
->op
].name
);
712 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
713 assert(nir_dest_bit_size(alu
->dest
.dest
) == 1 ||
714 alu
->op
== nir_op_b2b32
);
717 /* 1-bit values stored in 32-bit registers are only valid for certain
728 compile_assert(ctx
, nir_dest_bit_size(alu
->dest
.dest
) != 1);
732 ir3_put_dst(ctx
, &alu
->dest
.dest
);
736 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
737 struct ir3_instruction
**dst
)
739 struct ir3_block
*b
= ctx
->block
;
741 unsigned ncomp
= intr
->num_components
;
742 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
743 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
744 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
745 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
746 ldc
->cat6
.iim_val
= ncomp
;
747 ldc
->cat6
.d
= nir_intrinsic_base(intr
);
748 ldc
->cat6
.type
= TYPE_U32
;
750 nir_intrinsic_instr
*bindless
= ir3_bindless_resource(intr
->src
[0]);
752 ldc
->flags
|= IR3_INSTR_B
;
753 ldc
->cat6
.base
= nir_intrinsic_desc_set(bindless
);
754 ctx
->so
->bindless_ubo
= true;
757 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
761 /* handles direct/indirect UBO reads: */
763 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
764 struct ir3_instruction
**dst
)
766 struct ir3_block
*b
= ctx
->block
;
767 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
768 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
769 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0);
770 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
774 /* First src is ubo index, which could either be an immed or not: */
775 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
776 if (is_same_type_mov(src0
) &&
777 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
778 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
779 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
781 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
782 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
784 /* NOTE: since relative addressing is used, make sure constlen is
785 * at least big enough to cover all the UBO addresses, since the
786 * assembler won't know what the max address reg is.
788 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
789 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
792 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
795 if (nir_src_is_const(intr
->src
[1])) {
796 off
+= nir_src_as_uint(intr
->src
[1]);
798 /* For load_ubo_indirect, second src is indirect offset: */
799 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
801 /* and add offset to addr: */
802 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
805 /* if offset is to large to encode in the ldg, split it out: */
806 if ((off
+ (intr
->num_components
* 4)) > 1024) {
807 /* split out the minimal amount to improve the odds that
808 * cp can fit the immediate in the add.s instruction:
810 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
811 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
816 struct ir3_instruction
*carry
;
818 /* handle 32b rollover, ie:
819 * if (addr < base_lo)
822 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
823 carry
->cat2
.condition
= IR3_COND_LT
;
824 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
826 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
829 for (int i
= 0; i
< intr
->num_components
; i
++) {
830 struct ir3_instruction
*load
=
831 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
832 create_immed(b
, off
+ i
* 4), 0);
833 load
->cat6
.type
= TYPE_U32
;
838 /* src[] = { block_index } */
840 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
841 struct ir3_instruction
**dst
)
843 /* SSBO size stored as a const starting at ssbo_sizes: */
844 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
845 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
846 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
847 const_state
->ssbo_size
.off
[blk_idx
];
849 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
851 dst
[0] = create_uniform(ctx
->block
, idx
);
854 /* src[] = { offset }. const_index[] = { base } */
856 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
857 struct ir3_instruction
**dst
)
859 struct ir3_block
*b
= ctx
->block
;
860 struct ir3_instruction
*ldl
, *offset
;
863 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
864 base
= nir_intrinsic_base(intr
);
866 ldl
= ir3_LDL(b
, offset
, 0,
867 create_immed(b
, intr
->num_components
), 0,
868 create_immed(b
, base
), 0);
870 ldl
->cat6
.type
= utype_dst(intr
->dest
);
871 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
873 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
874 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
876 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
879 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
881 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
883 struct ir3_block
*b
= ctx
->block
;
884 struct ir3_instruction
*stl
, *offset
;
885 struct ir3_instruction
* const *value
;
886 unsigned base
, wrmask
, ncomp
;
888 value
= ir3_get_src(ctx
, &intr
->src
[0]);
889 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
891 base
= nir_intrinsic_base(intr
);
892 wrmask
= nir_intrinsic_write_mask(intr
);
893 ncomp
= ffs(~wrmask
) - 1;
895 assert(wrmask
== BITFIELD_MASK(intr
->num_components
));
897 stl
= ir3_STL(b
, offset
, 0,
898 ir3_create_collect(ctx
, value
, ncomp
), 0,
899 create_immed(b
, ncomp
), 0);
900 stl
->cat6
.dst_offset
= base
;
901 stl
->cat6
.type
= utype_src(intr
->src
[0]);
902 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
903 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
905 array_insert(b
, b
->keeps
, stl
);
908 /* src[] = { offset }. const_index[] = { base } */
910 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
911 struct ir3_instruction
**dst
)
913 struct ir3_block
*b
= ctx
->block
;
914 struct ir3_instruction
*load
, *offset
;
917 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
918 base
= nir_intrinsic_base(intr
);
920 load
= ir3_LDLW(b
, offset
, 0,
921 create_immed(b
, intr
->num_components
), 0,
922 create_immed(b
, base
), 0);
924 load
->cat6
.type
= utype_dst(intr
->dest
);
925 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
927 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
928 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
930 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
933 /* src[] = { value, offset }. const_index[] = { base } */
935 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
937 struct ir3_block
*b
= ctx
->block
;
938 struct ir3_instruction
*store
, *offset
;
939 struct ir3_instruction
* const *value
;
941 value
= ir3_get_src(ctx
, &intr
->src
[0]);
942 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
944 store
= ir3_STLW(b
, offset
, 0,
945 ir3_create_collect(ctx
, value
, intr
->num_components
), 0,
946 create_immed(b
, intr
->num_components
), 0);
948 store
->cat6
.dst_offset
= nir_intrinsic_base(intr
);
949 store
->cat6
.type
= utype_src(intr
->src
[0]);
950 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
951 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
953 array_insert(b
, b
->keeps
, store
);
957 * CS shared variable atomic intrinsics
959 * All of the shared variable atomic memory operations read a value from
960 * memory, compute a new value using one of the operations below, write the
961 * new value to memory, and return the original value read.
963 * All operations take 2 sources except CompSwap that takes 3. These
966 * 0: The offset into the shared variable storage region that the atomic
967 * operation will operate on.
968 * 1: The data parameter to the atomic function (i.e. the value to add
969 * in shared_atomic_add, etc).
970 * 2: For CompSwap only: the second data parameter.
972 static struct ir3_instruction
*
973 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
975 struct ir3_block
*b
= ctx
->block
;
976 struct ir3_instruction
*atomic
, *src0
, *src1
;
977 type_t type
= TYPE_U32
;
979 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
980 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
982 switch (intr
->intrinsic
) {
983 case nir_intrinsic_shared_atomic_add
:
984 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
986 case nir_intrinsic_shared_atomic_imin
:
987 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
990 case nir_intrinsic_shared_atomic_umin
:
991 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
993 case nir_intrinsic_shared_atomic_imax
:
994 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
997 case nir_intrinsic_shared_atomic_umax
:
998 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1000 case nir_intrinsic_shared_atomic_and
:
1001 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1003 case nir_intrinsic_shared_atomic_or
:
1004 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1006 case nir_intrinsic_shared_atomic_xor
:
1007 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1009 case nir_intrinsic_shared_atomic_exchange
:
1010 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1012 case nir_intrinsic_shared_atomic_comp_swap
:
1013 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1014 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1015 ir3_get_src(ctx
, &intr
->src
[2])[0],
1018 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1024 atomic
->cat6
.iim_val
= 1;
1026 atomic
->cat6
.type
= type
;
1027 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1028 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1030 /* even if nothing consume the result, we can't DCE the instruction: */
1031 array_insert(b
, b
->keeps
, atomic
);
1036 struct tex_src_info
{
1038 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1039 /* For normal tex instructions */
1040 unsigned base
, combined_idx
, a1_val
, flags
;
1041 struct ir3_instruction
*samp_tex
;
1044 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1045 * to handle with the image_mapping table..
1047 static struct tex_src_info
1048 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1050 struct ir3_block
*b
= ctx
->block
;
1051 struct tex_src_info info
= { 0 };
1052 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1053 ctx
->so
->bindless_tex
= true;
1057 info
.flags
|= IR3_INSTR_B
;
1059 /* Gather information required to determine which encoding to
1060 * choose as well as for prefetch.
1062 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1063 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1065 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1068 /* Choose encoding. */
1069 if (tex_const
&& info
.tex_idx
< 256) {
1070 if (info
.tex_idx
< 16) {
1071 /* Everything fits within the instruction */
1072 info
.base
= info
.tex_base
;
1073 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1075 info
.base
= info
.tex_base
;
1076 info
.a1_val
= info
.tex_idx
<< 3;
1077 info
.combined_idx
= 0;
1078 info
.flags
|= IR3_INSTR_A1EN
;
1080 info
.samp_tex
= NULL
;
1082 info
.flags
|= IR3_INSTR_S2EN
;
1083 info
.base
= info
.tex_base
;
1085 /* Note: the indirect source is now a vec2 instead of hvec2 */
1086 struct ir3_instruction
*texture
, *sampler
;
1088 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1089 sampler
= create_immed(b
, 0);
1090 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1096 info
.flags
|= IR3_INSTR_S2EN
;
1097 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1098 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1099 struct ir3_instruction
*texture
, *sampler
;
1101 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1102 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1104 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1113 static struct ir3_instruction
*
1114 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1115 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1116 struct ir3_instruction
*src1
)
1118 struct ir3_instruction
*sam
, *addr
;
1119 if (info
.flags
& IR3_INSTR_A1EN
) {
1120 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1122 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1123 info
.samp_tex
, src0
, src1
);
1124 if (info
.flags
& IR3_INSTR_A1EN
) {
1125 ir3_instr_set_address(sam
, addr
);
1127 if (info
.flags
& IR3_INSTR_B
) {
1128 sam
->cat5
.tex_base
= info
.base
;
1129 sam
->cat5
.samp
= info
.combined_idx
;
1134 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1136 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1137 struct ir3_instruction
**dst
)
1139 struct ir3_block
*b
= ctx
->block
;
1140 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1141 struct ir3_instruction
*sam
;
1142 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1143 struct ir3_instruction
*coords
[4];
1144 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1145 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1147 /* hmm, this seems a bit odd, but it is what blob does and (at least
1148 * a5xx) just faults on bogus addresses otherwise:
1150 if (flags
& IR3_INSTR_3D
) {
1151 flags
&= ~IR3_INSTR_3D
;
1152 flags
|= IR3_INSTR_A
;
1154 info
.flags
|= flags
;
1156 for (unsigned i
= 0; i
< ncoords
; i
++)
1157 coords
[i
] = src0
[i
];
1160 coords
[ncoords
++] = create_immed(b
, 0);
1162 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1163 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1165 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1166 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1168 ir3_split_dest(b
, dst
, sam
, 0, 4);
1172 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1173 struct ir3_instruction
**dst
)
1175 struct ir3_block
*b
= ctx
->block
;
1176 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1177 struct ir3_instruction
*sam
, *lod
;
1178 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1179 type_t dst_type
= nir_dest_bit_size(intr
->dest
) == 16 ?
1180 TYPE_U16
: TYPE_U32
;
1182 info
.flags
|= flags
;
1183 lod
= create_immed(b
, 0);
1184 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1186 /* Array size actually ends up in .w rather than .z. This doesn't
1187 * matter for miplevel 0, but for higher mips the value in z is
1188 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1189 * returned, which means that we have to add 1 to it for arrays for
1192 * Note use a temporary dst and then copy, since the size of the dst
1193 * array that is passed in is based on nir's understanding of the
1194 * result size, not the hardware's
1196 struct ir3_instruction
*tmp
[4];
1198 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1200 /* get_size instruction returns size in bytes instead of texels
1201 * for imageBuffer, so we need to divide it by the pixel size
1202 * of the image format.
1204 * TODO: This is at least true on a5xx. Check other gens.
1206 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1207 /* Since all the possible values the divisor can take are
1208 * power-of-two (4, 8, or 16), the division is implemented
1210 * During shader setup, the log2 of the image format's
1211 * bytes-per-pixel should have been emitted in 2nd slot of
1212 * image_dims. See ir3_shader::emit_image_dims().
1214 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1215 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1216 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1217 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1219 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1222 for (unsigned i
= 0; i
< ncoords
; i
++)
1225 if (flags
& IR3_INSTR_A
) {
1226 if (ctx
->compiler
->levels_add_one
) {
1227 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1229 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1235 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1237 struct ir3_block
*b
= ctx
->block
;
1238 struct ir3_instruction
*barrier
;
1240 switch (intr
->intrinsic
) {
1241 case nir_intrinsic_control_barrier
:
1242 barrier
= ir3_BAR(b
);
1243 barrier
->cat7
.g
= true;
1244 barrier
->cat7
.l
= true;
1245 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1246 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1248 case nir_intrinsic_memory_barrier
:
1249 barrier
= ir3_FENCE(b
);
1250 barrier
->cat7
.g
= true;
1251 barrier
->cat7
.r
= true;
1252 barrier
->cat7
.w
= true;
1253 barrier
->cat7
.l
= true;
1254 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1255 IR3_BARRIER_BUFFER_W
;
1256 barrier
->barrier_conflict
=
1257 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1258 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1260 case nir_intrinsic_memory_barrier_buffer
:
1261 barrier
= ir3_FENCE(b
);
1262 barrier
->cat7
.g
= true;
1263 barrier
->cat7
.r
= true;
1264 barrier
->cat7
.w
= true;
1265 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1266 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1267 IR3_BARRIER_BUFFER_W
;
1269 case nir_intrinsic_memory_barrier_image
:
1270 // TODO double check if this should have .g set
1271 barrier
= ir3_FENCE(b
);
1272 barrier
->cat7
.g
= true;
1273 barrier
->cat7
.r
= true;
1274 barrier
->cat7
.w
= true;
1275 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1276 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1277 IR3_BARRIER_IMAGE_W
;
1279 case nir_intrinsic_memory_barrier_shared
:
1280 barrier
= ir3_FENCE(b
);
1281 barrier
->cat7
.g
= true;
1282 barrier
->cat7
.l
= true;
1283 barrier
->cat7
.r
= true;
1284 barrier
->cat7
.w
= true;
1285 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1286 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1287 IR3_BARRIER_SHARED_W
;
1289 case nir_intrinsic_group_memory_barrier
:
1290 barrier
= ir3_FENCE(b
);
1291 barrier
->cat7
.g
= true;
1292 barrier
->cat7
.l
= true;
1293 barrier
->cat7
.r
= true;
1294 barrier
->cat7
.w
= true;
1295 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1296 IR3_BARRIER_IMAGE_W
|
1297 IR3_BARRIER_BUFFER_W
;
1298 barrier
->barrier_conflict
=
1299 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1300 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1301 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1307 /* make sure barrier doesn't get DCE'd */
1308 array_insert(b
, b
->keeps
, barrier
);
1311 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1312 gl_system_value slot
, unsigned compmask
,
1313 struct ir3_instruction
*instr
)
1315 struct ir3_shader_variant
*so
= ctx
->so
;
1316 unsigned n
= so
->inputs_count
++;
1318 assert(instr
->opc
== OPC_META_INPUT
);
1319 instr
->input
.inidx
= n
;
1320 instr
->input
.sysval
= slot
;
1322 so
->inputs
[n
].sysval
= true;
1323 so
->inputs
[n
].slot
= slot
;
1324 so
->inputs
[n
].compmask
= compmask
;
1325 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1329 static struct ir3_instruction
*
1330 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1334 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1335 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1339 static struct ir3_instruction
*
1340 get_barycentric_centroid(struct ir3_context
*ctx
)
1342 if (!ctx
->ij_centroid
) {
1343 struct ir3_instruction
*xy
[2];
1344 struct ir3_instruction
*ij
;
1346 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
, 0x3);
1347 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1349 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1352 return ctx
->ij_centroid
;
1355 static struct ir3_instruction
*
1356 get_barycentric_sample(struct ir3_context
*ctx
)
1358 if (!ctx
->ij_sample
) {
1359 struct ir3_instruction
*xy
[2];
1360 struct ir3_instruction
*ij
;
1362 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
, 0x3);
1363 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1365 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1368 return ctx
->ij_sample
;
1371 static struct ir3_instruction
*
1372 get_barycentric_pixel(struct ir3_context
*ctx
)
1374 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1375 * this to create ij_pixel only on demand:
1377 return ctx
->ij_pixel
;
1380 static struct ir3_instruction
*
1381 get_frag_coord(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1383 if (!ctx
->frag_coord
) {
1384 struct ir3_block
*b
= ctx
->in_block
;
1385 struct ir3_instruction
*xyzw
[4];
1386 struct ir3_instruction
*hw_frag_coord
;
1388 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1389 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1391 /* for frag_coord.xy, we get unsigned values.. we need
1392 * to subtract (integer) 8 and divide by 16 (right-
1393 * shift by 4) then convert to float:
1397 * mov.u32f32 dst, tmp
1400 for (int i
= 0; i
< 2; i
++) {
1401 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1402 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1405 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1408 ctx
->so
->fragcoord_compmask
|=
1409 nir_ssa_def_components_read(&intr
->dest
.ssa
);
1411 return ctx
->frag_coord
;
1415 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1417 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1418 struct ir3_instruction
**dst
;
1419 struct ir3_instruction
* const *src
;
1420 struct ir3_block
*b
= ctx
->block
;
1423 if (info
->has_dest
) {
1424 unsigned n
= nir_intrinsic_dest_components(intr
);
1425 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1430 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1431 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1433 switch (intr
->intrinsic
) {
1434 case nir_intrinsic_load_uniform
:
1435 idx
= nir_intrinsic_base(intr
);
1436 if (nir_src_is_const(intr
->src
[0])) {
1437 idx
+= nir_src_as_uint(intr
->src
[0]);
1438 for (int i
= 0; i
< intr
->num_components
; i
++) {
1439 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1440 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
);
1443 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1444 for (int i
= 0; i
< intr
->num_components
; i
++) {
1445 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1446 ir3_get_addr0(ctx
, src
[0], 1));
1448 /* NOTE: if relative addressing is used, we set
1449 * constlen in the compiler (to worst-case value)
1450 * since we don't know in the assembler what the max
1451 * addr reg value can be:
1453 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1454 ctx
->so
->shader
->ubo_state
.size
/ 16);
1458 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1459 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1461 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1462 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1464 case nir_intrinsic_load_hs_patch_stride_ir3
:
1465 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1467 case nir_intrinsic_load_patch_vertices_in
:
1468 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1470 case nir_intrinsic_load_tess_param_base_ir3
:
1471 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1472 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1474 case nir_intrinsic_load_tess_factor_base_ir3
:
1475 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1476 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1479 case nir_intrinsic_load_primitive_location_ir3
:
1480 idx
= nir_intrinsic_driver_location(intr
);
1481 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1484 case nir_intrinsic_load_gs_header_ir3
:
1485 dst
[0] = ctx
->gs_header
;
1487 case nir_intrinsic_load_tcs_header_ir3
:
1488 dst
[0] = ctx
->tcs_header
;
1491 case nir_intrinsic_load_primitive_id
:
1492 dst
[0] = ctx
->primitive_id
;
1495 case nir_intrinsic_load_tess_coord
:
1496 if (!ctx
->tess_coord
) {
1498 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1500 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1502 /* Unused, but ir3_put_dst() below wants to free something */
1503 dst
[2] = create_immed(b
, 0);
1506 case nir_intrinsic_end_patch_ir3
:
1507 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1508 struct ir3_instruction
*end
= ir3_PREDE(b
);
1509 array_insert(b
, b
->keeps
, end
);
1511 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1512 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1515 case nir_intrinsic_store_global_ir3
: {
1516 struct ir3_instruction
*value
, *addr
, *offset
;
1518 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1519 ir3_get_src(ctx
, &intr
->src
[1])[0],
1520 ir3_get_src(ctx
, &intr
->src
[1])[1]
1523 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1525 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]),
1526 intr
->num_components
);
1528 struct ir3_instruction
*stg
=
1529 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1530 create_immed(ctx
->block
, intr
->num_components
), 0, offset
, 0);
1531 stg
->cat6
.type
= TYPE_U32
;
1532 stg
->cat6
.iim_val
= 1;
1534 array_insert(b
, b
->keeps
, stg
);
1536 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1537 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1541 case nir_intrinsic_load_global_ir3
: {
1542 struct ir3_instruction
*addr
, *offset
;
1544 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1545 ir3_get_src(ctx
, &intr
->src
[0])[0],
1546 ir3_get_src(ctx
, &intr
->src
[0])[1]
1549 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1551 struct ir3_instruction
*load
=
1552 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, intr
->num_components
),
1554 load
->cat6
.type
= TYPE_U32
;
1555 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1557 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1558 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1560 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
1564 case nir_intrinsic_load_ubo
:
1565 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1567 case nir_intrinsic_load_ubo_ir3
:
1568 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
1570 case nir_intrinsic_load_frag_coord
:
1571 ir3_split_dest(b
, dst
, get_frag_coord(ctx
, intr
), 0, 4);
1573 case nir_intrinsic_load_sample_pos_from_id
: {
1574 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1575 * but that doesn't seem necessary.
1577 struct ir3_instruction
*offset
=
1578 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1579 offset
->regs
[0]->wrmask
= 0x3;
1580 offset
->cat5
.type
= TYPE_F32
;
1582 ir3_split_dest(b
, dst
, offset
, 0, 2);
1586 case nir_intrinsic_load_size_ir3
:
1587 if (!ctx
->ij_size
) {
1589 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1591 dst
[0] = ctx
->ij_size
;
1593 case nir_intrinsic_load_barycentric_centroid
:
1594 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1596 case nir_intrinsic_load_barycentric_sample
:
1597 if (ctx
->so
->key
.msaa
) {
1598 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1600 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1603 case nir_intrinsic_load_barycentric_pixel
:
1604 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1606 case nir_intrinsic_load_interpolated_input
:
1607 idx
= nir_intrinsic_base(intr
);
1608 comp
= nir_intrinsic_component(intr
);
1609 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1610 if (nir_src_is_const(intr
->src
[1])) {
1611 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1612 idx
+= nir_src_as_uint(intr
->src
[1]);
1613 for (int i
= 0; i
< intr
->num_components
; i
++) {
1614 unsigned inloc
= idx
* 4 + i
+ comp
;
1615 if (ctx
->so
->inputs
[idx
].bary
&&
1616 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1617 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1619 /* for non-varyings use the pre-setup input, since
1620 * that is easier than mapping things back to a
1621 * nir_variable to figure out what it is.
1623 dst
[i
] = ctx
->inputs
[inloc
];
1624 compile_assert(ctx
, dst
[i
]);
1628 ir3_context_error(ctx
, "unhandled");
1631 case nir_intrinsic_load_input
:
1632 idx
= nir_intrinsic_base(intr
);
1633 comp
= nir_intrinsic_component(intr
);
1634 if (nir_src_is_const(intr
->src
[0])) {
1635 idx
+= nir_src_as_uint(intr
->src
[0]);
1636 for (int i
= 0; i
< intr
->num_components
; i
++) {
1637 unsigned n
= idx
* 4 + i
+ comp
;
1638 dst
[i
] = ctx
->inputs
[n
];
1639 compile_assert(ctx
, ctx
->inputs
[n
]);
1642 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1643 struct ir3_instruction
*collect
=
1644 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1645 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1646 for (int i
= 0; i
< intr
->num_components
; i
++) {
1647 unsigned n
= idx
* 4 + i
+ comp
;
1648 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1653 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1654 * pass and replaced by an ir3-specifc version that adds the
1655 * dword-offset in the last source.
1657 case nir_intrinsic_load_ssbo_ir3
:
1658 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1660 case nir_intrinsic_store_ssbo_ir3
:
1661 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1662 !ctx
->s
->info
.fs
.early_fragment_tests
)
1663 ctx
->so
->no_earlyz
= true;
1664 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1666 case nir_intrinsic_get_buffer_size
:
1667 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1669 case nir_intrinsic_ssbo_atomic_add_ir3
:
1670 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1671 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1672 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1673 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1674 case nir_intrinsic_ssbo_atomic_and_ir3
:
1675 case nir_intrinsic_ssbo_atomic_or_ir3
:
1676 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1677 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1678 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1679 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1680 !ctx
->s
->info
.fs
.early_fragment_tests
)
1681 ctx
->so
->no_earlyz
= true;
1682 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1684 case nir_intrinsic_load_shared
:
1685 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1687 case nir_intrinsic_store_shared
:
1688 emit_intrinsic_store_shared(ctx
, intr
);
1690 case nir_intrinsic_shared_atomic_add
:
1691 case nir_intrinsic_shared_atomic_imin
:
1692 case nir_intrinsic_shared_atomic_umin
:
1693 case nir_intrinsic_shared_atomic_imax
:
1694 case nir_intrinsic_shared_atomic_umax
:
1695 case nir_intrinsic_shared_atomic_and
:
1696 case nir_intrinsic_shared_atomic_or
:
1697 case nir_intrinsic_shared_atomic_xor
:
1698 case nir_intrinsic_shared_atomic_exchange
:
1699 case nir_intrinsic_shared_atomic_comp_swap
:
1700 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1702 case nir_intrinsic_image_load
:
1703 emit_intrinsic_load_image(ctx
, intr
, dst
);
1705 case nir_intrinsic_bindless_image_load
:
1706 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1707 * so using isam doesn't work.
1709 * TODO: can we use isam if we fill out more fields?
1711 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1713 case nir_intrinsic_image_store
:
1714 case nir_intrinsic_bindless_image_store
:
1715 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1716 !ctx
->s
->info
.fs
.early_fragment_tests
)
1717 ctx
->so
->no_earlyz
= true;
1718 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1720 case nir_intrinsic_image_size
:
1721 case nir_intrinsic_bindless_image_size
:
1722 emit_intrinsic_image_size(ctx
, intr
, dst
);
1724 case nir_intrinsic_image_atomic_add
:
1725 case nir_intrinsic_bindless_image_atomic_add
:
1726 case nir_intrinsic_image_atomic_imin
:
1727 case nir_intrinsic_bindless_image_atomic_imin
:
1728 case nir_intrinsic_image_atomic_umin
:
1729 case nir_intrinsic_bindless_image_atomic_umin
:
1730 case nir_intrinsic_image_atomic_imax
:
1731 case nir_intrinsic_bindless_image_atomic_imax
:
1732 case nir_intrinsic_image_atomic_umax
:
1733 case nir_intrinsic_bindless_image_atomic_umax
:
1734 case nir_intrinsic_image_atomic_and
:
1735 case nir_intrinsic_bindless_image_atomic_and
:
1736 case nir_intrinsic_image_atomic_or
:
1737 case nir_intrinsic_bindless_image_atomic_or
:
1738 case nir_intrinsic_image_atomic_xor
:
1739 case nir_intrinsic_bindless_image_atomic_xor
:
1740 case nir_intrinsic_image_atomic_exchange
:
1741 case nir_intrinsic_bindless_image_atomic_exchange
:
1742 case nir_intrinsic_image_atomic_comp_swap
:
1743 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1744 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1745 !ctx
->s
->info
.fs
.early_fragment_tests
)
1746 ctx
->so
->no_earlyz
= true;
1747 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1749 case nir_intrinsic_control_barrier
:
1750 case nir_intrinsic_memory_barrier
:
1751 case nir_intrinsic_group_memory_barrier
:
1752 case nir_intrinsic_memory_barrier_buffer
:
1753 case nir_intrinsic_memory_barrier_image
:
1754 case nir_intrinsic_memory_barrier_shared
:
1755 emit_intrinsic_barrier(ctx
, intr
);
1756 /* note that blk ptr no longer valid, make that obvious: */
1759 case nir_intrinsic_store_output
:
1760 idx
= nir_intrinsic_base(intr
);
1761 comp
= nir_intrinsic_component(intr
);
1762 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1763 idx
+= nir_src_as_uint(intr
->src
[1]);
1765 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1766 for (int i
= 0; i
< intr
->num_components
; i
++) {
1767 unsigned n
= idx
* 4 + i
+ comp
;
1768 ctx
->outputs
[n
] = src
[i
];
1771 case nir_intrinsic_load_base_vertex
:
1772 case nir_intrinsic_load_first_vertex
:
1773 if (!ctx
->basevertex
) {
1774 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1776 dst
[0] = ctx
->basevertex
;
1778 case nir_intrinsic_load_base_instance
:
1779 if (!ctx
->base_instance
) {
1780 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1782 dst
[0] = ctx
->base_instance
;
1784 case nir_intrinsic_load_vertex_id_zero_base
:
1785 case nir_intrinsic_load_vertex_id
:
1786 if (!ctx
->vertex_id
) {
1787 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1788 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1789 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1791 dst
[0] = ctx
->vertex_id
;
1793 case nir_intrinsic_load_instance_id
:
1794 if (!ctx
->instance_id
) {
1795 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1797 dst
[0] = ctx
->instance_id
;
1799 case nir_intrinsic_load_sample_id
:
1800 ctx
->so
->per_samp
= true;
1802 case nir_intrinsic_load_sample_id_no_per_sample
:
1803 if (!ctx
->samp_id
) {
1804 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1805 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1807 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1809 case nir_intrinsic_load_sample_mask_in
:
1810 if (!ctx
->samp_mask_in
) {
1811 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1813 dst
[0] = ctx
->samp_mask_in
;
1815 case nir_intrinsic_load_user_clip_plane
:
1816 idx
= nir_intrinsic_ucp_id(intr
);
1817 for (int i
= 0; i
< intr
->num_components
; i
++) {
1818 unsigned n
= idx
* 4 + i
;
1819 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1822 case nir_intrinsic_load_front_face
:
1823 if (!ctx
->frag_face
) {
1824 ctx
->so
->frag_face
= true;
1825 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1826 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1828 /* for fragface, we get -1 for back and 0 for front. However this is
1829 * the inverse of what nir expects (where ~0 is true).
1831 dst
[0] = ir3_CMPS_S(b
,
1833 create_immed_typed(b
, 0, TYPE_U16
), 0);
1834 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1836 case nir_intrinsic_load_local_invocation_id
:
1837 if (!ctx
->local_invocation_id
) {
1838 ctx
->local_invocation_id
=
1839 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1841 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1843 case nir_intrinsic_load_work_group_id
:
1844 if (!ctx
->work_group_id
) {
1845 ctx
->work_group_id
=
1846 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1847 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1849 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1851 case nir_intrinsic_load_num_work_groups
:
1852 for (int i
= 0; i
< intr
->num_components
; i
++) {
1853 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1856 case nir_intrinsic_load_local_group_size
:
1857 for (int i
= 0; i
< intr
->num_components
; i
++) {
1858 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1861 case nir_intrinsic_discard_if
:
1862 case nir_intrinsic_discard
: {
1863 struct ir3_instruction
*cond
, *kill
;
1865 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1866 /* conditional discard: */
1867 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1870 /* unconditional discard: */
1871 cond
= create_immed(b
, 1);
1874 /* NOTE: only cmps.*.* can write p0.x: */
1875 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1876 cond
->cat2
.condition
= IR3_COND_NE
;
1878 /* condition always goes in predicate register: */
1879 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1880 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1882 kill
= ir3_KILL(b
, cond
, 0);
1883 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1884 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1886 array_insert(b
, b
->keeps
, kill
);
1887 ctx
->so
->no_earlyz
= true;
1892 case nir_intrinsic_cond_end_ir3
: {
1893 struct ir3_instruction
*cond
, *kill
;
1895 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1898 /* NOTE: only cmps.*.* can write p0.x: */
1899 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1900 cond
->cat2
.condition
= IR3_COND_NE
;
1902 /* condition always goes in predicate register: */
1903 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1905 kill
= ir3_PREDT(b
, cond
, 0);
1907 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1908 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1910 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1911 array_insert(b
, b
->keeps
, kill
);
1915 case nir_intrinsic_load_shared_ir3
:
1916 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1918 case nir_intrinsic_store_shared_ir3
:
1919 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1921 case nir_intrinsic_bindless_resource_ir3
:
1922 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
1925 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1926 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1931 ir3_put_dst(ctx
, &intr
->dest
);
1935 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1937 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1938 instr
->def
.num_components
);
1940 if (instr
->def
.bit_size
== 16) {
1941 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1942 dst
[i
] = create_immed_typed(ctx
->block
,
1943 instr
->value
[i
].u16
,
1946 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1947 dst
[i
] = create_immed_typed(ctx
->block
,
1948 instr
->value
[i
].u32
,
1955 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1957 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1958 undef
->def
.num_components
);
1959 type_t type
= (undef
->def
.bit_size
== 16) ? TYPE_U16
: TYPE_U32
;
1961 /* backend doesn't want undefined instructions, so just plug
1964 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1965 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1969 * texture fetch/sample instructions:
1973 get_tex_dest_type(nir_tex_instr
*tex
)
1977 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
1978 case nir_type_invalid
:
1979 case nir_type_float
:
1980 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_F16
: TYPE_F32
;
1983 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_S16
: TYPE_S32
;
1987 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_U16
: TYPE_U32
;
1990 unreachable("bad dest_type");
1997 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1999 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2002 /* note: would use tex->coord_components.. except txs.. also,
2003 * since array index goes after shadow ref, we don't want to
2007 flags
|= IR3_INSTR_3D
;
2009 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2010 flags
|= IR3_INSTR_S
;
2012 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2013 flags
|= IR3_INSTR_A
;
2019 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2020 * or immediate (in which case it will get lowered later to a non .s2en
2021 * version of the tex instruction which encode tex/samp as immediates:
2023 static struct tex_src_info
2024 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2026 struct ir3_block
*b
= ctx
->block
;
2027 struct tex_src_info info
= { 0 };
2028 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2029 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2030 struct ir3_instruction
*texture
, *sampler
;
2032 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2034 info
.flags
|= IR3_INSTR_B
;
2036 /* Gather information required to determine which encoding to
2037 * choose as well as for prefetch.
2039 nir_intrinsic_instr
*bindless_tex
= NULL
;
2041 if (texture_idx
>= 0) {
2042 ctx
->so
->bindless_tex
= true;
2043 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2044 assert(bindless_tex
);
2045 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2046 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2048 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2050 /* To simplify some of the logic below, assume the index is
2051 * constant 0 when it's not enabled.
2056 nir_intrinsic_instr
*bindless_samp
= NULL
;
2058 if (sampler_idx
>= 0) {
2059 ctx
->so
->bindless_samp
= true;
2060 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2061 assert(bindless_samp
);
2062 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2063 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2065 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2071 /* Choose encoding. */
2072 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2073 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2074 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2075 /* Everything fits within the instruction */
2076 info
.base
= info
.tex_base
;
2077 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2079 info
.base
= info
.tex_base
;
2080 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2081 info
.combined_idx
= info
.samp_idx
;
2082 info
.flags
|= IR3_INSTR_A1EN
;
2084 info
.samp_tex
= NULL
;
2086 info
.flags
|= IR3_INSTR_S2EN
;
2087 /* In the indirect case, we only use a1.x to store the sampler
2088 * base if it differs from the texture base.
2090 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2091 info
.base
= info
.tex_base
;
2093 info
.base
= info
.tex_base
;
2094 info
.a1_val
= info
.samp_base
;
2095 info
.flags
|= IR3_INSTR_A1EN
;
2098 /* Note: the indirect source is now a vec2 instead of hvec2, and
2099 * for some reason the texture and sampler are swapped.
2101 struct ir3_instruction
*texture
, *sampler
;
2104 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2106 texture
= create_immed(b
, 0);
2109 if (bindless_samp
) {
2110 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2112 sampler
= create_immed(b
, 0);
2114 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2120 info
.flags
|= IR3_INSTR_S2EN
;
2121 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2122 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2123 if (texture_idx
>= 0) {
2124 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2125 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2127 /* TODO what to do for dynamic case? I guess we only need the
2128 * max index for astc srgb workaround so maybe not a problem
2129 * to worry about if we don't enable indirect samplers for
2132 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2133 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2134 info
.tex_idx
= tex
->texture_index
;
2137 if (sampler_idx
>= 0) {
2138 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2139 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2141 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2142 info
.samp_idx
= tex
->texture_index
;
2145 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2155 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2157 struct ir3_block
*b
= ctx
->block
;
2158 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2159 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2160 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2161 struct tex_src_info info
= { 0 };
2162 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2163 unsigned i
, coords
, flags
, ncomp
;
2164 unsigned nsrc0
= 0, nsrc1
= 0;
2168 ncomp
= nir_dest_num_components(tex
->dest
);
2170 coord
= off
= ddx
= ddy
= NULL
;
2171 lod
= proj
= compare
= sample_index
= NULL
;
2173 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2175 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2176 switch (tex
->src
[i
].src_type
) {
2177 case nir_tex_src_coord
:
2178 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2180 case nir_tex_src_bias
:
2181 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2184 case nir_tex_src_lod
:
2185 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2188 case nir_tex_src_comparator
: /* shadow comparator */
2189 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2191 case nir_tex_src_projector
:
2192 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2195 case nir_tex_src_offset
:
2196 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2199 case nir_tex_src_ddx
:
2200 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2202 case nir_tex_src_ddy
:
2203 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2205 case nir_tex_src_ms_index
:
2206 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2208 case nir_tex_src_texture_offset
:
2209 case nir_tex_src_sampler_offset
:
2210 case nir_tex_src_texture_handle
:
2211 case nir_tex_src_sampler_handle
:
2212 /* handled in get_tex_samp_src() */
2215 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2216 tex
->src
[i
].src_type
);
2222 case nir_texop_tex_prefetch
:
2223 compile_assert(ctx
, !has_bias
);
2224 compile_assert(ctx
, !has_lod
);
2225 compile_assert(ctx
, !compare
);
2226 compile_assert(ctx
, !has_proj
);
2227 compile_assert(ctx
, !has_off
);
2228 compile_assert(ctx
, !ddx
);
2229 compile_assert(ctx
, !ddy
);
2230 compile_assert(ctx
, !sample_index
);
2231 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2232 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2234 if (ctx
->so
->num_sampler_prefetch
< ctx
->prefetch_limit
) {
2235 opc
= OPC_META_TEX_PREFETCH
;
2236 ctx
->so
->num_sampler_prefetch
++;
2240 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2241 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2242 case nir_texop_txl
: opc
= OPC_SAML
; break;
2243 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2244 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2245 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2247 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2248 * what blob does, seems gather is broken?), and a3xx did
2249 * not support it (but probably could also emulate).
2251 switch (tex
->component
) {
2252 case 0: opc
= OPC_GATHER4R
; break;
2253 case 1: opc
= OPC_GATHER4G
; break;
2254 case 2: opc
= OPC_GATHER4B
; break;
2255 case 3: opc
= OPC_GATHER4A
; break;
2258 case nir_texop_txf_ms_fb
:
2259 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2261 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2265 tex_info(tex
, &flags
, &coords
);
2268 * lay out the first argument in the proper order:
2269 * - actual coordinates first
2270 * - shadow reference
2273 * - starting at offset 4, dpdx.xy, dpdy.xy
2275 * bias/lod go into the second arg
2278 /* insert tex coords: */
2279 for (i
= 0; i
< coords
; i
++)
2284 /* scale up integer coords for TXF based on the LOD */
2285 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2287 for (i
= 0; i
< coords
; i
++)
2288 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2292 /* hw doesn't do 1d, so we treat it as 2d with
2293 * height of 1, and patch up the y coord.
2296 src0
[nsrc0
++] = create_immed(b
, 0);
2298 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2302 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2303 src0
[nsrc0
++] = compare
;
2305 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2306 struct ir3_instruction
*idx
= coord
[coords
];
2308 /* the array coord for cube arrays needs 0.5 added to it */
2309 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2310 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2312 src0
[nsrc0
++] = idx
;
2316 src0
[nsrc0
++] = proj
;
2317 flags
|= IR3_INSTR_P
;
2320 /* pad to 4, then ddx/ddy: */
2321 if (tex
->op
== nir_texop_txd
) {
2323 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2324 for (i
= 0; i
< coords
; i
++)
2325 src0
[nsrc0
++] = ddx
[i
];
2327 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2328 for (i
= 0; i
< coords
; i
++)
2329 src0
[nsrc0
++] = ddy
[i
];
2331 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2334 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2335 * with scaled x coord according to requested sample:
2337 if (opc
== OPC_ISAMM
) {
2338 if (ctx
->compiler
->txf_ms_with_isaml
) {
2339 /* the samples are laid out in x dimension as
2341 * x_ms = (x << ms) + sample_index;
2343 struct ir3_instruction
*ms
;
2344 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2346 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2347 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2351 src0
[nsrc0
++] = sample_index
;
2356 * second argument (if applicable):
2361 if (has_off
| has_lod
| has_bias
) {
2363 unsigned off_coords
= coords
;
2364 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2366 for (i
= 0; i
< off_coords
; i
++)
2367 src1
[nsrc1
++] = off
[i
];
2369 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2370 flags
|= IR3_INSTR_O
;
2373 if (has_lod
| has_bias
)
2374 src1
[nsrc1
++] = lod
;
2377 type
= get_tex_dest_type(tex
);
2379 if (opc
== OPC_GETLOD
)
2383 if (tex
->op
== nir_texop_txf_ms_fb
) {
2384 /* only expect a single txf_ms_fb per shader: */
2385 compile_assert(ctx
, !ctx
->so
->fb_read
);
2386 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2388 ctx
->so
->fb_read
= true;
2389 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2390 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2391 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2393 info
.flags
= IR3_INSTR_S2EN
;
2395 ctx
->so
->num_samp
++;
2397 info
= get_tex_samp_tex_src(ctx
, tex
);
2400 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2401 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2403 if (opc
== OPC_META_TEX_PREFETCH
) {
2404 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2406 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2408 sam
= ir3_META_TEX_PREFETCH(b
);
2409 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2410 __ssa_src(sam
, get_barycentric_pixel(ctx
), 0);
2411 sam
->prefetch
.input_offset
=
2412 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2413 /* make sure not to add irrelevant flags like S2EN */
2414 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2415 sam
->prefetch
.tex
= info
.tex_idx
;
2416 sam
->prefetch
.samp
= info
.samp_idx
;
2417 sam
->prefetch
.tex_base
= info
.tex_base
;
2418 sam
->prefetch
.samp_base
= info
.samp_base
;
2420 info
.flags
|= flags
;
2421 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2424 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2425 assert(opc
!= OPC_META_TEX_PREFETCH
);
2427 /* only need first 3 components: */
2428 sam
->regs
[0]->wrmask
= 0x7;
2429 ir3_split_dest(b
, dst
, sam
, 0, 3);
2431 /* we need to sample the alpha separately with a non-ASTC
2434 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2435 info
.samp_tex
, col0
, col1
);
2437 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2439 /* fixup .w component: */
2440 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2442 /* normal (non-workaround) case: */
2443 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2446 /* GETLOD returns results in 4.8 fixed point */
2447 if (opc
== OPC_GETLOD
) {
2448 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2450 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2451 for (i
= 0; i
< 2; i
++) {
2452 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2457 ir3_put_dst(ctx
, &tex
->dest
);
2461 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2463 struct ir3_block
*b
= ctx
->block
;
2464 struct ir3_instruction
**dst
, *sam
;
2465 type_t dst_type
= get_tex_dest_type(tex
);
2466 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2468 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2470 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2472 /* even though there is only one component, since it ends
2473 * up in .y/.z/.w rather than .x, we need a split_dest()
2475 ir3_split_dest(b
, dst
, sam
, idx
, 1);
2477 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2478 * the value in TEX_CONST_0 is zero-based.
2480 if (ctx
->compiler
->levels_add_one
)
2481 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2483 ir3_put_dst(ctx
, &tex
->dest
);
2487 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2489 struct ir3_block
*b
= ctx
->block
;
2490 struct ir3_instruction
**dst
, *sam
;
2491 struct ir3_instruction
*lod
;
2492 unsigned flags
, coords
;
2493 type_t dst_type
= get_tex_dest_type(tex
);
2494 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2496 tex_info(tex
, &flags
, &coords
);
2497 info
.flags
|= flags
;
2499 /* Actually we want the number of dimensions, not coordinates. This
2500 * distinction only matters for cubes.
2502 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2505 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2507 int lod_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_lod
);
2508 compile_assert(ctx
, lod_idx
>= 0);
2510 lod
= ir3_get_src(ctx
, &tex
->src
[lod_idx
].src
)[0];
2512 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2513 ir3_split_dest(b
, dst
, sam
, 0, 4);
2515 /* Array size actually ends up in .w rather than .z. This doesn't
2516 * matter for miplevel 0, but for higher mips the value in z is
2517 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2518 * returned, which means that we have to add 1 to it for arrays.
2520 if (tex
->is_array
) {
2521 if (ctx
->compiler
->levels_add_one
) {
2522 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2524 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2528 ir3_put_dst(ctx
, &tex
->dest
);
2532 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2534 switch (jump
->type
) {
2535 case nir_jump_break
:
2536 case nir_jump_continue
:
2537 case nir_jump_return
:
2538 /* I *think* we can simply just ignore this, and use the
2539 * successor block link to figure out where we need to
2540 * jump to for break/continue
2544 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2550 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2552 switch (instr
->type
) {
2553 case nir_instr_type_alu
:
2554 emit_alu(ctx
, nir_instr_as_alu(instr
));
2556 case nir_instr_type_deref
:
2557 /* ignored, handled as part of the intrinsic they are src to */
2559 case nir_instr_type_intrinsic
:
2560 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2562 case nir_instr_type_load_const
:
2563 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2565 case nir_instr_type_ssa_undef
:
2566 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2568 case nir_instr_type_tex
: {
2569 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2570 /* couple tex instructions get special-cased:
2574 emit_tex_txs(ctx
, tex
);
2576 case nir_texop_query_levels
:
2577 emit_tex_info(ctx
, tex
, 2);
2579 case nir_texop_texture_samples
:
2580 emit_tex_info(ctx
, tex
, 3);
2588 case nir_instr_type_jump
:
2589 emit_jump(ctx
, nir_instr_as_jump(instr
));
2591 case nir_instr_type_phi
:
2592 /* we have converted phi webs to regs in NIR by now */
2593 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2595 case nir_instr_type_call
:
2596 case nir_instr_type_parallel_copy
:
2597 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2602 static struct ir3_block
*
2603 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2605 struct ir3_block
*block
;
2606 struct hash_entry
*hentry
;
2608 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2610 return hentry
->data
;
2612 block
= ir3_block_create(ctx
->ir
);
2613 block
->nblock
= nblock
;
2614 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2616 set_foreach(nblock
->predecessors
, sentry
) {
2617 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2624 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2626 struct ir3_block
*block
= get_block(ctx
, nblock
);
2628 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2629 if (nblock
->successors
[i
]) {
2630 block
->successors
[i
] =
2631 get_block(ctx
, nblock
->successors
[i
]);
2636 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2638 /* re-emit addr register in each block if needed: */
2639 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2640 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2641 ctx
->addr0_ht
[i
] = NULL
;
2644 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2645 ctx
->addr1_ht
= NULL
;
2647 nir_foreach_instr (instr
, nblock
) {
2648 ctx
->cur_instr
= instr
;
2649 emit_instr(ctx
, instr
);
2650 ctx
->cur_instr
= NULL
;
2655 _mesa_hash_table_clear(ctx
->sel_cond_conversions
, NULL
);
2658 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2661 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2663 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2665 ctx
->block
->condition
= ir3_get_predicate(ctx
, condition
);
2667 emit_cf_list(ctx
, &nif
->then_list
);
2668 emit_cf_list(ctx
, &nif
->else_list
);
2672 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2674 emit_cf_list(ctx
, &nloop
->body
);
2679 stack_push(struct ir3_context
*ctx
)
2682 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2686 stack_pop(struct ir3_context
*ctx
)
2688 compile_assert(ctx
, ctx
->stack
> 0);
2693 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2695 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2696 switch (node
->type
) {
2697 case nir_cf_node_block
:
2698 emit_block(ctx
, nir_cf_node_as_block(node
));
2700 case nir_cf_node_if
:
2702 emit_if(ctx
, nir_cf_node_as_if(node
));
2705 case nir_cf_node_loop
:
2707 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2710 case nir_cf_node_function
:
2711 ir3_context_error(ctx
, "TODO\n");
2717 /* emit stream-out code. At this point, the current block is the original
2718 * (nir) end block, and nir ensures that all flow control paths terminate
2719 * into the end block. We re-purpose the original end block to generate
2720 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2721 * block holding stream-out write instructions, followed by the new end
2725 * p0.x = (vtxcnt < maxvtxcnt)
2726 * // succs: blockStreamOut, blockNewEnd
2729 * // preds: blockOrigEnd
2730 * ... stream-out instructions ...
2731 * // succs: blockNewEnd
2734 * // preds: blockOrigEnd, blockStreamOut
2738 emit_stream_out(struct ir3_context
*ctx
)
2740 struct ir3
*ir
= ctx
->ir
;
2741 struct ir3_stream_output_info
*strmout
=
2742 &ctx
->so
->shader
->stream_output
;
2743 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2744 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2745 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2747 /* create vtxcnt input in input block at top of shader,
2748 * so that it is seen as live over the entire duration
2751 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2752 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2754 /* at this point, we are at the original 'end' block,
2755 * re-purpose this block to stream-out condition, then
2756 * append stream-out block and new-end block
2758 orig_end_block
= ctx
->block
;
2760 // maybe w/ store_global intrinsic, we could do this
2761 // stuff in nir->nir pass
2763 stream_out_block
= ir3_block_create(ir
);
2764 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2766 new_end_block
= ir3_block_create(ir
);
2767 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2769 orig_end_block
->successors
[0] = stream_out_block
;
2770 orig_end_block
->successors
[1] = new_end_block
;
2772 stream_out_block
->successors
[0] = new_end_block
;
2773 _mesa_set_add(stream_out_block
->predecessors
, orig_end_block
);
2775 _mesa_set_add(new_end_block
->predecessors
, orig_end_block
);
2776 _mesa_set_add(new_end_block
->predecessors
, stream_out_block
);
2778 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2779 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2780 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2781 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2782 cond
->cat2
.condition
= IR3_COND_LT
;
2784 /* condition goes on previous block to the conditional,
2785 * since it is used to pick which of the two successor
2788 orig_end_block
->condition
= cond
;
2790 /* switch to stream_out_block to generate the stream-out
2793 ctx
->block
= stream_out_block
;
2795 /* Calculate base addresses based on vtxcnt. Instructions
2796 * generated for bases not used in following loop will be
2797 * stripped out in the backend.
2799 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2800 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2801 unsigned stride
= strmout
->stride
[i
];
2802 struct ir3_instruction
*base
, *off
;
2804 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2806 /* 24-bit should be enough: */
2807 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2808 create_immed(ctx
->block
, stride
* 4), 0);
2810 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2813 /* Generate the per-output store instructions: */
2814 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2815 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2816 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2817 struct ir3_instruction
*base
, *out
, *stg
;
2819 base
= bases
[strmout
->output
[i
].output_buffer
];
2820 out
= ctx
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2822 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2823 create_immed(ctx
->block
, 1), 0);
2824 stg
->cat6
.type
= TYPE_U32
;
2825 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2827 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2831 /* and finally switch to the new_end_block: */
2832 ctx
->block
= new_end_block
;
2836 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2838 nir_metadata_require(impl
, nir_metadata_block_index
);
2840 compile_assert(ctx
, ctx
->stack
== 0);
2842 emit_cf_list(ctx
, &impl
->body
);
2843 emit_block(ctx
, impl
->end_block
);
2845 compile_assert(ctx
, ctx
->stack
== 0);
2847 /* at this point, we should have a single empty block,
2848 * into which we emit the 'end' instruction.
2850 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2852 /* If stream-out (aka transform-feedback) enabled, emit the
2853 * stream-out instructions, followed by a new empty block (into
2854 * which the 'end' instruction lands).
2856 * NOTE: it is done in this order, rather than inserting before
2857 * we emit end_block, because NIR guarantees that all blocks
2858 * flow into end_block, and that end_block has no successors.
2859 * So by re-purposing end_block as the first block of stream-
2860 * out, we guarantee that all exit paths flow into the stream-
2863 if ((ctx
->compiler
->gpu_id
< 500) &&
2864 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2865 !ctx
->so
->binning_pass
) {
2866 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2867 emit_stream_out(ctx
);
2870 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2871 * NOP and has an epilogue that writes the VS outputs to local storage, to
2872 * be read by the HS. Then it resets execution mask (chmask) and chains
2873 * to the next shader (chsh).
2875 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2876 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2877 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2878 struct ir3_instruction
*chmask
=
2879 ir3_CHMASK(ctx
->block
);
2880 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2881 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2883 struct ir3_instruction
*chsh
=
2884 ir3_CHSH(ctx
->block
);
2885 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2886 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2888 ir3_END(ctx
->block
);
2893 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2895 struct ir3_shader_variant
*so
= ctx
->so
;
2896 unsigned ncomp
= glsl_get_components(in
->type
);
2897 unsigned n
= in
->data
.driver_location
;
2898 unsigned frac
= in
->data
.location_frac
;
2899 unsigned slot
= in
->data
.location
;
2901 /* Inputs are loaded using ldlw or ldg for these stages. */
2902 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2903 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2904 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2907 /* skip unread inputs, we could end up with (for example), unsplit
2908 * matrix/etc inputs in the case they are not read, so just silently
2914 so
->inputs
[n
].slot
= slot
;
2915 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2916 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2917 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2919 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2921 /* if any varyings have 'sample' qualifer, that triggers us
2922 * to run in per-sample mode:
2924 so
->per_samp
|= in
->data
.sample
;
2926 for (int i
= 0; i
< ncomp
; i
++) {
2927 struct ir3_instruction
*instr
= NULL
;
2928 unsigned idx
= (n
* 4) + i
+ frac
;
2930 if (slot
== VARYING_SLOT_POS
) {
2931 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2933 /* detect the special case for front/back colors where
2934 * we need to do flat vs smooth shading depending on
2937 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2939 case VARYING_SLOT_COL0
:
2940 case VARYING_SLOT_COL1
:
2941 case VARYING_SLOT_BFC0
:
2942 case VARYING_SLOT_BFC1
:
2943 so
->inputs
[n
].rasterflat
= true;
2950 if (ctx
->compiler
->flat_bypass
) {
2951 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2952 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2953 so
->inputs
[n
].use_ldlv
= true;
2956 so
->inputs
[n
].bary
= true;
2958 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2961 compile_assert(ctx
, idx
< ctx
->ninputs
);
2963 ctx
->inputs
[idx
] = instr
;
2965 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2966 struct ir3_instruction
*input
= NULL
, *in
;
2967 struct ir3_instruction
*components
[4];
2968 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
2970 foreach_input (in
, ctx
->ir
) {
2971 if (in
->input
.inidx
== n
) {
2978 input
= create_input(ctx
, mask
);
2979 input
->input
.inidx
= n
;
2981 input
->regs
[0]->wrmask
|= mask
;
2984 ir3_split_dest(ctx
->block
, components
, input
, frac
, ncomp
);
2986 for (int i
= 0; i
< ncomp
; i
++) {
2987 unsigned idx
= (n
* 4) + i
+ frac
;
2988 compile_assert(ctx
, idx
< ctx
->ninputs
);
2989 ctx
->inputs
[idx
] = components
[i
];
2992 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2995 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2996 so
->total_in
+= ncomp
;
3000 /* Initially we assign non-packed inloc's for varyings, as we don't really
3001 * know up-front which components will be unused. After all the compilation
3002 * stages we scan the shader to see which components are actually used, and
3003 * re-pack the inlocs to eliminate unneeded varyings.
3006 pack_inlocs(struct ir3_context
*ctx
)
3008 struct ir3_shader_variant
*so
= ctx
->so
;
3009 uint8_t used_components
[so
->inputs_count
];
3011 memset(used_components
, 0, sizeof(used_components
));
3014 * First Step: scan shader to find which bary.f/ldlv remain:
3017 foreach_block (block
, &ctx
->ir
->block_list
) {
3018 foreach_instr (instr
, &block
->instr_list
) {
3019 if (is_input(instr
)) {
3020 unsigned inloc
= instr
->regs
[1]->iim_val
;
3021 unsigned i
= inloc
/ 4;
3022 unsigned j
= inloc
% 4;
3024 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3025 compile_assert(ctx
, i
< so
->inputs_count
);
3027 used_components
[i
] |= 1 << j
;
3028 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3029 for (int n
= 0; n
< 2; n
++) {
3030 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3031 unsigned i
= inloc
/ 4;
3032 unsigned j
= inloc
% 4;
3034 compile_assert(ctx
, i
< so
->inputs_count
);
3036 used_components
[i
] |= 1 << j
;
3043 * Second Step: reassign varying inloc/slots:
3046 unsigned actual_in
= 0;
3049 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3050 unsigned compmask
= 0, maxcomp
= 0;
3052 so
->inputs
[i
].inloc
= inloc
;
3053 so
->inputs
[i
].bary
= false;
3055 for (unsigned j
= 0; j
< 4; j
++) {
3056 if (!(used_components
[i
] & (1 << j
)))
3059 compmask
|= (1 << j
);
3063 /* at this point, since used_components[i] mask is only
3064 * considering varyings (ie. not sysvals) we know this
3067 so
->inputs
[i
].bary
= true;
3070 if (so
->inputs
[i
].bary
) {
3072 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3078 * Third Step: reassign packed inloc's:
3081 foreach_block (block
, &ctx
->ir
->block_list
) {
3082 foreach_instr (instr
, &block
->instr_list
) {
3083 if (is_input(instr
)) {
3084 unsigned inloc
= instr
->regs
[1]->iim_val
;
3085 unsigned i
= inloc
/ 4;
3086 unsigned j
= inloc
% 4;
3088 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3089 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3090 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3091 unsigned j
= instr
->prefetch
.input_offset
% 4;
3092 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3099 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3101 struct ir3_shader_variant
*so
= ctx
->so
;
3102 unsigned slots
= glsl_count_vec4_slots(out
->type
, false, false);
3103 unsigned ncomp
= glsl_get_components(glsl_without_array(out
->type
));
3104 unsigned n
= out
->data
.driver_location
;
3105 unsigned frac
= out
->data
.location_frac
;
3106 unsigned slot
= out
->data
.location
;
3108 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3110 case FRAG_RESULT_DEPTH
:
3111 so
->writes_pos
= true;
3113 case FRAG_RESULT_COLOR
:
3116 case FRAG_RESULT_SAMPLE_MASK
:
3117 so
->writes_smask
= true;
3120 slot
+= out
->data
.index
; /* For dual-src blend */
3121 if (slot
>= FRAG_RESULT_DATA0
)
3123 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3124 gl_frag_result_name(slot
));
3126 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3127 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3128 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3130 case VARYING_SLOT_POS
:
3131 so
->writes_pos
= true;
3133 case VARYING_SLOT_PSIZ
:
3134 so
->writes_psize
= true;
3136 case VARYING_SLOT_PRIMITIVE_ID
:
3137 case VARYING_SLOT_LAYER
:
3138 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3139 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3141 case VARYING_SLOT_COL0
:
3142 case VARYING_SLOT_COL1
:
3143 case VARYING_SLOT_BFC0
:
3144 case VARYING_SLOT_BFC1
:
3145 case VARYING_SLOT_FOGC
:
3146 case VARYING_SLOT_CLIP_DIST0
:
3147 case VARYING_SLOT_CLIP_DIST1
:
3148 case VARYING_SLOT_CLIP_VERTEX
:
3151 if (slot
>= VARYING_SLOT_VAR0
)
3153 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3155 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3156 _mesa_shader_stage_to_string(ctx
->so
->type
),
3157 gl_varying_slot_name(slot
));
3159 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3160 /* output lowered to buffer writes. */
3163 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3167 so
->outputs_count
= out
->data
.driver_location
+ slots
;
3168 compile_assert(ctx
, so
->outputs_count
< ARRAY_SIZE(so
->outputs
));
3170 for (int i
= 0; i
< slots
; i
++) {
3171 int slot_base
= n
+ i
;
3172 so
->outputs
[slot_base
].slot
= slot
+ i
;
3174 for (int i
= 0; i
< ncomp
; i
++) {
3175 unsigned idx
= (slot_base
* 4) + i
+ frac
;
3176 compile_assert(ctx
, idx
< ctx
->noutputs
);
3177 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3180 /* if varying packing doesn't happen, we could end up in a situation
3181 * with "holes" in the output, and since the per-generation code that
3182 * sets up varying linkage registers doesn't expect to have more than
3183 * one varying per vec4 slot, pad the holes.
3185 * Note that this should probably generate a performance warning of
3188 for (int i
= 0; i
< frac
; i
++) {
3189 unsigned idx
= (slot_base
* 4) + i
;
3190 if (!ctx
->outputs
[idx
]) {
3191 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3198 emit_instructions(struct ir3_context
*ctx
)
3200 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3202 ctx
->ninputs
= ctx
->s
->num_inputs
* 4;
3203 ctx
->noutputs
= ctx
->s
->num_outputs
* 4;
3204 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3205 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3207 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3209 /* Create inputs in first block: */
3210 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3211 ctx
->in_block
= ctx
->block
;
3213 /* for fragment shader, the vcoord input register is used as the
3214 * base for bary.f varying fetch instrs:
3216 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3217 * until emit_intrinsic when we know they are actually needed.
3218 * For now, we defer creating ctx->ij_centroid, etc, since we
3219 * only need ij_pixel for "old style" varying inputs (ie.
3222 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3223 ctx
->ij_pixel
= create_input(ctx
, 0x3);
3227 nir_foreach_variable (var
, &ctx
->s
->inputs
) {
3228 setup_input(ctx
, var
);
3231 /* Defer add_sysval_input() stuff until after setup_inputs(),
3232 * because sysvals need to be appended after varyings:
3234 if (ctx
->ij_pixel
) {
3235 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3236 0x3, ctx
->ij_pixel
);
3240 /* Tesselation shaders always need primitive ID for indexing the
3241 * BO. Geometry shaders don't always need it but when they do it has be
3242 * delivered and unclobbered in the VS. To make things easy, we always
3243 * make room for it in VS/DS.
3245 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3246 bool has_gs
= ctx
->so
->key
.has_gs
;
3247 switch (ctx
->so
->type
) {
3248 case MESA_SHADER_VERTEX
:
3250 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3251 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3252 } else if (has_gs
) {
3253 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3254 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3257 case MESA_SHADER_TESS_CTRL
:
3258 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3259 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3261 case MESA_SHADER_TESS_EVAL
:
3263 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3264 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3266 case MESA_SHADER_GEOMETRY
:
3267 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3268 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3274 /* Setup outputs: */
3275 nir_foreach_variable (var
, &ctx
->s
->outputs
) {
3276 setup_output(ctx
, var
);
3279 /* Find # of samplers: */
3280 nir_foreach_variable (var
, &ctx
->s
->uniforms
) {
3281 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
3282 /* just assume that we'll be reading from images.. if it
3283 * is write-only we don't have to count it, but not sure
3284 * if there is a good way to know?
3286 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
3289 /* NOTE: need to do something more clever when we support >1 fxn */
3290 nir_foreach_register (reg
, &fxn
->registers
) {
3291 ir3_declare_array(ctx
, reg
);
3293 /* And emit the body: */
3295 emit_function(ctx
, fxn
);
3298 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3299 * need to assign the tex state indexes for these after we know the
3303 fixup_astc_srgb(struct ir3_context
*ctx
)
3305 struct ir3_shader_variant
*so
= ctx
->so
;
3306 /* indexed by original tex idx, value is newly assigned alpha sampler
3307 * state tex idx. Zero is invalid since there is at least one sampler
3310 unsigned alt_tex_state
[16] = {0};
3311 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3314 so
->astc_srgb
.base
= tex_idx
;
3316 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3317 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3319 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3321 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3322 /* assign new alternate/alpha tex state slot: */
3323 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3324 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3325 so
->astc_srgb
.count
++;
3328 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3333 fixup_binning_pass(struct ir3_context
*ctx
)
3335 struct ir3_shader_variant
*so
= ctx
->so
;
3336 struct ir3
*ir
= ctx
->ir
;
3339 /* first pass, remove unused outputs from the IR level outputs: */
3340 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3341 struct ir3_instruction
*out
= ir
->outputs
[i
];
3342 assert(out
->opc
== OPC_META_COLLECT
);
3343 unsigned outidx
= out
->collect
.outidx
;
3344 unsigned slot
= so
->outputs
[outidx
].slot
;
3346 /* throw away everything but first position/psize */
3347 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3348 ir
->outputs
[j
] = ir
->outputs
[i
];
3352 ir
->outputs_count
= j
;
3354 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3357 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3358 unsigned slot
= so
->outputs
[i
].slot
;
3360 /* throw away everything but first position/psize */
3361 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3362 so
->outputs
[j
] = so
->outputs
[i
];
3364 /* fixup outidx to point to new output table entry: */
3365 struct ir3_instruction
*out
;
3366 foreach_output (out
, ir
) {
3367 if (out
->collect
.outidx
== i
) {
3368 out
->collect
.outidx
= j
;
3376 so
->outputs_count
= j
;
3380 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3384 /* Collect sampling instructions eligible for pre-dispatch. */
3385 foreach_block (block
, &ir
->block_list
) {
3386 foreach_instr_safe (instr
, &block
->instr_list
) {
3387 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3388 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3389 struct ir3_sampler_prefetch
*fetch
=
3390 &ctx
->so
->sampler_prefetch
[idx
];
3393 if (instr
->flags
& IR3_INSTR_B
) {
3394 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3395 /* In bindless mode, the index is actually the base */
3396 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3397 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3398 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3399 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3401 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3402 fetch
->tex_id
= instr
->prefetch
.tex
;
3403 fetch
->samp_id
= instr
->prefetch
.samp
;
3405 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3406 fetch
->dst
= instr
->regs
[0]->num
;
3407 fetch
->src
= instr
->prefetch
.input_offset
;
3410 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3412 /* Disable half precision until supported. */
3413 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3415 /* Remove the prefetch placeholder instruction: */
3416 list_delinit(&instr
->node
);
3423 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3424 struct ir3_shader_variant
*so
)
3426 struct ir3_context
*ctx
;
3428 int ret
= 0, max_bary
;
3432 ctx
= ir3_context_init(compiler
, so
);
3434 DBG("INIT failed!");
3439 emit_instructions(ctx
);
3442 DBG("EMIT failed!");
3447 ir
= so
->ir
= ctx
->ir
;
3449 assert((ctx
->noutputs
% 4) == 0);
3451 /* Setup IR level outputs, which are "collects" that gather
3452 * the scalar components of outputs.
3454 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3456 /* figure out the # of components written:
3458 * TODO do we need to handle holes, ie. if .x and .z
3459 * components written, but .y component not written?
3461 for (unsigned j
= 0; j
< 4; j
++) {
3462 if (!ctx
->outputs
[i
+ j
])
3467 /* Note that in some stages, like TCS, store_output is
3468 * lowered to memory writes, so no components of the
3469 * are "written" from the PoV of traditional store-
3470 * output instructions:
3475 struct ir3_instruction
*out
=
3476 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3479 assert(outidx
< so
->outputs_count
);
3481 /* stash index into so->outputs[] so we can map the
3482 * output back to slot/etc later:
3484 out
->collect
.outidx
= outidx
;
3486 array_insert(ir
, ir
->outputs
, out
);
3489 /* Set up the gs header as an output for the vertex shader so it won't
3490 * clobber it for the tess ctrl shader.
3492 * TODO this could probably be done more cleanly in a nir pass.
3494 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3495 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3496 if (ctx
->primitive_id
) {
3497 unsigned n
= so
->outputs_count
++;
3498 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3500 struct ir3_instruction
*out
=
3501 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3502 out
->collect
.outidx
= n
;
3503 array_insert(ir
, ir
->outputs
, out
);
3506 if (ctx
->gs_header
) {
3507 unsigned n
= so
->outputs_count
++;
3508 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3509 struct ir3_instruction
*out
=
3510 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3511 out
->collect
.outidx
= n
;
3512 array_insert(ir
, ir
->outputs
, out
);
3515 if (ctx
->tcs_header
) {
3516 unsigned n
= so
->outputs_count
++;
3517 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3518 struct ir3_instruction
*out
=
3519 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3520 out
->collect
.outidx
= n
;
3521 array_insert(ir
, ir
->outputs
, out
);
3525 /* at this point, for binning pass, throw away unneeded outputs: */
3526 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3527 fixup_binning_pass(ctx
);
3529 ir3_debug_print(ir
, "BEFORE CF");
3533 ir3_debug_print(ir
, "BEFORE CP");
3537 /* at this point, for binning pass, throw away unneeded outputs:
3538 * Note that for a6xx and later, we do this after ir3_cp to ensure
3539 * that the uniform/constant layout for BS and VS matches, so that
3540 * we can re-use same VS_CONST state group.
3542 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3543 fixup_binning_pass(ctx
);
3545 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3546 * need to make sure not to remove any inputs that are used by
3547 * the nonbinning VS.
3549 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3550 so
->type
== MESA_SHADER_VERTEX
) {
3551 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3552 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3560 debug_assert(n
< so
->nonbinning
->inputs_count
);
3562 if (so
->nonbinning
->inputs
[n
].sysval
)
3565 /* be sure to keep inputs, even if only used in VS */
3566 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3567 array_insert(in
->block
, in
->block
->keeps
, in
);
3571 ir3_debug_print(ir
, "BEFORE GROUPING");
3573 ir3_sched_add_deps(ir
);
3575 /* Group left/right neighbors, inserting mov's where needed to
3580 ir3_debug_print(ir
, "AFTER GROUPING");
3584 ir3_debug_print(ir
, "AFTER DCE");
3586 ret
= ir3_sched(ir
);
3588 DBG("SCHED failed!");
3592 ir3_debug_print(ir
, "AFTER SCHED");
3594 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3595 * with draw pass VS, so binning and draw pass can both use the
3598 * Note that VS inputs are expected to be full precision.
3600 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3601 (ir
->type
== MESA_SHADER_VERTEX
) &&
3604 if (pre_assign_inputs
) {
3605 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3606 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3613 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3615 instr
->regs
[0]->num
= regid
;
3618 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3619 } else if (ctx
->tcs_header
) {
3620 /* We need to have these values in the same registers between VS and TCS
3621 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3624 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3625 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3626 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3627 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3628 } else if (ctx
->gs_header
) {
3629 /* We need to have these values in the same registers between producer
3630 * (VS or DS) and GS since the producer chains to GS and doesn't get
3631 * the sysvals redelivered.
3634 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3635 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3636 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3637 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3638 } else if (so
->num_sampler_prefetch
) {
3639 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3640 struct ir3_instruction
*instr
, *precolor
[2];
3643 foreach_input (instr
, ir
) {
3644 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3647 assert(idx
< ARRAY_SIZE(precolor
));
3649 precolor
[idx
] = instr
;
3650 instr
->regs
[0]->num
= idx
;
3654 ret
= ir3_ra(so
, precolor
, idx
);
3656 ret
= ir3_ra(so
, NULL
, 0);
3665 ir3_debug_print(ir
, "AFTER POSTSCHED");
3667 if (compiler
->gpu_id
>= 600) {
3668 if (ir3_a6xx_fixup_atomic_dests(ir
, so
)) {
3669 ir3_debug_print(ir
, "AFTER ATOMIC FIXUP");
3673 if (so
->type
== MESA_SHADER_FRAGMENT
)
3677 * Fixup inputs/outputs to point to the actual registers assigned:
3679 * 1) initialize to r63.x (invalid/unused)
3680 * 2) iterate IR level inputs/outputs and update the variants
3681 * inputs/outputs table based on the assigned registers for
3682 * the remaining inputs/outputs.
3685 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3686 so
->inputs
[i
].regid
= INVALID_REG
;
3687 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3688 so
->outputs
[i
].regid
= INVALID_REG
;
3690 struct ir3_instruction
*out
;
3691 foreach_output (out
, ir
) {
3692 assert(out
->opc
== OPC_META_COLLECT
);
3693 unsigned outidx
= out
->collect
.outidx
;
3695 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3696 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3699 struct ir3_instruction
*in
;
3700 foreach_input (in
, ir
) {
3701 assert(in
->opc
== OPC_META_INPUT
);
3702 unsigned inidx
= in
->input
.inidx
;
3704 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3705 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3706 compile_assert(ctx
, in
->regs
[0]->num
==
3707 so
->nonbinning
->inputs
[inidx
].regid
);
3708 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3709 so
->nonbinning
->inputs
[inidx
].half
);
3711 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3712 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3714 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3715 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3720 fixup_astc_srgb(ctx
);
3722 /* We need to do legalize after (for frag shader's) the "bary.f"
3723 * offsets (inloc) have been assigned.
3725 ir3_legalize(ir
, so
, &max_bary
);
3727 ir3_debug_print(ir
, "AFTER LEGALIZE");
3729 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3730 * know what we might have to wait on when coming in from VS chsh.
3732 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3733 so
->type
== MESA_SHADER_GEOMETRY
) {
3734 foreach_block (block
, &ir
->block_list
) {
3735 foreach_instr (instr
, &block
->instr_list
) {
3736 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3742 so
->branchstack
= ctx
->max_stack
;
3744 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3745 if (so
->type
== MESA_SHADER_FRAGMENT
)
3746 so
->total_in
= max_bary
+ 1;
3748 /* Collect sampling instructions eligible for pre-dispatch. */
3749 collect_tex_prefetches(ctx
, ir
);
3751 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3752 ctx
->s
->info
.fs
.needs_helper_invocations
)
3753 so
->need_pixlod
= true;
3758 ir3_destroy(so
->ir
);
3761 ir3_context_free(ctx
);