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freedreno/ir3: Add unit tests for derivatives disasm.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42 void
43 ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
44 {
45 nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
46 if (!intrin)
47 return;
48
49 instr->flags |= IR3_INSTR_B;
50 instr->cat6.base = nir_intrinsic_desc_set(intrin);
51 }
52
53 static struct ir3_instruction *
54 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
55 struct ir3_instruction *address, struct ir3_instruction *collect)
56 {
57 struct ir3_block *block = ctx->block;
58 struct ir3_instruction *mov;
59 struct ir3_register *src;
60
61 mov = ir3_instr_create(block, OPC_MOV);
62 mov->cat1.src_type = TYPE_U32;
63 mov->cat1.dst_type = TYPE_U32;
64 __ssa_dst(mov);
65 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
66 src->size = arrsz;
67 src->array.offset = n;
68
69 ir3_instr_set_address(mov, address);
70
71 return mov;
72 }
73
74 static struct ir3_instruction *
75 create_input(struct ir3_context *ctx, unsigned compmask)
76 {
77 struct ir3_instruction *in;
78
79 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
80 in->input.sysval = ~0;
81 __ssa_dst(in)->wrmask = compmask;
82
83 array_insert(ctx->ir, ctx->ir->inputs, in);
84
85 return in;
86 }
87
88 static struct ir3_instruction *
89 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
90 {
91 struct ir3_block *block = ctx->block;
92 struct ir3_instruction *instr;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction *inloc = create_immed(block, n);
95
96 if (use_ldlv) {
97 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
98 instr->cat6.type = TYPE_U32;
99 instr->cat6.iim_val = 1;
100 } else {
101 instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0);
102 instr->regs[2]->wrmask = 0x3;
103 }
104
105 return instr;
106 }
107
108 static struct ir3_instruction *
109 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
110 {
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
114 unsigned n = const_state->offsets.driver_param;
115 unsigned r = regid(n + dp / 4, dp % 4);
116 return create_uniform(ctx->block, r);
117 }
118
119 /*
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
124 * 0.
125 */
126
127 /*
128 * alu/sfu instructions:
129 */
130
131 static struct ir3_instruction *
132 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
133 unsigned src_bitsize, nir_op op)
134 {
135 type_t src_type, dst_type;
136
137 switch (op) {
138 case nir_op_f2f32:
139 case nir_op_f2f16_rtne:
140 case nir_op_f2f16_rtz:
141 case nir_op_f2f16:
142 case nir_op_f2i32:
143 case nir_op_f2i16:
144 case nir_op_f2i8:
145 case nir_op_f2u32:
146 case nir_op_f2u16:
147 case nir_op_f2u8:
148 switch (src_bitsize) {
149 case 32:
150 src_type = TYPE_F32;
151 break;
152 case 16:
153 src_type = TYPE_F16;
154 break;
155 default:
156 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
157 }
158 break;
159
160 case nir_op_i2f32:
161 case nir_op_i2f16:
162 case nir_op_i2i32:
163 case nir_op_i2i16:
164 case nir_op_i2i8:
165 switch (src_bitsize) {
166 case 32:
167 src_type = TYPE_S32;
168 break;
169 case 16:
170 src_type = TYPE_S16;
171 break;
172 case 8:
173 src_type = TYPE_S8;
174 break;
175 default:
176 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
177 }
178 break;
179
180 case nir_op_u2f32:
181 case nir_op_u2f16:
182 case nir_op_u2u32:
183 case nir_op_u2u16:
184 case nir_op_u2u8:
185 switch (src_bitsize) {
186 case 32:
187 src_type = TYPE_U32;
188 break;
189 case 16:
190 src_type = TYPE_U16;
191 break;
192 case 8:
193 src_type = TYPE_U8;
194 break;
195 default:
196 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
197 }
198 break;
199
200 case nir_op_b2f16:
201 case nir_op_b2f32:
202 case nir_op_b2i8:
203 case nir_op_b2i16:
204 case nir_op_b2i32:
205 src_type = TYPE_U32;
206 break;
207
208 default:
209 ir3_context_error(ctx, "invalid conversion op: %u", op);
210 }
211
212 switch (op) {
213 case nir_op_f2f32:
214 case nir_op_i2f32:
215 case nir_op_u2f32:
216 case nir_op_b2f32:
217 dst_type = TYPE_F32;
218 break;
219
220 case nir_op_f2f16_rtne:
221 case nir_op_f2f16_rtz:
222 case nir_op_f2f16:
223 case nir_op_i2f16:
224 case nir_op_u2f16:
225 case nir_op_b2f16:
226 dst_type = TYPE_F16;
227 break;
228
229 case nir_op_f2i32:
230 case nir_op_i2i32:
231 case nir_op_b2i32:
232 dst_type = TYPE_S32;
233 break;
234
235 case nir_op_f2i16:
236 case nir_op_i2i16:
237 case nir_op_b2i16:
238 dst_type = TYPE_S16;
239 break;
240
241 case nir_op_f2i8:
242 case nir_op_i2i8:
243 case nir_op_b2i8:
244 dst_type = TYPE_S8;
245 break;
246
247 case nir_op_f2u32:
248 case nir_op_u2u32:
249 dst_type = TYPE_U32;
250 break;
251
252 case nir_op_f2u16:
253 case nir_op_u2u16:
254 dst_type = TYPE_U16;
255 break;
256
257 case nir_op_f2u8:
258 case nir_op_u2u8:
259 dst_type = TYPE_U8;
260 break;
261
262 default:
263 ir3_context_error(ctx, "invalid conversion op: %u", op);
264 }
265
266 if (src_type == dst_type)
267 return src;
268
269 struct ir3_instruction *cov =
270 ir3_COV(ctx->block, src, src_type, dst_type);
271
272 if (op == nir_op_f2f16_rtne)
273 cov->regs[0]->flags |= IR3_REG_EVEN;
274
275 return cov;
276 }
277
278 static void
279 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
280 {
281 const nir_op_info *info = &nir_op_infos[alu->op];
282 struct ir3_instruction **dst, *src[info->num_inputs];
283 unsigned bs[info->num_inputs]; /* bit size */
284 struct ir3_block *b = ctx->block;
285 unsigned dst_sz, wrmask;
286 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
287 TYPE_U16 : TYPE_U32;
288
289 if (alu->dest.dest.is_ssa) {
290 dst_sz = alu->dest.dest.ssa.num_components;
291 wrmask = (1 << dst_sz) - 1;
292 } else {
293 dst_sz = alu->dest.dest.reg.reg->num_components;
294 wrmask = alu->dest.write_mask;
295 }
296
297 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
298
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
302 */
303 if ((alu->op == nir_op_vec2) ||
304 (alu->op == nir_op_vec3) ||
305 (alu->op == nir_op_vec4)) {
306
307 for (int i = 0; i < info->num_inputs; i++) {
308 nir_alu_src *asrc = &alu->src[i];
309
310 compile_assert(ctx, !asrc->abs);
311 compile_assert(ctx, !asrc->negate);
312
313 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
314 if (!src[i])
315 src[i] = create_immed_typed(ctx->block, 0, dst_type);
316 dst[i] = ir3_MOV(b, src[i], dst_type);
317 }
318
319 ir3_put_dst(ctx, &alu->dest.dest);
320 return;
321 }
322
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
325 */
326 if (alu->op == nir_op_mov) {
327 nir_alu_src *asrc = &alu->src[0];
328 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
329
330 for (unsigned i = 0; i < dst_sz; i++) {
331 if (wrmask & (1 << i)) {
332 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
333 } else {
334 dst[i] = NULL;
335 }
336 }
337
338 ir3_put_dst(ctx, &alu->dest.dest);
339 return;
340 }
341
342 /* General case: We can just grab the one used channel per src. */
343 for (int i = 0; i < info->num_inputs; i++) {
344 unsigned chan = ffs(alu->dest.write_mask) - 1;
345 nir_alu_src *asrc = &alu->src[i];
346
347 compile_assert(ctx, !asrc->abs);
348 compile_assert(ctx, !asrc->negate);
349
350 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
351 bs[i] = nir_src_bit_size(asrc->src);
352
353 compile_assert(ctx, src[i]);
354 }
355
356 switch (alu->op) {
357 case nir_op_f2f32:
358 case nir_op_f2f16_rtne:
359 case nir_op_f2f16_rtz:
360 case nir_op_f2f16:
361 case nir_op_f2i32:
362 case nir_op_f2i16:
363 case nir_op_f2i8:
364 case nir_op_f2u32:
365 case nir_op_f2u16:
366 case nir_op_f2u8:
367 case nir_op_i2f32:
368 case nir_op_i2f16:
369 case nir_op_i2i32:
370 case nir_op_i2i16:
371 case nir_op_i2i8:
372 case nir_op_u2f32:
373 case nir_op_u2f16:
374 case nir_op_u2u32:
375 case nir_op_u2u16:
376 case nir_op_u2u8:
377 case nir_op_b2f16:
378 case nir_op_b2f32:
379 case nir_op_b2i8:
380 case nir_op_b2i16:
381 case nir_op_b2i32:
382 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
383 break;
384
385 case nir_op_fquantize2f16:
386 dst[0] = create_cov(ctx,
387 create_cov(ctx, src[0], 32, nir_op_f2f16),
388 16, nir_op_f2f32);
389 break;
390 case nir_op_f2b1:
391 dst[0] = ir3_CMPS_F(b,
392 src[0], 0,
393 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
394 dst[0]->cat2.condition = IR3_COND_NE;
395 break;
396
397 case nir_op_i2b1:
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
400 */
401 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
402 dst[0]->cat2.condition = IR3_COND_NE;
403 break;
404
405 case nir_op_b2b1:
406 /* b2b1 will appear when translating from
407 *
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
410 *
411 * A negate can turn those into a 1 or 0 for us.
412 */
413 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
414 break;
415
416 case nir_op_b2b32:
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
418 * argument.
419 *
420 * A negate can turn those into a ~0 for us.
421 */
422 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
423 break;
424
425 case nir_op_fneg:
426 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
427 break;
428 case nir_op_fabs:
429 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
430 break;
431 case nir_op_fmax:
432 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
433 break;
434 case nir_op_fmin:
435 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
436 break;
437 case nir_op_fsat:
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
441 * to eliminate.
442 *
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
445 * everywhere.
446 *
447 * TODO probably opc_cat==4 is ok too
448 */
449 if (alu->src[0].src.is_ssa &&
450 src[0]->opc != OPC_BARY_F &&
451 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
452 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
453 src[0]->flags |= IR3_INSTR_SAT;
454 dst[0] = ir3_MOV(b, src[0], dst_type);
455 } else {
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
458 */
459 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
460 dst[0]->flags |= IR3_INSTR_SAT;
461 }
462 break;
463 case nir_op_fmul:
464 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
465 break;
466 case nir_op_fadd:
467 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
468 break;
469 case nir_op_fsub:
470 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
471 break;
472 case nir_op_ffma:
473 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
474 break;
475 case nir_op_fddx:
476 case nir_op_fddx_coarse:
477 dst[0] = ir3_DSX(b, src[0], 0);
478 dst[0]->cat5.type = TYPE_F32;
479 break;
480 case nir_op_fddx_fine:
481 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_fddy:
485 case nir_op_fddy_coarse:
486 dst[0] = ir3_DSY(b, src[0], 0);
487 dst[0]->cat5.type = TYPE_F32;
488 break;
489 break;
490 case nir_op_fddy_fine:
491 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
492 dst[0]->cat5.type = TYPE_F32;
493 break;
494 case nir_op_flt:
495 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
496 dst[0]->cat2.condition = IR3_COND_LT;
497 break;
498 case nir_op_fge:
499 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
500 dst[0]->cat2.condition = IR3_COND_GE;
501 break;
502 case nir_op_feq:
503 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
504 dst[0]->cat2.condition = IR3_COND_EQ;
505 break;
506 case nir_op_fne:
507 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
508 dst[0]->cat2.condition = IR3_COND_NE;
509 break;
510 case nir_op_fceil:
511 dst[0] = ir3_CEIL_F(b, src[0], 0);
512 break;
513 case nir_op_ffloor:
514 dst[0] = ir3_FLOOR_F(b, src[0], 0);
515 break;
516 case nir_op_ftrunc:
517 dst[0] = ir3_TRUNC_F(b, src[0], 0);
518 break;
519 case nir_op_fround_even:
520 dst[0] = ir3_RNDNE_F(b, src[0], 0);
521 break;
522 case nir_op_fsign:
523 dst[0] = ir3_SIGN_F(b, src[0], 0);
524 break;
525
526 case nir_op_fsin:
527 dst[0] = ir3_SIN(b, src[0], 0);
528 break;
529 case nir_op_fcos:
530 dst[0] = ir3_COS(b, src[0], 0);
531 break;
532 case nir_op_frsq:
533 dst[0] = ir3_RSQ(b, src[0], 0);
534 break;
535 case nir_op_frcp:
536 dst[0] = ir3_RCP(b, src[0], 0);
537 break;
538 case nir_op_flog2:
539 dst[0] = ir3_LOG2(b, src[0], 0);
540 break;
541 case nir_op_fexp2:
542 dst[0] = ir3_EXP2(b, src[0], 0);
543 break;
544 case nir_op_fsqrt:
545 dst[0] = ir3_SQRT(b, src[0], 0);
546 break;
547
548 case nir_op_iabs:
549 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
550 break;
551 case nir_op_iadd:
552 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_iand:
555 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imax:
558 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umax:
561 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_imin:
564 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_umin:
567 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_umul_low:
570 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_imadsh_mix16:
573 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
574 break;
575 case nir_op_imad24_ir3:
576 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
577 break;
578 case nir_op_imul24:
579 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
580 break;
581 case nir_op_ineg:
582 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
583 break;
584 case nir_op_inot:
585 if (bs[0] == 1) {
586 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
587 } else {
588 dst[0] = ir3_NOT_B(b, src[0], 0);
589 }
590 break;
591 case nir_op_ior:
592 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ishl:
595 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
596 break;
597 case nir_op_ishr:
598 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
599 break;
600 case nir_op_isub:
601 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
602 break;
603 case nir_op_ixor:
604 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
605 break;
606 case nir_op_ushr:
607 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
608 break;
609 case nir_op_ilt:
610 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
611 dst[0]->cat2.condition = IR3_COND_LT;
612 break;
613 case nir_op_ige:
614 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
615 dst[0]->cat2.condition = IR3_COND_GE;
616 break;
617 case nir_op_ieq:
618 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_EQ;
620 break;
621 case nir_op_ine:
622 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
623 dst[0]->cat2.condition = IR3_COND_NE;
624 break;
625 case nir_op_ult:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_LT;
628 break;
629 case nir_op_uge:
630 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
631 dst[0]->cat2.condition = IR3_COND_GE;
632 break;
633
634 case nir_op_bcsel: {
635 struct ir3_instruction *cond = src[0];
636
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
640 */
641 if (cond->opc == OPC_ABSNEG_S &&
642 cond->flags == 0 &&
643 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
644 cond = cond->regs[1]->instr;
645 }
646
647 compile_assert(ctx, bs[1] == bs[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
650 */
651 if (bs[1] == 16) {
652 struct hash_entry *prev_entry =
653 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
654 if (prev_entry) {
655 cond = prev_entry->data;
656 } else {
657 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
658 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
659 }
660 }
661
662 if (bs[1] != 16)
663 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
664 else
665 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
666 break;
667 }
668 case nir_op_bit_count: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction *hi, *lo;
673
674 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
675 TYPE_U32, TYPE_U16);
676 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
677
678 hi = ir3_CBITS_B(b, hi, 0);
679 lo = ir3_CBITS_B(b, lo, 0);
680
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi->regs[0]->flags |= IR3_REG_HALF;
685 lo->regs[0]->flags |= IR3_REG_HALF;
686
687 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
688 dst[0]->regs[0]->flags |= IR3_REG_HALF;
689 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
690 break;
691 }
692 case nir_op_ifind_msb: {
693 struct ir3_instruction *cmp;
694 dst[0] = ir3_CLZ_S(b, src[0], 0);
695 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
696 cmp->cat2.condition = IR3_COND_GE;
697 dst[0] = ir3_SEL_B32(b,
698 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
699 cmp, 0, dst[0], 0);
700 break;
701 }
702 case nir_op_ufind_msb:
703 dst[0] = ir3_CLZ_B(b, src[0], 0);
704 dst[0] = ir3_SEL_B32(b,
705 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
706 src[0], 0, dst[0], 0);
707 break;
708 case nir_op_find_lsb:
709 dst[0] = ir3_BFREV_B(b, src[0], 0);
710 dst[0] = ir3_CLZ_B(b, dst[0], 0);
711 break;
712 case nir_op_bitfield_reverse:
713 dst[0] = ir3_BFREV_B(b, src[0], 0);
714 break;
715
716 default:
717 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
718 nir_op_infos[alu->op].name);
719 break;
720 }
721
722 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
723 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
724 alu->op == nir_op_b2b32);
725 assert(dst_sz == 1);
726 } else {
727 /* 1-bit values stored in 32-bit registers are only valid for certain
728 * ALU ops.
729 */
730 switch (alu->op) {
731 case nir_op_iand:
732 case nir_op_ior:
733 case nir_op_ixor:
734 case nir_op_inot:
735 case nir_op_bcsel:
736 break;
737 default:
738 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
739 }
740 }
741
742 ir3_put_dst(ctx, &alu->dest.dest);
743 }
744
745 static void
746 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
747 struct ir3_instruction **dst)
748 {
749 struct ir3_block *b = ctx->block;
750
751 unsigned ncomp = intr->num_components;
752 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
753 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
754 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
755 ldc->regs[0]->wrmask = MASK(ncomp);
756 ldc->cat6.iim_val = ncomp;
757 ldc->cat6.d = nir_intrinsic_base(intr);
758 ldc->cat6.type = TYPE_U32;
759
760 ir3_handle_bindless_cat6(ldc, intr->src[0]);
761 if (ldc->flags & IR3_INSTR_B)
762 ctx->so->bindless_ubo = true;
763
764 ir3_split_dest(b, dst, ldc, 0, ncomp);
765 }
766
767
768 /* handles direct/indirect UBO reads: */
769 static void
770 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
771 struct ir3_instruction **dst)
772 {
773 struct ir3_block *b = ctx->block;
774 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
775 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
776 unsigned ubo = regid(const_state->offsets.ubo, 0);
777 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
778
779 int off = 0;
780
781 /* First src is ubo index, which could either be an immed or not: */
782 src0 = ir3_get_src(ctx, &intr->src[0])[0];
783 if (is_same_type_mov(src0) &&
784 (src0->regs[1]->flags & IR3_REG_IMMED)) {
785 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
786 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
787 } else {
788 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
789 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
790
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
794 */
795 ctx->so->constlen = MAX2(ctx->so->constlen,
796 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
797 }
798
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
800 addr = base_lo;
801
802 if (nir_src_is_const(intr->src[1])) {
803 off += nir_src_as_uint(intr->src[1]);
804 } else {
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1 = ir3_get_src(ctx, &intr->src[1])[0];
807
808 /* and add offset to addr: */
809 addr = ir3_ADD_S(b, addr, 0, src1, 0);
810 }
811
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off + (intr->num_components * 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
816 */
817 unsigned off2 = off + (intr->num_components * 4) - 1024;
818 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
819 off -= off2;
820 }
821
822 if (ptrsz == 2) {
823 struct ir3_instruction *carry;
824
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
827 * base_hi++
828 */
829 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
830 carry->cat2.condition = IR3_COND_LT;
831 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
832
833 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
834 }
835
836 for (int i = 0; i < intr->num_components; i++) {
837 struct ir3_instruction *load =
838 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
839 create_immed(b, off + i * 4), 0);
840 load->cat6.type = TYPE_U32;
841 dst[i] = load;
842 }
843 }
844
845 /* src[] = { block_index } */
846 static void
847 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
848 struct ir3_instruction **dst)
849 {
850 /* SSBO size stored as a const starting at ssbo_sizes: */
851 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
852 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
853 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
854 const_state->ssbo_size.off[blk_idx];
855
856 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
857
858 dst[0] = create_uniform(ctx->block, idx);
859 }
860
861 /* src[] = { offset }. const_index[] = { base } */
862 static void
863 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
864 struct ir3_instruction **dst)
865 {
866 struct ir3_block *b = ctx->block;
867 struct ir3_instruction *ldl, *offset;
868 unsigned base;
869
870 offset = ir3_get_src(ctx, &intr->src[0])[0];
871 base = nir_intrinsic_base(intr);
872
873 ldl = ir3_LDL(b, offset, 0,
874 create_immed(b, intr->num_components), 0,
875 create_immed(b, base), 0);
876
877 ldl->cat6.type = utype_dst(intr->dest);
878 ldl->regs[0]->wrmask = MASK(intr->num_components);
879
880 ldl->barrier_class = IR3_BARRIER_SHARED_R;
881 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
882
883 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
884 }
885
886 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
887 static void
888 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
889 {
890 struct ir3_block *b = ctx->block;
891 struct ir3_instruction *stl, *offset;
892 struct ir3_instruction * const *value;
893 unsigned base, wrmask, ncomp;
894
895 value = ir3_get_src(ctx, &intr->src[0]);
896 offset = ir3_get_src(ctx, &intr->src[1])[0];
897
898 base = nir_intrinsic_base(intr);
899 wrmask = nir_intrinsic_write_mask(intr);
900 ncomp = ffs(~wrmask) - 1;
901
902 assert(wrmask == BITFIELD_MASK(intr->num_components));
903
904 stl = ir3_STL(b, offset, 0,
905 ir3_create_collect(ctx, value, ncomp), 0,
906 create_immed(b, ncomp), 0);
907 stl->cat6.dst_offset = base;
908 stl->cat6.type = utype_src(intr->src[0]);
909 stl->barrier_class = IR3_BARRIER_SHARED_W;
910 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
911
912 array_insert(b, b->keeps, stl);
913 }
914
915 /* src[] = { offset }. const_index[] = { base } */
916 static void
917 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
918 struct ir3_instruction **dst)
919 {
920 struct ir3_block *b = ctx->block;
921 struct ir3_instruction *load, *offset;
922 unsigned base;
923
924 offset = ir3_get_src(ctx, &intr->src[0])[0];
925 base = nir_intrinsic_base(intr);
926
927 load = ir3_LDLW(b, offset, 0,
928 create_immed(b, intr->num_components), 0,
929 create_immed(b, base), 0);
930
931 /* for a650, use LDL for tess ctrl inputs: */
932 if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
933 load->opc = OPC_LDL;
934
935 load->cat6.type = utype_dst(intr->dest);
936 load->regs[0]->wrmask = MASK(intr->num_components);
937
938 load->barrier_class = IR3_BARRIER_SHARED_R;
939 load->barrier_conflict = IR3_BARRIER_SHARED_W;
940
941 ir3_split_dest(b, dst, load, 0, intr->num_components);
942 }
943
944 /* src[] = { value, offset }. const_index[] = { base } */
945 static void
946 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
947 {
948 struct ir3_block *b = ctx->block;
949 struct ir3_instruction *store, *offset;
950 struct ir3_instruction * const *value;
951
952 value = ir3_get_src(ctx, &intr->src[0]);
953 offset = ir3_get_src(ctx, &intr->src[1])[0];
954
955 store = ir3_STLW(b, offset, 0,
956 ir3_create_collect(ctx, value, intr->num_components), 0,
957 create_immed(b, intr->num_components), 0);
958
959 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
960 if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
961 ctx->compiler->tess_use_shared)
962 store->opc = OPC_STL;
963
964 store->cat6.dst_offset = nir_intrinsic_base(intr);
965 store->cat6.type = utype_src(intr->src[0]);
966 store->barrier_class = IR3_BARRIER_SHARED_W;
967 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
968
969 array_insert(b, b->keeps, store);
970 }
971
972 /*
973 * CS shared variable atomic intrinsics
974 *
975 * All of the shared variable atomic memory operations read a value from
976 * memory, compute a new value using one of the operations below, write the
977 * new value to memory, and return the original value read.
978 *
979 * All operations take 2 sources except CompSwap that takes 3. These
980 * sources represent:
981 *
982 * 0: The offset into the shared variable storage region that the atomic
983 * operation will operate on.
984 * 1: The data parameter to the atomic function (i.e. the value to add
985 * in shared_atomic_add, etc).
986 * 2: For CompSwap only: the second data parameter.
987 */
988 static struct ir3_instruction *
989 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
990 {
991 struct ir3_block *b = ctx->block;
992 struct ir3_instruction *atomic, *src0, *src1;
993 type_t type = TYPE_U32;
994
995 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
996 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
997
998 switch (intr->intrinsic) {
999 case nir_intrinsic_shared_atomic_add:
1000 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1001 break;
1002 case nir_intrinsic_shared_atomic_imin:
1003 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1004 type = TYPE_S32;
1005 break;
1006 case nir_intrinsic_shared_atomic_umin:
1007 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1008 break;
1009 case nir_intrinsic_shared_atomic_imax:
1010 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1011 type = TYPE_S32;
1012 break;
1013 case nir_intrinsic_shared_atomic_umax:
1014 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1015 break;
1016 case nir_intrinsic_shared_atomic_and:
1017 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1018 break;
1019 case nir_intrinsic_shared_atomic_or:
1020 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1021 break;
1022 case nir_intrinsic_shared_atomic_xor:
1023 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1024 break;
1025 case nir_intrinsic_shared_atomic_exchange:
1026 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1027 break;
1028 case nir_intrinsic_shared_atomic_comp_swap:
1029 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1030 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1031 ir3_get_src(ctx, &intr->src[2])[0],
1032 src1,
1033 }, 2);
1034 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1035 break;
1036 default:
1037 unreachable("boo");
1038 }
1039
1040 atomic->cat6.iim_val = 1;
1041 atomic->cat6.d = 1;
1042 atomic->cat6.type = type;
1043 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1044 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1045
1046 /* even if nothing consume the result, we can't DCE the instruction: */
1047 array_insert(b, b->keeps, atomic);
1048
1049 return atomic;
1050 }
1051
1052 struct tex_src_info {
1053 /* For prefetch */
1054 unsigned tex_base, samp_base, tex_idx, samp_idx;
1055 /* For normal tex instructions */
1056 unsigned base, combined_idx, a1_val, flags;
1057 struct ir3_instruction *samp_tex;
1058 };
1059
1060 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1061 * to handle with the image_mapping table..
1062 */
1063 static struct tex_src_info
1064 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1065 {
1066 struct ir3_block *b = ctx->block;
1067 struct tex_src_info info = { 0 };
1068 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1069 ctx->so->bindless_tex = true;
1070
1071 if (bindless_tex) {
1072 /* Bindless case */
1073 info.flags |= IR3_INSTR_B;
1074
1075 /* Gather information required to determine which encoding to
1076 * choose as well as for prefetch.
1077 */
1078 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1079 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1080 if (tex_const)
1081 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1082 info.samp_idx = 0;
1083
1084 /* Choose encoding. */
1085 if (tex_const && info.tex_idx < 256) {
1086 if (info.tex_idx < 16) {
1087 /* Everything fits within the instruction */
1088 info.base = info.tex_base;
1089 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1090 } else {
1091 info.base = info.tex_base;
1092 info.a1_val = info.tex_idx << 3;
1093 info.combined_idx = 0;
1094 info.flags |= IR3_INSTR_A1EN;
1095 }
1096 info.samp_tex = NULL;
1097 } else {
1098 info.flags |= IR3_INSTR_S2EN;
1099 info.base = info.tex_base;
1100
1101 /* Note: the indirect source is now a vec2 instead of hvec2 */
1102 struct ir3_instruction *texture, *sampler;
1103
1104 texture = ir3_get_src(ctx, &intr->src[0])[0];
1105 sampler = create_immed(b, 0);
1106 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1107 texture,
1108 sampler,
1109 }, 2);
1110 }
1111 } else {
1112 info.flags |= IR3_INSTR_S2EN;
1113 unsigned slot = nir_src_as_uint(intr->src[0]);
1114 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1115 struct ir3_instruction *texture, *sampler;
1116
1117 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1118 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1119
1120 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1121 sampler,
1122 texture,
1123 }, 2);
1124 }
1125
1126 return info;
1127 }
1128
1129 static struct ir3_instruction *
1130 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1131 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1132 struct ir3_instruction *src1)
1133 {
1134 struct ir3_instruction *sam, *addr;
1135 if (info.flags & IR3_INSTR_A1EN) {
1136 addr = ir3_get_addr1(ctx, info.a1_val);
1137 }
1138 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1139 info.samp_tex, src0, src1);
1140 if (info.flags & IR3_INSTR_A1EN) {
1141 ir3_instr_set_address(sam, addr);
1142 }
1143 if (info.flags & IR3_INSTR_B) {
1144 sam->cat5.tex_base = info.base;
1145 sam->cat5.samp = info.combined_idx;
1146 }
1147 return sam;
1148 }
1149
1150 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1151 static void
1152 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1153 struct ir3_instruction **dst)
1154 {
1155 struct ir3_block *b = ctx->block;
1156 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1157 struct ir3_instruction *sam;
1158 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1159 struct ir3_instruction *coords[4];
1160 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1161 type_t type = ir3_get_type_for_image_intrinsic(intr);
1162
1163 /* hmm, this seems a bit odd, but it is what blob does and (at least
1164 * a5xx) just faults on bogus addresses otherwise:
1165 */
1166 if (flags & IR3_INSTR_3D) {
1167 flags &= ~IR3_INSTR_3D;
1168 flags |= IR3_INSTR_A;
1169 }
1170 info.flags |= flags;
1171
1172 for (unsigned i = 0; i < ncoords; i++)
1173 coords[i] = src0[i];
1174
1175 if (ncoords == 1)
1176 coords[ncoords++] = create_immed(b, 0);
1177
1178 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1179 ir3_create_collect(ctx, coords, ncoords), NULL);
1180
1181 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1182 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1183
1184 ir3_split_dest(b, dst, sam, 0, 4);
1185 }
1186
1187 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1188 void
1189 emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1190 struct ir3_instruction **dst)
1191 {
1192 struct ir3_block *b = ctx->block;
1193 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1194 struct ir3_instruction *sam, *lod;
1195 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1196 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1197 TYPE_U16 : TYPE_U32;
1198
1199 info.flags |= flags;
1200 lod = create_immed(b, 0);
1201 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1202
1203 /* Array size actually ends up in .w rather than .z. This doesn't
1204 * matter for miplevel 0, but for higher mips the value in z is
1205 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1206 * returned, which means that we have to add 1 to it for arrays for
1207 * a3xx.
1208 *
1209 * Note use a temporary dst and then copy, since the size of the dst
1210 * array that is passed in is based on nir's understanding of the
1211 * result size, not the hardware's
1212 */
1213 struct ir3_instruction *tmp[4];
1214
1215 ir3_split_dest(b, tmp, sam, 0, 4);
1216
1217 /* get_size instruction returns size in bytes instead of texels
1218 * for imageBuffer, so we need to divide it by the pixel size
1219 * of the image format.
1220 *
1221 * TODO: This is at least true on a5xx. Check other gens.
1222 */
1223 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1224 /* Since all the possible values the divisor can take are
1225 * power-of-two (4, 8, or 16), the division is implemented
1226 * as a shift-right.
1227 * During shader setup, the log2 of the image format's
1228 * bytes-per-pixel should have been emitted in 2nd slot of
1229 * image_dims. See ir3_shader::emit_image_dims().
1230 */
1231 const struct ir3_const_state *const_state =
1232 ir3_const_state(ctx->so);
1233 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1234 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1235 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1236
1237 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1238 }
1239
1240 for (unsigned i = 0; i < ncoords; i++)
1241 dst[i] = tmp[i];
1242
1243 if (flags & IR3_INSTR_A) {
1244 if (ctx->compiler->levels_add_one) {
1245 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1246 } else {
1247 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1248 }
1249 }
1250 }
1251
1252 static void
1253 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1254 {
1255 struct ir3_block *b = ctx->block;
1256 struct ir3_instruction *barrier;
1257
1258 switch (intr->intrinsic) {
1259 case nir_intrinsic_control_barrier:
1260 barrier = ir3_BAR(b);
1261 barrier->cat7.g = true;
1262 barrier->cat7.l = true;
1263 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1264 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1265 break;
1266 case nir_intrinsic_memory_barrier:
1267 barrier = ir3_FENCE(b);
1268 barrier->cat7.g = true;
1269 barrier->cat7.r = true;
1270 barrier->cat7.w = true;
1271 barrier->cat7.l = true;
1272 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1273 IR3_BARRIER_BUFFER_W;
1274 barrier->barrier_conflict =
1275 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1276 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1277 break;
1278 case nir_intrinsic_memory_barrier_buffer:
1279 barrier = ir3_FENCE(b);
1280 barrier->cat7.g = true;
1281 barrier->cat7.r = true;
1282 barrier->cat7.w = true;
1283 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1284 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1285 IR3_BARRIER_BUFFER_W;
1286 break;
1287 case nir_intrinsic_memory_barrier_image:
1288 // TODO double check if this should have .g set
1289 barrier = ir3_FENCE(b);
1290 barrier->cat7.g = true;
1291 barrier->cat7.r = true;
1292 barrier->cat7.w = true;
1293 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1294 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1295 IR3_BARRIER_IMAGE_W;
1296 break;
1297 case nir_intrinsic_memory_barrier_shared:
1298 barrier = ir3_FENCE(b);
1299 barrier->cat7.g = true;
1300 barrier->cat7.l = true;
1301 barrier->cat7.r = true;
1302 barrier->cat7.w = true;
1303 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1304 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1305 IR3_BARRIER_SHARED_W;
1306 break;
1307 case nir_intrinsic_group_memory_barrier:
1308 barrier = ir3_FENCE(b);
1309 barrier->cat7.g = true;
1310 barrier->cat7.l = true;
1311 barrier->cat7.r = true;
1312 barrier->cat7.w = true;
1313 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1314 IR3_BARRIER_IMAGE_W |
1315 IR3_BARRIER_BUFFER_W;
1316 barrier->barrier_conflict =
1317 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1318 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1319 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1320 break;
1321 default:
1322 unreachable("boo");
1323 }
1324
1325 /* make sure barrier doesn't get DCE'd */
1326 array_insert(b, b->keeps, barrier);
1327 }
1328
1329 static void add_sysval_input_compmask(struct ir3_context *ctx,
1330 gl_system_value slot, unsigned compmask,
1331 struct ir3_instruction *instr)
1332 {
1333 struct ir3_shader_variant *so = ctx->so;
1334 unsigned n = so->inputs_count++;
1335
1336 assert(instr->opc == OPC_META_INPUT);
1337 instr->input.inidx = n;
1338 instr->input.sysval = slot;
1339
1340 so->inputs[n].sysval = true;
1341 so->inputs[n].slot = slot;
1342 so->inputs[n].compmask = compmask;
1343 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1344 so->total_in++;
1345 }
1346
1347 static struct ir3_instruction *
1348 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1349 unsigned compmask)
1350 {
1351 assert(compmask);
1352 struct ir3_instruction *sysval = create_input(ctx, compmask);
1353 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1354 return sysval;
1355 }
1356
1357 static struct ir3_instruction *
1358 get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
1359 {
1360 static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1361
1362 STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1363 STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1364 STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1365 STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1366 STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
1367 STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
1368 STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
1369
1370 if (!ctx->ij[bary]) {
1371 struct ir3_instruction *xy[2];
1372 struct ir3_instruction *ij;
1373
1374 ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
1375 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1376
1377 ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
1378 }
1379
1380 return ctx->ij[bary];
1381 }
1382
1383 /* TODO: make this a common NIR helper?
1384 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1385 * can't be extended to work with this
1386 */
1387 static gl_system_value
1388 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
1389 {
1390 enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
1391 gl_system_value sysval;
1392
1393 switch (intr->intrinsic) {
1394 case nir_intrinsic_load_barycentric_pixel:
1395 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1396 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1397 else
1398 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1399 break;
1400 case nir_intrinsic_load_barycentric_centroid:
1401 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1402 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID;
1403 else
1404 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID;
1405 break;
1406 case nir_intrinsic_load_barycentric_sample:
1407 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1408 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE;
1409 else
1410 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE;
1411 break;
1412 default:
1413 unreachable("invalid barycentric intrinsic");
1414 }
1415
1416 return sysval;
1417 }
1418
1419 static void
1420 emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1421 struct ir3_instruction **dst)
1422 {
1423 gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
1424
1425 if (!ctx->so->key.msaa) {
1426 if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE)
1427 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1428 if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE)
1429 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1430 }
1431
1432 enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1433
1434 struct ir3_instruction *ij = get_barycentric(ctx, bary);
1435 ir3_split_dest(ctx->block, dst, ij, 0, 2);
1436 }
1437
1438 static struct ir3_instruction *
1439 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1440 {
1441 if (!ctx->frag_coord) {
1442 struct ir3_block *b = ctx->in_block;
1443 struct ir3_instruction *xyzw[4];
1444 struct ir3_instruction *hw_frag_coord;
1445
1446 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1447 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1448
1449 /* for frag_coord.xy, we get unsigned values.. we need
1450 * to subtract (integer) 8 and divide by 16 (right-
1451 * shift by 4) then convert to float:
1452 *
1453 * sub.s tmp, src, 8
1454 * shr.b tmp, tmp, 4
1455 * mov.u32f32 dst, tmp
1456 *
1457 */
1458 for (int i = 0; i < 2; i++) {
1459 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1460 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1461 }
1462
1463 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1464 }
1465
1466 ctx->so->fragcoord_compmask |=
1467 nir_ssa_def_components_read(&intr->dest.ssa);
1468
1469 return ctx->frag_coord;
1470 }
1471
1472 static void
1473 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1474 {
1475 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1476 struct ir3_instruction **dst;
1477 struct ir3_instruction * const *src;
1478 struct ir3_block *b = ctx->block;
1479 unsigned dest_components = nir_intrinsic_dest_components(intr);
1480 int idx, comp;
1481
1482 if (info->has_dest) {
1483 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
1484 } else {
1485 dst = NULL;
1486 }
1487
1488 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
1489 const unsigned primitive_param = const_state->offsets.primitive_param * 4;
1490 const unsigned primitive_map = const_state->offsets.primitive_map * 4;
1491
1492 switch (intr->intrinsic) {
1493 case nir_intrinsic_load_uniform:
1494 idx = nir_intrinsic_base(intr);
1495 if (nir_src_is_const(intr->src[0])) {
1496 idx += nir_src_as_uint(intr->src[0]);
1497 for (int i = 0; i < dest_components; i++) {
1498 dst[i] = create_uniform_typed(b, idx + i,
1499 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1500 }
1501 } else {
1502 src = ir3_get_src(ctx, &intr->src[0]);
1503 for (int i = 0; i < dest_components; i++) {
1504 dst[i] = create_uniform_indirect(b, idx + i,
1505 ir3_get_addr0(ctx, src[0], 1));
1506 }
1507 /* NOTE: if relative addressing is used, we set
1508 * constlen in the compiler (to worst-case value)
1509 * since we don't know in the assembler what the max
1510 * addr reg value can be:
1511 */
1512 ctx->so->constlen = MAX2(ctx->so->constlen,
1513 const_state->ubo_state.size / 16);
1514 }
1515 break;
1516
1517 case nir_intrinsic_load_vs_primitive_stride_ir3:
1518 dst[0] = create_uniform(b, primitive_param + 0);
1519 break;
1520 case nir_intrinsic_load_vs_vertex_stride_ir3:
1521 dst[0] = create_uniform(b, primitive_param + 1);
1522 break;
1523 case nir_intrinsic_load_hs_patch_stride_ir3:
1524 dst[0] = create_uniform(b, primitive_param + 2);
1525 break;
1526 case nir_intrinsic_load_patch_vertices_in:
1527 dst[0] = create_uniform(b, primitive_param + 3);
1528 break;
1529 case nir_intrinsic_load_tess_param_base_ir3:
1530 dst[0] = create_uniform(b, primitive_param + 4);
1531 dst[1] = create_uniform(b, primitive_param + 5);
1532 break;
1533 case nir_intrinsic_load_tess_factor_base_ir3:
1534 dst[0] = create_uniform(b, primitive_param + 6);
1535 dst[1] = create_uniform(b, primitive_param + 7);
1536 break;
1537
1538 case nir_intrinsic_load_primitive_location_ir3:
1539 idx = nir_intrinsic_driver_location(intr);
1540 dst[0] = create_uniform(b, primitive_map + idx);
1541 break;
1542
1543 case nir_intrinsic_load_gs_header_ir3:
1544 dst[0] = ctx->gs_header;
1545 break;
1546 case nir_intrinsic_load_tcs_header_ir3:
1547 dst[0] = ctx->tcs_header;
1548 break;
1549
1550 case nir_intrinsic_load_primitive_id:
1551 dst[0] = ctx->primitive_id;
1552 break;
1553
1554 case nir_intrinsic_load_tess_coord:
1555 if (!ctx->tess_coord) {
1556 ctx->tess_coord =
1557 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1558 }
1559 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1560
1561 /* Unused, but ir3_put_dst() below wants to free something */
1562 dst[2] = create_immed(b, 0);
1563 break;
1564
1565 case nir_intrinsic_end_patch_ir3:
1566 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1567 struct ir3_instruction *end = ir3_PREDE(b);
1568 array_insert(b, b->keeps, end);
1569
1570 end->barrier_class = IR3_BARRIER_EVERYTHING;
1571 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1572 break;
1573
1574 case nir_intrinsic_store_global_ir3: {
1575 struct ir3_instruction *value, *addr, *offset;
1576 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
1577
1578 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1579 ir3_get_src(ctx, &intr->src[1])[0],
1580 ir3_get_src(ctx, &intr->src[1])[1]
1581 }, 2);
1582
1583 offset = ir3_get_src(ctx, &intr->src[2])[0];
1584
1585 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
1586
1587 struct ir3_instruction *stg =
1588 ir3_STG_G(ctx->block, addr, 0, value, 0,
1589 create_immed(ctx->block, ncomp), 0, offset, 0);
1590 stg->cat6.type = TYPE_U32;
1591 stg->cat6.iim_val = 1;
1592
1593 array_insert(b, b->keeps, stg);
1594
1595 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1596 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1597 break;
1598 }
1599
1600 case nir_intrinsic_load_global_ir3: {
1601 struct ir3_instruction *addr, *offset;
1602
1603 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1604 ir3_get_src(ctx, &intr->src[0])[0],
1605 ir3_get_src(ctx, &intr->src[0])[1]
1606 }, 2);
1607
1608 offset = ir3_get_src(ctx, &intr->src[1])[0];
1609
1610 struct ir3_instruction *load =
1611 ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components),
1612 0, offset, 0);
1613 load->cat6.type = TYPE_U32;
1614 load->regs[0]->wrmask = MASK(dest_components);
1615
1616 load->barrier_class = IR3_BARRIER_BUFFER_R;
1617 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1618
1619 ir3_split_dest(b, dst, load, 0, dest_components);
1620 break;
1621 }
1622
1623 case nir_intrinsic_load_ubo:
1624 emit_intrinsic_load_ubo(ctx, intr, dst);
1625 break;
1626 case nir_intrinsic_load_ubo_ir3:
1627 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1628 break;
1629 case nir_intrinsic_load_frag_coord:
1630 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1631 break;
1632 case nir_intrinsic_load_sample_pos_from_id: {
1633 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1634 * but that doesn't seem necessary.
1635 */
1636 struct ir3_instruction *offset =
1637 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1638 offset->regs[0]->wrmask = 0x3;
1639 offset->cat5.type = TYPE_F32;
1640
1641 ir3_split_dest(b, dst, offset, 0, 2);
1642
1643 break;
1644 }
1645 case nir_intrinsic_load_size_ir3:
1646 if (!ctx->ij[IJ_PERSP_SIZE]) {
1647 ctx->ij[IJ_PERSP_SIZE] =
1648 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1649 }
1650 dst[0] = ctx->ij[IJ_PERSP_SIZE];
1651 break;
1652 case nir_intrinsic_load_barycentric_centroid:
1653 case nir_intrinsic_load_barycentric_sample:
1654 case nir_intrinsic_load_barycentric_pixel:
1655 emit_intrinsic_barycentric(ctx, intr, dst);
1656 break;
1657 case nir_intrinsic_load_interpolated_input:
1658 idx = nir_intrinsic_base(intr);
1659 comp = nir_intrinsic_component(intr);
1660 src = ir3_get_src(ctx, &intr->src[0]);
1661 if (nir_src_is_const(intr->src[1])) {
1662 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1663 idx += nir_src_as_uint(intr->src[1]);
1664 for (int i = 0; i < dest_components; i++) {
1665 unsigned inloc = idx * 4 + i + comp;
1666 if (ctx->so->inputs[idx].bary &&
1667 !ctx->so->inputs[idx].use_ldlv) {
1668 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1669 } else {
1670 /* for non-varyings use the pre-setup input, since
1671 * that is easier than mapping things back to a
1672 * nir_variable to figure out what it is.
1673 */
1674 dst[i] = ctx->inputs[inloc];
1675 compile_assert(ctx, dst[i]);
1676 }
1677 }
1678 } else {
1679 ir3_context_error(ctx, "unhandled");
1680 }
1681 break;
1682 case nir_intrinsic_load_input:
1683 idx = nir_intrinsic_base(intr);
1684 comp = nir_intrinsic_component(intr);
1685 if (nir_src_is_const(intr->src[0])) {
1686 idx += nir_src_as_uint(intr->src[0]);
1687 for (int i = 0; i < dest_components; i++) {
1688 unsigned n = idx * 4 + i + comp;
1689 dst[i] = ctx->inputs[n];
1690 compile_assert(ctx, ctx->inputs[n]);
1691 }
1692 } else {
1693 src = ir3_get_src(ctx, &intr->src[0]);
1694 struct ir3_instruction *collect =
1695 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1696 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1697 for (int i = 0; i < dest_components; i++) {
1698 unsigned n = idx * 4 + i + comp;
1699 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1700 n, addr, collect);
1701 }
1702 }
1703 break;
1704 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1705 * pass and replaced by an ir3-specifc version that adds the
1706 * dword-offset in the last source.
1707 */
1708 case nir_intrinsic_load_ssbo_ir3:
1709 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1710 break;
1711 case nir_intrinsic_store_ssbo_ir3:
1712 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1713 !ctx->s->info.fs.early_fragment_tests)
1714 ctx->so->no_earlyz = true;
1715 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1716 break;
1717 case nir_intrinsic_get_buffer_size:
1718 emit_intrinsic_ssbo_size(ctx, intr, dst);
1719 break;
1720 case nir_intrinsic_ssbo_atomic_add_ir3:
1721 case nir_intrinsic_ssbo_atomic_imin_ir3:
1722 case nir_intrinsic_ssbo_atomic_umin_ir3:
1723 case nir_intrinsic_ssbo_atomic_imax_ir3:
1724 case nir_intrinsic_ssbo_atomic_umax_ir3:
1725 case nir_intrinsic_ssbo_atomic_and_ir3:
1726 case nir_intrinsic_ssbo_atomic_or_ir3:
1727 case nir_intrinsic_ssbo_atomic_xor_ir3:
1728 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1729 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1730 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1731 !ctx->s->info.fs.early_fragment_tests)
1732 ctx->so->no_earlyz = true;
1733 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1734 break;
1735 case nir_intrinsic_load_shared:
1736 emit_intrinsic_load_shared(ctx, intr, dst);
1737 break;
1738 case nir_intrinsic_store_shared:
1739 emit_intrinsic_store_shared(ctx, intr);
1740 break;
1741 case nir_intrinsic_shared_atomic_add:
1742 case nir_intrinsic_shared_atomic_imin:
1743 case nir_intrinsic_shared_atomic_umin:
1744 case nir_intrinsic_shared_atomic_imax:
1745 case nir_intrinsic_shared_atomic_umax:
1746 case nir_intrinsic_shared_atomic_and:
1747 case nir_intrinsic_shared_atomic_or:
1748 case nir_intrinsic_shared_atomic_xor:
1749 case nir_intrinsic_shared_atomic_exchange:
1750 case nir_intrinsic_shared_atomic_comp_swap:
1751 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1752 break;
1753 case nir_intrinsic_image_load:
1754 emit_intrinsic_load_image(ctx, intr, dst);
1755 break;
1756 case nir_intrinsic_bindless_image_load:
1757 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1758 * so using isam doesn't work.
1759 *
1760 * TODO: can we use isam if we fill out more fields?
1761 */
1762 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1763 break;
1764 case nir_intrinsic_image_store:
1765 case nir_intrinsic_bindless_image_store:
1766 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1767 !ctx->s->info.fs.early_fragment_tests)
1768 ctx->so->no_earlyz = true;
1769 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1770 break;
1771 case nir_intrinsic_image_size:
1772 case nir_intrinsic_bindless_image_size:
1773 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
1774 break;
1775 case nir_intrinsic_image_atomic_add:
1776 case nir_intrinsic_bindless_image_atomic_add:
1777 case nir_intrinsic_image_atomic_imin:
1778 case nir_intrinsic_bindless_image_atomic_imin:
1779 case nir_intrinsic_image_atomic_umin:
1780 case nir_intrinsic_bindless_image_atomic_umin:
1781 case nir_intrinsic_image_atomic_imax:
1782 case nir_intrinsic_bindless_image_atomic_imax:
1783 case nir_intrinsic_image_atomic_umax:
1784 case nir_intrinsic_bindless_image_atomic_umax:
1785 case nir_intrinsic_image_atomic_and:
1786 case nir_intrinsic_bindless_image_atomic_and:
1787 case nir_intrinsic_image_atomic_or:
1788 case nir_intrinsic_bindless_image_atomic_or:
1789 case nir_intrinsic_image_atomic_xor:
1790 case nir_intrinsic_bindless_image_atomic_xor:
1791 case nir_intrinsic_image_atomic_exchange:
1792 case nir_intrinsic_bindless_image_atomic_exchange:
1793 case nir_intrinsic_image_atomic_comp_swap:
1794 case nir_intrinsic_bindless_image_atomic_comp_swap:
1795 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1796 !ctx->s->info.fs.early_fragment_tests)
1797 ctx->so->no_earlyz = true;
1798 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1799 break;
1800 case nir_intrinsic_control_barrier:
1801 case nir_intrinsic_memory_barrier:
1802 case nir_intrinsic_group_memory_barrier:
1803 case nir_intrinsic_memory_barrier_buffer:
1804 case nir_intrinsic_memory_barrier_image:
1805 case nir_intrinsic_memory_barrier_shared:
1806 emit_intrinsic_barrier(ctx, intr);
1807 /* note that blk ptr no longer valid, make that obvious: */
1808 b = NULL;
1809 break;
1810 case nir_intrinsic_store_output:
1811 idx = nir_intrinsic_base(intr);
1812 comp = nir_intrinsic_component(intr);
1813 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1814 idx += nir_src_as_uint(intr->src[1]);
1815
1816 src = ir3_get_src(ctx, &intr->src[0]);
1817 for (int i = 0; i < nir_intrinsic_src_components(intr, 0); i++) {
1818 unsigned n = idx * 4 + i + comp;
1819 ctx->outputs[n] = src[i];
1820 }
1821 break;
1822 case nir_intrinsic_load_base_vertex:
1823 case nir_intrinsic_load_first_vertex:
1824 if (!ctx->basevertex) {
1825 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1826 }
1827 dst[0] = ctx->basevertex;
1828 break;
1829 case nir_intrinsic_load_draw_id:
1830 if (!ctx->draw_id) {
1831 ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
1832 }
1833 dst[0] = ctx->draw_id;
1834 break;
1835 case nir_intrinsic_load_base_instance:
1836 if (!ctx->base_instance) {
1837 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1838 }
1839 dst[0] = ctx->base_instance;
1840 break;
1841 case nir_intrinsic_load_vertex_id_zero_base:
1842 case nir_intrinsic_load_vertex_id:
1843 if (!ctx->vertex_id) {
1844 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1845 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1846 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1847 }
1848 dst[0] = ctx->vertex_id;
1849 break;
1850 case nir_intrinsic_load_instance_id:
1851 if (!ctx->instance_id) {
1852 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1853 }
1854 dst[0] = ctx->instance_id;
1855 break;
1856 case nir_intrinsic_load_sample_id:
1857 ctx->so->per_samp = true;
1858 /* fall-thru */
1859 case nir_intrinsic_load_sample_id_no_per_sample:
1860 if (!ctx->samp_id) {
1861 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1862 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1863 }
1864 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1865 break;
1866 case nir_intrinsic_load_sample_mask_in:
1867 if (!ctx->samp_mask_in) {
1868 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1869 }
1870 dst[0] = ctx->samp_mask_in;
1871 break;
1872 case nir_intrinsic_load_user_clip_plane:
1873 idx = nir_intrinsic_ucp_id(intr);
1874 for (int i = 0; i < dest_components; i++) {
1875 unsigned n = idx * 4 + i;
1876 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1877 }
1878 break;
1879 case nir_intrinsic_load_front_face:
1880 if (!ctx->frag_face) {
1881 ctx->so->frag_face = true;
1882 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1883 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1884 }
1885 /* for fragface, we get -1 for back and 0 for front. However this is
1886 * the inverse of what nir expects (where ~0 is true).
1887 */
1888 dst[0] = ir3_CMPS_S(b,
1889 ctx->frag_face, 0,
1890 create_immed_typed(b, 0, TYPE_U16), 0);
1891 dst[0]->cat2.condition = IR3_COND_EQ;
1892 break;
1893 case nir_intrinsic_load_local_invocation_id:
1894 if (!ctx->local_invocation_id) {
1895 ctx->local_invocation_id =
1896 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1897 }
1898 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1899 break;
1900 case nir_intrinsic_load_work_group_id:
1901 if (!ctx->work_group_id) {
1902 ctx->work_group_id =
1903 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1904 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1905 }
1906 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1907 break;
1908 case nir_intrinsic_load_num_work_groups:
1909 for (int i = 0; i < dest_components; i++) {
1910 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1911 }
1912 break;
1913 case nir_intrinsic_load_local_group_size:
1914 for (int i = 0; i < dest_components; i++) {
1915 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1916 }
1917 break;
1918 case nir_intrinsic_discard_if:
1919 case nir_intrinsic_discard: {
1920 struct ir3_instruction *cond, *kill;
1921
1922 if (intr->intrinsic == nir_intrinsic_discard_if) {
1923 /* conditional discard: */
1924 src = ir3_get_src(ctx, &intr->src[0]);
1925 cond = src[0];
1926 } else {
1927 /* unconditional discard: */
1928 cond = create_immed(b, 1);
1929 }
1930
1931 /* NOTE: only cmps.*.* can write p0.x: */
1932 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1933 cond->cat2.condition = IR3_COND_NE;
1934
1935 /* condition always goes in predicate register: */
1936 cond->regs[0]->num = regid(REG_P0, 0);
1937 cond->regs[0]->flags &= ~IR3_REG_SSA;
1938
1939 kill = ir3_KILL(b, cond, 0);
1940 kill->regs[1]->num = regid(REG_P0, 0);
1941 array_insert(ctx->ir, ctx->ir->predicates, kill);
1942
1943 array_insert(b, b->keeps, kill);
1944 ctx->so->has_kill = true;
1945
1946 break;
1947 }
1948
1949 case nir_intrinsic_cond_end_ir3: {
1950 struct ir3_instruction *cond, *kill;
1951
1952 src = ir3_get_src(ctx, &intr->src[0]);
1953 cond = src[0];
1954
1955 /* NOTE: only cmps.*.* can write p0.x: */
1956 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1957 cond->cat2.condition = IR3_COND_NE;
1958
1959 /* condition always goes in predicate register: */
1960 cond->regs[0]->num = regid(REG_P0, 0);
1961
1962 kill = ir3_PREDT(b, cond, 0);
1963
1964 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1965 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1966
1967 array_insert(ctx->ir, ctx->ir->predicates, kill);
1968 array_insert(b, b->keeps, kill);
1969 break;
1970 }
1971
1972 case nir_intrinsic_load_shared_ir3:
1973 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1974 break;
1975 case nir_intrinsic_store_shared_ir3:
1976 emit_intrinsic_store_shared_ir3(ctx, intr);
1977 break;
1978 case nir_intrinsic_bindless_resource_ir3:
1979 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1980 break;
1981 default:
1982 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1983 nir_intrinsic_infos[intr->intrinsic].name);
1984 break;
1985 }
1986
1987 if (info->has_dest)
1988 ir3_put_dst(ctx, &intr->dest);
1989 }
1990
1991 static void
1992 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1993 {
1994 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1995 instr->def.num_components);
1996
1997 if (instr->def.bit_size == 16) {
1998 for (int i = 0; i < instr->def.num_components; i++)
1999 dst[i] = create_immed_typed(ctx->block,
2000 instr->value[i].u16,
2001 TYPE_U16);
2002 } else {
2003 for (int i = 0; i < instr->def.num_components; i++)
2004 dst[i] = create_immed_typed(ctx->block,
2005 instr->value[i].u32,
2006 TYPE_U32);
2007 }
2008
2009 }
2010
2011 static void
2012 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
2013 {
2014 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
2015 undef->def.num_components);
2016 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
2017
2018 /* backend doesn't want undefined instructions, so just plug
2019 * in 0.0..
2020 */
2021 for (int i = 0; i < undef->def.num_components; i++)
2022 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2023 }
2024
2025 /*
2026 * texture fetch/sample instructions:
2027 */
2028
2029 static type_t
2030 get_tex_dest_type(nir_tex_instr *tex)
2031 {
2032 type_t type;
2033
2034 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2035 case nir_type_invalid:
2036 case nir_type_float:
2037 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2038 break;
2039 case nir_type_int:
2040 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2041 break;
2042 case nir_type_uint:
2043 case nir_type_bool:
2044 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2045 break;
2046 default:
2047 unreachable("bad dest_type");
2048 }
2049
2050 return type;
2051 }
2052
2053 static void
2054 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2055 {
2056 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2057 unsigned flags = 0;
2058
2059 /* note: would use tex->coord_components.. except txs.. also,
2060 * since array index goes after shadow ref, we don't want to
2061 * count it:
2062 */
2063 if (coords == 3)
2064 flags |= IR3_INSTR_3D;
2065
2066 if (tex->is_shadow && tex->op != nir_texop_lod)
2067 flags |= IR3_INSTR_S;
2068
2069 if (tex->is_array && tex->op != nir_texop_lod)
2070 flags |= IR3_INSTR_A;
2071
2072 *flagsp = flags;
2073 *coordsp = coords;
2074 }
2075
2076 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2077 * or immediate (in which case it will get lowered later to a non .s2en
2078 * version of the tex instruction which encode tex/samp as immediates:
2079 */
2080 static struct tex_src_info
2081 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2082 {
2083 struct ir3_block *b = ctx->block;
2084 struct tex_src_info info = { 0 };
2085 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2086 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2087 struct ir3_instruction *texture, *sampler;
2088
2089 if (texture_idx >= 0 || sampler_idx >= 0) {
2090 /* Bindless case */
2091 info.flags |= IR3_INSTR_B;
2092
2093 /* Gather information required to determine which encoding to
2094 * choose as well as for prefetch.
2095 */
2096 nir_intrinsic_instr *bindless_tex = NULL;
2097 bool tex_const;
2098 if (texture_idx >= 0) {
2099 ctx->so->bindless_tex = true;
2100 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2101 assert(bindless_tex);
2102 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2103 tex_const = nir_src_is_const(bindless_tex->src[0]);
2104 if (tex_const)
2105 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2106 } else {
2107 /* To simplify some of the logic below, assume the index is
2108 * constant 0 when it's not enabled.
2109 */
2110 tex_const = true;
2111 info.tex_idx = 0;
2112 }
2113 nir_intrinsic_instr *bindless_samp = NULL;
2114 bool samp_const;
2115 if (sampler_idx >= 0) {
2116 ctx->so->bindless_samp = true;
2117 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2118 assert(bindless_samp);
2119 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2120 samp_const = nir_src_is_const(bindless_samp->src[0]);
2121 if (samp_const)
2122 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2123 } else {
2124 samp_const = true;
2125 info.samp_idx = 0;
2126 }
2127
2128 /* Choose encoding. */
2129 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2130 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2131 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2132 /* Everything fits within the instruction */
2133 info.base = info.tex_base;
2134 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2135 } else {
2136 info.base = info.tex_base;
2137 info.a1_val = info.tex_idx << 3 | info.samp_base;
2138 info.combined_idx = info.samp_idx;
2139 info.flags |= IR3_INSTR_A1EN;
2140 }
2141 info.samp_tex = NULL;
2142 } else {
2143 info.flags |= IR3_INSTR_S2EN;
2144 /* In the indirect case, we only use a1.x to store the sampler
2145 * base if it differs from the texture base.
2146 */
2147 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2148 info.base = info.tex_base;
2149 } else {
2150 info.base = info.tex_base;
2151 info.a1_val = info.samp_base;
2152 info.flags |= IR3_INSTR_A1EN;
2153 }
2154
2155 /* Note: the indirect source is now a vec2 instead of hvec2, and
2156 * for some reason the texture and sampler are swapped.
2157 */
2158 struct ir3_instruction *texture, *sampler;
2159
2160 if (bindless_tex) {
2161 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2162 } else {
2163 texture = create_immed(b, 0);
2164 }
2165
2166 if (bindless_samp) {
2167 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2168 } else {
2169 sampler = create_immed(b, 0);
2170 }
2171 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2172 texture,
2173 sampler,
2174 }, 2);
2175 }
2176 } else {
2177 info.flags |= IR3_INSTR_S2EN;
2178 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2179 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2180 if (texture_idx >= 0) {
2181 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2182 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2183 } else {
2184 /* TODO what to do for dynamic case? I guess we only need the
2185 * max index for astc srgb workaround so maybe not a problem
2186 * to worry about if we don't enable indirect samplers for
2187 * a4xx?
2188 */
2189 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2190 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2191 info.tex_idx = tex->texture_index;
2192 }
2193
2194 if (sampler_idx >= 0) {
2195 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2196 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2197 } else {
2198 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2199 info.samp_idx = tex->texture_index;
2200 }
2201
2202 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2203 sampler,
2204 texture,
2205 }, 2);
2206 }
2207
2208 return info;
2209 }
2210
2211 static void
2212 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2213 {
2214 struct ir3_block *b = ctx->block;
2215 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2216 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2217 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2218 struct tex_src_info info = { 0 };
2219 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2220 unsigned i, coords, flags, ncomp;
2221 unsigned nsrc0 = 0, nsrc1 = 0;
2222 type_t type;
2223 opc_t opc = 0;
2224
2225 ncomp = nir_dest_num_components(tex->dest);
2226
2227 coord = off = ddx = ddy = NULL;
2228 lod = proj = compare = sample_index = NULL;
2229
2230 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2231
2232 for (unsigned i = 0; i < tex->num_srcs; i++) {
2233 switch (tex->src[i].src_type) {
2234 case nir_tex_src_coord:
2235 coord = ir3_get_src(ctx, &tex->src[i].src);
2236 break;
2237 case nir_tex_src_bias:
2238 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2239 has_bias = true;
2240 break;
2241 case nir_tex_src_lod:
2242 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2243 has_lod = true;
2244 break;
2245 case nir_tex_src_comparator: /* shadow comparator */
2246 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2247 break;
2248 case nir_tex_src_projector:
2249 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2250 has_proj = true;
2251 break;
2252 case nir_tex_src_offset:
2253 off = ir3_get_src(ctx, &tex->src[i].src);
2254 has_off = true;
2255 break;
2256 case nir_tex_src_ddx:
2257 ddx = ir3_get_src(ctx, &tex->src[i].src);
2258 break;
2259 case nir_tex_src_ddy:
2260 ddy = ir3_get_src(ctx, &tex->src[i].src);
2261 break;
2262 case nir_tex_src_ms_index:
2263 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2264 break;
2265 case nir_tex_src_texture_offset:
2266 case nir_tex_src_sampler_offset:
2267 case nir_tex_src_texture_handle:
2268 case nir_tex_src_sampler_handle:
2269 /* handled in get_tex_samp_src() */
2270 break;
2271 default:
2272 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2273 tex->src[i].src_type);
2274 return;
2275 }
2276 }
2277
2278 switch (tex->op) {
2279 case nir_texop_tex_prefetch:
2280 compile_assert(ctx, !has_bias);
2281 compile_assert(ctx, !has_lod);
2282 compile_assert(ctx, !compare);
2283 compile_assert(ctx, !has_proj);
2284 compile_assert(ctx, !has_off);
2285 compile_assert(ctx, !ddx);
2286 compile_assert(ctx, !ddy);
2287 compile_assert(ctx, !sample_index);
2288 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2289 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2290
2291 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2292 opc = OPC_META_TEX_PREFETCH;
2293 ctx->so->num_sampler_prefetch++;
2294 break;
2295 }
2296 /* fallthru */
2297 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2298 case nir_texop_txb: opc = OPC_SAMB; break;
2299 case nir_texop_txl: opc = OPC_SAML; break;
2300 case nir_texop_txd: opc = OPC_SAMGQ; break;
2301 case nir_texop_txf: opc = OPC_ISAML; break;
2302 case nir_texop_lod: opc = OPC_GETLOD; break;
2303 case nir_texop_tg4:
2304 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2305 * what blob does, seems gather is broken?), and a3xx did
2306 * not support it (but probably could also emulate).
2307 */
2308 switch (tex->component) {
2309 case 0: opc = OPC_GATHER4R; break;
2310 case 1: opc = OPC_GATHER4G; break;
2311 case 2: opc = OPC_GATHER4B; break;
2312 case 3: opc = OPC_GATHER4A; break;
2313 }
2314 break;
2315 case nir_texop_txf_ms_fb:
2316 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2317 default:
2318 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2319 return;
2320 }
2321
2322 tex_info(tex, &flags, &coords);
2323
2324 /*
2325 * lay out the first argument in the proper order:
2326 * - actual coordinates first
2327 * - shadow reference
2328 * - array index
2329 * - projection w
2330 * - starting at offset 4, dpdx.xy, dpdy.xy
2331 *
2332 * bias/lod go into the second arg
2333 */
2334
2335 /* insert tex coords: */
2336 for (i = 0; i < coords; i++)
2337 src0[i] = coord[i];
2338
2339 nsrc0 = i;
2340
2341 /* scale up integer coords for TXF based on the LOD */
2342 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2343 assert(has_lod);
2344 for (i = 0; i < coords; i++)
2345 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2346 }
2347
2348 if (coords == 1) {
2349 /* hw doesn't do 1d, so we treat it as 2d with
2350 * height of 1, and patch up the y coord.
2351 */
2352 if (is_isam(opc)) {
2353 src0[nsrc0++] = create_immed(b, 0);
2354 } else {
2355 src0[nsrc0++] = create_immed(b, fui(0.5));
2356 }
2357 }
2358
2359 if (tex->is_shadow && tex->op != nir_texop_lod)
2360 src0[nsrc0++] = compare;
2361
2362 if (tex->is_array && tex->op != nir_texop_lod) {
2363 struct ir3_instruction *idx = coord[coords];
2364
2365 /* the array coord for cube arrays needs 0.5 added to it */
2366 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2367 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2368
2369 src0[nsrc0++] = idx;
2370 }
2371
2372 if (has_proj) {
2373 src0[nsrc0++] = proj;
2374 flags |= IR3_INSTR_P;
2375 }
2376
2377 /* pad to 4, then ddx/ddy: */
2378 if (tex->op == nir_texop_txd) {
2379 while (nsrc0 < 4)
2380 src0[nsrc0++] = create_immed(b, fui(0.0));
2381 for (i = 0; i < coords; i++)
2382 src0[nsrc0++] = ddx[i];
2383 if (coords < 2)
2384 src0[nsrc0++] = create_immed(b, fui(0.0));
2385 for (i = 0; i < coords; i++)
2386 src0[nsrc0++] = ddy[i];
2387 if (coords < 2)
2388 src0[nsrc0++] = create_immed(b, fui(0.0));
2389 }
2390
2391 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2392 * with scaled x coord according to requested sample:
2393 */
2394 if (opc == OPC_ISAMM) {
2395 if (ctx->compiler->txf_ms_with_isaml) {
2396 /* the samples are laid out in x dimension as
2397 * 0 1 2 3
2398 * x_ms = (x << ms) + sample_index;
2399 */
2400 struct ir3_instruction *ms;
2401 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2402
2403 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2404 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2405
2406 opc = OPC_ISAML;
2407 } else {
2408 src0[nsrc0++] = sample_index;
2409 }
2410 }
2411
2412 /*
2413 * second argument (if applicable):
2414 * - offsets
2415 * - lod
2416 * - bias
2417 */
2418 if (has_off | has_lod | has_bias) {
2419 if (has_off) {
2420 unsigned off_coords = coords;
2421 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2422 off_coords--;
2423 for (i = 0; i < off_coords; i++)
2424 src1[nsrc1++] = off[i];
2425 if (off_coords < 2)
2426 src1[nsrc1++] = create_immed(b, fui(0.0));
2427 flags |= IR3_INSTR_O;
2428 }
2429
2430 if (has_lod | has_bias)
2431 src1[nsrc1++] = lod;
2432 }
2433
2434 type = get_tex_dest_type(tex);
2435
2436 if (opc == OPC_GETLOD)
2437 type = TYPE_S32;
2438
2439
2440 if (tex->op == nir_texop_txf_ms_fb) {
2441 /* only expect a single txf_ms_fb per shader: */
2442 compile_assert(ctx, !ctx->so->fb_read);
2443 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2444
2445 ctx->so->fb_read = true;
2446 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2447 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2448 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2449 }, 2);
2450 info.flags = IR3_INSTR_S2EN;
2451
2452 ctx->so->num_samp++;
2453 } else {
2454 info = get_tex_samp_tex_src(ctx, tex);
2455 }
2456
2457 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2458 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2459
2460 if (opc == OPC_META_TEX_PREFETCH) {
2461 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2462
2463 compile_assert(ctx, tex->src[idx].src.is_ssa);
2464
2465 sam = ir3_META_TEX_PREFETCH(b);
2466 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2467 __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
2468 sam->prefetch.input_offset =
2469 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2470 /* make sure not to add irrelevant flags like S2EN */
2471 sam->flags = flags | (info.flags & IR3_INSTR_B);
2472 sam->prefetch.tex = info.tex_idx;
2473 sam->prefetch.samp = info.samp_idx;
2474 sam->prefetch.tex_base = info.tex_base;
2475 sam->prefetch.samp_base = info.samp_base;
2476 } else {
2477 info.flags |= flags;
2478 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2479 }
2480
2481 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2482 assert(opc != OPC_META_TEX_PREFETCH);
2483
2484 /* only need first 3 components: */
2485 sam->regs[0]->wrmask = 0x7;
2486 ir3_split_dest(b, dst, sam, 0, 3);
2487
2488 /* we need to sample the alpha separately with a non-ASTC
2489 * texture state:
2490 */
2491 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2492 info.samp_tex, col0, col1);
2493
2494 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2495
2496 /* fixup .w component: */
2497 ir3_split_dest(b, &dst[3], sam, 3, 1);
2498 } else {
2499 /* normal (non-workaround) case: */
2500 ir3_split_dest(b, dst, sam, 0, ncomp);
2501 }
2502
2503 /* GETLOD returns results in 4.8 fixed point */
2504 if (opc == OPC_GETLOD) {
2505 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2506
2507 compile_assert(ctx, tex->dest_type == nir_type_float);
2508 for (i = 0; i < 2; i++) {
2509 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2510 factor, 0);
2511 }
2512 }
2513
2514 ir3_put_dst(ctx, &tex->dest);
2515 }
2516
2517 static void
2518 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2519 {
2520 struct ir3_block *b = ctx->block;
2521 struct ir3_instruction **dst, *sam;
2522 type_t dst_type = get_tex_dest_type(tex);
2523 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2524
2525 dst = ir3_get_dst(ctx, &tex->dest, 1);
2526
2527 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2528
2529 /* even though there is only one component, since it ends
2530 * up in .y/.z/.w rather than .x, we need a split_dest()
2531 */
2532 ir3_split_dest(b, dst, sam, idx, 1);
2533
2534 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2535 * the value in TEX_CONST_0 is zero-based.
2536 */
2537 if (ctx->compiler->levels_add_one)
2538 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2539
2540 ir3_put_dst(ctx, &tex->dest);
2541 }
2542
2543 static void
2544 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2545 {
2546 struct ir3_block *b = ctx->block;
2547 struct ir3_instruction **dst, *sam;
2548 struct ir3_instruction *lod;
2549 unsigned flags, coords;
2550 type_t dst_type = get_tex_dest_type(tex);
2551 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2552
2553 tex_info(tex, &flags, &coords);
2554 info.flags |= flags;
2555
2556 /* Actually we want the number of dimensions, not coordinates. This
2557 * distinction only matters for cubes.
2558 */
2559 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2560 coords = 2;
2561
2562 dst = ir3_get_dst(ctx, &tex->dest, 4);
2563
2564 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2565 compile_assert(ctx, lod_idx >= 0);
2566
2567 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2568
2569 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2570 ir3_split_dest(b, dst, sam, 0, 4);
2571
2572 /* Array size actually ends up in .w rather than .z. This doesn't
2573 * matter for miplevel 0, but for higher mips the value in z is
2574 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2575 * returned, which means that we have to add 1 to it for arrays.
2576 */
2577 if (tex->is_array) {
2578 if (ctx->compiler->levels_add_one) {
2579 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2580 } else {
2581 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2582 }
2583 }
2584
2585 ir3_put_dst(ctx, &tex->dest);
2586 }
2587
2588 static void
2589 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2590 {
2591 switch (jump->type) {
2592 case nir_jump_break:
2593 case nir_jump_continue:
2594 case nir_jump_return:
2595 /* I *think* we can simply just ignore this, and use the
2596 * successor block link to figure out where we need to
2597 * jump to for break/continue
2598 */
2599 break;
2600 default:
2601 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2602 break;
2603 }
2604 }
2605
2606 static void
2607 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2608 {
2609 switch (instr->type) {
2610 case nir_instr_type_alu:
2611 emit_alu(ctx, nir_instr_as_alu(instr));
2612 break;
2613 case nir_instr_type_deref:
2614 /* ignored, handled as part of the intrinsic they are src to */
2615 break;
2616 case nir_instr_type_intrinsic:
2617 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2618 break;
2619 case nir_instr_type_load_const:
2620 emit_load_const(ctx, nir_instr_as_load_const(instr));
2621 break;
2622 case nir_instr_type_ssa_undef:
2623 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2624 break;
2625 case nir_instr_type_tex: {
2626 nir_tex_instr *tex = nir_instr_as_tex(instr);
2627 /* couple tex instructions get special-cased:
2628 */
2629 switch (tex->op) {
2630 case nir_texop_txs:
2631 emit_tex_txs(ctx, tex);
2632 break;
2633 case nir_texop_query_levels:
2634 emit_tex_info(ctx, tex, 2);
2635 break;
2636 case nir_texop_texture_samples:
2637 emit_tex_info(ctx, tex, 3);
2638 break;
2639 default:
2640 emit_tex(ctx, tex);
2641 break;
2642 }
2643 break;
2644 }
2645 case nir_instr_type_jump:
2646 emit_jump(ctx, nir_instr_as_jump(instr));
2647 break;
2648 case nir_instr_type_phi:
2649 /* we have converted phi webs to regs in NIR by now */
2650 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2651 break;
2652 case nir_instr_type_call:
2653 case nir_instr_type_parallel_copy:
2654 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2655 break;
2656 }
2657 }
2658
2659 static struct ir3_block *
2660 get_block(struct ir3_context *ctx, const nir_block *nblock)
2661 {
2662 struct ir3_block *block;
2663 struct hash_entry *hentry;
2664
2665 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2666 if (hentry)
2667 return hentry->data;
2668
2669 block = ir3_block_create(ctx->ir);
2670 block->nblock = nblock;
2671 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2672
2673 set_foreach(nblock->predecessors, sentry) {
2674 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2675 }
2676
2677 return block;
2678 }
2679
2680 static void
2681 emit_block(struct ir3_context *ctx, nir_block *nblock)
2682 {
2683 struct ir3_block *block = get_block(ctx, nblock);
2684
2685 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2686 if (nblock->successors[i]) {
2687 block->successors[i] =
2688 get_block(ctx, nblock->successors[i]);
2689 }
2690 }
2691
2692 ctx->block = block;
2693 list_addtail(&block->node, &ctx->ir->block_list);
2694
2695 /* re-emit addr register in each block if needed: */
2696 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2697 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2698 ctx->addr0_ht[i] = NULL;
2699 }
2700
2701 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2702 ctx->addr1_ht = NULL;
2703
2704 nir_foreach_instr (instr, nblock) {
2705 ctx->cur_instr = instr;
2706 emit_instr(ctx, instr);
2707 ctx->cur_instr = NULL;
2708 if (ctx->error)
2709 return;
2710 }
2711
2712 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2713 }
2714
2715 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2716
2717 static void
2718 emit_if(struct ir3_context *ctx, nir_if *nif)
2719 {
2720 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2721
2722 ctx->block->condition = ir3_get_predicate(ctx, condition);
2723
2724 emit_cf_list(ctx, &nif->then_list);
2725 emit_cf_list(ctx, &nif->else_list);
2726 }
2727
2728 static void
2729 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2730 {
2731 emit_cf_list(ctx, &nloop->body);
2732 ctx->so->loops++;
2733 }
2734
2735 static void
2736 stack_push(struct ir3_context *ctx)
2737 {
2738 ctx->stack++;
2739 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2740 }
2741
2742 static void
2743 stack_pop(struct ir3_context *ctx)
2744 {
2745 compile_assert(ctx, ctx->stack > 0);
2746 ctx->stack--;
2747 }
2748
2749 static void
2750 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2751 {
2752 foreach_list_typed (nir_cf_node, node, node, list) {
2753 switch (node->type) {
2754 case nir_cf_node_block:
2755 emit_block(ctx, nir_cf_node_as_block(node));
2756 break;
2757 case nir_cf_node_if:
2758 stack_push(ctx);
2759 emit_if(ctx, nir_cf_node_as_if(node));
2760 stack_pop(ctx);
2761 break;
2762 case nir_cf_node_loop:
2763 stack_push(ctx);
2764 emit_loop(ctx, nir_cf_node_as_loop(node));
2765 stack_pop(ctx);
2766 break;
2767 case nir_cf_node_function:
2768 ir3_context_error(ctx, "TODO\n");
2769 break;
2770 }
2771 }
2772 }
2773
2774 /* emit stream-out code. At this point, the current block is the original
2775 * (nir) end block, and nir ensures that all flow control paths terminate
2776 * into the end block. We re-purpose the original end block to generate
2777 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2778 * block holding stream-out write instructions, followed by the new end
2779 * block:
2780 *
2781 * blockOrigEnd {
2782 * p0.x = (vtxcnt < maxvtxcnt)
2783 * // succs: blockStreamOut, blockNewEnd
2784 * }
2785 * blockStreamOut {
2786 * // preds: blockOrigEnd
2787 * ... stream-out instructions ...
2788 * // succs: blockNewEnd
2789 * }
2790 * blockNewEnd {
2791 * // preds: blockOrigEnd, blockStreamOut
2792 * }
2793 */
2794 static void
2795 emit_stream_out(struct ir3_context *ctx)
2796 {
2797 struct ir3 *ir = ctx->ir;
2798 struct ir3_stream_output_info *strmout =
2799 &ctx->so->shader->stream_output;
2800 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2801 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2802 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2803
2804 /* create vtxcnt input in input block at top of shader,
2805 * so that it is seen as live over the entire duration
2806 * of the shader:
2807 */
2808 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2809 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2810
2811 /* at this point, we are at the original 'end' block,
2812 * re-purpose this block to stream-out condition, then
2813 * append stream-out block and new-end block
2814 */
2815 orig_end_block = ctx->block;
2816
2817 // maybe w/ store_global intrinsic, we could do this
2818 // stuff in nir->nir pass
2819
2820 stream_out_block = ir3_block_create(ir);
2821 list_addtail(&stream_out_block->node, &ir->block_list);
2822
2823 new_end_block = ir3_block_create(ir);
2824 list_addtail(&new_end_block->node, &ir->block_list);
2825
2826 orig_end_block->successors[0] = stream_out_block;
2827 orig_end_block->successors[1] = new_end_block;
2828
2829 stream_out_block->successors[0] = new_end_block;
2830 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2831
2832 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2833 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2834
2835 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2836 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2837 cond->regs[0]->num = regid(REG_P0, 0);
2838 cond->regs[0]->flags &= ~IR3_REG_SSA;
2839 cond->cat2.condition = IR3_COND_LT;
2840
2841 /* condition goes on previous block to the conditional,
2842 * since it is used to pick which of the two successor
2843 * paths to take:
2844 */
2845 orig_end_block->condition = cond;
2846
2847 /* switch to stream_out_block to generate the stream-out
2848 * instructions:
2849 */
2850 ctx->block = stream_out_block;
2851
2852 /* Calculate base addresses based on vtxcnt. Instructions
2853 * generated for bases not used in following loop will be
2854 * stripped out in the backend.
2855 */
2856 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2857 const struct ir3_const_state *const_state =
2858 ir3_const_state(ctx->so);
2859 unsigned stride = strmout->stride[i];
2860 struct ir3_instruction *base, *off;
2861
2862 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2863
2864 /* 24-bit should be enough: */
2865 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2866 create_immed(ctx->block, stride * 4), 0);
2867
2868 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2869 }
2870
2871 /* Generate the per-output store instructions: */
2872 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2873 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2874 unsigned c = j + strmout->output[i].start_component;
2875 struct ir3_instruction *base, *out, *stg;
2876
2877 base = bases[strmout->output[i].output_buffer];
2878 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2879
2880 stg = ir3_STG(ctx->block, base, 0, out, 0,
2881 create_immed(ctx->block, 1), 0);
2882 stg->cat6.type = TYPE_U32;
2883 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2884
2885 array_insert(ctx->block, ctx->block->keeps, stg);
2886 }
2887 }
2888
2889 /* and finally switch to the new_end_block: */
2890 ctx->block = new_end_block;
2891 }
2892
2893 static void
2894 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2895 {
2896 nir_metadata_require(impl, nir_metadata_block_index);
2897
2898 compile_assert(ctx, ctx->stack == 0);
2899
2900 emit_cf_list(ctx, &impl->body);
2901 emit_block(ctx, impl->end_block);
2902
2903 compile_assert(ctx, ctx->stack == 0);
2904
2905 /* at this point, we should have a single empty block,
2906 * into which we emit the 'end' instruction.
2907 */
2908 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2909
2910 /* If stream-out (aka transform-feedback) enabled, emit the
2911 * stream-out instructions, followed by a new empty block (into
2912 * which the 'end' instruction lands).
2913 *
2914 * NOTE: it is done in this order, rather than inserting before
2915 * we emit end_block, because NIR guarantees that all blocks
2916 * flow into end_block, and that end_block has no successors.
2917 * So by re-purposing end_block as the first block of stream-
2918 * out, we guarantee that all exit paths flow into the stream-
2919 * out instructions.
2920 */
2921 if ((ctx->compiler->gpu_id < 500) &&
2922 (ctx->so->shader->stream_output.num_outputs > 0) &&
2923 !ctx->so->binning_pass) {
2924 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2925 emit_stream_out(ctx);
2926 }
2927
2928 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2929 * NOP and has an epilogue that writes the VS outputs to local storage, to
2930 * be read by the HS. Then it resets execution mask (chmask) and chains
2931 * to the next shader (chsh).
2932 */
2933 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2934 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2935 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2936 struct ir3_instruction *chmask =
2937 ir3_CHMASK(ctx->block);
2938 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2939 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2940
2941 struct ir3_instruction *chsh =
2942 ir3_CHSH(ctx->block);
2943 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2944 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2945 } else {
2946 ir3_END(ctx->block);
2947 }
2948 }
2949
2950 static void
2951 setup_input(struct ir3_context *ctx, nir_variable *in)
2952 {
2953 struct ir3_shader_variant *so = ctx->so;
2954 unsigned ncomp = glsl_get_components(in->type);
2955 unsigned n = in->data.driver_location;
2956 unsigned frac = in->data.location_frac;
2957 unsigned slot = in->data.location;
2958
2959 /* Inputs are loaded using ldlw or ldg for these stages. */
2960 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2961 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2962 ctx->so->type == MESA_SHADER_GEOMETRY)
2963 return;
2964
2965 /* skip unread inputs, we could end up with (for example), unsplit
2966 * matrix/etc inputs in the case they are not read, so just silently
2967 * skip these.
2968 */
2969 if (ncomp > 4)
2970 return;
2971
2972 so->inputs[n].slot = slot;
2973 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2974 so->inputs_count = MAX2(so->inputs_count, n + 1);
2975 so->inputs[n].interpolate = in->data.interpolation;
2976
2977 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2978
2979 /* if any varyings have 'sample' qualifer, that triggers us
2980 * to run in per-sample mode:
2981 */
2982 so->per_samp |= in->data.sample;
2983
2984 for (int i = 0; i < ncomp; i++) {
2985 struct ir3_instruction *instr = NULL;
2986 unsigned idx = (n * 4) + i + frac;
2987
2988 if (slot == VARYING_SLOT_POS) {
2989 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2990 } else {
2991 /* detect the special case for front/back colors where
2992 * we need to do flat vs smooth shading depending on
2993 * rast state:
2994 */
2995 if (in->data.interpolation == INTERP_MODE_NONE) {
2996 switch (slot) {
2997 case VARYING_SLOT_COL0:
2998 case VARYING_SLOT_COL1:
2999 case VARYING_SLOT_BFC0:
3000 case VARYING_SLOT_BFC1:
3001 so->inputs[n].rasterflat = true;
3002 break;
3003 default:
3004 break;
3005 }
3006 }
3007
3008 if (ctx->compiler->flat_bypass) {
3009 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
3010 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
3011 so->inputs[n].use_ldlv = true;
3012 }
3013
3014 so->inputs[n].bary = true;
3015
3016 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3017 }
3018
3019 compile_assert(ctx, idx < ctx->ninputs);
3020
3021 ctx->inputs[idx] = instr;
3022 }
3023 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3024 struct ir3_instruction *input = NULL;
3025 struct ir3_instruction *components[4];
3026 /* input as setup as frac=0 with "ncomp + frac" components,
3027 * this avoids getting a sparse writemask
3028 */
3029 unsigned mask = (1 << (ncomp + frac)) - 1;
3030
3031 foreach_input (in, ctx->ir) {
3032 if (in->input.inidx == n) {
3033 input = in;
3034 break;
3035 }
3036 }
3037
3038 if (!input) {
3039 input = create_input(ctx, mask);
3040 input->input.inidx = n;
3041 } else {
3042 /* For aliased inputs, just append to the wrmask.. ie. if we
3043 * first see a vec2 index at slot N, and then later a vec4,
3044 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3045 *
3046 * If the new input that aliases a previously processed input
3047 * sets no new bits, then just bail as there is nothing to see
3048 * here.
3049 */
3050 if (!(mask & ~input->regs[0]->wrmask))
3051 return;
3052 input->regs[0]->wrmask |= mask;
3053 }
3054
3055 ir3_split_dest(ctx->block, components, input, 0, ncomp + frac);
3056
3057 for (int i = 0; i < ncomp + frac; i++) {
3058 unsigned idx = (n * 4) + i;
3059 compile_assert(ctx, idx < ctx->ninputs);
3060
3061 /* With aliased inputs, since we add to the wrmask above, we
3062 * can end up with stale meta:split instructions in the inputs
3063 * table. This is basically harmless, since eventually they
3064 * will get swept away by DCE, but the mismatch wrmask (since
3065 * they would be using the previous wrmask before we OR'd in
3066 * more bits) angers ir3_validate. So just preemptively clean
3067 * them up. See:
3068 *
3069 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3070 *
3071 * Note however that split_dest() will return the src if it is
3072 * scalar, so the previous ctx->inputs[idx] could be the input
3073 * itself (which we don't want to remove)
3074 */
3075 if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) {
3076 list_del(&ctx->inputs[idx]->node);
3077 }
3078
3079 ctx->inputs[idx] = components[i];
3080 }
3081 } else {
3082 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3083 }
3084
3085 /* note: this can be wrong for sparse vertex inputs, this happens with
3086 * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
3087 */
3088 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3089 so->total_in += ncomp;
3090 }
3091 }
3092
3093 /* Initially we assign non-packed inloc's for varyings, as we don't really
3094 * know up-front which components will be unused. After all the compilation
3095 * stages we scan the shader to see which components are actually used, and
3096 * re-pack the inlocs to eliminate unneeded varyings.
3097 */
3098 static void
3099 pack_inlocs(struct ir3_context *ctx)
3100 {
3101 struct ir3_shader_variant *so = ctx->so;
3102 uint8_t used_components[so->inputs_count];
3103
3104 memset(used_components, 0, sizeof(used_components));
3105
3106 /*
3107 * First Step: scan shader to find which bary.f/ldlv remain:
3108 */
3109
3110 foreach_block (block, &ctx->ir->block_list) {
3111 foreach_instr (instr, &block->instr_list) {
3112 if (is_input(instr)) {
3113 unsigned inloc = instr->regs[1]->iim_val;
3114 unsigned i = inloc / 4;
3115 unsigned j = inloc % 4;
3116
3117 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3118 compile_assert(ctx, i < so->inputs_count);
3119
3120 used_components[i] |= 1 << j;
3121 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3122 for (int n = 0; n < 2; n++) {
3123 unsigned inloc = instr->prefetch.input_offset + n;
3124 unsigned i = inloc / 4;
3125 unsigned j = inloc % 4;
3126
3127 compile_assert(ctx, i < so->inputs_count);
3128
3129 used_components[i] |= 1 << j;
3130 }
3131 }
3132 }
3133 }
3134
3135 /*
3136 * Second Step: reassign varying inloc/slots:
3137 */
3138
3139 unsigned actual_in = 0;
3140 unsigned inloc = 0;
3141
3142 for (unsigned i = 0; i < so->inputs_count; i++) {
3143 unsigned compmask = 0, maxcomp = 0;
3144
3145 so->inputs[i].inloc = inloc;
3146 so->inputs[i].bary = false;
3147
3148 for (unsigned j = 0; j < 4; j++) {
3149 if (!(used_components[i] & (1 << j)))
3150 continue;
3151
3152 compmask |= (1 << j);
3153 actual_in++;
3154 maxcomp = j + 1;
3155
3156 /* at this point, since used_components[i] mask is only
3157 * considering varyings (ie. not sysvals) we know this
3158 * is a varying:
3159 */
3160 so->inputs[i].bary = true;
3161 }
3162
3163 if (so->inputs[i].bary) {
3164 so->varying_in++;
3165 so->inputs[i].compmask = (1 << maxcomp) - 1;
3166 inloc += maxcomp;
3167 }
3168 }
3169
3170 /*
3171 * Third Step: reassign packed inloc's:
3172 */
3173
3174 foreach_block (block, &ctx->ir->block_list) {
3175 foreach_instr (instr, &block->instr_list) {
3176 if (is_input(instr)) {
3177 unsigned inloc = instr->regs[1]->iim_val;
3178 unsigned i = inloc / 4;
3179 unsigned j = inloc % 4;
3180
3181 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3182 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3183 unsigned i = instr->prefetch.input_offset / 4;
3184 unsigned j = instr->prefetch.input_offset % 4;
3185 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3186 }
3187 }
3188 }
3189 }
3190
3191 static void
3192 setup_output(struct ir3_context *ctx, nir_variable *out)
3193 {
3194 struct ir3_shader_variant *so = ctx->so;
3195 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3196 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3197 unsigned n = out->data.driver_location;
3198 unsigned frac = out->data.location_frac;
3199 unsigned slot = out->data.location;
3200
3201 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3202 switch (slot) {
3203 case FRAG_RESULT_DEPTH:
3204 so->writes_pos = true;
3205 break;
3206 case FRAG_RESULT_COLOR:
3207 so->color0_mrt = 1;
3208 break;
3209 case FRAG_RESULT_SAMPLE_MASK:
3210 so->writes_smask = true;
3211 break;
3212 case FRAG_RESULT_STENCIL:
3213 so->writes_stencilref = true;
3214 break;
3215 default:
3216 slot += out->data.index; /* For dual-src blend */
3217 if (slot >= FRAG_RESULT_DATA0)
3218 break;
3219 ir3_context_error(ctx, "unknown FS output name: %s\n",
3220 gl_frag_result_name(slot));
3221 }
3222 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3223 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3224 ctx->so->type == MESA_SHADER_GEOMETRY) {
3225 switch (slot) {
3226 case VARYING_SLOT_POS:
3227 so->writes_pos = true;
3228 break;
3229 case VARYING_SLOT_PSIZ:
3230 so->writes_psize = true;
3231 break;
3232 case VARYING_SLOT_PRIMITIVE_ID:
3233 case VARYING_SLOT_LAYER:
3234 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3235 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3236 /* fall through */
3237 case VARYING_SLOT_COL0:
3238 case VARYING_SLOT_COL1:
3239 case VARYING_SLOT_BFC0:
3240 case VARYING_SLOT_BFC1:
3241 case VARYING_SLOT_FOGC:
3242 case VARYING_SLOT_CLIP_DIST0:
3243 case VARYING_SLOT_CLIP_DIST1:
3244 case VARYING_SLOT_CLIP_VERTEX:
3245 break;
3246 default:
3247 if (slot >= VARYING_SLOT_VAR0)
3248 break;
3249 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3250 break;
3251 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3252 _mesa_shader_stage_to_string(ctx->so->type),
3253 gl_varying_slot_name(slot));
3254 }
3255 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3256 /* output lowered to buffer writes. */
3257 return;
3258 } else {
3259 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3260 }
3261
3262
3263 so->outputs_count = out->data.driver_location + slots;
3264 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3265
3266 for (int i = 0; i < slots; i++) {
3267 int slot_base = n + i;
3268 so->outputs[slot_base].slot = slot + i;
3269
3270 for (int i = 0; i < ncomp; i++) {
3271 unsigned idx = (slot_base * 4) + i + frac;
3272 compile_assert(ctx, idx < ctx->noutputs);
3273 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3274 }
3275
3276 /* if varying packing doesn't happen, we could end up in a situation
3277 * with "holes" in the output, and since the per-generation code that
3278 * sets up varying linkage registers doesn't expect to have more than
3279 * one varying per vec4 slot, pad the holes.
3280 *
3281 * Note that this should probably generate a performance warning of
3282 * some sort.
3283 */
3284 for (int i = 0; i < frac; i++) {
3285 unsigned idx = (slot_base * 4) + i;
3286 if (!ctx->outputs[idx]) {
3287 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3288 }
3289 }
3290 }
3291 }
3292
3293 static void
3294 emit_instructions(struct ir3_context *ctx)
3295 {
3296 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3297
3298 ctx->ninputs = ctx->s->num_inputs * 4;
3299 ctx->noutputs = ctx->s->num_outputs * 4;
3300 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3301 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3302
3303 ctx->ir = ir3_create(ctx->compiler, ctx->so);
3304
3305 /* Create inputs in first block: */
3306 ctx->block = get_block(ctx, nir_start_block(fxn));
3307 ctx->in_block = ctx->block;
3308
3309 /* for fragment shader, the vcoord input register is used as the
3310 * base for bary.f varying fetch instrs:
3311 *
3312 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3313 * until emit_intrinsic when we know they are actually needed.
3314 * For now, we defer creating ctx->ij_centroid, etc, since we
3315 * only need ij_pixel for "old style" varying inputs (ie.
3316 * tgsi_to_nir)
3317 */
3318 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3319 ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3);
3320 }
3321
3322 /* Setup inputs: */
3323 nir_foreach_variable (var, &ctx->s->inputs) {
3324 setup_input(ctx, var);
3325 }
3326
3327 /* Defer add_sysval_input() stuff until after setup_inputs(),
3328 * because sysvals need to be appended after varyings:
3329 */
3330 if (ctx->ij[IJ_PERSP_PIXEL]) {
3331 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3332 0x3, ctx->ij[IJ_PERSP_PIXEL]);
3333 }
3334
3335
3336 /* Tesselation shaders always need primitive ID for indexing the
3337 * BO. Geometry shaders don't always need it but when they do it has be
3338 * delivered and unclobbered in the VS. To make things easy, we always
3339 * make room for it in VS/DS.
3340 */
3341 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3342 bool has_gs = ctx->so->key.has_gs;
3343 switch (ctx->so->type) {
3344 case MESA_SHADER_VERTEX:
3345 if (has_tess) {
3346 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3347 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3348 } else if (has_gs) {
3349 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3350 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3351 }
3352 break;
3353 case MESA_SHADER_TESS_CTRL:
3354 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3355 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3356 break;
3357 case MESA_SHADER_TESS_EVAL:
3358 if (has_gs)
3359 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3360 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3361 break;
3362 case MESA_SHADER_GEOMETRY:
3363 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3364 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3365 break;
3366 default:
3367 break;
3368 }
3369
3370 /* Setup outputs: */
3371 nir_foreach_variable (var, &ctx->s->outputs) {
3372 setup_output(ctx, var);
3373 }
3374
3375 /* Find # of samplers. Just assume that we'll be reading from images.. if
3376 * it is write-only we don't have to count it, but after lowering derefs
3377 * is too late to compact indices for that.
3378 */
3379 ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images;
3380
3381 /* NOTE: need to do something more clever when we support >1 fxn */
3382 nir_foreach_register (reg, &fxn->registers) {
3383 ir3_declare_array(ctx, reg);
3384 }
3385 /* And emit the body: */
3386 ctx->impl = fxn;
3387 emit_function(ctx, fxn);
3388 }
3389
3390 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3391 * need to assign the tex state indexes for these after we know the
3392 * max tex index.
3393 */
3394 static void
3395 fixup_astc_srgb(struct ir3_context *ctx)
3396 {
3397 struct ir3_shader_variant *so = ctx->so;
3398 /* indexed by original tex idx, value is newly assigned alpha sampler
3399 * state tex idx. Zero is invalid since there is at least one sampler
3400 * if we get here.
3401 */
3402 unsigned alt_tex_state[16] = {0};
3403 unsigned tex_idx = ctx->max_texture_index + 1;
3404 unsigned idx = 0;
3405
3406 so->astc_srgb.base = tex_idx;
3407
3408 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3409 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3410
3411 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3412
3413 if (alt_tex_state[sam->cat5.tex] == 0) {
3414 /* assign new alternate/alpha tex state slot: */
3415 alt_tex_state[sam->cat5.tex] = tex_idx++;
3416 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3417 so->astc_srgb.count++;
3418 }
3419
3420 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3421 }
3422 }
3423
3424 static void
3425 fixup_binning_pass(struct ir3_context *ctx)
3426 {
3427 struct ir3_shader_variant *so = ctx->so;
3428 struct ir3 *ir = ctx->ir;
3429 unsigned i, j;
3430
3431 /* first pass, remove unused outputs from the IR level outputs: */
3432 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3433 struct ir3_instruction *out = ir->outputs[i];
3434 assert(out->opc == OPC_META_COLLECT);
3435 unsigned outidx = out->collect.outidx;
3436 unsigned slot = so->outputs[outidx].slot;
3437
3438 /* throw away everything but first position/psize */
3439 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3440 ir->outputs[j] = ir->outputs[i];
3441 j++;
3442 }
3443 }
3444 ir->outputs_count = j;
3445
3446 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3447 * table:
3448 */
3449 for (i = 0, j = 0; i < so->outputs_count; i++) {
3450 unsigned slot = so->outputs[i].slot;
3451
3452 /* throw away everything but first position/psize */
3453 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3454 so->outputs[j] = so->outputs[i];
3455
3456 /* fixup outidx to point to new output table entry: */
3457 foreach_output (out, ir) {
3458 if (out->collect.outidx == i) {
3459 out->collect.outidx = j;
3460 break;
3461 }
3462 }
3463
3464 j++;
3465 }
3466 }
3467 so->outputs_count = j;
3468 }
3469
3470 static void
3471 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3472 {
3473 unsigned idx = 0;
3474
3475 /* Collect sampling instructions eligible for pre-dispatch. */
3476 foreach_block (block, &ir->block_list) {
3477 foreach_instr_safe (instr, &block->instr_list) {
3478 if (instr->opc == OPC_META_TEX_PREFETCH) {
3479 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3480 struct ir3_sampler_prefetch *fetch =
3481 &ctx->so->sampler_prefetch[idx];
3482 idx++;
3483
3484 if (instr->flags & IR3_INSTR_B) {
3485 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3486 /* In bindless mode, the index is actually the base */
3487 fetch->tex_id = instr->prefetch.tex_base;
3488 fetch->samp_id = instr->prefetch.samp_base;
3489 fetch->tex_bindless_id = instr->prefetch.tex;
3490 fetch->samp_bindless_id = instr->prefetch.samp;
3491 } else {
3492 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3493 fetch->tex_id = instr->prefetch.tex;
3494 fetch->samp_id = instr->prefetch.samp;
3495 }
3496 fetch->wrmask = instr->regs[0]->wrmask;
3497 fetch->dst = instr->regs[0]->num;
3498 fetch->src = instr->prefetch.input_offset;
3499
3500 /* These are the limits on a5xx/a6xx, we might need to
3501 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3502 */
3503 assert(fetch->dst <= 0x3f);
3504 assert(fetch->tex_id <= 0x1f);
3505 assert(fetch->samp_id < 0xf);
3506
3507 ctx->so->total_in =
3508 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3509
3510 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3511
3512 /* Remove the prefetch placeholder instruction: */
3513 list_delinit(&instr->node);
3514 }
3515 }
3516 }
3517 }
3518
3519 int
3520 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3521 struct ir3_shader_variant *so)
3522 {
3523 struct ir3_context *ctx;
3524 struct ir3 *ir;
3525 int ret = 0, max_bary;
3526 bool progress;
3527
3528 assert(!so->ir);
3529
3530 ctx = ir3_context_init(compiler, so);
3531 if (!ctx) {
3532 DBG("INIT failed!");
3533 ret = -1;
3534 goto out;
3535 }
3536
3537 emit_instructions(ctx);
3538
3539 if (ctx->error) {
3540 DBG("EMIT failed!");
3541 ret = -1;
3542 goto out;
3543 }
3544
3545 ir = so->ir = ctx->ir;
3546
3547 assert((ctx->noutputs % 4) == 0);
3548
3549 /* Setup IR level outputs, which are "collects" that gather
3550 * the scalar components of outputs.
3551 */
3552 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3553 unsigned ncomp = 0;
3554 /* figure out the # of components written:
3555 *
3556 * TODO do we need to handle holes, ie. if .x and .z
3557 * components written, but .y component not written?
3558 */
3559 for (unsigned j = 0; j < 4; j++) {
3560 if (!ctx->outputs[i + j])
3561 break;
3562 ncomp++;
3563 }
3564
3565 /* Note that in some stages, like TCS, store_output is
3566 * lowered to memory writes, so no components of the
3567 * are "written" from the PoV of traditional store-
3568 * output instructions:
3569 */
3570 if (!ncomp)
3571 continue;
3572
3573 struct ir3_instruction *out =
3574 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3575
3576 int outidx = i / 4;
3577 assert(outidx < so->outputs_count);
3578
3579 /* stash index into so->outputs[] so we can map the
3580 * output back to slot/etc later:
3581 */
3582 out->collect.outidx = outidx;
3583
3584 array_insert(ir, ir->outputs, out);
3585 }
3586
3587 /* Set up the gs header as an output for the vertex shader so it won't
3588 * clobber it for the tess ctrl shader.
3589 *
3590 * TODO this could probably be done more cleanly in a nir pass.
3591 */
3592 if (ctx->so->type == MESA_SHADER_VERTEX ||
3593 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3594 if (ctx->primitive_id) {
3595 unsigned n = so->outputs_count++;
3596 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3597
3598 struct ir3_instruction *out =
3599 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3600 out->collect.outidx = n;
3601 array_insert(ir, ir->outputs, out);
3602 }
3603
3604 if (ctx->gs_header) {
3605 unsigned n = so->outputs_count++;
3606 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3607 struct ir3_instruction *out =
3608 ir3_create_collect(ctx, &ctx->gs_header, 1);
3609 out->collect.outidx = n;
3610 array_insert(ir, ir->outputs, out);
3611 }
3612
3613 if (ctx->tcs_header) {
3614 unsigned n = so->outputs_count++;
3615 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3616 struct ir3_instruction *out =
3617 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3618 out->collect.outidx = n;
3619 array_insert(ir, ir->outputs, out);
3620 }
3621 }
3622
3623 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3624 * need to make sure not to remove any inputs that are used by
3625 * the nonbinning VS.
3626 */
3627 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3628 so->type == MESA_SHADER_VERTEX) {
3629 for (int i = 0; i < ctx->ninputs; i++) {
3630 struct ir3_instruction *in = ctx->inputs[i];
3631
3632 if (!in)
3633 continue;
3634
3635 unsigned n = i / 4;
3636 unsigned c = i % 4;
3637
3638 debug_assert(n < so->nonbinning->inputs_count);
3639
3640 if (so->nonbinning->inputs[n].sysval)
3641 continue;
3642
3643 /* be sure to keep inputs, even if only used in VS */
3644 if (so->nonbinning->inputs[n].compmask & (1 << c))
3645 array_insert(in->block, in->block->keeps, in);
3646 }
3647 }
3648
3649 /* at this point, for binning pass, throw away unneeded outputs: */
3650 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3651 fixup_binning_pass(ctx);
3652
3653 ir3_debug_print(ir, "AFTER: nir->ir3");
3654 ir3_validate(ir);
3655
3656 do {
3657 progress = false;
3658
3659 progress |= IR3_PASS(ir, ir3_cf);
3660 progress |= IR3_PASS(ir, ir3_cp, so);
3661 progress |= IR3_PASS(ir, ir3_dce, so);
3662 } while (progress);
3663
3664 /* at this point, for binning pass, throw away unneeded outputs:
3665 * Note that for a6xx and later, we do this after ir3_cp to ensure
3666 * that the uniform/constant layout for BS and VS matches, so that
3667 * we can re-use same VS_CONST state group.
3668 */
3669 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
3670 fixup_binning_pass(ctx);
3671 /* cleanup the result of removing unneeded outputs: */
3672 while (IR3_PASS(ir, ir3_dce, so)) {}
3673 }
3674
3675 IR3_PASS(ir, ir3_sched_add_deps);
3676
3677 /* Group left/right neighbors, inserting mov's where needed to
3678 * solve conflicts:
3679 */
3680 IR3_PASS(ir, ir3_group);
3681
3682 /* At this point, all the dead code should be long gone: */
3683 assert(!IR3_PASS(ir, ir3_dce, so));
3684
3685 ret = ir3_sched(ir);
3686 if (ret) {
3687 DBG("SCHED failed!");
3688 goto out;
3689 }
3690
3691 ir3_debug_print(ir, "AFTER: ir3_sched");
3692
3693 if (IR3_PASS(ir, ir3_cp_postsched)) {
3694 /* cleanup the result of removing unneeded mov's: */
3695 while (IR3_PASS(ir, ir3_dce, so)) {}
3696 }
3697
3698 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3699 * with draw pass VS, so binning and draw pass can both use the
3700 * same VBO state.
3701 *
3702 * Note that VS inputs are expected to be full precision.
3703 */
3704 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3705 (ir->type == MESA_SHADER_VERTEX) &&
3706 so->binning_pass;
3707
3708 if (pre_assign_inputs) {
3709 for (unsigned i = 0; i < ctx->ninputs; i++) {
3710 struct ir3_instruction *instr = ctx->inputs[i];
3711
3712 if (!instr)
3713 continue;
3714
3715 unsigned n = i / 4;
3716 unsigned c = i % 4;
3717 unsigned regid = so->nonbinning->inputs[n].regid + c;
3718
3719 instr->regs[0]->num = regid;
3720 }
3721
3722 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3723 } else if (ctx->tcs_header) {
3724 /* We need to have these values in the same registers between VS and TCS
3725 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3726 */
3727
3728 ctx->tcs_header->regs[0]->num = regid(0, 0);
3729 ctx->primitive_id->regs[0]->num = regid(0, 1);
3730 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3731 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3732 } else if (ctx->gs_header) {
3733 /* We need to have these values in the same registers between producer
3734 * (VS or DS) and GS since the producer chains to GS and doesn't get
3735 * the sysvals redelivered.
3736 */
3737
3738 ctx->gs_header->regs[0]->num = regid(0, 0);
3739 ctx->primitive_id->regs[0]->num = regid(0, 1);
3740 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3741 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3742 } else if (so->num_sampler_prefetch) {
3743 assert(so->type == MESA_SHADER_FRAGMENT);
3744 struct ir3_instruction *precolor[2];
3745 int idx = 0;
3746
3747 foreach_input (instr, ir) {
3748 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3749 continue;
3750
3751 assert(idx < ARRAY_SIZE(precolor));
3752
3753 precolor[idx] = instr;
3754 instr->regs[0]->num = idx;
3755
3756 idx++;
3757 }
3758 ret = ir3_ra(so, precolor, idx);
3759 } else {
3760 ret = ir3_ra(so, NULL, 0);
3761 }
3762
3763 if (ret) {
3764 DBG("RA failed!");
3765 goto out;
3766 }
3767
3768 IR3_PASS(ir, ir3_postsched, so);
3769
3770 if (compiler->gpu_id >= 600) {
3771 IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
3772 }
3773
3774 if (so->type == MESA_SHADER_FRAGMENT)
3775 pack_inlocs(ctx);
3776
3777 /*
3778 * Fixup inputs/outputs to point to the actual registers assigned:
3779 *
3780 * 1) initialize to r63.x (invalid/unused)
3781 * 2) iterate IR level inputs/outputs and update the variants
3782 * inputs/outputs table based on the assigned registers for
3783 * the remaining inputs/outputs.
3784 */
3785
3786 for (unsigned i = 0; i < so->inputs_count; i++)
3787 so->inputs[i].regid = INVALID_REG;
3788 for (unsigned i = 0; i < so->outputs_count; i++)
3789 so->outputs[i].regid = INVALID_REG;
3790
3791 foreach_output (out, ir) {
3792 assert(out->opc == OPC_META_COLLECT);
3793 unsigned outidx = out->collect.outidx;
3794
3795 so->outputs[outidx].regid = out->regs[0]->num;
3796 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3797 }
3798
3799 foreach_input (in, ir) {
3800 assert(in->opc == OPC_META_INPUT);
3801 unsigned inidx = in->input.inidx;
3802
3803 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3804 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3805 compile_assert(ctx, in->regs[0]->num ==
3806 so->nonbinning->inputs[inidx].regid);
3807 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3808 so->nonbinning->inputs[inidx].half);
3809 }
3810 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3811 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3812 } else {
3813 so->inputs[inidx].regid = in->regs[0]->num;
3814 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3815 }
3816 }
3817
3818 if (ctx->astc_srgb)
3819 fixup_astc_srgb(ctx);
3820
3821 /* We need to do legalize after (for frag shader's) the "bary.f"
3822 * offsets (inloc) have been assigned.
3823 */
3824 IR3_PASS(ir, ir3_legalize, so, &max_bary);
3825
3826 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3827 * know what we might have to wait on when coming in from VS chsh.
3828 */
3829 if (so->type == MESA_SHADER_TESS_CTRL ||
3830 so->type == MESA_SHADER_GEOMETRY ) {
3831 foreach_block (block, &ir->block_list) {
3832 foreach_instr (instr, &block->instr_list) {
3833 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3834 break;
3835 }
3836 }
3837 }
3838
3839 so->branchstack = ctx->max_stack;
3840
3841 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3842 if (so->type == MESA_SHADER_FRAGMENT)
3843 so->total_in = max_bary + 1;
3844
3845 /* Collect sampling instructions eligible for pre-dispatch. */
3846 collect_tex_prefetches(ctx, ir);
3847
3848 if (so->type == MESA_SHADER_FRAGMENT &&
3849 ctx->s->info.fs.needs_helper_invocations)
3850 so->need_pixlod = true;
3851
3852 out:
3853 if (ret) {
3854 if (so->ir)
3855 ir3_destroy(so->ir);
3856 so->ir = NULL;
3857 }
3858 ir3_context_free(ctx);
3859
3860 return ret;
3861 }