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[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* actual inloc is assigned and fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, 0);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count: {
620 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
621 // double check on earlier gen's. Once half-precision support is
622 // in place, this should probably move to a NIR lowering pass:
623 struct ir3_instruction *hi, *lo;
624
625 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
626 TYPE_U32, TYPE_U16);
627 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
628
629 hi = ir3_CBITS_B(b, hi, 0);
630 lo = ir3_CBITS_B(b, lo, 0);
631
632 // TODO maybe the builders should default to making dst half-precision
633 // if the src's were half precision, to make this less awkward.. otoh
634 // we should probably just do this lowering in NIR.
635 hi->regs[0]->flags |= IR3_REG_HALF;
636 lo->regs[0]->flags |= IR3_REG_HALF;
637
638 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
639 dst[0]->regs[0]->flags |= IR3_REG_HALF;
640 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
641 break;
642 }
643 case nir_op_ifind_msb: {
644 struct ir3_instruction *cmp;
645 dst[0] = ir3_CLZ_S(b, src[0], 0);
646 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
647 cmp->cat2.condition = IR3_COND_GE;
648 dst[0] = ir3_SEL_B32(b,
649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
650 cmp, 0, dst[0], 0);
651 break;
652 }
653 case nir_op_ufind_msb:
654 dst[0] = ir3_CLZ_B(b, src[0], 0);
655 dst[0] = ir3_SEL_B32(b,
656 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
657 src[0], 0, dst[0], 0);
658 break;
659 case nir_op_find_lsb:
660 dst[0] = ir3_BFREV_B(b, src[0], 0);
661 dst[0] = ir3_CLZ_B(b, dst[0], 0);
662 break;
663 case nir_op_bitfield_reverse:
664 dst[0] = ir3_BFREV_B(b, src[0], 0);
665 break;
666
667 default:
668 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
669 nir_op_infos[alu->op].name);
670 break;
671 }
672
673 ir3_put_dst(ctx, &alu->dest.dest);
674 }
675
676 /* handles direct/indirect UBO reads: */
677 static void
678 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
679 struct ir3_instruction **dst)
680 {
681 struct ir3_block *b = ctx->block;
682 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
683 nir_const_value *const_offset;
684 /* UBO addresses are the first driver params, but subtract 2 here to
685 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
686 * is the uniforms: */
687 unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2;
688 const unsigned ptrsz = ir3_pointer_size(ctx);
689
690 int off = 0;
691
692 /* First src is ubo index, which could either be an immed or not: */
693 src0 = ir3_get_src(ctx, &intr->src[0])[0];
694 if (is_same_type_mov(src0) &&
695 (src0->regs[1]->flags & IR3_REG_IMMED)) {
696 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
697 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
698 } else {
699 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
700 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
701 }
702
703 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
704 addr = base_lo;
705
706 const_offset = nir_src_as_const_value(intr->src[1]);
707 if (const_offset) {
708 off += const_offset->u32[0];
709 } else {
710 /* For load_ubo_indirect, second src is indirect offset: */
711 src1 = ir3_get_src(ctx, &intr->src[1])[0];
712
713 /* and add offset to addr: */
714 addr = ir3_ADD_S(b, addr, 0, src1, 0);
715 }
716
717 /* if offset is to large to encode in the ldg, split it out: */
718 if ((off + (intr->num_components * 4)) > 1024) {
719 /* split out the minimal amount to improve the odds that
720 * cp can fit the immediate in the add.s instruction:
721 */
722 unsigned off2 = off + (intr->num_components * 4) - 1024;
723 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
724 off -= off2;
725 }
726
727 if (ptrsz == 2) {
728 struct ir3_instruction *carry;
729
730 /* handle 32b rollover, ie:
731 * if (addr < base_lo)
732 * base_hi++
733 */
734 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
735 carry->cat2.condition = IR3_COND_LT;
736 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
737
738 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
739 }
740
741 for (int i = 0; i < intr->num_components; i++) {
742 struct ir3_instruction *load =
743 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
744 load->cat6.type = TYPE_U32;
745 load->cat6.src_offset = off + i * 4; /* byte offset */
746 dst[i] = load;
747 }
748 }
749
750 /* src[] = { block_index } */
751 static void
752 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
753 struct ir3_instruction **dst)
754 {
755 /* SSBO size stored as a const starting at ssbo_sizes: */
756 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
757 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
758 ctx->so->const_layout.ssbo_size.off[blk_idx];
759
760 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
761
762 dst[0] = create_uniform(ctx->block, idx);
763 }
764
765 /* src[] = { offset }. const_index[] = { base } */
766 static void
767 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
768 struct ir3_instruction **dst)
769 {
770 struct ir3_block *b = ctx->block;
771 struct ir3_instruction *ldl, *offset;
772 unsigned base;
773
774 offset = ir3_get_src(ctx, &intr->src[0])[0];
775 base = nir_intrinsic_base(intr);
776
777 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
778 ldl->cat6.src_offset = base;
779 ldl->cat6.type = utype_dst(intr->dest);
780 ldl->regs[0]->wrmask = MASK(intr->num_components);
781
782 ldl->barrier_class = IR3_BARRIER_SHARED_R;
783 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
784
785 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
786 }
787
788 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
789 static void
790 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
791 {
792 struct ir3_block *b = ctx->block;
793 struct ir3_instruction *stl, *offset;
794 struct ir3_instruction * const *value;
795 unsigned base, wrmask;
796
797 value = ir3_get_src(ctx, &intr->src[0]);
798 offset = ir3_get_src(ctx, &intr->src[1])[0];
799
800 base = nir_intrinsic_base(intr);
801 wrmask = nir_intrinsic_write_mask(intr);
802
803 /* Combine groups of consecutive enabled channels in one write
804 * message. We use ffs to find the first enabled channel and then ffs on
805 * the bit-inverse, down-shifted writemask to determine the length of
806 * the block of enabled bits.
807 *
808 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
809 */
810 while (wrmask) {
811 unsigned first_component = ffs(wrmask) - 1;
812 unsigned length = ffs(~(wrmask >> first_component)) - 1;
813
814 stl = ir3_STL(b, offset, 0,
815 ir3_create_collect(ctx, &value[first_component], length), 0,
816 create_immed(b, length), 0);
817 stl->cat6.dst_offset = first_component + base;
818 stl->cat6.type = utype_src(intr->src[0]);
819 stl->barrier_class = IR3_BARRIER_SHARED_W;
820 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
821
822 array_insert(b, b->keeps, stl);
823
824 /* Clear the bits in the writemask that we just wrote, then try
825 * again to see if more channels are left.
826 */
827 wrmask &= (15 << (first_component + length));
828 }
829 }
830
831 /*
832 * CS shared variable atomic intrinsics
833 *
834 * All of the shared variable atomic memory operations read a value from
835 * memory, compute a new value using one of the operations below, write the
836 * new value to memory, and return the original value read.
837 *
838 * All operations take 2 sources except CompSwap that takes 3. These
839 * sources represent:
840 *
841 * 0: The offset into the shared variable storage region that the atomic
842 * operation will operate on.
843 * 1: The data parameter to the atomic function (i.e. the value to add
844 * in shared_atomic_add, etc).
845 * 2: For CompSwap only: the second data parameter.
846 */
847 static struct ir3_instruction *
848 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
849 {
850 struct ir3_block *b = ctx->block;
851 struct ir3_instruction *atomic, *src0, *src1;
852 type_t type = TYPE_U32;
853
854 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
855 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
856
857 switch (intr->intrinsic) {
858 case nir_intrinsic_shared_atomic_add:
859 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
860 break;
861 case nir_intrinsic_shared_atomic_imin:
862 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
863 type = TYPE_S32;
864 break;
865 case nir_intrinsic_shared_atomic_umin:
866 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
867 break;
868 case nir_intrinsic_shared_atomic_imax:
869 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
870 type = TYPE_S32;
871 break;
872 case nir_intrinsic_shared_atomic_umax:
873 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
874 break;
875 case nir_intrinsic_shared_atomic_and:
876 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
877 break;
878 case nir_intrinsic_shared_atomic_or:
879 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
880 break;
881 case nir_intrinsic_shared_atomic_xor:
882 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
883 break;
884 case nir_intrinsic_shared_atomic_exchange:
885 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
886 break;
887 case nir_intrinsic_shared_atomic_comp_swap:
888 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
889 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
890 ir3_get_src(ctx, &intr->src[2])[0],
891 src1,
892 }, 2);
893 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
894 break;
895 default:
896 unreachable("boo");
897 }
898
899 atomic->cat6.iim_val = 1;
900 atomic->cat6.d = 1;
901 atomic->cat6.type = type;
902 atomic->barrier_class = IR3_BARRIER_SHARED_W;
903 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
904
905 /* even if nothing consume the result, we can't DCE the instruction: */
906 array_insert(b, b->keeps, atomic);
907
908 return atomic;
909 }
910
911 /* TODO handle actual indirect/dynamic case.. which is going to be weird
912 * to handle with the image_mapping table..
913 */
914 static struct ir3_instruction *
915 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
916 {
917 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
918 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
919 struct ir3_instruction *texture, *sampler;
920
921 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
922 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
923
924 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
925 sampler,
926 texture,
927 }, 2);
928 }
929
930 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
931 static void
932 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
933 struct ir3_instruction **dst)
934 {
935 struct ir3_block *b = ctx->block;
936 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
937 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
938 struct ir3_instruction *sam;
939 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
940 struct ir3_instruction *coords[4];
941 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
942 type_t type = ir3_get_image_type(var);
943
944 /* hmm, this seems a bit odd, but it is what blob does and (at least
945 * a5xx) just faults on bogus addresses otherwise:
946 */
947 if (flags & IR3_INSTR_3D) {
948 flags &= ~IR3_INSTR_3D;
949 flags |= IR3_INSTR_A;
950 }
951
952 for (unsigned i = 0; i < ncoords; i++)
953 coords[i] = src0[i];
954
955 if (ncoords == 1)
956 coords[ncoords++] = create_immed(b, 0);
957
958 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
959 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
960
961 sam->barrier_class = IR3_BARRIER_IMAGE_R;
962 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
963
964 ir3_split_dest(b, dst, sam, 0, 4);
965 }
966
967 static void
968 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
969 struct ir3_instruction **dst)
970 {
971 struct ir3_block *b = ctx->block;
972 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
973 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
974 struct ir3_instruction *sam, *lod;
975 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
976
977 lod = create_immed(b, 0);
978 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
979 samp_tex, lod, NULL);
980
981 /* Array size actually ends up in .w rather than .z. This doesn't
982 * matter for miplevel 0, but for higher mips the value in z is
983 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
984 * returned, which means that we have to add 1 to it for arrays for
985 * a3xx.
986 *
987 * Note use a temporary dst and then copy, since the size of the dst
988 * array that is passed in is based on nir's understanding of the
989 * result size, not the hardware's
990 */
991 struct ir3_instruction *tmp[4];
992
993 ir3_split_dest(b, tmp, sam, 0, 4);
994
995 /* get_size instruction returns size in bytes instead of texels
996 * for imageBuffer, so we need to divide it by the pixel size
997 * of the image format.
998 *
999 * TODO: This is at least true on a5xx. Check other gens.
1000 */
1001 enum glsl_sampler_dim dim =
1002 glsl_get_sampler_dim(glsl_without_array(var->type));
1003 if (dim == GLSL_SAMPLER_DIM_BUF) {
1004 /* Since all the possible values the divisor can take are
1005 * power-of-two (4, 8, or 16), the division is implemented
1006 * as a shift-right.
1007 * During shader setup, the log2 of the image format's
1008 * bytes-per-pixel should have been emitted in 2nd slot of
1009 * image_dims. See ir3_shader::emit_image_dims().
1010 */
1011 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1012 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1013 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1014
1015 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1016 }
1017
1018 for (unsigned i = 0; i < ncoords; i++)
1019 dst[i] = tmp[i];
1020
1021 if (flags & IR3_INSTR_A) {
1022 if (ctx->compiler->levels_add_one) {
1023 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1024 } else {
1025 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1026 }
1027 }
1028 }
1029
1030 static void
1031 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1032 {
1033 struct ir3_block *b = ctx->block;
1034 struct ir3_instruction *barrier;
1035
1036 switch (intr->intrinsic) {
1037 case nir_intrinsic_barrier:
1038 barrier = ir3_BAR(b);
1039 barrier->cat7.g = true;
1040 barrier->cat7.l = true;
1041 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1042 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1043 break;
1044 case nir_intrinsic_memory_barrier:
1045 barrier = ir3_FENCE(b);
1046 barrier->cat7.g = true;
1047 barrier->cat7.r = true;
1048 barrier->cat7.w = true;
1049 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1050 IR3_BARRIER_BUFFER_W;
1051 barrier->barrier_conflict =
1052 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1053 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1054 break;
1055 case nir_intrinsic_memory_barrier_atomic_counter:
1056 case nir_intrinsic_memory_barrier_buffer:
1057 barrier = ir3_FENCE(b);
1058 barrier->cat7.g = true;
1059 barrier->cat7.r = true;
1060 barrier->cat7.w = true;
1061 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1062 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1063 IR3_BARRIER_BUFFER_W;
1064 break;
1065 case nir_intrinsic_memory_barrier_image:
1066 // TODO double check if this should have .g set
1067 barrier = ir3_FENCE(b);
1068 barrier->cat7.g = true;
1069 barrier->cat7.r = true;
1070 barrier->cat7.w = true;
1071 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1072 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1073 IR3_BARRIER_IMAGE_W;
1074 break;
1075 case nir_intrinsic_memory_barrier_shared:
1076 barrier = ir3_FENCE(b);
1077 barrier->cat7.g = true;
1078 barrier->cat7.l = true;
1079 barrier->cat7.r = true;
1080 barrier->cat7.w = true;
1081 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1082 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1083 IR3_BARRIER_SHARED_W;
1084 break;
1085 case nir_intrinsic_group_memory_barrier:
1086 barrier = ir3_FENCE(b);
1087 barrier->cat7.g = true;
1088 barrier->cat7.l = true;
1089 barrier->cat7.r = true;
1090 barrier->cat7.w = true;
1091 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1092 IR3_BARRIER_IMAGE_W |
1093 IR3_BARRIER_BUFFER_W;
1094 barrier->barrier_conflict =
1095 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1096 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1097 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1098 break;
1099 default:
1100 unreachable("boo");
1101 }
1102
1103 /* make sure barrier doesn't get DCE'd */
1104 array_insert(b, b->keeps, barrier);
1105 }
1106
1107 static void add_sysval_input_compmask(struct ir3_context *ctx,
1108 gl_system_value slot, unsigned compmask,
1109 struct ir3_instruction *instr)
1110 {
1111 struct ir3_shader_variant *so = ctx->so;
1112 unsigned r = regid(so->inputs_count, 0);
1113 unsigned n = so->inputs_count++;
1114
1115 so->inputs[n].sysval = true;
1116 so->inputs[n].slot = slot;
1117 so->inputs[n].compmask = compmask;
1118 so->inputs[n].regid = r;
1119 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1120 so->total_in++;
1121
1122 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1123 ctx->ir->inputs[r] = instr;
1124 }
1125
1126 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1127 struct ir3_instruction *instr)
1128 {
1129 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1130 }
1131
1132 static void
1133 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1134 {
1135 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1136 struct ir3_instruction **dst;
1137 struct ir3_instruction * const *src;
1138 struct ir3_block *b = ctx->block;
1139 nir_const_value *const_offset;
1140 int idx, comp;
1141
1142 if (info->has_dest) {
1143 unsigned n = nir_intrinsic_dest_components(intr);
1144 dst = ir3_get_dst(ctx, &intr->dest, n);
1145 } else {
1146 dst = NULL;
1147 }
1148
1149 switch (intr->intrinsic) {
1150 case nir_intrinsic_load_uniform:
1151 idx = nir_intrinsic_base(intr);
1152 const_offset = nir_src_as_const_value(intr->src[0]);
1153 if (const_offset) {
1154 idx += const_offset->u32[0];
1155 for (int i = 0; i < intr->num_components; i++) {
1156 dst[i] = create_uniform(b, idx + i);
1157 }
1158 } else {
1159 src = ir3_get_src(ctx, &intr->src[0]);
1160 for (int i = 0; i < intr->num_components; i++) {
1161 dst[i] = create_uniform_indirect(b, idx + i,
1162 ir3_get_addr(ctx, src[0], 1));
1163 }
1164 /* NOTE: if relative addressing is used, we set
1165 * constlen in the compiler (to worst-case value)
1166 * since we don't know in the assembler what the max
1167 * addr reg value can be:
1168 */
1169 ctx->so->constlen = ctx->s->num_uniforms;
1170 }
1171 break;
1172 case nir_intrinsic_load_ubo:
1173 emit_intrinsic_load_ubo(ctx, intr, dst);
1174 break;
1175 case nir_intrinsic_load_input:
1176 idx = nir_intrinsic_base(intr);
1177 comp = nir_intrinsic_component(intr);
1178 const_offset = nir_src_as_const_value(intr->src[0]);
1179 if (const_offset) {
1180 idx += const_offset->u32[0];
1181 for (int i = 0; i < intr->num_components; i++) {
1182 unsigned n = idx * 4 + i + comp;
1183 dst[i] = ctx->ir->inputs[n];
1184 }
1185 } else {
1186 src = ir3_get_src(ctx, &intr->src[0]);
1187 struct ir3_instruction *collect =
1188 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1189 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1190 for (int i = 0; i < intr->num_components; i++) {
1191 unsigned n = idx * 4 + i + comp;
1192 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1193 n, addr, collect);
1194 }
1195 }
1196 break;
1197 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1198 * pass and replaced by an ir3-specifc version that adds the
1199 * dword-offset in the last source.
1200 */
1201 case nir_intrinsic_load_ssbo_ir3:
1202 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1203 break;
1204 case nir_intrinsic_store_ssbo_ir3:
1205 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1206 !ctx->s->info.fs.early_fragment_tests)
1207 ctx->so->no_earlyz = true;
1208 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1209 break;
1210 case nir_intrinsic_get_buffer_size:
1211 emit_intrinsic_ssbo_size(ctx, intr, dst);
1212 break;
1213 case nir_intrinsic_ssbo_atomic_add_ir3:
1214 case nir_intrinsic_ssbo_atomic_imin_ir3:
1215 case nir_intrinsic_ssbo_atomic_umin_ir3:
1216 case nir_intrinsic_ssbo_atomic_imax_ir3:
1217 case nir_intrinsic_ssbo_atomic_umax_ir3:
1218 case nir_intrinsic_ssbo_atomic_and_ir3:
1219 case nir_intrinsic_ssbo_atomic_or_ir3:
1220 case nir_intrinsic_ssbo_atomic_xor_ir3:
1221 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1222 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1223 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1224 !ctx->s->info.fs.early_fragment_tests)
1225 ctx->so->no_earlyz = true;
1226 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1227 break;
1228 case nir_intrinsic_load_shared:
1229 emit_intrinsic_load_shared(ctx, intr, dst);
1230 break;
1231 case nir_intrinsic_store_shared:
1232 emit_intrinsic_store_shared(ctx, intr);
1233 break;
1234 case nir_intrinsic_shared_atomic_add:
1235 case nir_intrinsic_shared_atomic_imin:
1236 case nir_intrinsic_shared_atomic_umin:
1237 case nir_intrinsic_shared_atomic_imax:
1238 case nir_intrinsic_shared_atomic_umax:
1239 case nir_intrinsic_shared_atomic_and:
1240 case nir_intrinsic_shared_atomic_or:
1241 case nir_intrinsic_shared_atomic_xor:
1242 case nir_intrinsic_shared_atomic_exchange:
1243 case nir_intrinsic_shared_atomic_comp_swap:
1244 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1245 break;
1246 case nir_intrinsic_image_deref_load:
1247 emit_intrinsic_load_image(ctx, intr, dst);
1248 break;
1249 case nir_intrinsic_image_deref_store:
1250 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1251 !ctx->s->info.fs.early_fragment_tests)
1252 ctx->so->no_earlyz = true;
1253 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1254 break;
1255 case nir_intrinsic_image_deref_size:
1256 emit_intrinsic_image_size(ctx, intr, dst);
1257 break;
1258 case nir_intrinsic_image_deref_atomic_add:
1259 case nir_intrinsic_image_deref_atomic_min:
1260 case nir_intrinsic_image_deref_atomic_max:
1261 case nir_intrinsic_image_deref_atomic_and:
1262 case nir_intrinsic_image_deref_atomic_or:
1263 case nir_intrinsic_image_deref_atomic_xor:
1264 case nir_intrinsic_image_deref_atomic_exchange:
1265 case nir_intrinsic_image_deref_atomic_comp_swap:
1266 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1267 !ctx->s->info.fs.early_fragment_tests)
1268 ctx->so->no_earlyz = true;
1269 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1270 break;
1271 case nir_intrinsic_barrier:
1272 case nir_intrinsic_memory_barrier:
1273 case nir_intrinsic_group_memory_barrier:
1274 case nir_intrinsic_memory_barrier_atomic_counter:
1275 case nir_intrinsic_memory_barrier_buffer:
1276 case nir_intrinsic_memory_barrier_image:
1277 case nir_intrinsic_memory_barrier_shared:
1278 emit_intrinsic_barrier(ctx, intr);
1279 /* note that blk ptr no longer valid, make that obvious: */
1280 b = NULL;
1281 break;
1282 case nir_intrinsic_store_output:
1283 idx = nir_intrinsic_base(intr);
1284 comp = nir_intrinsic_component(intr);
1285 const_offset = nir_src_as_const_value(intr->src[1]);
1286 compile_assert(ctx, const_offset != NULL);
1287 idx += const_offset->u32[0];
1288
1289 src = ir3_get_src(ctx, &intr->src[0]);
1290 for (int i = 0; i < intr->num_components; i++) {
1291 unsigned n = idx * 4 + i + comp;
1292 ctx->ir->outputs[n] = src[i];
1293 }
1294 break;
1295 case nir_intrinsic_load_base_vertex:
1296 case nir_intrinsic_load_first_vertex:
1297 if (!ctx->basevertex) {
1298 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1299 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1300 }
1301 dst[0] = ctx->basevertex;
1302 break;
1303 case nir_intrinsic_load_vertex_id_zero_base:
1304 case nir_intrinsic_load_vertex_id:
1305 if (!ctx->vertex_id) {
1306 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1307 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1308 ctx->vertex_id = create_input(ctx, 0);
1309 add_sysval_input(ctx, sv, ctx->vertex_id);
1310 }
1311 dst[0] = ctx->vertex_id;
1312 break;
1313 case nir_intrinsic_load_instance_id:
1314 if (!ctx->instance_id) {
1315 ctx->instance_id = create_input(ctx, 0);
1316 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1317 ctx->instance_id);
1318 }
1319 dst[0] = ctx->instance_id;
1320 break;
1321 case nir_intrinsic_load_sample_id:
1322 case nir_intrinsic_load_sample_id_no_per_sample:
1323 if (!ctx->samp_id) {
1324 ctx->samp_id = create_input(ctx, 0);
1325 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1326 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1327 ctx->samp_id);
1328 }
1329 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1330 break;
1331 case nir_intrinsic_load_sample_mask_in:
1332 if (!ctx->samp_mask_in) {
1333 ctx->samp_mask_in = create_input(ctx, 0);
1334 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1335 ctx->samp_mask_in);
1336 }
1337 dst[0] = ctx->samp_mask_in;
1338 break;
1339 case nir_intrinsic_load_user_clip_plane:
1340 idx = nir_intrinsic_ucp_id(intr);
1341 for (int i = 0; i < intr->num_components; i++) {
1342 unsigned n = idx * 4 + i;
1343 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1344 }
1345 break;
1346 case nir_intrinsic_load_front_face:
1347 if (!ctx->frag_face) {
1348 ctx->so->frag_face = true;
1349 ctx->frag_face = create_input(ctx, 0);
1350 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1351 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1352 }
1353 /* for fragface, we get -1 for back and 0 for front. However this is
1354 * the inverse of what nir expects (where ~0 is true).
1355 */
1356 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1357 dst[0] = ir3_NOT_B(b, dst[0], 0);
1358 break;
1359 case nir_intrinsic_load_local_invocation_id:
1360 if (!ctx->local_invocation_id) {
1361 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1362 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1363 0x7, ctx->local_invocation_id);
1364 }
1365 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1366 break;
1367 case nir_intrinsic_load_work_group_id:
1368 if (!ctx->work_group_id) {
1369 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1370 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1371 0x7, ctx->work_group_id);
1372 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1373 }
1374 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1375 break;
1376 case nir_intrinsic_load_num_work_groups:
1377 for (int i = 0; i < intr->num_components; i++) {
1378 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1379 }
1380 break;
1381 case nir_intrinsic_load_local_group_size:
1382 for (int i = 0; i < intr->num_components; i++) {
1383 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1384 }
1385 break;
1386 case nir_intrinsic_discard_if:
1387 case nir_intrinsic_discard: {
1388 struct ir3_instruction *cond, *kill;
1389
1390 if (intr->intrinsic == nir_intrinsic_discard_if) {
1391 /* conditional discard: */
1392 src = ir3_get_src(ctx, &intr->src[0]);
1393 cond = ir3_b2n(b, src[0]);
1394 } else {
1395 /* unconditional discard: */
1396 cond = create_immed(b, 1);
1397 }
1398
1399 /* NOTE: only cmps.*.* can write p0.x: */
1400 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1401 cond->cat2.condition = IR3_COND_NE;
1402
1403 /* condition always goes in predicate register: */
1404 cond->regs[0]->num = regid(REG_P0, 0);
1405
1406 kill = ir3_KILL(b, cond, 0);
1407 array_insert(ctx->ir, ctx->ir->predicates, kill);
1408
1409 array_insert(b, b->keeps, kill);
1410 ctx->so->no_earlyz = true;
1411
1412 break;
1413 }
1414 default:
1415 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1416 nir_intrinsic_infos[intr->intrinsic].name);
1417 break;
1418 }
1419
1420 if (info->has_dest)
1421 ir3_put_dst(ctx, &intr->dest);
1422 }
1423
1424 static void
1425 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1426 {
1427 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1428 instr->def.num_components);
1429 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1430
1431 for (int i = 0; i < instr->def.num_components; i++)
1432 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1433 }
1434
1435 static void
1436 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1437 {
1438 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1439 undef->def.num_components);
1440 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1441
1442 /* backend doesn't want undefined instructions, so just plug
1443 * in 0.0..
1444 */
1445 for (int i = 0; i < undef->def.num_components; i++)
1446 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1447 }
1448
1449 /*
1450 * texture fetch/sample instructions:
1451 */
1452
1453 static void
1454 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1455 {
1456 unsigned coords, flags = 0;
1457
1458 /* note: would use tex->coord_components.. except txs.. also,
1459 * since array index goes after shadow ref, we don't want to
1460 * count it:
1461 */
1462 switch (tex->sampler_dim) {
1463 case GLSL_SAMPLER_DIM_1D:
1464 case GLSL_SAMPLER_DIM_BUF:
1465 coords = 1;
1466 break;
1467 case GLSL_SAMPLER_DIM_2D:
1468 case GLSL_SAMPLER_DIM_RECT:
1469 case GLSL_SAMPLER_DIM_EXTERNAL:
1470 case GLSL_SAMPLER_DIM_MS:
1471 coords = 2;
1472 break;
1473 case GLSL_SAMPLER_DIM_3D:
1474 case GLSL_SAMPLER_DIM_CUBE:
1475 coords = 3;
1476 flags |= IR3_INSTR_3D;
1477 break;
1478 default:
1479 unreachable("bad sampler_dim");
1480 }
1481
1482 if (tex->is_shadow && tex->op != nir_texop_lod)
1483 flags |= IR3_INSTR_S;
1484
1485 if (tex->is_array && tex->op != nir_texop_lod)
1486 flags |= IR3_INSTR_A;
1487
1488 *flagsp = flags;
1489 *coordsp = coords;
1490 }
1491
1492 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1493 * or immediate (in which case it will get lowered later to a non .s2en
1494 * version of the tex instruction which encode tex/samp as immediates:
1495 */
1496 static struct ir3_instruction *
1497 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1498 {
1499 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1500 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1501 struct ir3_instruction *texture, *sampler;
1502
1503 if (texture_idx >= 0) {
1504 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1505 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1506 } else {
1507 /* TODO what to do for dynamic case? I guess we only need the
1508 * max index for astc srgb workaround so maybe not a problem
1509 * to worry about if we don't enable indirect samplers for
1510 * a4xx?
1511 */
1512 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1513 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1514 }
1515
1516 if (sampler_idx >= 0) {
1517 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1518 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1519 } else {
1520 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1521 }
1522
1523 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1524 sampler,
1525 texture,
1526 }, 2);
1527 }
1528
1529 static void
1530 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1531 {
1532 struct ir3_block *b = ctx->block;
1533 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1534 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1535 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1536 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1537 unsigned i, coords, flags, ncomp;
1538 unsigned nsrc0 = 0, nsrc1 = 0;
1539 type_t type;
1540 opc_t opc = 0;
1541
1542 ncomp = nir_dest_num_components(tex->dest);
1543
1544 coord = off = ddx = ddy = NULL;
1545 lod = proj = compare = sample_index = NULL;
1546
1547 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1548
1549 for (unsigned i = 0; i < tex->num_srcs; i++) {
1550 switch (tex->src[i].src_type) {
1551 case nir_tex_src_coord:
1552 coord = ir3_get_src(ctx, &tex->src[i].src);
1553 break;
1554 case nir_tex_src_bias:
1555 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1556 has_bias = true;
1557 break;
1558 case nir_tex_src_lod:
1559 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1560 has_lod = true;
1561 break;
1562 case nir_tex_src_comparator: /* shadow comparator */
1563 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1564 break;
1565 case nir_tex_src_projector:
1566 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1567 has_proj = true;
1568 break;
1569 case nir_tex_src_offset:
1570 off = ir3_get_src(ctx, &tex->src[i].src);
1571 has_off = true;
1572 break;
1573 case nir_tex_src_ddx:
1574 ddx = ir3_get_src(ctx, &tex->src[i].src);
1575 break;
1576 case nir_tex_src_ddy:
1577 ddy = ir3_get_src(ctx, &tex->src[i].src);
1578 break;
1579 case nir_tex_src_ms_index:
1580 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1581 break;
1582 case nir_tex_src_texture_offset:
1583 case nir_tex_src_sampler_offset:
1584 /* handled in get_tex_samp_src() */
1585 break;
1586 default:
1587 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1588 tex->src[i].src_type);
1589 return;
1590 }
1591 }
1592
1593 switch (tex->op) {
1594 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1595 case nir_texop_txb: opc = OPC_SAMB; break;
1596 case nir_texop_txl: opc = OPC_SAML; break;
1597 case nir_texop_txd: opc = OPC_SAMGQ; break;
1598 case nir_texop_txf: opc = OPC_ISAML; break;
1599 case nir_texop_lod: opc = OPC_GETLOD; break;
1600 case nir_texop_tg4:
1601 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1602 * what blob does, seems gather is broken?), and a3xx did
1603 * not support it (but probably could also emulate).
1604 */
1605 switch (tex->component) {
1606 case 0: opc = OPC_GATHER4R; break;
1607 case 1: opc = OPC_GATHER4G; break;
1608 case 2: opc = OPC_GATHER4B; break;
1609 case 3: opc = OPC_GATHER4A; break;
1610 }
1611 break;
1612 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1613 case nir_texop_txs:
1614 case nir_texop_query_levels:
1615 case nir_texop_texture_samples:
1616 case nir_texop_samples_identical:
1617 case nir_texop_txf_ms_mcs:
1618 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1619 return;
1620 }
1621
1622 tex_info(tex, &flags, &coords);
1623
1624 /*
1625 * lay out the first argument in the proper order:
1626 * - actual coordinates first
1627 * - shadow reference
1628 * - array index
1629 * - projection w
1630 * - starting at offset 4, dpdx.xy, dpdy.xy
1631 *
1632 * bias/lod go into the second arg
1633 */
1634
1635 /* insert tex coords: */
1636 for (i = 0; i < coords; i++)
1637 src0[i] = coord[i];
1638
1639 nsrc0 = i;
1640
1641 /* scale up integer coords for TXF based on the LOD */
1642 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1643 assert(has_lod);
1644 for (i = 0; i < coords; i++)
1645 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1646 }
1647
1648 if (coords == 1) {
1649 /* hw doesn't do 1d, so we treat it as 2d with
1650 * height of 1, and patch up the y coord.
1651 */
1652 if (is_isam(opc)) {
1653 src0[nsrc0++] = create_immed(b, 0);
1654 } else {
1655 src0[nsrc0++] = create_immed(b, fui(0.5));
1656 }
1657 }
1658
1659 if (tex->is_shadow && tex->op != nir_texop_lod)
1660 src0[nsrc0++] = compare;
1661
1662 if (tex->is_array && tex->op != nir_texop_lod) {
1663 struct ir3_instruction *idx = coord[coords];
1664
1665 /* the array coord for cube arrays needs 0.5 added to it */
1666 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1667 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1668
1669 src0[nsrc0++] = idx;
1670 }
1671
1672 if (has_proj) {
1673 src0[nsrc0++] = proj;
1674 flags |= IR3_INSTR_P;
1675 }
1676
1677 /* pad to 4, then ddx/ddy: */
1678 if (tex->op == nir_texop_txd) {
1679 while (nsrc0 < 4)
1680 src0[nsrc0++] = create_immed(b, fui(0.0));
1681 for (i = 0; i < coords; i++)
1682 src0[nsrc0++] = ddx[i];
1683 if (coords < 2)
1684 src0[nsrc0++] = create_immed(b, fui(0.0));
1685 for (i = 0; i < coords; i++)
1686 src0[nsrc0++] = ddy[i];
1687 if (coords < 2)
1688 src0[nsrc0++] = create_immed(b, fui(0.0));
1689 }
1690
1691 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1692 * with scaled x coord according to requested sample:
1693 */
1694 if (tex->op == nir_texop_txf_ms) {
1695 if (ctx->compiler->txf_ms_with_isaml) {
1696 /* the samples are laid out in x dimension as
1697 * 0 1 2 3
1698 * x_ms = (x << ms) + sample_index;
1699 */
1700 struct ir3_instruction *ms;
1701 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1702
1703 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1704 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1705
1706 opc = OPC_ISAML;
1707 } else {
1708 src0[nsrc0++] = sample_index;
1709 }
1710 }
1711
1712 /*
1713 * second argument (if applicable):
1714 * - offsets
1715 * - lod
1716 * - bias
1717 */
1718 if (has_off | has_lod | has_bias) {
1719 if (has_off) {
1720 unsigned off_coords = coords;
1721 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1722 off_coords--;
1723 for (i = 0; i < off_coords; i++)
1724 src1[nsrc1++] = off[i];
1725 if (off_coords < 2)
1726 src1[nsrc1++] = create_immed(b, fui(0.0));
1727 flags |= IR3_INSTR_O;
1728 }
1729
1730 if (has_lod | has_bias)
1731 src1[nsrc1++] = lod;
1732 }
1733
1734 switch (tex->dest_type) {
1735 case nir_type_invalid:
1736 case nir_type_float:
1737 type = TYPE_F32;
1738 break;
1739 case nir_type_int:
1740 type = TYPE_S32;
1741 break;
1742 case nir_type_uint:
1743 case nir_type_bool:
1744 type = TYPE_U32;
1745 break;
1746 default:
1747 unreachable("bad dest_type");
1748 }
1749
1750 if (opc == OPC_GETLOD)
1751 type = TYPE_U32;
1752
1753 struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
1754 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1755 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1756
1757 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1758 samp_tex, col0, col1);
1759
1760 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1761 /* only need first 3 components: */
1762 sam->regs[0]->wrmask = 0x7;
1763 ir3_split_dest(b, dst, sam, 0, 3);
1764
1765 /* we need to sample the alpha separately with a non-ASTC
1766 * texture state:
1767 */
1768 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1769 samp_tex, col0, col1);
1770
1771 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1772
1773 /* fixup .w component: */
1774 ir3_split_dest(b, &dst[3], sam, 3, 1);
1775 } else {
1776 /* normal (non-workaround) case: */
1777 ir3_split_dest(b, dst, sam, 0, ncomp);
1778 }
1779
1780 /* GETLOD returns results in 4.8 fixed point */
1781 if (opc == OPC_GETLOD) {
1782 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1783
1784 compile_assert(ctx, tex->dest_type == nir_type_float);
1785 for (i = 0; i < 2; i++) {
1786 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1787 factor, 0);
1788 }
1789 }
1790
1791 ir3_put_dst(ctx, &tex->dest);
1792 }
1793
1794 static void
1795 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1796 {
1797 struct ir3_block *b = ctx->block;
1798 struct ir3_instruction **dst, *sam;
1799
1800 dst = ir3_get_dst(ctx, &tex->dest, 1);
1801
1802 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1803 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1804
1805 /* even though there is only one component, since it ends
1806 * up in .z rather than .x, we need a split_dest()
1807 */
1808 ir3_split_dest(b, dst, sam, 0, 3);
1809
1810 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1811 * the value in TEX_CONST_0 is zero-based.
1812 */
1813 if (ctx->compiler->levels_add_one)
1814 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1815
1816 ir3_put_dst(ctx, &tex->dest);
1817 }
1818
1819 static void
1820 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1821 {
1822 struct ir3_block *b = ctx->block;
1823 struct ir3_instruction **dst, *sam;
1824 struct ir3_instruction *lod;
1825 unsigned flags, coords;
1826
1827 tex_info(tex, &flags, &coords);
1828
1829 /* Actually we want the number of dimensions, not coordinates. This
1830 * distinction only matters for cubes.
1831 */
1832 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1833 coords = 2;
1834
1835 dst = ir3_get_dst(ctx, &tex->dest, 4);
1836
1837 compile_assert(ctx, tex->num_srcs == 1);
1838 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1839
1840 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
1841
1842 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1843 get_tex_samp_tex_src(ctx, tex), lod, NULL);
1844
1845 ir3_split_dest(b, dst, sam, 0, 4);
1846
1847 /* Array size actually ends up in .w rather than .z. This doesn't
1848 * matter for miplevel 0, but for higher mips the value in z is
1849 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1850 * returned, which means that we have to add 1 to it for arrays.
1851 */
1852 if (tex->is_array) {
1853 if (ctx->compiler->levels_add_one) {
1854 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1855 } else {
1856 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1857 }
1858 }
1859
1860 ir3_put_dst(ctx, &tex->dest);
1861 }
1862
1863 static void
1864 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
1865 {
1866 switch (jump->type) {
1867 case nir_jump_break:
1868 case nir_jump_continue:
1869 case nir_jump_return:
1870 /* I *think* we can simply just ignore this, and use the
1871 * successor block link to figure out where we need to
1872 * jump to for break/continue
1873 */
1874 break;
1875 default:
1876 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
1877 break;
1878 }
1879 }
1880
1881 static void
1882 emit_instr(struct ir3_context *ctx, nir_instr *instr)
1883 {
1884 switch (instr->type) {
1885 case nir_instr_type_alu:
1886 emit_alu(ctx, nir_instr_as_alu(instr));
1887 break;
1888 case nir_instr_type_deref:
1889 /* ignored, handled as part of the intrinsic they are src to */
1890 break;
1891 case nir_instr_type_intrinsic:
1892 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1893 break;
1894 case nir_instr_type_load_const:
1895 emit_load_const(ctx, nir_instr_as_load_const(instr));
1896 break;
1897 case nir_instr_type_ssa_undef:
1898 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1899 break;
1900 case nir_instr_type_tex: {
1901 nir_tex_instr *tex = nir_instr_as_tex(instr);
1902 /* couple tex instructions get special-cased:
1903 */
1904 switch (tex->op) {
1905 case nir_texop_txs:
1906 emit_tex_txs(ctx, tex);
1907 break;
1908 case nir_texop_query_levels:
1909 emit_tex_query_levels(ctx, tex);
1910 break;
1911 default:
1912 emit_tex(ctx, tex);
1913 break;
1914 }
1915 break;
1916 }
1917 case nir_instr_type_jump:
1918 emit_jump(ctx, nir_instr_as_jump(instr));
1919 break;
1920 case nir_instr_type_phi:
1921 /* we have converted phi webs to regs in NIR by now */
1922 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
1923 break;
1924 case nir_instr_type_call:
1925 case nir_instr_type_parallel_copy:
1926 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1927 break;
1928 }
1929 }
1930
1931 static struct ir3_block *
1932 get_block(struct ir3_context *ctx, const nir_block *nblock)
1933 {
1934 struct ir3_block *block;
1935 struct hash_entry *hentry;
1936 unsigned i;
1937
1938 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
1939 if (hentry)
1940 return hentry->data;
1941
1942 block = ir3_block_create(ctx->ir);
1943 block->nblock = nblock;
1944 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
1945
1946 block->predecessors_count = nblock->predecessors->entries;
1947 block->predecessors = ralloc_array_size(block,
1948 sizeof(block->predecessors[0]), block->predecessors_count);
1949 i = 0;
1950 set_foreach(nblock->predecessors, sentry) {
1951 block->predecessors[i++] = get_block(ctx, sentry->key);
1952 }
1953
1954 return block;
1955 }
1956
1957 static void
1958 emit_block(struct ir3_context *ctx, nir_block *nblock)
1959 {
1960 struct ir3_block *block = get_block(ctx, nblock);
1961
1962 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
1963 if (nblock->successors[i]) {
1964 block->successors[i] =
1965 get_block(ctx, nblock->successors[i]);
1966 }
1967 }
1968
1969 ctx->block = block;
1970 list_addtail(&block->node, &ctx->ir->block_list);
1971
1972 /* re-emit addr register in each block if needed: */
1973 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
1974 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
1975 ctx->addr_ht[i] = NULL;
1976 }
1977
1978 nir_foreach_instr(instr, nblock) {
1979 ctx->cur_instr = instr;
1980 emit_instr(ctx, instr);
1981 ctx->cur_instr = NULL;
1982 if (ctx->error)
1983 return;
1984 }
1985 }
1986
1987 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
1988
1989 static void
1990 emit_if(struct ir3_context *ctx, nir_if *nif)
1991 {
1992 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
1993
1994 ctx->block->condition =
1995 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
1996
1997 emit_cf_list(ctx, &nif->then_list);
1998 emit_cf_list(ctx, &nif->else_list);
1999 }
2000
2001 static void
2002 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2003 {
2004 emit_cf_list(ctx, &nloop->body);
2005 }
2006
2007 static void
2008 stack_push(struct ir3_context *ctx)
2009 {
2010 ctx->stack++;
2011 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2012 }
2013
2014 static void
2015 stack_pop(struct ir3_context *ctx)
2016 {
2017 compile_assert(ctx, ctx->stack > 0);
2018 ctx->stack--;
2019 }
2020
2021 static void
2022 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2023 {
2024 foreach_list_typed(nir_cf_node, node, node, list) {
2025 switch (node->type) {
2026 case nir_cf_node_block:
2027 emit_block(ctx, nir_cf_node_as_block(node));
2028 break;
2029 case nir_cf_node_if:
2030 stack_push(ctx);
2031 emit_if(ctx, nir_cf_node_as_if(node));
2032 stack_pop(ctx);
2033 break;
2034 case nir_cf_node_loop:
2035 stack_push(ctx);
2036 emit_loop(ctx, nir_cf_node_as_loop(node));
2037 stack_pop(ctx);
2038 break;
2039 case nir_cf_node_function:
2040 ir3_context_error(ctx, "TODO\n");
2041 break;
2042 }
2043 }
2044 }
2045
2046 /* emit stream-out code. At this point, the current block is the original
2047 * (nir) end block, and nir ensures that all flow control paths terminate
2048 * into the end block. We re-purpose the original end block to generate
2049 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2050 * block holding stream-out write instructions, followed by the new end
2051 * block:
2052 *
2053 * blockOrigEnd {
2054 * p0.x = (vtxcnt < maxvtxcnt)
2055 * // succs: blockStreamOut, blockNewEnd
2056 * }
2057 * blockStreamOut {
2058 * ... stream-out instructions ...
2059 * // succs: blockNewEnd
2060 * }
2061 * blockNewEnd {
2062 * }
2063 */
2064 static void
2065 emit_stream_out(struct ir3_context *ctx)
2066 {
2067 struct ir3_shader_variant *v = ctx->so;
2068 struct ir3 *ir = ctx->ir;
2069 struct ir3_stream_output_info *strmout =
2070 &ctx->so->shader->stream_output;
2071 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2072 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2073 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2074
2075 /* create vtxcnt input in input block at top of shader,
2076 * so that it is seen as live over the entire duration
2077 * of the shader:
2078 */
2079 vtxcnt = create_input(ctx, 0);
2080 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2081
2082 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2083
2084 /* at this point, we are at the original 'end' block,
2085 * re-purpose this block to stream-out condition, then
2086 * append stream-out block and new-end block
2087 */
2088 orig_end_block = ctx->block;
2089
2090 // TODO these blocks need to update predecessors..
2091 // maybe w/ store_global intrinsic, we could do this
2092 // stuff in nir->nir pass
2093
2094 stream_out_block = ir3_block_create(ir);
2095 list_addtail(&stream_out_block->node, &ir->block_list);
2096
2097 new_end_block = ir3_block_create(ir);
2098 list_addtail(&new_end_block->node, &ir->block_list);
2099
2100 orig_end_block->successors[0] = stream_out_block;
2101 orig_end_block->successors[1] = new_end_block;
2102 stream_out_block->successors[0] = new_end_block;
2103
2104 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2105 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2106 cond->regs[0]->num = regid(REG_P0, 0);
2107 cond->cat2.condition = IR3_COND_LT;
2108
2109 /* condition goes on previous block to the conditional,
2110 * since it is used to pick which of the two successor
2111 * paths to take:
2112 */
2113 orig_end_block->condition = cond;
2114
2115 /* switch to stream_out_block to generate the stream-out
2116 * instructions:
2117 */
2118 ctx->block = stream_out_block;
2119
2120 /* Calculate base addresses based on vtxcnt. Instructions
2121 * generated for bases not used in following loop will be
2122 * stripped out in the backend.
2123 */
2124 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2125 unsigned stride = strmout->stride[i];
2126 struct ir3_instruction *base, *off;
2127
2128 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2129
2130 /* 24-bit should be enough: */
2131 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2132 create_immed(ctx->block, stride * 4), 0);
2133
2134 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2135 }
2136
2137 /* Generate the per-output store instructions: */
2138 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2139 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2140 unsigned c = j + strmout->output[i].start_component;
2141 struct ir3_instruction *base, *out, *stg;
2142
2143 base = bases[strmout->output[i].output_buffer];
2144 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2145
2146 stg = ir3_STG(ctx->block, base, 0, out, 0,
2147 create_immed(ctx->block, 1), 0);
2148 stg->cat6.type = TYPE_U32;
2149 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2150
2151 array_insert(ctx->block, ctx->block->keeps, stg);
2152 }
2153 }
2154
2155 /* and finally switch to the new_end_block: */
2156 ctx->block = new_end_block;
2157 }
2158
2159 static void
2160 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2161 {
2162 nir_metadata_require(impl, nir_metadata_block_index);
2163
2164 compile_assert(ctx, ctx->stack == 0);
2165
2166 emit_cf_list(ctx, &impl->body);
2167 emit_block(ctx, impl->end_block);
2168
2169 compile_assert(ctx, ctx->stack == 0);
2170
2171 /* at this point, we should have a single empty block,
2172 * into which we emit the 'end' instruction.
2173 */
2174 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2175
2176 /* If stream-out (aka transform-feedback) enabled, emit the
2177 * stream-out instructions, followed by a new empty block (into
2178 * which the 'end' instruction lands).
2179 *
2180 * NOTE: it is done in this order, rather than inserting before
2181 * we emit end_block, because NIR guarantees that all blocks
2182 * flow into end_block, and that end_block has no successors.
2183 * So by re-purposing end_block as the first block of stream-
2184 * out, we guarantee that all exit paths flow into the stream-
2185 * out instructions.
2186 */
2187 if ((ctx->compiler->gpu_id < 500) &&
2188 (ctx->so->shader->stream_output.num_outputs > 0) &&
2189 !ctx->so->binning_pass) {
2190 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2191 emit_stream_out(ctx);
2192 }
2193
2194 ir3_END(ctx->block);
2195 }
2196
2197 static struct ir3_instruction *
2198 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2199 {
2200 struct ir3_block *block = ctx->block;
2201 struct ir3_instruction *instr;
2202
2203 if (!ctx->frag_coord) {
2204 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2205 /* defer add_sysval_input() until after all inputs created */
2206 }
2207
2208 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2209
2210 switch (comp) {
2211 case 0: /* .x */
2212 case 1: /* .y */
2213 /* for frag_coord, we get unsigned values.. we need
2214 * to subtract (integer) 8 and divide by 16 (right-
2215 * shift by 4) then convert to float:
2216 *
2217 * sub.s tmp, src, 8
2218 * shr.b tmp, tmp, 4
2219 * mov.u32f32 dst, tmp
2220 *
2221 */
2222 instr = ir3_SUB_S(block, instr, 0,
2223 create_immed(block, 8), 0);
2224 instr = ir3_SHR_B(block, instr, 0,
2225 create_immed(block, 4), 0);
2226 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2227
2228 return instr;
2229 case 2: /* .z */
2230 case 3: /* .w */
2231 default:
2232 /* seems that we can use these as-is: */
2233 return instr;
2234 }
2235 }
2236
2237 static void
2238 setup_input(struct ir3_context *ctx, nir_variable *in)
2239 {
2240 struct ir3_shader_variant *so = ctx->so;
2241 unsigned ncomp = glsl_get_components(in->type);
2242 unsigned n = in->data.driver_location;
2243 unsigned frac = in->data.location_frac;
2244 unsigned slot = in->data.location;
2245
2246 /* skip unread inputs, we could end up with (for example), unsplit
2247 * matrix/etc inputs in the case they are not read, so just silently
2248 * skip these.
2249 */
2250 if (ncomp > 4)
2251 return;
2252
2253 so->inputs[n].slot = slot;
2254 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2255 so->inputs_count = MAX2(so->inputs_count, n + 1);
2256 so->inputs[n].interpolate = in->data.interpolation;
2257
2258 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2259 for (int i = 0; i < ncomp; i++) {
2260 struct ir3_instruction *instr = NULL;
2261 unsigned idx = (n * 4) + i + frac;
2262
2263 if (slot == VARYING_SLOT_POS) {
2264 so->inputs[n].bary = false;
2265 so->frag_coord = true;
2266 instr = create_frag_coord(ctx, i);
2267 } else if (slot == VARYING_SLOT_PNTC) {
2268 /* see for example st_nir_fixup_varying_slots().. this is
2269 * maybe a bit mesa/st specific. But we need things to line
2270 * up for this in fdN_program:
2271 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2272 * if (emit->sprite_coord_enable & texmask) {
2273 * ...
2274 * }
2275 */
2276 so->inputs[n].slot = VARYING_SLOT_VAR8;
2277 so->inputs[n].bary = true;
2278 instr = create_frag_input(ctx, false);
2279 } else {
2280 bool use_ldlv = false;
2281
2282 /* detect the special case for front/back colors where
2283 * we need to do flat vs smooth shading depending on
2284 * rast state:
2285 */
2286 if (in->data.interpolation == INTERP_MODE_NONE) {
2287 switch (slot) {
2288 case VARYING_SLOT_COL0:
2289 case VARYING_SLOT_COL1:
2290 case VARYING_SLOT_BFC0:
2291 case VARYING_SLOT_BFC1:
2292 so->inputs[n].rasterflat = true;
2293 break;
2294 default:
2295 break;
2296 }
2297 }
2298
2299 if (ctx->compiler->flat_bypass) {
2300 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2301 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2302 use_ldlv = true;
2303 }
2304
2305 so->inputs[n].bary = true;
2306
2307 instr = create_frag_input(ctx, use_ldlv);
2308 }
2309
2310 compile_assert(ctx, idx < ctx->ir->ninputs);
2311
2312 ctx->ir->inputs[idx] = instr;
2313 }
2314 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2315 for (int i = 0; i < ncomp; i++) {
2316 unsigned idx = (n * 4) + i + frac;
2317 compile_assert(ctx, idx < ctx->ir->ninputs);
2318 ctx->ir->inputs[idx] = create_input(ctx, idx);
2319 }
2320 } else {
2321 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2322 }
2323
2324 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2325 so->total_in += ncomp;
2326 }
2327 }
2328
2329 static void
2330 setup_output(struct ir3_context *ctx, nir_variable *out)
2331 {
2332 struct ir3_shader_variant *so = ctx->so;
2333 unsigned ncomp = glsl_get_components(out->type);
2334 unsigned n = out->data.driver_location;
2335 unsigned frac = out->data.location_frac;
2336 unsigned slot = out->data.location;
2337 unsigned comp = 0;
2338
2339 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2340 switch (slot) {
2341 case FRAG_RESULT_DEPTH:
2342 comp = 2; /* tgsi will write to .z component */
2343 so->writes_pos = true;
2344 break;
2345 case FRAG_RESULT_COLOR:
2346 so->color0_mrt = 1;
2347 break;
2348 default:
2349 if (slot >= FRAG_RESULT_DATA0)
2350 break;
2351 ir3_context_error(ctx, "unknown FS output name: %s\n",
2352 gl_frag_result_name(slot));
2353 }
2354 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2355 switch (slot) {
2356 case VARYING_SLOT_POS:
2357 so->writes_pos = true;
2358 break;
2359 case VARYING_SLOT_PSIZ:
2360 so->writes_psize = true;
2361 break;
2362 case VARYING_SLOT_COL0:
2363 case VARYING_SLOT_COL1:
2364 case VARYING_SLOT_BFC0:
2365 case VARYING_SLOT_BFC1:
2366 case VARYING_SLOT_FOGC:
2367 case VARYING_SLOT_CLIP_DIST0:
2368 case VARYING_SLOT_CLIP_DIST1:
2369 case VARYING_SLOT_CLIP_VERTEX:
2370 break;
2371 default:
2372 if (slot >= VARYING_SLOT_VAR0)
2373 break;
2374 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2375 break;
2376 ir3_context_error(ctx, "unknown VS output name: %s\n",
2377 gl_varying_slot_name(slot));
2378 }
2379 } else {
2380 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2381 }
2382
2383 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2384
2385 so->outputs[n].slot = slot;
2386 so->outputs[n].regid = regid(n, comp);
2387 so->outputs_count = MAX2(so->outputs_count, n + 1);
2388
2389 for (int i = 0; i < ncomp; i++) {
2390 unsigned idx = (n * 4) + i + frac;
2391 compile_assert(ctx, idx < ctx->ir->noutputs);
2392 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2393 }
2394
2395 /* if varying packing doesn't happen, we could end up in a situation
2396 * with "holes" in the output, and since the per-generation code that
2397 * sets up varying linkage registers doesn't expect to have more than
2398 * one varying per vec4 slot, pad the holes.
2399 *
2400 * Note that this should probably generate a performance warning of
2401 * some sort.
2402 */
2403 for (int i = 0; i < frac; i++) {
2404 unsigned idx = (n * 4) + i;
2405 if (!ctx->ir->outputs[idx]) {
2406 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2407 }
2408 }
2409 }
2410
2411 static int
2412 max_drvloc(struct exec_list *vars)
2413 {
2414 int drvloc = -1;
2415 nir_foreach_variable(var, vars) {
2416 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2417 }
2418 return drvloc;
2419 }
2420
2421 static const unsigned max_sysvals[] = {
2422 [MESA_SHADER_FRAGMENT] = 24, // TODO
2423 [MESA_SHADER_VERTEX] = 16,
2424 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2425 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2426 };
2427
2428 static void
2429 emit_instructions(struct ir3_context *ctx)
2430 {
2431 unsigned ninputs, noutputs;
2432 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2433
2434 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2435 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2436
2437 /* we need to leave room for sysvals:
2438 */
2439 ninputs += max_sysvals[ctx->so->type];
2440
2441 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2442
2443 /* Create inputs in first block: */
2444 ctx->block = get_block(ctx, nir_start_block(fxn));
2445 ctx->in_block = ctx->block;
2446 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2447
2448 ninputs -= max_sysvals[ctx->so->type];
2449
2450 /* for fragment shader, the vcoord input register is used as the
2451 * base for bary.f varying fetch instrs:
2452 */
2453 struct ir3_instruction *vcoord = NULL;
2454 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2455 struct ir3_instruction *xy[2];
2456
2457 vcoord = create_input_compmask(ctx, 0, 0x3);
2458 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2459
2460 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2461 }
2462
2463 /* Setup inputs: */
2464 nir_foreach_variable(var, &ctx->s->inputs) {
2465 setup_input(ctx, var);
2466 }
2467
2468 /* Defer add_sysval_input() stuff until after setup_inputs(),
2469 * because sysvals need to be appended after varyings:
2470 */
2471 if (vcoord) {
2472 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2473 0x3, vcoord);
2474 }
2475
2476 if (ctx->frag_coord) {
2477 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2478 0xf, ctx->frag_coord);
2479 }
2480
2481 /* Setup outputs: */
2482 nir_foreach_variable(var, &ctx->s->outputs) {
2483 setup_output(ctx, var);
2484 }
2485
2486 /* Find # of samplers: */
2487 nir_foreach_variable(var, &ctx->s->uniforms) {
2488 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2489 /* just assume that we'll be reading from images.. if it
2490 * is write-only we don't have to count it, but not sure
2491 * if there is a good way to know?
2492 */
2493 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2494 }
2495
2496 /* Setup registers (which should only be arrays): */
2497 nir_foreach_register(reg, &ctx->s->registers) {
2498 ir3_declare_array(ctx, reg);
2499 }
2500
2501 /* NOTE: need to do something more clever when we support >1 fxn */
2502 nir_foreach_register(reg, &fxn->registers) {
2503 ir3_declare_array(ctx, reg);
2504 }
2505 /* And emit the body: */
2506 ctx->impl = fxn;
2507 emit_function(ctx, fxn);
2508 }
2509
2510 /* from NIR perspective, we actually have varying inputs. But the varying
2511 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2512 * only actual inputs are the sysvals.
2513 */
2514 static void
2515 fixup_frag_inputs(struct ir3_context *ctx)
2516 {
2517 struct ir3_shader_variant *so = ctx->so;
2518 struct ir3 *ir = ctx->ir;
2519 unsigned i = 0;
2520
2521 /* sysvals should appear at the end of the inputs, drop everything else: */
2522 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2523 i++;
2524
2525 /* at IR level, inputs are always blocks of 4 scalars: */
2526 i *= 4;
2527
2528 ir->inputs = &ir->inputs[i];
2529 ir->ninputs -= i;
2530 }
2531
2532 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2533 * need to assign the tex state indexes for these after we know the
2534 * max tex index.
2535 */
2536 static void
2537 fixup_astc_srgb(struct ir3_context *ctx)
2538 {
2539 struct ir3_shader_variant *so = ctx->so;
2540 /* indexed by original tex idx, value is newly assigned alpha sampler
2541 * state tex idx. Zero is invalid since there is at least one sampler
2542 * if we get here.
2543 */
2544 unsigned alt_tex_state[16] = {0};
2545 unsigned tex_idx = ctx->max_texture_index + 1;
2546 unsigned idx = 0;
2547
2548 so->astc_srgb.base = tex_idx;
2549
2550 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2551 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2552
2553 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2554
2555 if (alt_tex_state[sam->cat5.tex] == 0) {
2556 /* assign new alternate/alpha tex state slot: */
2557 alt_tex_state[sam->cat5.tex] = tex_idx++;
2558 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2559 so->astc_srgb.count++;
2560 }
2561
2562 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2563 }
2564 }
2565
2566 static void
2567 fixup_binning_pass(struct ir3_context *ctx)
2568 {
2569 struct ir3_shader_variant *so = ctx->so;
2570 struct ir3 *ir = ctx->ir;
2571 unsigned i, j;
2572
2573 for (i = 0, j = 0; i < so->outputs_count; i++) {
2574 unsigned slot = so->outputs[i].slot;
2575
2576 /* throw away everything but first position/psize */
2577 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2578 if (i != j) {
2579 so->outputs[j] = so->outputs[i];
2580 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2581 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2582 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2583 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2584 }
2585 j++;
2586 }
2587 }
2588 so->outputs_count = j;
2589 ir->noutputs = j * 4;
2590 }
2591
2592 int
2593 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2594 struct ir3_shader_variant *so)
2595 {
2596 struct ir3_context *ctx;
2597 struct ir3 *ir;
2598 struct ir3_instruction **inputs;
2599 unsigned i, actual_in, inloc;
2600 int ret = 0, max_bary;
2601
2602 assert(!so->ir);
2603
2604 ctx = ir3_context_init(compiler, so);
2605 if (!ctx) {
2606 DBG("INIT failed!");
2607 ret = -1;
2608 goto out;
2609 }
2610
2611 emit_instructions(ctx);
2612
2613 if (ctx->error) {
2614 DBG("EMIT failed!");
2615 ret = -1;
2616 goto out;
2617 }
2618
2619 ir = so->ir = ctx->ir;
2620
2621 /* keep track of the inputs from TGSI perspective.. */
2622 inputs = ir->inputs;
2623
2624 /* but fixup actual inputs for frag shader: */
2625 if (so->type == MESA_SHADER_FRAGMENT)
2626 fixup_frag_inputs(ctx);
2627
2628 /* at this point, for binning pass, throw away unneeded outputs: */
2629 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2630 fixup_binning_pass(ctx);
2631
2632 /* if we want half-precision outputs, mark the output registers
2633 * as half:
2634 */
2635 if (so->key.half_precision) {
2636 for (i = 0; i < ir->noutputs; i++) {
2637 struct ir3_instruction *out = ir->outputs[i];
2638
2639 if (!out)
2640 continue;
2641
2642 /* if frag shader writes z, that needs to be full precision: */
2643 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2644 continue;
2645
2646 out->regs[0]->flags |= IR3_REG_HALF;
2647 /* output could be a fanout (ie. texture fetch output)
2648 * in which case we need to propagate the half-reg flag
2649 * up to the definer so that RA sees it:
2650 */
2651 if (out->opc == OPC_META_FO) {
2652 out = out->regs[1]->instr;
2653 out->regs[0]->flags |= IR3_REG_HALF;
2654 }
2655
2656 if (out->opc == OPC_MOV) {
2657 out->cat1.dst_type = half_type(out->cat1.dst_type);
2658 }
2659 }
2660 }
2661
2662 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2663 printf("BEFORE CP:\n");
2664 ir3_print(ir);
2665 }
2666
2667 ir3_cp(ir, so);
2668
2669 /* at this point, for binning pass, throw away unneeded outputs:
2670 * Note that for a6xx and later, we do this after ir3_cp to ensure
2671 * that the uniform/constant layout for BS and VS matches, so that
2672 * we can re-use same VS_CONST state group.
2673 */
2674 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2675 fixup_binning_pass(ctx);
2676
2677 /* Insert mov if there's same instruction for each output.
2678 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2679 */
2680 for (int i = ir->noutputs - 1; i >= 0; i--) {
2681 if (!ir->outputs[i])
2682 continue;
2683 for (unsigned j = 0; j < i; j++) {
2684 if (ir->outputs[i] == ir->outputs[j]) {
2685 ir->outputs[i] =
2686 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2687 }
2688 }
2689 }
2690
2691 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2692 printf("BEFORE GROUPING:\n");
2693 ir3_print(ir);
2694 }
2695
2696 ir3_sched_add_deps(ir);
2697
2698 /* Group left/right neighbors, inserting mov's where needed to
2699 * solve conflicts:
2700 */
2701 ir3_group(ir);
2702
2703 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2704 printf("AFTER GROUPING:\n");
2705 ir3_print(ir);
2706 }
2707
2708 ir3_depth(ir);
2709
2710 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2711 printf("AFTER DEPTH:\n");
2712 ir3_print(ir);
2713 }
2714
2715 /* do Sethi–Ullman numbering before scheduling: */
2716 ir3_sun(ir);
2717
2718 ret = ir3_sched(ir);
2719 if (ret) {
2720 DBG("SCHED failed!");
2721 goto out;
2722 }
2723
2724 if (compiler->gpu_id >= 600) {
2725 ir3_a6xx_fixup_atomic_dests(ir, so);
2726 }
2727
2728 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2729 printf("AFTER SCHED:\n");
2730 ir3_print(ir);
2731 }
2732
2733 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2734 if (ret) {
2735 DBG("RA failed!");
2736 goto out;
2737 }
2738
2739 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2740 printf("AFTER RA:\n");
2741 ir3_print(ir);
2742 }
2743
2744 /* fixup input/outputs: */
2745 for (i = 0; i < so->outputs_count; i++) {
2746 /* sometimes we get outputs that don't write the .x coord, like:
2747 *
2748 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2749 *
2750 * Presumably the result of varying packing and then eliminating
2751 * some unneeded varyings? Just skip head to the first valid
2752 * component of the output.
2753 */
2754 for (unsigned j = 0; j < 4; j++) {
2755 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2756 if (instr) {
2757 so->outputs[i].regid = instr->regs[0]->num;
2758 break;
2759 }
2760 }
2761 }
2762
2763 /* Note that some or all channels of an input may be unused: */
2764 actual_in = 0;
2765 inloc = 0;
2766 for (i = 0; i < so->inputs_count; i++) {
2767 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
2768 so->inputs[i].ncomp = 0;
2769 so->inputs[i].inloc = inloc;
2770 for (j = 0; j < 4; j++) {
2771 struct ir3_instruction *in = inputs[(i*4) + j];
2772 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2773 compmask |= (1 << j);
2774 reg = in->regs[0]->num - j;
2775 actual_in++;
2776 so->inputs[i].ncomp++;
2777 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
2778 /* assign inloc: */
2779 assert(in->regs[1]->flags & IR3_REG_IMMED);
2780 in->regs[1]->iim_val = inloc + j;
2781 maxcomp = j + 1;
2782 }
2783 }
2784 }
2785 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
2786 so->varying_in++;
2787 so->inputs[i].compmask = (1 << maxcomp) - 1;
2788 inloc += maxcomp;
2789 } else if (!so->inputs[i].sysval) {
2790 so->inputs[i].compmask = compmask;
2791 }
2792 so->inputs[i].regid = reg;
2793 }
2794
2795 if (ctx->astc_srgb)
2796 fixup_astc_srgb(ctx);
2797
2798 /* We need to do legalize after (for frag shader's) the "bary.f"
2799 * offsets (inloc) have been assigned.
2800 */
2801 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
2802
2803 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2804 printf("AFTER LEGALIZE:\n");
2805 ir3_print(ir);
2806 }
2807
2808 so->branchstack = ctx->max_stack;
2809
2810 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2811 if (so->type == MESA_SHADER_VERTEX)
2812 so->total_in = actual_in;
2813 else
2814 so->total_in = max_bary + 1;
2815
2816 so->max_sun = ir->max_sun;
2817
2818 out:
2819 if (ret) {
2820 if (so->ir)
2821 ir3_destroy(so->ir);
2822 so->ir = NULL;
2823 }
2824 ir3_context_free(ctx);
2825
2826 return ret;
2827 }