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ir3: Fixup dual-source blending slot
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
111 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
112 * trust that we will only see and/or/xor on those 1-bit values, so we can
113 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
114 * 0.
115 */
116
117 /*
118 * alu/sfu instructions:
119 */
120
121 static struct ir3_instruction *
122 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
123 unsigned src_bitsize, nir_op op)
124 {
125 type_t src_type, dst_type;
126
127 switch (op) {
128 case nir_op_f2f32:
129 case nir_op_f2f16_rtne:
130 case nir_op_f2f16_rtz:
131 case nir_op_f2f16:
132 case nir_op_f2i32:
133 case nir_op_f2i16:
134 case nir_op_f2i8:
135 case nir_op_f2u32:
136 case nir_op_f2u16:
137 case nir_op_f2u8:
138 switch (src_bitsize) {
139 case 32:
140 src_type = TYPE_F32;
141 break;
142 case 16:
143 src_type = TYPE_F16;
144 break;
145 default:
146 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
147 }
148 break;
149
150 case nir_op_i2f32:
151 case nir_op_i2f16:
152 case nir_op_i2i32:
153 case nir_op_i2i16:
154 case nir_op_i2i8:
155 switch (src_bitsize) {
156 case 32:
157 src_type = TYPE_S32;
158 break;
159 case 16:
160 src_type = TYPE_S16;
161 break;
162 case 8:
163 src_type = TYPE_S8;
164 break;
165 default:
166 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
167 }
168 break;
169
170 case nir_op_u2f32:
171 case nir_op_u2f16:
172 case nir_op_u2u32:
173 case nir_op_u2u16:
174 case nir_op_u2u8:
175 switch (src_bitsize) {
176 case 32:
177 src_type = TYPE_U32;
178 break;
179 case 16:
180 src_type = TYPE_U16;
181 break;
182 case 8:
183 src_type = TYPE_U8;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_b2f16:
191 case nir_op_b2f32:
192 case nir_op_b2i8:
193 case nir_op_b2i16:
194 case nir_op_b2i32:
195 src_type = TYPE_U32;
196 break;
197
198 default:
199 ir3_context_error(ctx, "invalid conversion op: %u", op);
200 }
201
202 switch (op) {
203 case nir_op_f2f32:
204 case nir_op_i2f32:
205 case nir_op_u2f32:
206 case nir_op_b2f32:
207 dst_type = TYPE_F32;
208 break;
209
210 case nir_op_f2f16_rtne:
211 case nir_op_f2f16_rtz:
212 case nir_op_f2f16:
213 case nir_op_i2f16:
214 case nir_op_u2f16:
215 case nir_op_b2f16:
216 dst_type = TYPE_F16;
217 break;
218
219 case nir_op_f2i32:
220 case nir_op_i2i32:
221 case nir_op_b2i32:
222 dst_type = TYPE_S32;
223 break;
224
225 case nir_op_f2i16:
226 case nir_op_i2i16:
227 case nir_op_b2i16:
228 dst_type = TYPE_S16;
229 break;
230
231 case nir_op_f2i8:
232 case nir_op_i2i8:
233 case nir_op_b2i8:
234 dst_type = TYPE_S8;
235 break;
236
237 case nir_op_f2u32:
238 case nir_op_u2u32:
239 dst_type = TYPE_U32;
240 break;
241
242 case nir_op_f2u16:
243 case nir_op_u2u16:
244 dst_type = TYPE_U16;
245 break;
246
247 case nir_op_f2u8:
248 case nir_op_u2u8:
249 dst_type = TYPE_U8;
250 break;
251
252 default:
253 ir3_context_error(ctx, "invalid conversion op: %u", op);
254 }
255
256 if (src_type == dst_type)
257 return src;
258
259 struct ir3_instruction *cov =
260 ir3_COV(ctx->block, src, src_type, dst_type);
261
262 if (op == nir_op_f2f16_rtne)
263 cov->regs[0]->flags |= IR3_REG_EVEN;
264
265 return cov;
266 }
267
268 static void
269 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
270 {
271 const nir_op_info *info = &nir_op_infos[alu->op];
272 struct ir3_instruction **dst, *src[info->num_inputs];
273 unsigned bs[info->num_inputs]; /* bit size */
274 struct ir3_block *b = ctx->block;
275 unsigned dst_sz, wrmask;
276 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
277 TYPE_U16 : TYPE_U32;
278
279 if (alu->dest.dest.is_ssa) {
280 dst_sz = alu->dest.dest.ssa.num_components;
281 wrmask = (1 << dst_sz) - 1;
282 } else {
283 dst_sz = alu->dest.dest.reg.reg->num_components;
284 wrmask = alu->dest.write_mask;
285 }
286
287 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
288
289 /* Vectors are special in that they have non-scalarized writemasks,
290 * and just take the first swizzle channel for each argument in
291 * order into each writemask channel.
292 */
293 if ((alu->op == nir_op_vec2) ||
294 (alu->op == nir_op_vec3) ||
295 (alu->op == nir_op_vec4)) {
296
297 for (int i = 0; i < info->num_inputs; i++) {
298 nir_alu_src *asrc = &alu->src[i];
299
300 compile_assert(ctx, !asrc->abs);
301 compile_assert(ctx, !asrc->negate);
302
303 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
304 if (!src[i])
305 src[i] = create_immed_typed(ctx->block, 0, dst_type);
306 dst[i] = ir3_MOV(b, src[i], dst_type);
307 }
308
309 ir3_put_dst(ctx, &alu->dest.dest);
310 return;
311 }
312
313 /* We also get mov's with more than one component for mov's so
314 * handle those specially:
315 */
316 if (alu->op == nir_op_mov) {
317 nir_alu_src *asrc = &alu->src[0];
318 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
319
320 for (unsigned i = 0; i < dst_sz; i++) {
321 if (wrmask & (1 << i)) {
322 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
323 } else {
324 dst[i] = NULL;
325 }
326 }
327
328 ir3_put_dst(ctx, &alu->dest.dest);
329 return;
330 }
331
332 /* General case: We can just grab the one used channel per src. */
333 for (int i = 0; i < info->num_inputs; i++) {
334 unsigned chan = ffs(alu->dest.write_mask) - 1;
335 nir_alu_src *asrc = &alu->src[i];
336
337 compile_assert(ctx, !asrc->abs);
338 compile_assert(ctx, !asrc->negate);
339
340 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
341 bs[i] = nir_src_bit_size(asrc->src);
342
343 compile_assert(ctx, src[i]);
344 }
345
346 switch (alu->op) {
347 case nir_op_f2f32:
348 case nir_op_f2f16_rtne:
349 case nir_op_f2f16_rtz:
350 case nir_op_f2f16:
351 case nir_op_f2i32:
352 case nir_op_f2i16:
353 case nir_op_f2i8:
354 case nir_op_f2u32:
355 case nir_op_f2u16:
356 case nir_op_f2u8:
357 case nir_op_i2f32:
358 case nir_op_i2f16:
359 case nir_op_i2i32:
360 case nir_op_i2i16:
361 case nir_op_i2i8:
362 case nir_op_u2f32:
363 case nir_op_u2f16:
364 case nir_op_u2u32:
365 case nir_op_u2u16:
366 case nir_op_u2u8:
367 case nir_op_b2f16:
368 case nir_op_b2f32:
369 case nir_op_b2i8:
370 case nir_op_b2i16:
371 case nir_op_b2i32:
372 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
373 break;
374
375 case nir_op_fquantize2f16:
376 dst[0] = create_cov(ctx,
377 create_cov(ctx, src[0], 32, nir_op_f2f16),
378 16, nir_op_f2f32);
379 break;
380 case nir_op_f2b1:
381 dst[0] = ir3_CMPS_F(b,
382 src[0], 0,
383 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
384 dst[0]->cat2.condition = IR3_COND_NE;
385 break;
386
387 case nir_op_i2b1:
388 /* i2b1 will appear when translating from nir_load_ubo or
389 * nir_intrinsic_load_ssbo, where any non-zero value is true.
390 */
391 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
392 dst[0]->cat2.condition = IR3_COND_NE;
393 break;
394
395 case nir_op_b2b1:
396 /* b2b1 will appear when translating from
397 *
398 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
399 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
400 *
401 * A negate can turn those into a 1 or 0 for us.
402 */
403 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
404 break;
405
406 case nir_op_b2b32:
407 /* b2b32 will appear when converting our 1-bit bools to a store_shared
408 * argument.
409 *
410 * A negate can turn those into a ~0 for us.
411 */
412 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
413 break;
414
415 case nir_op_fneg:
416 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
417 break;
418 case nir_op_fabs:
419 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
420 break;
421 case nir_op_fmax:
422 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
423 break;
424 case nir_op_fmin:
425 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
426 break;
427 case nir_op_fsat:
428 /* if there is just a single use of the src, and it supports
429 * (sat) bit, we can just fold the (sat) flag back to the
430 * src instruction and create a mov. This is easier for cp
431 * to eliminate.
432 *
433 * TODO probably opc_cat==4 is ok too
434 */
435 if (alu->src[0].src.is_ssa &&
436 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
437 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
438 src[0]->flags |= IR3_INSTR_SAT;
439 dst[0] = ir3_MOV(b, src[0], dst_type);
440 } else {
441 /* otherwise generate a max.f that saturates.. blob does
442 * similar (generating a cat2 mov using max.f)
443 */
444 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
445 dst[0]->flags |= IR3_INSTR_SAT;
446 }
447 break;
448 case nir_op_fmul:
449 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
450 break;
451 case nir_op_fadd:
452 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
453 break;
454 case nir_op_fsub:
455 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
456 break;
457 case nir_op_ffma:
458 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
459 break;
460 case nir_op_fddx:
461 case nir_op_fddx_coarse:
462 dst[0] = ir3_DSX(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 case nir_op_fddx_fine:
466 dst[0] = ir3_DSXPP_1(b, src[0], 0);
467 dst[0]->cat5.type = TYPE_F32;
468 break;
469 case nir_op_fddy:
470 case nir_op_fddy_coarse:
471 dst[0] = ir3_DSY(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 break;
475 case nir_op_fddy_fine:
476 dst[0] = ir3_DSYPP_1(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 case nir_op_flt:
480 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
481 dst[0]->cat2.condition = IR3_COND_LT;
482 break;
483 case nir_op_fge:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_GE;
486 break;
487 case nir_op_feq:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne:
492 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
493 dst[0]->cat2.condition = IR3_COND_NE;
494 break;
495 case nir_op_fceil:
496 dst[0] = ir3_CEIL_F(b, src[0], 0);
497 break;
498 case nir_op_ffloor:
499 dst[0] = ir3_FLOOR_F(b, src[0], 0);
500 break;
501 case nir_op_ftrunc:
502 dst[0] = ir3_TRUNC_F(b, src[0], 0);
503 break;
504 case nir_op_fround_even:
505 dst[0] = ir3_RNDNE_F(b, src[0], 0);
506 break;
507 case nir_op_fsign:
508 dst[0] = ir3_SIGN_F(b, src[0], 0);
509 break;
510
511 case nir_op_fsin:
512 dst[0] = ir3_SIN(b, src[0], 0);
513 break;
514 case nir_op_fcos:
515 dst[0] = ir3_COS(b, src[0], 0);
516 break;
517 case nir_op_frsq:
518 dst[0] = ir3_RSQ(b, src[0], 0);
519 break;
520 case nir_op_frcp:
521 dst[0] = ir3_RCP(b, src[0], 0);
522 break;
523 case nir_op_flog2:
524 dst[0] = ir3_LOG2(b, src[0], 0);
525 break;
526 case nir_op_fexp2:
527 dst[0] = ir3_EXP2(b, src[0], 0);
528 break;
529 case nir_op_fsqrt:
530 dst[0] = ir3_SQRT(b, src[0], 0);
531 break;
532
533 case nir_op_iabs:
534 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
535 break;
536 case nir_op_iadd:
537 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_iand:
540 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imax:
543 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umax:
546 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_imin:
549 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_umin:
552 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umul_low:
555 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imadsh_mix16:
558 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
559 break;
560 case nir_op_imad24_ir3:
561 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
562 break;
563 case nir_op_imul24:
564 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_ineg:
567 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
568 break;
569 case nir_op_inot:
570 if (bs[0] == 1) {
571 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
572 } else {
573 dst[0] = ir3_NOT_B(b, src[0], 0);
574 }
575 break;
576 case nir_op_ior:
577 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishl:
580 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ishr:
583 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_isub:
586 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ixor:
589 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ushr:
592 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ilt:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_LT;
597 break;
598 case nir_op_ige:
599 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
600 dst[0]->cat2.condition = IR3_COND_GE;
601 break;
602 case nir_op_ieq:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine:
607 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
608 dst[0]->cat2.condition = IR3_COND_NE;
609 break;
610 case nir_op_ult:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_LT;
613 break;
614 case nir_op_uge:
615 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
616 dst[0]->cat2.condition = IR3_COND_GE;
617 break;
618
619 case nir_op_bcsel: {
620 struct ir3_instruction *cond = src[0];
621
622 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
623 * we can ignore that and use original cond, since the nonzero-ness of
624 * cond stays the same.
625 */
626 if (cond->opc == OPC_ABSNEG_S &&
627 cond->flags == 0 &&
628 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
629 cond = cond->regs[1]->instr;
630 }
631
632 compile_assert(ctx, bs[1] == bs[2]);
633 /* The condition's size has to match the other two arguments' size, so
634 * convert down if necessary.
635 */
636 if (bs[1] == 16) {
637 struct hash_entry *prev_entry =
638 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
639 if (prev_entry) {
640 cond = prev_entry->data;
641 } else {
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
644 }
645 }
646
647 if (bs[1] != 16)
648 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
649 else
650 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
651 break;
652 }
653 case nir_op_bit_count: {
654 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
655 // double check on earlier gen's. Once half-precision support is
656 // in place, this should probably move to a NIR lowering pass:
657 struct ir3_instruction *hi, *lo;
658
659 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
660 TYPE_U32, TYPE_U16);
661 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
662
663 hi = ir3_CBITS_B(b, hi, 0);
664 lo = ir3_CBITS_B(b, lo, 0);
665
666 // TODO maybe the builders should default to making dst half-precision
667 // if the src's were half precision, to make this less awkward.. otoh
668 // we should probably just do this lowering in NIR.
669 hi->regs[0]->flags |= IR3_REG_HALF;
670 lo->regs[0]->flags |= IR3_REG_HALF;
671
672 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
673 dst[0]->regs[0]->flags |= IR3_REG_HALF;
674 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
675 break;
676 }
677 case nir_op_ifind_msb: {
678 struct ir3_instruction *cmp;
679 dst[0] = ir3_CLZ_S(b, src[0], 0);
680 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
681 cmp->cat2.condition = IR3_COND_GE;
682 dst[0] = ir3_SEL_B32(b,
683 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
684 cmp, 0, dst[0], 0);
685 break;
686 }
687 case nir_op_ufind_msb:
688 dst[0] = ir3_CLZ_B(b, src[0], 0);
689 dst[0] = ir3_SEL_B32(b,
690 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
691 src[0], 0, dst[0], 0);
692 break;
693 case nir_op_find_lsb:
694 dst[0] = ir3_BFREV_B(b, src[0], 0);
695 dst[0] = ir3_CLZ_B(b, dst[0], 0);
696 break;
697 case nir_op_bitfield_reverse:
698 dst[0] = ir3_BFREV_B(b, src[0], 0);
699 break;
700
701 default:
702 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
703 nir_op_infos[alu->op].name);
704 break;
705 }
706
707 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
708 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
709 alu->op == nir_op_b2b32);
710 assert(dst_sz == 1);
711 } else {
712 /* 1-bit values stored in 32-bit registers are only valid for certain
713 * ALU ops.
714 */
715 switch (alu->op) {
716 case nir_op_iand:
717 case nir_op_ior:
718 case nir_op_ixor:
719 case nir_op_inot:
720 case nir_op_bcsel:
721 break;
722 default:
723 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
724 }
725 }
726
727 ir3_put_dst(ctx, &alu->dest.dest);
728 }
729
730 static void
731 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
732 struct ir3_instruction **dst)
733 {
734 struct ir3_block *b = ctx->block;
735
736 unsigned ncomp = intr->num_components;
737 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
738 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
739 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
740 ldc->regs[0]->wrmask = MASK(ncomp);
741 ldc->cat6.iim_val = ncomp;
742 ldc->cat6.d = nir_intrinsic_base(intr);
743 ldc->cat6.type = TYPE_U32;
744
745 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
746 if (bindless) {
747 ldc->flags |= IR3_INSTR_B;
748 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
749 ctx->so->bindless_ubo = true;
750 }
751
752 ir3_split_dest(b, dst, ldc, 0, ncomp);
753 }
754
755
756 /* handles direct/indirect UBO reads: */
757 static void
758 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
759 struct ir3_instruction **dst)
760 {
761 struct ir3_block *b = ctx->block;
762 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
763 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
764 unsigned ubo = regid(const_state->offsets.ubo, 0);
765 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
766
767 int off = 0;
768
769 /* First src is ubo index, which could either be an immed or not: */
770 src0 = ir3_get_src(ctx, &intr->src[0])[0];
771 if (is_same_type_mov(src0) &&
772 (src0->regs[1]->flags & IR3_REG_IMMED)) {
773 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
774 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
775 } else {
776 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
777 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
778
779 /* NOTE: since relative addressing is used, make sure constlen is
780 * at least big enough to cover all the UBO addresses, since the
781 * assembler won't know what the max address reg is.
782 */
783 ctx->so->constlen = MAX2(ctx->so->constlen,
784 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
785 }
786
787 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
788 addr = base_lo;
789
790 if (nir_src_is_const(intr->src[1])) {
791 off += nir_src_as_uint(intr->src[1]);
792 } else {
793 /* For load_ubo_indirect, second src is indirect offset: */
794 src1 = ir3_get_src(ctx, &intr->src[1])[0];
795
796 /* and add offset to addr: */
797 addr = ir3_ADD_S(b, addr, 0, src1, 0);
798 }
799
800 /* if offset is to large to encode in the ldg, split it out: */
801 if ((off + (intr->num_components * 4)) > 1024) {
802 /* split out the minimal amount to improve the odds that
803 * cp can fit the immediate in the add.s instruction:
804 */
805 unsigned off2 = off + (intr->num_components * 4) - 1024;
806 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
807 off -= off2;
808 }
809
810 if (ptrsz == 2) {
811 struct ir3_instruction *carry;
812
813 /* handle 32b rollover, ie:
814 * if (addr < base_lo)
815 * base_hi++
816 */
817 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
818 carry->cat2.condition = IR3_COND_LT;
819 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
820
821 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
822 }
823
824 for (int i = 0; i < intr->num_components; i++) {
825 struct ir3_instruction *load =
826 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
827 create_immed(b, off + i * 4), 0);
828 load->cat6.type = TYPE_U32;
829 dst[i] = load;
830 }
831 }
832
833 /* src[] = { block_index } */
834 static void
835 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
836 struct ir3_instruction **dst)
837 {
838 /* SSBO size stored as a const starting at ssbo_sizes: */
839 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
840 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
841 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
842 const_state->ssbo_size.off[blk_idx];
843
844 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
845
846 dst[0] = create_uniform(ctx->block, idx);
847 }
848
849 /* src[] = { offset }. const_index[] = { base } */
850 static void
851 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
852 struct ir3_instruction **dst)
853 {
854 struct ir3_block *b = ctx->block;
855 struct ir3_instruction *ldl, *offset;
856 unsigned base;
857
858 offset = ir3_get_src(ctx, &intr->src[0])[0];
859 base = nir_intrinsic_base(intr);
860
861 ldl = ir3_LDL(b, offset, 0,
862 create_immed(b, intr->num_components), 0,
863 create_immed(b, base), 0);
864
865 ldl->cat6.type = utype_dst(intr->dest);
866 ldl->regs[0]->wrmask = MASK(intr->num_components);
867
868 ldl->barrier_class = IR3_BARRIER_SHARED_R;
869 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
870
871 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
872 }
873
874 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
875 static void
876 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
877 {
878 struct ir3_block *b = ctx->block;
879 struct ir3_instruction *stl, *offset;
880 struct ir3_instruction * const *value;
881 unsigned base, wrmask, ncomp;
882
883 value = ir3_get_src(ctx, &intr->src[0]);
884 offset = ir3_get_src(ctx, &intr->src[1])[0];
885
886 base = nir_intrinsic_base(intr);
887 wrmask = nir_intrinsic_write_mask(intr);
888 ncomp = ffs(~wrmask) - 1;
889
890 assert(wrmask == BITFIELD_MASK(intr->num_components));
891
892 stl = ir3_STL(b, offset, 0,
893 ir3_create_collect(ctx, value, ncomp), 0,
894 create_immed(b, ncomp), 0);
895 stl->cat6.dst_offset = base;
896 stl->cat6.type = utype_src(intr->src[0]);
897 stl->barrier_class = IR3_BARRIER_SHARED_W;
898 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
899
900 array_insert(b, b->keeps, stl);
901 }
902
903 /* src[] = { offset }. const_index[] = { base } */
904 static void
905 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
906 struct ir3_instruction **dst)
907 {
908 struct ir3_block *b = ctx->block;
909 struct ir3_instruction *load, *offset;
910 unsigned base;
911
912 offset = ir3_get_src(ctx, &intr->src[0])[0];
913 base = nir_intrinsic_base(intr);
914
915 load = ir3_LDLW(b, offset, 0,
916 create_immed(b, intr->num_components), 0,
917 create_immed(b, base), 0);
918
919 load->cat6.type = utype_dst(intr->dest);
920 load->regs[0]->wrmask = MASK(intr->num_components);
921
922 load->barrier_class = IR3_BARRIER_SHARED_R;
923 load->barrier_conflict = IR3_BARRIER_SHARED_W;
924
925 ir3_split_dest(b, dst, load, 0, intr->num_components);
926 }
927
928 /* src[] = { value, offset }. const_index[] = { base } */
929 static void
930 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
931 {
932 struct ir3_block *b = ctx->block;
933 struct ir3_instruction *store, *offset;
934 struct ir3_instruction * const *value;
935
936 value = ir3_get_src(ctx, &intr->src[0]);
937 offset = ir3_get_src(ctx, &intr->src[1])[0];
938
939 store = ir3_STLW(b, offset, 0,
940 ir3_create_collect(ctx, value, intr->num_components), 0,
941 create_immed(b, intr->num_components), 0);
942
943 store->cat6.dst_offset = nir_intrinsic_base(intr);
944 store->cat6.type = utype_src(intr->src[0]);
945 store->barrier_class = IR3_BARRIER_SHARED_W;
946 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
947
948 array_insert(b, b->keeps, store);
949 }
950
951 /*
952 * CS shared variable atomic intrinsics
953 *
954 * All of the shared variable atomic memory operations read a value from
955 * memory, compute a new value using one of the operations below, write the
956 * new value to memory, and return the original value read.
957 *
958 * All operations take 2 sources except CompSwap that takes 3. These
959 * sources represent:
960 *
961 * 0: The offset into the shared variable storage region that the atomic
962 * operation will operate on.
963 * 1: The data parameter to the atomic function (i.e. the value to add
964 * in shared_atomic_add, etc).
965 * 2: For CompSwap only: the second data parameter.
966 */
967 static struct ir3_instruction *
968 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
969 {
970 struct ir3_block *b = ctx->block;
971 struct ir3_instruction *atomic, *src0, *src1;
972 type_t type = TYPE_U32;
973
974 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
975 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
976
977 switch (intr->intrinsic) {
978 case nir_intrinsic_shared_atomic_add:
979 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
980 break;
981 case nir_intrinsic_shared_atomic_imin:
982 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
983 type = TYPE_S32;
984 break;
985 case nir_intrinsic_shared_atomic_umin:
986 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
987 break;
988 case nir_intrinsic_shared_atomic_imax:
989 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
990 type = TYPE_S32;
991 break;
992 case nir_intrinsic_shared_atomic_umax:
993 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
994 break;
995 case nir_intrinsic_shared_atomic_and:
996 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
997 break;
998 case nir_intrinsic_shared_atomic_or:
999 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1000 break;
1001 case nir_intrinsic_shared_atomic_xor:
1002 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1003 break;
1004 case nir_intrinsic_shared_atomic_exchange:
1005 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_comp_swap:
1008 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1009 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1010 ir3_get_src(ctx, &intr->src[2])[0],
1011 src1,
1012 }, 2);
1013 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1014 break;
1015 default:
1016 unreachable("boo");
1017 }
1018
1019 atomic->cat6.iim_val = 1;
1020 atomic->cat6.d = 1;
1021 atomic->cat6.type = type;
1022 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1023 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1024
1025 /* even if nothing consume the result, we can't DCE the instruction: */
1026 array_insert(b, b->keeps, atomic);
1027
1028 return atomic;
1029 }
1030
1031 struct tex_src_info {
1032 /* For prefetch */
1033 unsigned tex_base, samp_base, tex_idx, samp_idx;
1034 /* For normal tex instructions */
1035 unsigned base, combined_idx, a1_val, flags;
1036 struct ir3_instruction *samp_tex;
1037 };
1038
1039 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1040 * to handle with the image_mapping table..
1041 */
1042 static struct tex_src_info
1043 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1044 {
1045 struct ir3_block *b = ctx->block;
1046 struct tex_src_info info = { 0 };
1047 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1048 ctx->so->bindless_tex = true;
1049
1050 if (bindless_tex) {
1051 /* Bindless case */
1052 info.flags |= IR3_INSTR_B;
1053
1054 /* Gather information required to determine which encoding to
1055 * choose as well as for prefetch.
1056 */
1057 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1058 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1059 if (tex_const)
1060 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1061 info.samp_idx = 0;
1062
1063 /* Choose encoding. */
1064 if (tex_const && info.tex_idx < 256) {
1065 if (info.tex_idx < 16) {
1066 /* Everything fits within the instruction */
1067 info.base = info.tex_base;
1068 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1069 } else {
1070 info.base = info.tex_base;
1071 info.a1_val = info.tex_idx << 3;
1072 info.combined_idx = 0;
1073 info.flags |= IR3_INSTR_A1EN;
1074 }
1075 info.samp_tex = NULL;
1076 } else {
1077 info.flags |= IR3_INSTR_S2EN;
1078 info.base = info.tex_base;
1079
1080 /* Note: the indirect source is now a vec2 instead of hvec2 */
1081 struct ir3_instruction *texture, *sampler;
1082
1083 texture = ir3_get_src(ctx, &intr->src[0])[0];
1084 sampler = create_immed(b, 0);
1085 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1086 texture,
1087 sampler,
1088 }, 2);
1089 }
1090 } else {
1091 info.flags |= IR3_INSTR_S2EN;
1092 unsigned slot = nir_src_as_uint(intr->src[0]);
1093 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1094 struct ir3_instruction *texture, *sampler;
1095
1096 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1097 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1098
1099 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1100 sampler,
1101 texture,
1102 }, 2);
1103 }
1104
1105 return info;
1106 }
1107
1108 static struct ir3_instruction *
1109 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1110 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1111 struct ir3_instruction *src1)
1112 {
1113 struct ir3_instruction *sam, *addr;
1114 if (info.flags & IR3_INSTR_A1EN) {
1115 addr = ir3_get_addr1(ctx, info.a1_val);
1116 }
1117 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1118 info.samp_tex, src0, src1);
1119 if (info.flags & IR3_INSTR_A1EN) {
1120 ir3_instr_set_address(sam, addr);
1121 }
1122 if (info.flags & IR3_INSTR_B) {
1123 sam->cat5.tex_base = info.base;
1124 sam->cat5.samp = info.combined_idx;
1125 }
1126 return sam;
1127 }
1128
1129 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1130 static void
1131 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1132 struct ir3_instruction **dst)
1133 {
1134 struct ir3_block *b = ctx->block;
1135 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1136 struct ir3_instruction *sam;
1137 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1138 struct ir3_instruction *coords[4];
1139 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1140 type_t type = ir3_get_type_for_image_intrinsic(intr);
1141
1142 /* hmm, this seems a bit odd, but it is what blob does and (at least
1143 * a5xx) just faults on bogus addresses otherwise:
1144 */
1145 if (flags & IR3_INSTR_3D) {
1146 flags &= ~IR3_INSTR_3D;
1147 flags |= IR3_INSTR_A;
1148 }
1149 info.flags |= flags;
1150
1151 for (unsigned i = 0; i < ncoords; i++)
1152 coords[i] = src0[i];
1153
1154 if (ncoords == 1)
1155 coords[ncoords++] = create_immed(b, 0);
1156
1157 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1158 ir3_create_collect(ctx, coords, ncoords), NULL);
1159
1160 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1161 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1162
1163 ir3_split_dest(b, dst, sam, 0, 4);
1164 }
1165
1166 static void
1167 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1168 struct ir3_instruction **dst)
1169 {
1170 struct ir3_block *b = ctx->block;
1171 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1172 struct ir3_instruction *sam, *lod;
1173 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1174 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1175 TYPE_U16 : TYPE_U32;
1176
1177 info.flags |= flags;
1178 lod = create_immed(b, 0);
1179 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1180
1181 /* Array size actually ends up in .w rather than .z. This doesn't
1182 * matter for miplevel 0, but for higher mips the value in z is
1183 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1184 * returned, which means that we have to add 1 to it for arrays for
1185 * a3xx.
1186 *
1187 * Note use a temporary dst and then copy, since the size of the dst
1188 * array that is passed in is based on nir's understanding of the
1189 * result size, not the hardware's
1190 */
1191 struct ir3_instruction *tmp[4];
1192
1193 ir3_split_dest(b, tmp, sam, 0, 4);
1194
1195 /* get_size instruction returns size in bytes instead of texels
1196 * for imageBuffer, so we need to divide it by the pixel size
1197 * of the image format.
1198 *
1199 * TODO: This is at least true on a5xx. Check other gens.
1200 */
1201 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1202 /* Since all the possible values the divisor can take are
1203 * power-of-two (4, 8, or 16), the division is implemented
1204 * as a shift-right.
1205 * During shader setup, the log2 of the image format's
1206 * bytes-per-pixel should have been emitted in 2nd slot of
1207 * image_dims. See ir3_shader::emit_image_dims().
1208 */
1209 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1210 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1211 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1212 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1213
1214 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1215 }
1216
1217 for (unsigned i = 0; i < ncoords; i++)
1218 dst[i] = tmp[i];
1219
1220 if (flags & IR3_INSTR_A) {
1221 if (ctx->compiler->levels_add_one) {
1222 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1223 } else {
1224 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1225 }
1226 }
1227 }
1228
1229 static void
1230 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1231 {
1232 struct ir3_block *b = ctx->block;
1233 struct ir3_instruction *barrier;
1234
1235 switch (intr->intrinsic) {
1236 case nir_intrinsic_control_barrier:
1237 barrier = ir3_BAR(b);
1238 barrier->cat7.g = true;
1239 barrier->cat7.l = true;
1240 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1241 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1242 break;
1243 case nir_intrinsic_memory_barrier:
1244 barrier = ir3_FENCE(b);
1245 barrier->cat7.g = true;
1246 barrier->cat7.r = true;
1247 barrier->cat7.w = true;
1248 barrier->cat7.l = true;
1249 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1250 IR3_BARRIER_BUFFER_W;
1251 barrier->barrier_conflict =
1252 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1253 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1254 break;
1255 case nir_intrinsic_memory_barrier_buffer:
1256 barrier = ir3_FENCE(b);
1257 barrier->cat7.g = true;
1258 barrier->cat7.r = true;
1259 barrier->cat7.w = true;
1260 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1261 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1262 IR3_BARRIER_BUFFER_W;
1263 break;
1264 case nir_intrinsic_memory_barrier_image:
1265 // TODO double check if this should have .g set
1266 barrier = ir3_FENCE(b);
1267 barrier->cat7.g = true;
1268 barrier->cat7.r = true;
1269 barrier->cat7.w = true;
1270 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1271 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1272 IR3_BARRIER_IMAGE_W;
1273 break;
1274 case nir_intrinsic_memory_barrier_shared:
1275 barrier = ir3_FENCE(b);
1276 barrier->cat7.g = true;
1277 barrier->cat7.l = true;
1278 barrier->cat7.r = true;
1279 barrier->cat7.w = true;
1280 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1281 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1282 IR3_BARRIER_SHARED_W;
1283 break;
1284 case nir_intrinsic_group_memory_barrier:
1285 barrier = ir3_FENCE(b);
1286 barrier->cat7.g = true;
1287 barrier->cat7.l = true;
1288 barrier->cat7.r = true;
1289 barrier->cat7.w = true;
1290 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1291 IR3_BARRIER_IMAGE_W |
1292 IR3_BARRIER_BUFFER_W;
1293 barrier->barrier_conflict =
1294 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1295 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1296 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1297 break;
1298 default:
1299 unreachable("boo");
1300 }
1301
1302 /* make sure barrier doesn't get DCE'd */
1303 array_insert(b, b->keeps, barrier);
1304 }
1305
1306 static void add_sysval_input_compmask(struct ir3_context *ctx,
1307 gl_system_value slot, unsigned compmask,
1308 struct ir3_instruction *instr)
1309 {
1310 struct ir3_shader_variant *so = ctx->so;
1311 unsigned n = so->inputs_count++;
1312
1313 assert(instr->opc == OPC_META_INPUT);
1314 instr->input.inidx = n;
1315 instr->input.sysval = slot;
1316
1317 so->inputs[n].sysval = true;
1318 so->inputs[n].slot = slot;
1319 so->inputs[n].compmask = compmask;
1320 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1321 so->total_in++;
1322 }
1323
1324 static struct ir3_instruction *
1325 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1326 unsigned compmask)
1327 {
1328 assert(compmask);
1329 struct ir3_instruction *sysval = create_input(ctx, compmask);
1330 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1331 return sysval;
1332 }
1333
1334 static struct ir3_instruction *
1335 get_barycentric_centroid(struct ir3_context *ctx)
1336 {
1337 if (!ctx->ij_centroid) {
1338 struct ir3_instruction *xy[2];
1339 struct ir3_instruction *ij;
1340
1341 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1342 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1343
1344 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1345 }
1346
1347 return ctx->ij_centroid;
1348 }
1349
1350 static struct ir3_instruction *
1351 get_barycentric_sample(struct ir3_context *ctx)
1352 {
1353 if (!ctx->ij_sample) {
1354 struct ir3_instruction *xy[2];
1355 struct ir3_instruction *ij;
1356
1357 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1358 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1359
1360 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1361 }
1362
1363 return ctx->ij_sample;
1364 }
1365
1366 static struct ir3_instruction *
1367 get_barycentric_pixel(struct ir3_context *ctx)
1368 {
1369 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1370 * this to create ij_pixel only on demand:
1371 */
1372 return ctx->ij_pixel;
1373 }
1374
1375 static struct ir3_instruction *
1376 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1377 {
1378 if (!ctx->frag_coord) {
1379 struct ir3_block *b = ctx->in_block;
1380 struct ir3_instruction *xyzw[4];
1381 struct ir3_instruction *hw_frag_coord;
1382
1383 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1384 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1385
1386 /* for frag_coord.xy, we get unsigned values.. we need
1387 * to subtract (integer) 8 and divide by 16 (right-
1388 * shift by 4) then convert to float:
1389 *
1390 * sub.s tmp, src, 8
1391 * shr.b tmp, tmp, 4
1392 * mov.u32f32 dst, tmp
1393 *
1394 */
1395 for (int i = 0; i < 2; i++) {
1396 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1397 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1398 }
1399
1400 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1401 }
1402
1403 ctx->so->fragcoord_compmask |=
1404 nir_ssa_def_components_read(&intr->dest.ssa);
1405
1406 return ctx->frag_coord;
1407 }
1408
1409 static void
1410 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1411 {
1412 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1413 struct ir3_instruction **dst;
1414 struct ir3_instruction * const *src;
1415 struct ir3_block *b = ctx->block;
1416 int idx, comp;
1417
1418 if (info->has_dest) {
1419 unsigned n = nir_intrinsic_dest_components(intr);
1420 dst = ir3_get_dst(ctx, &intr->dest, n);
1421 } else {
1422 dst = NULL;
1423 }
1424
1425 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1426 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1427
1428 switch (intr->intrinsic) {
1429 case nir_intrinsic_load_uniform:
1430 idx = nir_intrinsic_base(intr);
1431 if (nir_src_is_const(intr->src[0])) {
1432 idx += nir_src_as_uint(intr->src[0]);
1433 for (int i = 0; i < intr->num_components; i++) {
1434 dst[i] = create_uniform_typed(b, idx + i,
1435 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1436 }
1437 } else {
1438 src = ir3_get_src(ctx, &intr->src[0]);
1439 for (int i = 0; i < intr->num_components; i++) {
1440 dst[i] = create_uniform_indirect(b, idx + i,
1441 ir3_get_addr0(ctx, src[0], 1));
1442 }
1443 /* NOTE: if relative addressing is used, we set
1444 * constlen in the compiler (to worst-case value)
1445 * since we don't know in the assembler what the max
1446 * addr reg value can be:
1447 */
1448 ctx->so->constlen = MAX2(ctx->so->constlen,
1449 ctx->so->shader->ubo_state.size / 16);
1450 }
1451 break;
1452
1453 case nir_intrinsic_load_vs_primitive_stride_ir3:
1454 dst[0] = create_uniform(b, primitive_param + 0);
1455 break;
1456 case nir_intrinsic_load_vs_vertex_stride_ir3:
1457 dst[0] = create_uniform(b, primitive_param + 1);
1458 break;
1459 case nir_intrinsic_load_hs_patch_stride_ir3:
1460 dst[0] = create_uniform(b, primitive_param + 2);
1461 break;
1462 case nir_intrinsic_load_patch_vertices_in:
1463 dst[0] = create_uniform(b, primitive_param + 3);
1464 break;
1465 case nir_intrinsic_load_tess_param_base_ir3:
1466 dst[0] = create_uniform(b, primitive_param + 4);
1467 dst[1] = create_uniform(b, primitive_param + 5);
1468 break;
1469 case nir_intrinsic_load_tess_factor_base_ir3:
1470 dst[0] = create_uniform(b, primitive_param + 6);
1471 dst[1] = create_uniform(b, primitive_param + 7);
1472 break;
1473
1474 case nir_intrinsic_load_primitive_location_ir3:
1475 idx = nir_intrinsic_driver_location(intr);
1476 dst[0] = create_uniform(b, primitive_map + idx);
1477 break;
1478
1479 case nir_intrinsic_load_gs_header_ir3:
1480 dst[0] = ctx->gs_header;
1481 break;
1482 case nir_intrinsic_load_tcs_header_ir3:
1483 dst[0] = ctx->tcs_header;
1484 break;
1485
1486 case nir_intrinsic_load_primitive_id:
1487 dst[0] = ctx->primitive_id;
1488 break;
1489
1490 case nir_intrinsic_load_tess_coord:
1491 if (!ctx->tess_coord) {
1492 ctx->tess_coord =
1493 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1494 }
1495 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1496
1497 /* Unused, but ir3_put_dst() below wants to free something */
1498 dst[2] = create_immed(b, 0);
1499 break;
1500
1501 case nir_intrinsic_end_patch_ir3:
1502 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1503 struct ir3_instruction *end = ir3_PREDE(b);
1504 array_insert(b, b->keeps, end);
1505
1506 end->barrier_class = IR3_BARRIER_EVERYTHING;
1507 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1508 break;
1509
1510 case nir_intrinsic_store_global_ir3: {
1511 struct ir3_instruction *value, *addr, *offset;
1512
1513 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1514 ir3_get_src(ctx, &intr->src[1])[0],
1515 ir3_get_src(ctx, &intr->src[1])[1]
1516 }, 2);
1517
1518 offset = ir3_get_src(ctx, &intr->src[2])[0];
1519
1520 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1521 intr->num_components);
1522
1523 struct ir3_instruction *stg =
1524 ir3_STG_G(ctx->block, addr, 0, value, 0,
1525 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1526 stg->cat6.type = TYPE_U32;
1527 stg->cat6.iim_val = 1;
1528
1529 array_insert(b, b->keeps, stg);
1530
1531 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1532 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1533 break;
1534 }
1535
1536 case nir_intrinsic_load_global_ir3: {
1537 struct ir3_instruction *addr, *offset;
1538
1539 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1540 ir3_get_src(ctx, &intr->src[0])[0],
1541 ir3_get_src(ctx, &intr->src[0])[1]
1542 }, 2);
1543
1544 offset = ir3_get_src(ctx, &intr->src[1])[0];
1545
1546 struct ir3_instruction *load =
1547 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1548 0, offset, 0);
1549 load->cat6.type = TYPE_U32;
1550 load->regs[0]->wrmask = MASK(intr->num_components);
1551
1552 load->barrier_class = IR3_BARRIER_BUFFER_R;
1553 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1554
1555 ir3_split_dest(b, dst, load, 0, intr->num_components);
1556 break;
1557 }
1558
1559 case nir_intrinsic_load_ubo:
1560 emit_intrinsic_load_ubo(ctx, intr, dst);
1561 break;
1562 case nir_intrinsic_load_ubo_ir3:
1563 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1564 break;
1565 case nir_intrinsic_load_frag_coord:
1566 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1567 break;
1568 case nir_intrinsic_load_sample_pos_from_id: {
1569 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1570 * but that doesn't seem necessary.
1571 */
1572 struct ir3_instruction *offset =
1573 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1574 offset->regs[0]->wrmask = 0x3;
1575 offset->cat5.type = TYPE_F32;
1576
1577 ir3_split_dest(b, dst, offset, 0, 2);
1578
1579 break;
1580 }
1581 case nir_intrinsic_load_size_ir3:
1582 if (!ctx->ij_size) {
1583 ctx->ij_size =
1584 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1585 }
1586 dst[0] = ctx->ij_size;
1587 break;
1588 case nir_intrinsic_load_barycentric_centroid:
1589 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1590 break;
1591 case nir_intrinsic_load_barycentric_sample:
1592 if (ctx->so->key.msaa) {
1593 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1594 } else {
1595 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1596 }
1597 break;
1598 case nir_intrinsic_load_barycentric_pixel:
1599 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1600 break;
1601 case nir_intrinsic_load_interpolated_input:
1602 idx = nir_intrinsic_base(intr);
1603 comp = nir_intrinsic_component(intr);
1604 src = ir3_get_src(ctx, &intr->src[0]);
1605 if (nir_src_is_const(intr->src[1])) {
1606 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1607 idx += nir_src_as_uint(intr->src[1]);
1608 for (int i = 0; i < intr->num_components; i++) {
1609 unsigned inloc = idx * 4 + i + comp;
1610 if (ctx->so->inputs[idx].bary &&
1611 !ctx->so->inputs[idx].use_ldlv) {
1612 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1613 } else {
1614 /* for non-varyings use the pre-setup input, since
1615 * that is easier than mapping things back to a
1616 * nir_variable to figure out what it is.
1617 */
1618 dst[i] = ctx->inputs[inloc];
1619 compile_assert(ctx, dst[i]);
1620 }
1621 }
1622 } else {
1623 ir3_context_error(ctx, "unhandled");
1624 }
1625 break;
1626 case nir_intrinsic_load_input:
1627 idx = nir_intrinsic_base(intr);
1628 comp = nir_intrinsic_component(intr);
1629 if (nir_src_is_const(intr->src[0])) {
1630 idx += nir_src_as_uint(intr->src[0]);
1631 for (int i = 0; i < intr->num_components; i++) {
1632 unsigned n = idx * 4 + i + comp;
1633 dst[i] = ctx->inputs[n];
1634 compile_assert(ctx, ctx->inputs[n]);
1635 }
1636 } else {
1637 src = ir3_get_src(ctx, &intr->src[0]);
1638 struct ir3_instruction *collect =
1639 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1640 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1641 for (int i = 0; i < intr->num_components; i++) {
1642 unsigned n = idx * 4 + i + comp;
1643 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1644 n, addr, collect);
1645 }
1646 }
1647 break;
1648 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1649 * pass and replaced by an ir3-specifc version that adds the
1650 * dword-offset in the last source.
1651 */
1652 case nir_intrinsic_load_ssbo_ir3:
1653 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1654 break;
1655 case nir_intrinsic_store_ssbo_ir3:
1656 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1657 !ctx->s->info.fs.early_fragment_tests)
1658 ctx->so->no_earlyz = true;
1659 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1660 break;
1661 case nir_intrinsic_get_buffer_size:
1662 emit_intrinsic_ssbo_size(ctx, intr, dst);
1663 break;
1664 case nir_intrinsic_ssbo_atomic_add_ir3:
1665 case nir_intrinsic_ssbo_atomic_imin_ir3:
1666 case nir_intrinsic_ssbo_atomic_umin_ir3:
1667 case nir_intrinsic_ssbo_atomic_imax_ir3:
1668 case nir_intrinsic_ssbo_atomic_umax_ir3:
1669 case nir_intrinsic_ssbo_atomic_and_ir3:
1670 case nir_intrinsic_ssbo_atomic_or_ir3:
1671 case nir_intrinsic_ssbo_atomic_xor_ir3:
1672 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1673 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1674 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1675 !ctx->s->info.fs.early_fragment_tests)
1676 ctx->so->no_earlyz = true;
1677 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1678 break;
1679 case nir_intrinsic_load_shared:
1680 emit_intrinsic_load_shared(ctx, intr, dst);
1681 break;
1682 case nir_intrinsic_store_shared:
1683 emit_intrinsic_store_shared(ctx, intr);
1684 break;
1685 case nir_intrinsic_shared_atomic_add:
1686 case nir_intrinsic_shared_atomic_imin:
1687 case nir_intrinsic_shared_atomic_umin:
1688 case nir_intrinsic_shared_atomic_imax:
1689 case nir_intrinsic_shared_atomic_umax:
1690 case nir_intrinsic_shared_atomic_and:
1691 case nir_intrinsic_shared_atomic_or:
1692 case nir_intrinsic_shared_atomic_xor:
1693 case nir_intrinsic_shared_atomic_exchange:
1694 case nir_intrinsic_shared_atomic_comp_swap:
1695 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1696 break;
1697 case nir_intrinsic_image_load:
1698 emit_intrinsic_load_image(ctx, intr, dst);
1699 break;
1700 case nir_intrinsic_bindless_image_load:
1701 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1702 * so using isam doesn't work.
1703 *
1704 * TODO: can we use isam if we fill out more fields?
1705 */
1706 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1707 break;
1708 case nir_intrinsic_image_store:
1709 case nir_intrinsic_bindless_image_store:
1710 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1711 !ctx->s->info.fs.early_fragment_tests)
1712 ctx->so->no_earlyz = true;
1713 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1714 break;
1715 case nir_intrinsic_image_size:
1716 case nir_intrinsic_bindless_image_size:
1717 emit_intrinsic_image_size(ctx, intr, dst);
1718 break;
1719 case nir_intrinsic_image_atomic_add:
1720 case nir_intrinsic_bindless_image_atomic_add:
1721 case nir_intrinsic_image_atomic_imin:
1722 case nir_intrinsic_bindless_image_atomic_imin:
1723 case nir_intrinsic_image_atomic_umin:
1724 case nir_intrinsic_bindless_image_atomic_umin:
1725 case nir_intrinsic_image_atomic_imax:
1726 case nir_intrinsic_bindless_image_atomic_imax:
1727 case nir_intrinsic_image_atomic_umax:
1728 case nir_intrinsic_bindless_image_atomic_umax:
1729 case nir_intrinsic_image_atomic_and:
1730 case nir_intrinsic_bindless_image_atomic_and:
1731 case nir_intrinsic_image_atomic_or:
1732 case nir_intrinsic_bindless_image_atomic_or:
1733 case nir_intrinsic_image_atomic_xor:
1734 case nir_intrinsic_bindless_image_atomic_xor:
1735 case nir_intrinsic_image_atomic_exchange:
1736 case nir_intrinsic_bindless_image_atomic_exchange:
1737 case nir_intrinsic_image_atomic_comp_swap:
1738 case nir_intrinsic_bindless_image_atomic_comp_swap:
1739 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1740 !ctx->s->info.fs.early_fragment_tests)
1741 ctx->so->no_earlyz = true;
1742 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1743 break;
1744 case nir_intrinsic_control_barrier:
1745 case nir_intrinsic_memory_barrier:
1746 case nir_intrinsic_group_memory_barrier:
1747 case nir_intrinsic_memory_barrier_buffer:
1748 case nir_intrinsic_memory_barrier_image:
1749 case nir_intrinsic_memory_barrier_shared:
1750 emit_intrinsic_barrier(ctx, intr);
1751 /* note that blk ptr no longer valid, make that obvious: */
1752 b = NULL;
1753 break;
1754 case nir_intrinsic_store_output:
1755 idx = nir_intrinsic_base(intr);
1756 comp = nir_intrinsic_component(intr);
1757 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1758 idx += nir_src_as_uint(intr->src[1]);
1759
1760 src = ir3_get_src(ctx, &intr->src[0]);
1761 for (int i = 0; i < intr->num_components; i++) {
1762 unsigned n = idx * 4 + i + comp;
1763 ctx->outputs[n] = src[i];
1764 }
1765 break;
1766 case nir_intrinsic_load_base_vertex:
1767 case nir_intrinsic_load_first_vertex:
1768 if (!ctx->basevertex) {
1769 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1770 }
1771 dst[0] = ctx->basevertex;
1772 break;
1773 case nir_intrinsic_load_base_instance:
1774 if (!ctx->base_instance) {
1775 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1776 }
1777 dst[0] = ctx->base_instance;
1778 break;
1779 case nir_intrinsic_load_vertex_id_zero_base:
1780 case nir_intrinsic_load_vertex_id:
1781 if (!ctx->vertex_id) {
1782 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1783 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1784 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1785 }
1786 dst[0] = ctx->vertex_id;
1787 break;
1788 case nir_intrinsic_load_instance_id:
1789 if (!ctx->instance_id) {
1790 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1791 }
1792 dst[0] = ctx->instance_id;
1793 break;
1794 case nir_intrinsic_load_sample_id:
1795 ctx->so->per_samp = true;
1796 /* fall-thru */
1797 case nir_intrinsic_load_sample_id_no_per_sample:
1798 if (!ctx->samp_id) {
1799 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1800 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1801 }
1802 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1803 break;
1804 case nir_intrinsic_load_sample_mask_in:
1805 if (!ctx->samp_mask_in) {
1806 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1807 }
1808 dst[0] = ctx->samp_mask_in;
1809 break;
1810 case nir_intrinsic_load_user_clip_plane:
1811 idx = nir_intrinsic_ucp_id(intr);
1812 for (int i = 0; i < intr->num_components; i++) {
1813 unsigned n = idx * 4 + i;
1814 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1815 }
1816 break;
1817 case nir_intrinsic_load_front_face:
1818 if (!ctx->frag_face) {
1819 ctx->so->frag_face = true;
1820 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1821 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1822 }
1823 /* for fragface, we get -1 for back and 0 for front. However this is
1824 * the inverse of what nir expects (where ~0 is true).
1825 */
1826 dst[0] = ir3_CMPS_S(b,
1827 ctx->frag_face, 0,
1828 create_immed_typed(b, 0, TYPE_U16), 0);
1829 dst[0]->cat2.condition = IR3_COND_EQ;
1830 break;
1831 case nir_intrinsic_load_local_invocation_id:
1832 if (!ctx->local_invocation_id) {
1833 ctx->local_invocation_id =
1834 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1835 }
1836 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1837 break;
1838 case nir_intrinsic_load_work_group_id:
1839 if (!ctx->work_group_id) {
1840 ctx->work_group_id =
1841 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1842 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1843 }
1844 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1845 break;
1846 case nir_intrinsic_load_num_work_groups:
1847 for (int i = 0; i < intr->num_components; i++) {
1848 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1849 }
1850 break;
1851 case nir_intrinsic_load_local_group_size:
1852 for (int i = 0; i < intr->num_components; i++) {
1853 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1854 }
1855 break;
1856 case nir_intrinsic_discard_if:
1857 case nir_intrinsic_discard: {
1858 struct ir3_instruction *cond, *kill;
1859
1860 if (intr->intrinsic == nir_intrinsic_discard_if) {
1861 /* conditional discard: */
1862 src = ir3_get_src(ctx, &intr->src[0]);
1863 cond = src[0];
1864 } else {
1865 /* unconditional discard: */
1866 cond = create_immed(b, 1);
1867 }
1868
1869 /* NOTE: only cmps.*.* can write p0.x: */
1870 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1871 cond->cat2.condition = IR3_COND_NE;
1872
1873 /* condition always goes in predicate register: */
1874 cond->regs[0]->num = regid(REG_P0, 0);
1875 cond->regs[0]->flags &= ~IR3_REG_SSA;
1876
1877 kill = ir3_KILL(b, cond, 0);
1878 kill->regs[1]->num = regid(REG_P0, 0);
1879 array_insert(ctx->ir, ctx->ir->predicates, kill);
1880
1881 array_insert(b, b->keeps, kill);
1882 ctx->so->no_earlyz = true;
1883
1884 break;
1885 }
1886
1887 case nir_intrinsic_cond_end_ir3: {
1888 struct ir3_instruction *cond, *kill;
1889
1890 src = ir3_get_src(ctx, &intr->src[0]);
1891 cond = src[0];
1892
1893 /* NOTE: only cmps.*.* can write p0.x: */
1894 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1895 cond->cat2.condition = IR3_COND_NE;
1896
1897 /* condition always goes in predicate register: */
1898 cond->regs[0]->num = regid(REG_P0, 0);
1899
1900 kill = ir3_PREDT(b, cond, 0);
1901
1902 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1903 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1904
1905 array_insert(ctx->ir, ctx->ir->predicates, kill);
1906 array_insert(b, b->keeps, kill);
1907 break;
1908 }
1909
1910 case nir_intrinsic_load_shared_ir3:
1911 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1912 break;
1913 case nir_intrinsic_store_shared_ir3:
1914 emit_intrinsic_store_shared_ir3(ctx, intr);
1915 break;
1916 case nir_intrinsic_bindless_resource_ir3:
1917 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1918 break;
1919 default:
1920 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1921 nir_intrinsic_infos[intr->intrinsic].name);
1922 break;
1923 }
1924
1925 if (info->has_dest)
1926 ir3_put_dst(ctx, &intr->dest);
1927 }
1928
1929 static void
1930 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1931 {
1932 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1933 instr->def.num_components);
1934
1935 if (instr->def.bit_size == 16) {
1936 for (int i = 0; i < instr->def.num_components; i++)
1937 dst[i] = create_immed_typed(ctx->block,
1938 instr->value[i].u16,
1939 TYPE_U16);
1940 } else {
1941 for (int i = 0; i < instr->def.num_components; i++)
1942 dst[i] = create_immed_typed(ctx->block,
1943 instr->value[i].u32,
1944 TYPE_U32);
1945 }
1946
1947 }
1948
1949 static void
1950 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1951 {
1952 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1953 undef->def.num_components);
1954 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
1955
1956 /* backend doesn't want undefined instructions, so just plug
1957 * in 0.0..
1958 */
1959 for (int i = 0; i < undef->def.num_components; i++)
1960 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1961 }
1962
1963 /*
1964 * texture fetch/sample instructions:
1965 */
1966
1967 static type_t
1968 get_tex_dest_type(nir_tex_instr *tex)
1969 {
1970 type_t type;
1971
1972 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1973 case nir_type_invalid:
1974 case nir_type_float:
1975 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
1976 break;
1977 case nir_type_int:
1978 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
1979 break;
1980 case nir_type_uint:
1981 case nir_type_bool:
1982 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
1983 break;
1984 default:
1985 unreachable("bad dest_type");
1986 }
1987
1988 return type;
1989 }
1990
1991 static void
1992 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1993 {
1994 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
1995 unsigned flags = 0;
1996
1997 /* note: would use tex->coord_components.. except txs.. also,
1998 * since array index goes after shadow ref, we don't want to
1999 * count it:
2000 */
2001 if (coords == 3)
2002 flags |= IR3_INSTR_3D;
2003
2004 if (tex->is_shadow && tex->op != nir_texop_lod)
2005 flags |= IR3_INSTR_S;
2006
2007 if (tex->is_array && tex->op != nir_texop_lod)
2008 flags |= IR3_INSTR_A;
2009
2010 *flagsp = flags;
2011 *coordsp = coords;
2012 }
2013
2014 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2015 * or immediate (in which case it will get lowered later to a non .s2en
2016 * version of the tex instruction which encode tex/samp as immediates:
2017 */
2018 static struct tex_src_info
2019 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2020 {
2021 struct ir3_block *b = ctx->block;
2022 struct tex_src_info info = { 0 };
2023 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2024 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2025 struct ir3_instruction *texture, *sampler;
2026
2027 if (texture_idx >= 0 || sampler_idx >= 0) {
2028 /* Bindless case */
2029 info.flags |= IR3_INSTR_B;
2030
2031 /* Gather information required to determine which encoding to
2032 * choose as well as for prefetch.
2033 */
2034 nir_intrinsic_instr *bindless_tex = NULL;
2035 bool tex_const;
2036 if (texture_idx >= 0) {
2037 ctx->so->bindless_tex = true;
2038 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2039 assert(bindless_tex);
2040 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2041 tex_const = nir_src_is_const(bindless_tex->src[0]);
2042 if (tex_const)
2043 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2044 } else {
2045 /* To simplify some of the logic below, assume the index is
2046 * constant 0 when it's not enabled.
2047 */
2048 tex_const = true;
2049 info.tex_idx = 0;
2050 }
2051 nir_intrinsic_instr *bindless_samp = NULL;
2052 bool samp_const;
2053 if (sampler_idx >= 0) {
2054 ctx->so->bindless_samp = true;
2055 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2056 assert(bindless_samp);
2057 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2058 samp_const = nir_src_is_const(bindless_samp->src[0]);
2059 if (samp_const)
2060 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2061 } else {
2062 samp_const = true;
2063 info.samp_idx = 0;
2064 }
2065
2066 /* Choose encoding. */
2067 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2068 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2069 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2070 /* Everything fits within the instruction */
2071 info.base = info.tex_base;
2072 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2073 } else {
2074 info.base = info.tex_base;
2075 info.a1_val = info.tex_idx << 3 | info.samp_base;
2076 info.combined_idx = info.samp_idx;
2077 info.flags |= IR3_INSTR_A1EN;
2078 }
2079 info.samp_tex = NULL;
2080 } else {
2081 info.flags |= IR3_INSTR_S2EN;
2082 /* In the indirect case, we only use a1.x to store the sampler
2083 * base if it differs from the texture base.
2084 */
2085 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2086 info.base = info.tex_base;
2087 } else {
2088 info.base = info.tex_base;
2089 info.a1_val = info.samp_base;
2090 info.flags |= IR3_INSTR_A1EN;
2091 }
2092
2093 /* Note: the indirect source is now a vec2 instead of hvec2, and
2094 * for some reason the texture and sampler are swapped.
2095 */
2096 struct ir3_instruction *texture, *sampler;
2097
2098 if (bindless_tex) {
2099 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2100 } else {
2101 texture = create_immed(b, 0);
2102 }
2103
2104 if (bindless_samp) {
2105 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2106 } else {
2107 sampler = create_immed(b, 0);
2108 }
2109 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2110 texture,
2111 sampler,
2112 }, 2);
2113 }
2114 } else {
2115 info.flags |= IR3_INSTR_S2EN;
2116 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2117 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2118 if (texture_idx >= 0) {
2119 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2120 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2121 } else {
2122 /* TODO what to do for dynamic case? I guess we only need the
2123 * max index for astc srgb workaround so maybe not a problem
2124 * to worry about if we don't enable indirect samplers for
2125 * a4xx?
2126 */
2127 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2128 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2129 info.tex_idx = tex->texture_index;
2130 }
2131
2132 if (sampler_idx >= 0) {
2133 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2134 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2135 } else {
2136 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2137 info.samp_idx = tex->texture_index;
2138 }
2139
2140 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2141 sampler,
2142 texture,
2143 }, 2);
2144 }
2145
2146 return info;
2147 }
2148
2149 static void
2150 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2151 {
2152 struct ir3_block *b = ctx->block;
2153 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2154 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2155 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2156 struct tex_src_info info = { 0 };
2157 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2158 unsigned i, coords, flags, ncomp;
2159 unsigned nsrc0 = 0, nsrc1 = 0;
2160 type_t type;
2161 opc_t opc = 0;
2162
2163 ncomp = nir_dest_num_components(tex->dest);
2164
2165 coord = off = ddx = ddy = NULL;
2166 lod = proj = compare = sample_index = NULL;
2167
2168 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2169
2170 for (unsigned i = 0; i < tex->num_srcs; i++) {
2171 switch (tex->src[i].src_type) {
2172 case nir_tex_src_coord:
2173 coord = ir3_get_src(ctx, &tex->src[i].src);
2174 break;
2175 case nir_tex_src_bias:
2176 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2177 has_bias = true;
2178 break;
2179 case nir_tex_src_lod:
2180 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2181 has_lod = true;
2182 break;
2183 case nir_tex_src_comparator: /* shadow comparator */
2184 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2185 break;
2186 case nir_tex_src_projector:
2187 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2188 has_proj = true;
2189 break;
2190 case nir_tex_src_offset:
2191 off = ir3_get_src(ctx, &tex->src[i].src);
2192 has_off = true;
2193 break;
2194 case nir_tex_src_ddx:
2195 ddx = ir3_get_src(ctx, &tex->src[i].src);
2196 break;
2197 case nir_tex_src_ddy:
2198 ddy = ir3_get_src(ctx, &tex->src[i].src);
2199 break;
2200 case nir_tex_src_ms_index:
2201 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2202 break;
2203 case nir_tex_src_texture_offset:
2204 case nir_tex_src_sampler_offset:
2205 case nir_tex_src_texture_handle:
2206 case nir_tex_src_sampler_handle:
2207 /* handled in get_tex_samp_src() */
2208 break;
2209 default:
2210 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2211 tex->src[i].src_type);
2212 return;
2213 }
2214 }
2215
2216 switch (tex->op) {
2217 case nir_texop_tex_prefetch:
2218 compile_assert(ctx, !has_bias);
2219 compile_assert(ctx, !has_lod);
2220 compile_assert(ctx, !compare);
2221 compile_assert(ctx, !has_proj);
2222 compile_assert(ctx, !has_off);
2223 compile_assert(ctx, !ddx);
2224 compile_assert(ctx, !ddy);
2225 compile_assert(ctx, !sample_index);
2226 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2227 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2228
2229 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2230 opc = OPC_META_TEX_PREFETCH;
2231 ctx->so->num_sampler_prefetch++;
2232 break;
2233 }
2234 /* fallthru */
2235 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2236 case nir_texop_txb: opc = OPC_SAMB; break;
2237 case nir_texop_txl: opc = OPC_SAML; break;
2238 case nir_texop_txd: opc = OPC_SAMGQ; break;
2239 case nir_texop_txf: opc = OPC_ISAML; break;
2240 case nir_texop_lod: opc = OPC_GETLOD; break;
2241 case nir_texop_tg4:
2242 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2243 * what blob does, seems gather is broken?), and a3xx did
2244 * not support it (but probably could also emulate).
2245 */
2246 switch (tex->component) {
2247 case 0: opc = OPC_GATHER4R; break;
2248 case 1: opc = OPC_GATHER4G; break;
2249 case 2: opc = OPC_GATHER4B; break;
2250 case 3: opc = OPC_GATHER4A; break;
2251 }
2252 break;
2253 case nir_texop_txf_ms_fb:
2254 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2255 default:
2256 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2257 return;
2258 }
2259
2260 tex_info(tex, &flags, &coords);
2261
2262 /*
2263 * lay out the first argument in the proper order:
2264 * - actual coordinates first
2265 * - shadow reference
2266 * - array index
2267 * - projection w
2268 * - starting at offset 4, dpdx.xy, dpdy.xy
2269 *
2270 * bias/lod go into the second arg
2271 */
2272
2273 /* insert tex coords: */
2274 for (i = 0; i < coords; i++)
2275 src0[i] = coord[i];
2276
2277 nsrc0 = i;
2278
2279 /* scale up integer coords for TXF based on the LOD */
2280 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2281 assert(has_lod);
2282 for (i = 0; i < coords; i++)
2283 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2284 }
2285
2286 if (coords == 1) {
2287 /* hw doesn't do 1d, so we treat it as 2d with
2288 * height of 1, and patch up the y coord.
2289 */
2290 if (is_isam(opc)) {
2291 src0[nsrc0++] = create_immed(b, 0);
2292 } else {
2293 src0[nsrc0++] = create_immed(b, fui(0.5));
2294 }
2295 }
2296
2297 if (tex->is_shadow && tex->op != nir_texop_lod)
2298 src0[nsrc0++] = compare;
2299
2300 if (tex->is_array && tex->op != nir_texop_lod) {
2301 struct ir3_instruction *idx = coord[coords];
2302
2303 /* the array coord for cube arrays needs 0.5 added to it */
2304 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2305 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2306
2307 src0[nsrc0++] = idx;
2308 }
2309
2310 if (has_proj) {
2311 src0[nsrc0++] = proj;
2312 flags |= IR3_INSTR_P;
2313 }
2314
2315 /* pad to 4, then ddx/ddy: */
2316 if (tex->op == nir_texop_txd) {
2317 while (nsrc0 < 4)
2318 src0[nsrc0++] = create_immed(b, fui(0.0));
2319 for (i = 0; i < coords; i++)
2320 src0[nsrc0++] = ddx[i];
2321 if (coords < 2)
2322 src0[nsrc0++] = create_immed(b, fui(0.0));
2323 for (i = 0; i < coords; i++)
2324 src0[nsrc0++] = ddy[i];
2325 if (coords < 2)
2326 src0[nsrc0++] = create_immed(b, fui(0.0));
2327 }
2328
2329 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2330 * with scaled x coord according to requested sample:
2331 */
2332 if (opc == OPC_ISAMM) {
2333 if (ctx->compiler->txf_ms_with_isaml) {
2334 /* the samples are laid out in x dimension as
2335 * 0 1 2 3
2336 * x_ms = (x << ms) + sample_index;
2337 */
2338 struct ir3_instruction *ms;
2339 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2340
2341 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2342 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2343
2344 opc = OPC_ISAML;
2345 } else {
2346 src0[nsrc0++] = sample_index;
2347 }
2348 }
2349
2350 /*
2351 * second argument (if applicable):
2352 * - offsets
2353 * - lod
2354 * - bias
2355 */
2356 if (has_off | has_lod | has_bias) {
2357 if (has_off) {
2358 unsigned off_coords = coords;
2359 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2360 off_coords--;
2361 for (i = 0; i < off_coords; i++)
2362 src1[nsrc1++] = off[i];
2363 if (off_coords < 2)
2364 src1[nsrc1++] = create_immed(b, fui(0.0));
2365 flags |= IR3_INSTR_O;
2366 }
2367
2368 if (has_lod | has_bias)
2369 src1[nsrc1++] = lod;
2370 }
2371
2372 type = get_tex_dest_type(tex);
2373
2374 if (opc == OPC_GETLOD)
2375 type = TYPE_S32;
2376
2377
2378 if (tex->op == nir_texop_txf_ms_fb) {
2379 /* only expect a single txf_ms_fb per shader: */
2380 compile_assert(ctx, !ctx->so->fb_read);
2381 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2382
2383 ctx->so->fb_read = true;
2384 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2385 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2386 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2387 }, 2);
2388 info.flags = IR3_INSTR_S2EN;
2389
2390 ctx->so->num_samp++;
2391 } else {
2392 info = get_tex_samp_tex_src(ctx, tex);
2393 }
2394
2395 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2396 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2397
2398 if (opc == OPC_META_TEX_PREFETCH) {
2399 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2400
2401 compile_assert(ctx, tex->src[idx].src.is_ssa);
2402
2403 sam = ir3_META_TEX_PREFETCH(b);
2404 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2405 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2406 sam->prefetch.input_offset =
2407 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2408 /* make sure not to add irrelevant flags like S2EN */
2409 sam->flags = flags | (info.flags & IR3_INSTR_B);
2410 sam->prefetch.tex = info.tex_idx;
2411 sam->prefetch.samp = info.samp_idx;
2412 sam->prefetch.tex_base = info.tex_base;
2413 sam->prefetch.samp_base = info.samp_base;
2414 } else {
2415 info.flags |= flags;
2416 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2417 }
2418
2419 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2420 assert(opc != OPC_META_TEX_PREFETCH);
2421
2422 /* only need first 3 components: */
2423 sam->regs[0]->wrmask = 0x7;
2424 ir3_split_dest(b, dst, sam, 0, 3);
2425
2426 /* we need to sample the alpha separately with a non-ASTC
2427 * texture state:
2428 */
2429 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2430 info.samp_tex, col0, col1);
2431
2432 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2433
2434 /* fixup .w component: */
2435 ir3_split_dest(b, &dst[3], sam, 3, 1);
2436 } else {
2437 /* normal (non-workaround) case: */
2438 ir3_split_dest(b, dst, sam, 0, ncomp);
2439 }
2440
2441 /* GETLOD returns results in 4.8 fixed point */
2442 if (opc == OPC_GETLOD) {
2443 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2444
2445 compile_assert(ctx, tex->dest_type == nir_type_float);
2446 for (i = 0; i < 2; i++) {
2447 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2448 factor, 0);
2449 }
2450 }
2451
2452 ir3_put_dst(ctx, &tex->dest);
2453 }
2454
2455 static void
2456 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2457 {
2458 struct ir3_block *b = ctx->block;
2459 struct ir3_instruction **dst, *sam;
2460 type_t dst_type = get_tex_dest_type(tex);
2461 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2462
2463 dst = ir3_get_dst(ctx, &tex->dest, 1);
2464
2465 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2466
2467 /* even though there is only one component, since it ends
2468 * up in .y/.z/.w rather than .x, we need a split_dest()
2469 */
2470 ir3_split_dest(b, dst, sam, idx, 1);
2471
2472 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2473 * the value in TEX_CONST_0 is zero-based.
2474 */
2475 if (ctx->compiler->levels_add_one)
2476 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2477
2478 ir3_put_dst(ctx, &tex->dest);
2479 }
2480
2481 static void
2482 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2483 {
2484 struct ir3_block *b = ctx->block;
2485 struct ir3_instruction **dst, *sam;
2486 struct ir3_instruction *lod;
2487 unsigned flags, coords;
2488 type_t dst_type = get_tex_dest_type(tex);
2489 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2490
2491 tex_info(tex, &flags, &coords);
2492 info.flags |= flags;
2493
2494 /* Actually we want the number of dimensions, not coordinates. This
2495 * distinction only matters for cubes.
2496 */
2497 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2498 coords = 2;
2499
2500 dst = ir3_get_dst(ctx, &tex->dest, 4);
2501
2502 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2503 compile_assert(ctx, lod_idx >= 0);
2504
2505 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2506
2507 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2508 ir3_split_dest(b, dst, sam, 0, 4);
2509
2510 /* Array size actually ends up in .w rather than .z. This doesn't
2511 * matter for miplevel 0, but for higher mips the value in z is
2512 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2513 * returned, which means that we have to add 1 to it for arrays.
2514 */
2515 if (tex->is_array) {
2516 if (ctx->compiler->levels_add_one) {
2517 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2518 } else {
2519 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2520 }
2521 }
2522
2523 ir3_put_dst(ctx, &tex->dest);
2524 }
2525
2526 static void
2527 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2528 {
2529 switch (jump->type) {
2530 case nir_jump_break:
2531 case nir_jump_continue:
2532 case nir_jump_return:
2533 /* I *think* we can simply just ignore this, and use the
2534 * successor block link to figure out where we need to
2535 * jump to for break/continue
2536 */
2537 break;
2538 default:
2539 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2540 break;
2541 }
2542 }
2543
2544 static void
2545 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2546 {
2547 switch (instr->type) {
2548 case nir_instr_type_alu:
2549 emit_alu(ctx, nir_instr_as_alu(instr));
2550 break;
2551 case nir_instr_type_deref:
2552 /* ignored, handled as part of the intrinsic they are src to */
2553 break;
2554 case nir_instr_type_intrinsic:
2555 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2556 break;
2557 case nir_instr_type_load_const:
2558 emit_load_const(ctx, nir_instr_as_load_const(instr));
2559 break;
2560 case nir_instr_type_ssa_undef:
2561 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2562 break;
2563 case nir_instr_type_tex: {
2564 nir_tex_instr *tex = nir_instr_as_tex(instr);
2565 /* couple tex instructions get special-cased:
2566 */
2567 switch (tex->op) {
2568 case nir_texop_txs:
2569 emit_tex_txs(ctx, tex);
2570 break;
2571 case nir_texop_query_levels:
2572 emit_tex_info(ctx, tex, 2);
2573 break;
2574 case nir_texop_texture_samples:
2575 emit_tex_info(ctx, tex, 3);
2576 break;
2577 default:
2578 emit_tex(ctx, tex);
2579 break;
2580 }
2581 break;
2582 }
2583 case nir_instr_type_jump:
2584 emit_jump(ctx, nir_instr_as_jump(instr));
2585 break;
2586 case nir_instr_type_phi:
2587 /* we have converted phi webs to regs in NIR by now */
2588 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2589 break;
2590 case nir_instr_type_call:
2591 case nir_instr_type_parallel_copy:
2592 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2593 break;
2594 }
2595 }
2596
2597 static struct ir3_block *
2598 get_block(struct ir3_context *ctx, const nir_block *nblock)
2599 {
2600 struct ir3_block *block;
2601 struct hash_entry *hentry;
2602
2603 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2604 if (hentry)
2605 return hentry->data;
2606
2607 block = ir3_block_create(ctx->ir);
2608 block->nblock = nblock;
2609 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2610
2611 set_foreach(nblock->predecessors, sentry) {
2612 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2613 }
2614
2615 return block;
2616 }
2617
2618 static void
2619 emit_block(struct ir3_context *ctx, nir_block *nblock)
2620 {
2621 struct ir3_block *block = get_block(ctx, nblock);
2622
2623 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2624 if (nblock->successors[i]) {
2625 block->successors[i] =
2626 get_block(ctx, nblock->successors[i]);
2627 }
2628 }
2629
2630 ctx->block = block;
2631 list_addtail(&block->node, &ctx->ir->block_list);
2632
2633 /* re-emit addr register in each block if needed: */
2634 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2635 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2636 ctx->addr0_ht[i] = NULL;
2637 }
2638
2639 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2640 ctx->addr1_ht = NULL;
2641
2642 nir_foreach_instr (instr, nblock) {
2643 ctx->cur_instr = instr;
2644 emit_instr(ctx, instr);
2645 ctx->cur_instr = NULL;
2646 if (ctx->error)
2647 return;
2648 }
2649
2650 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2651 }
2652
2653 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2654
2655 static void
2656 emit_if(struct ir3_context *ctx, nir_if *nif)
2657 {
2658 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2659
2660 ctx->block->condition = ir3_get_predicate(ctx, condition);
2661
2662 emit_cf_list(ctx, &nif->then_list);
2663 emit_cf_list(ctx, &nif->else_list);
2664 }
2665
2666 static void
2667 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2668 {
2669 emit_cf_list(ctx, &nloop->body);
2670 ctx->so->loops++;
2671 }
2672
2673 static void
2674 stack_push(struct ir3_context *ctx)
2675 {
2676 ctx->stack++;
2677 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2678 }
2679
2680 static void
2681 stack_pop(struct ir3_context *ctx)
2682 {
2683 compile_assert(ctx, ctx->stack > 0);
2684 ctx->stack--;
2685 }
2686
2687 static void
2688 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2689 {
2690 foreach_list_typed (nir_cf_node, node, node, list) {
2691 switch (node->type) {
2692 case nir_cf_node_block:
2693 emit_block(ctx, nir_cf_node_as_block(node));
2694 break;
2695 case nir_cf_node_if:
2696 stack_push(ctx);
2697 emit_if(ctx, nir_cf_node_as_if(node));
2698 stack_pop(ctx);
2699 break;
2700 case nir_cf_node_loop:
2701 stack_push(ctx);
2702 emit_loop(ctx, nir_cf_node_as_loop(node));
2703 stack_pop(ctx);
2704 break;
2705 case nir_cf_node_function:
2706 ir3_context_error(ctx, "TODO\n");
2707 break;
2708 }
2709 }
2710 }
2711
2712 /* emit stream-out code. At this point, the current block is the original
2713 * (nir) end block, and nir ensures that all flow control paths terminate
2714 * into the end block. We re-purpose the original end block to generate
2715 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2716 * block holding stream-out write instructions, followed by the new end
2717 * block:
2718 *
2719 * blockOrigEnd {
2720 * p0.x = (vtxcnt < maxvtxcnt)
2721 * // succs: blockStreamOut, blockNewEnd
2722 * }
2723 * blockStreamOut {
2724 * // preds: blockOrigEnd
2725 * ... stream-out instructions ...
2726 * // succs: blockNewEnd
2727 * }
2728 * blockNewEnd {
2729 * // preds: blockOrigEnd, blockStreamOut
2730 * }
2731 */
2732 static void
2733 emit_stream_out(struct ir3_context *ctx)
2734 {
2735 struct ir3 *ir = ctx->ir;
2736 struct ir3_stream_output_info *strmout =
2737 &ctx->so->shader->stream_output;
2738 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2739 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2740 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2741
2742 /* create vtxcnt input in input block at top of shader,
2743 * so that it is seen as live over the entire duration
2744 * of the shader:
2745 */
2746 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2747 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2748
2749 /* at this point, we are at the original 'end' block,
2750 * re-purpose this block to stream-out condition, then
2751 * append stream-out block and new-end block
2752 */
2753 orig_end_block = ctx->block;
2754
2755 // maybe w/ store_global intrinsic, we could do this
2756 // stuff in nir->nir pass
2757
2758 stream_out_block = ir3_block_create(ir);
2759 list_addtail(&stream_out_block->node, &ir->block_list);
2760
2761 new_end_block = ir3_block_create(ir);
2762 list_addtail(&new_end_block->node, &ir->block_list);
2763
2764 orig_end_block->successors[0] = stream_out_block;
2765 orig_end_block->successors[1] = new_end_block;
2766
2767 stream_out_block->successors[0] = new_end_block;
2768 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2769
2770 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2771 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2772
2773 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2774 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2775 cond->regs[0]->num = regid(REG_P0, 0);
2776 cond->regs[0]->flags &= ~IR3_REG_SSA;
2777 cond->cat2.condition = IR3_COND_LT;
2778
2779 /* condition goes on previous block to the conditional,
2780 * since it is used to pick which of the two successor
2781 * paths to take:
2782 */
2783 orig_end_block->condition = cond;
2784
2785 /* switch to stream_out_block to generate the stream-out
2786 * instructions:
2787 */
2788 ctx->block = stream_out_block;
2789
2790 /* Calculate base addresses based on vtxcnt. Instructions
2791 * generated for bases not used in following loop will be
2792 * stripped out in the backend.
2793 */
2794 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2795 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2796 unsigned stride = strmout->stride[i];
2797 struct ir3_instruction *base, *off;
2798
2799 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2800
2801 /* 24-bit should be enough: */
2802 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2803 create_immed(ctx->block, stride * 4), 0);
2804
2805 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2806 }
2807
2808 /* Generate the per-output store instructions: */
2809 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2810 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2811 unsigned c = j + strmout->output[i].start_component;
2812 struct ir3_instruction *base, *out, *stg;
2813
2814 base = bases[strmout->output[i].output_buffer];
2815 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2816
2817 stg = ir3_STG(ctx->block, base, 0, out, 0,
2818 create_immed(ctx->block, 1), 0);
2819 stg->cat6.type = TYPE_U32;
2820 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2821
2822 array_insert(ctx->block, ctx->block->keeps, stg);
2823 }
2824 }
2825
2826 /* and finally switch to the new_end_block: */
2827 ctx->block = new_end_block;
2828 }
2829
2830 static void
2831 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2832 {
2833 nir_metadata_require(impl, nir_metadata_block_index);
2834
2835 compile_assert(ctx, ctx->stack == 0);
2836
2837 emit_cf_list(ctx, &impl->body);
2838 emit_block(ctx, impl->end_block);
2839
2840 compile_assert(ctx, ctx->stack == 0);
2841
2842 /* at this point, we should have a single empty block,
2843 * into which we emit the 'end' instruction.
2844 */
2845 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2846
2847 /* If stream-out (aka transform-feedback) enabled, emit the
2848 * stream-out instructions, followed by a new empty block (into
2849 * which the 'end' instruction lands).
2850 *
2851 * NOTE: it is done in this order, rather than inserting before
2852 * we emit end_block, because NIR guarantees that all blocks
2853 * flow into end_block, and that end_block has no successors.
2854 * So by re-purposing end_block as the first block of stream-
2855 * out, we guarantee that all exit paths flow into the stream-
2856 * out instructions.
2857 */
2858 if ((ctx->compiler->gpu_id < 500) &&
2859 (ctx->so->shader->stream_output.num_outputs > 0) &&
2860 !ctx->so->binning_pass) {
2861 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2862 emit_stream_out(ctx);
2863 }
2864
2865 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2866 * NOP and has an epilogue that writes the VS outputs to local storage, to
2867 * be read by the HS. Then it resets execution mask (chmask) and chains
2868 * to the next shader (chsh).
2869 */
2870 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2871 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2872 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2873 struct ir3_instruction *chmask =
2874 ir3_CHMASK(ctx->block);
2875 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2876 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2877
2878 struct ir3_instruction *chsh =
2879 ir3_CHSH(ctx->block);
2880 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2881 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2882 } else {
2883 ir3_END(ctx->block);
2884 }
2885 }
2886
2887 static void
2888 setup_input(struct ir3_context *ctx, nir_variable *in)
2889 {
2890 struct ir3_shader_variant *so = ctx->so;
2891 unsigned ncomp = glsl_get_components(in->type);
2892 unsigned n = in->data.driver_location;
2893 unsigned frac = in->data.location_frac;
2894 unsigned slot = in->data.location;
2895
2896 /* Inputs are loaded using ldlw or ldg for these stages. */
2897 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2898 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2899 ctx->so->type == MESA_SHADER_GEOMETRY)
2900 return;
2901
2902 /* skip unread inputs, we could end up with (for example), unsplit
2903 * matrix/etc inputs in the case they are not read, so just silently
2904 * skip these.
2905 */
2906 if (ncomp > 4)
2907 return;
2908
2909 so->inputs[n].slot = slot;
2910 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2911 so->inputs_count = MAX2(so->inputs_count, n + 1);
2912 so->inputs[n].interpolate = in->data.interpolation;
2913
2914 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2915
2916 /* if any varyings have 'sample' qualifer, that triggers us
2917 * to run in per-sample mode:
2918 */
2919 so->per_samp |= in->data.sample;
2920
2921 for (int i = 0; i < ncomp; i++) {
2922 struct ir3_instruction *instr = NULL;
2923 unsigned idx = (n * 4) + i + frac;
2924
2925 if (slot == VARYING_SLOT_POS) {
2926 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2927 } else {
2928 /* detect the special case for front/back colors where
2929 * we need to do flat vs smooth shading depending on
2930 * rast state:
2931 */
2932 if (in->data.interpolation == INTERP_MODE_NONE) {
2933 switch (slot) {
2934 case VARYING_SLOT_COL0:
2935 case VARYING_SLOT_COL1:
2936 case VARYING_SLOT_BFC0:
2937 case VARYING_SLOT_BFC1:
2938 so->inputs[n].rasterflat = true;
2939 break;
2940 default:
2941 break;
2942 }
2943 }
2944
2945 if (ctx->compiler->flat_bypass) {
2946 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2947 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2948 so->inputs[n].use_ldlv = true;
2949 }
2950
2951 so->inputs[n].bary = true;
2952
2953 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2954 }
2955
2956 compile_assert(ctx, idx < ctx->ninputs);
2957
2958 ctx->inputs[idx] = instr;
2959 }
2960 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2961 struct ir3_instruction *input = NULL, *in;
2962 struct ir3_instruction *components[4];
2963 unsigned mask = (1 << (ncomp + frac)) - 1;
2964
2965 foreach_input (in, ctx->ir) {
2966 if (in->input.inidx == n) {
2967 input = in;
2968 break;
2969 }
2970 }
2971
2972 if (!input) {
2973 input = create_input(ctx, mask);
2974 input->input.inidx = n;
2975 } else {
2976 input->regs[0]->wrmask |= mask;
2977 }
2978
2979 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2980
2981 for (int i = 0; i < ncomp; i++) {
2982 unsigned idx = (n * 4) + i + frac;
2983 compile_assert(ctx, idx < ctx->ninputs);
2984 ctx->inputs[idx] = components[i];
2985 }
2986 } else {
2987 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2988 }
2989
2990 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2991 so->total_in += ncomp;
2992 }
2993 }
2994
2995 /* Initially we assign non-packed inloc's for varyings, as we don't really
2996 * know up-front which components will be unused. After all the compilation
2997 * stages we scan the shader to see which components are actually used, and
2998 * re-pack the inlocs to eliminate unneeded varyings.
2999 */
3000 static void
3001 pack_inlocs(struct ir3_context *ctx)
3002 {
3003 struct ir3_shader_variant *so = ctx->so;
3004 uint8_t used_components[so->inputs_count];
3005
3006 memset(used_components, 0, sizeof(used_components));
3007
3008 /*
3009 * First Step: scan shader to find which bary.f/ldlv remain:
3010 */
3011
3012 foreach_block (block, &ctx->ir->block_list) {
3013 foreach_instr (instr, &block->instr_list) {
3014 if (is_input(instr)) {
3015 unsigned inloc = instr->regs[1]->iim_val;
3016 unsigned i = inloc / 4;
3017 unsigned j = inloc % 4;
3018
3019 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3020 compile_assert(ctx, i < so->inputs_count);
3021
3022 used_components[i] |= 1 << j;
3023 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3024 for (int n = 0; n < 2; n++) {
3025 unsigned inloc = instr->prefetch.input_offset + n;
3026 unsigned i = inloc / 4;
3027 unsigned j = inloc % 4;
3028
3029 compile_assert(ctx, i < so->inputs_count);
3030
3031 used_components[i] |= 1 << j;
3032 }
3033 }
3034 }
3035 }
3036
3037 /*
3038 * Second Step: reassign varying inloc/slots:
3039 */
3040
3041 unsigned actual_in = 0;
3042 unsigned inloc = 0;
3043
3044 for (unsigned i = 0; i < so->inputs_count; i++) {
3045 unsigned compmask = 0, maxcomp = 0;
3046
3047 so->inputs[i].inloc = inloc;
3048 so->inputs[i].bary = false;
3049
3050 for (unsigned j = 0; j < 4; j++) {
3051 if (!(used_components[i] & (1 << j)))
3052 continue;
3053
3054 compmask |= (1 << j);
3055 actual_in++;
3056 maxcomp = j + 1;
3057
3058 /* at this point, since used_components[i] mask is only
3059 * considering varyings (ie. not sysvals) we know this
3060 * is a varying:
3061 */
3062 so->inputs[i].bary = true;
3063 }
3064
3065 if (so->inputs[i].bary) {
3066 so->varying_in++;
3067 so->inputs[i].compmask = (1 << maxcomp) - 1;
3068 inloc += maxcomp;
3069 }
3070 }
3071
3072 /*
3073 * Third Step: reassign packed inloc's:
3074 */
3075
3076 foreach_block (block, &ctx->ir->block_list) {
3077 foreach_instr (instr, &block->instr_list) {
3078 if (is_input(instr)) {
3079 unsigned inloc = instr->regs[1]->iim_val;
3080 unsigned i = inloc / 4;
3081 unsigned j = inloc % 4;
3082
3083 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3084 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3085 unsigned i = instr->prefetch.input_offset / 4;
3086 unsigned j = instr->prefetch.input_offset % 4;
3087 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3088 }
3089 }
3090 }
3091 }
3092
3093 static void
3094 setup_output(struct ir3_context *ctx, nir_variable *out)
3095 {
3096 struct ir3_shader_variant *so = ctx->so;
3097 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3098 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3099 unsigned n = out->data.driver_location;
3100 unsigned frac = out->data.location_frac;
3101 unsigned slot = out->data.location;
3102
3103 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3104 switch (slot) {
3105 case FRAG_RESULT_DEPTH:
3106 so->writes_pos = true;
3107 break;
3108 case FRAG_RESULT_COLOR:
3109 so->color0_mrt = 1;
3110 break;
3111 case FRAG_RESULT_SAMPLE_MASK:
3112 so->writes_smask = true;
3113 break;
3114 default:
3115 slot += out->data.index; /* For dual-src blend */
3116 if (slot >= FRAG_RESULT_DATA0)
3117 break;
3118 ir3_context_error(ctx, "unknown FS output name: %s\n",
3119 gl_frag_result_name(slot));
3120 }
3121 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3122 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3123 ctx->so->type == MESA_SHADER_GEOMETRY) {
3124 switch (slot) {
3125 case VARYING_SLOT_POS:
3126 so->writes_pos = true;
3127 break;
3128 case VARYING_SLOT_PSIZ:
3129 so->writes_psize = true;
3130 break;
3131 case VARYING_SLOT_PRIMITIVE_ID:
3132 case VARYING_SLOT_LAYER:
3133 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3134 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3135 /* fall through */
3136 case VARYING_SLOT_COL0:
3137 case VARYING_SLOT_COL1:
3138 case VARYING_SLOT_BFC0:
3139 case VARYING_SLOT_BFC1:
3140 case VARYING_SLOT_FOGC:
3141 case VARYING_SLOT_CLIP_DIST0:
3142 case VARYING_SLOT_CLIP_DIST1:
3143 case VARYING_SLOT_CLIP_VERTEX:
3144 break;
3145 default:
3146 if (slot >= VARYING_SLOT_VAR0)
3147 break;
3148 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3149 break;
3150 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3151 _mesa_shader_stage_to_string(ctx->so->type),
3152 gl_varying_slot_name(slot));
3153 }
3154 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3155 /* output lowered to buffer writes. */
3156 return;
3157 } else {
3158 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3159 }
3160
3161
3162 so->outputs_count = out->data.driver_location + slots;
3163 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3164
3165 for (int i = 0; i < slots; i++) {
3166 int slot_base = n + i;
3167 so->outputs[slot_base].slot = slot + i;
3168
3169 for (int i = 0; i < ncomp; i++) {
3170 unsigned idx = (slot_base * 4) + i + frac;
3171 compile_assert(ctx, idx < ctx->noutputs);
3172 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3173 }
3174
3175 /* if varying packing doesn't happen, we could end up in a situation
3176 * with "holes" in the output, and since the per-generation code that
3177 * sets up varying linkage registers doesn't expect to have more than
3178 * one varying per vec4 slot, pad the holes.
3179 *
3180 * Note that this should probably generate a performance warning of
3181 * some sort.
3182 */
3183 for (int i = 0; i < frac; i++) {
3184 unsigned idx = (slot_base * 4) + i;
3185 if (!ctx->outputs[idx]) {
3186 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3187 }
3188 }
3189 }
3190 }
3191
3192 static void
3193 emit_instructions(struct ir3_context *ctx)
3194 {
3195 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3196
3197 ctx->ninputs = ctx->s->num_inputs * 4;
3198 ctx->noutputs = ctx->s->num_outputs * 4;
3199 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3200 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3201
3202 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3203
3204 /* Create inputs in first block: */
3205 ctx->block = get_block(ctx, nir_start_block(fxn));
3206 ctx->in_block = ctx->block;
3207
3208 /* for fragment shader, the vcoord input register is used as the
3209 * base for bary.f varying fetch instrs:
3210 *
3211 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3212 * until emit_intrinsic when we know they are actually needed.
3213 * For now, we defer creating ctx->ij_centroid, etc, since we
3214 * only need ij_pixel for "old style" varying inputs (ie.
3215 * tgsi_to_nir)
3216 */
3217 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3218 ctx->ij_pixel = create_input(ctx, 0x3);
3219 }
3220
3221 /* Setup inputs: */
3222 nir_foreach_variable (var, &ctx->s->inputs) {
3223 setup_input(ctx, var);
3224 }
3225
3226 /* Defer add_sysval_input() stuff until after setup_inputs(),
3227 * because sysvals need to be appended after varyings:
3228 */
3229 if (ctx->ij_pixel) {
3230 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3231 0x3, ctx->ij_pixel);
3232 }
3233
3234
3235 /* Tesselation shaders always need primitive ID for indexing the
3236 * BO. Geometry shaders don't always need it but when they do it has be
3237 * delivered and unclobbered in the VS. To make things easy, we always
3238 * make room for it in VS/DS.
3239 */
3240 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3241 bool has_gs = ctx->so->key.has_gs;
3242 switch (ctx->so->type) {
3243 case MESA_SHADER_VERTEX:
3244 if (has_tess) {
3245 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3246 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3247 } else if (has_gs) {
3248 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3249 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3250 }
3251 break;
3252 case MESA_SHADER_TESS_CTRL:
3253 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3254 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3255 break;
3256 case MESA_SHADER_TESS_EVAL:
3257 if (has_gs)
3258 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3259 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3260 break;
3261 case MESA_SHADER_GEOMETRY:
3262 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3263 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3264 break;
3265 default:
3266 break;
3267 }
3268
3269 /* Setup outputs: */
3270 nir_foreach_variable (var, &ctx->s->outputs) {
3271 setup_output(ctx, var);
3272 }
3273
3274 /* Find # of samplers: */
3275 nir_foreach_variable (var, &ctx->s->uniforms) {
3276 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3277 /* just assume that we'll be reading from images.. if it
3278 * is write-only we don't have to count it, but not sure
3279 * if there is a good way to know?
3280 */
3281 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3282 }
3283
3284 /* NOTE: need to do something more clever when we support >1 fxn */
3285 nir_foreach_register (reg, &fxn->registers) {
3286 ir3_declare_array(ctx, reg);
3287 }
3288 /* And emit the body: */
3289 ctx->impl = fxn;
3290 emit_function(ctx, fxn);
3291 }
3292
3293 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3294 * need to assign the tex state indexes for these after we know the
3295 * max tex index.
3296 */
3297 static void
3298 fixup_astc_srgb(struct ir3_context *ctx)
3299 {
3300 struct ir3_shader_variant *so = ctx->so;
3301 /* indexed by original tex idx, value is newly assigned alpha sampler
3302 * state tex idx. Zero is invalid since there is at least one sampler
3303 * if we get here.
3304 */
3305 unsigned alt_tex_state[16] = {0};
3306 unsigned tex_idx = ctx->max_texture_index + 1;
3307 unsigned idx = 0;
3308
3309 so->astc_srgb.base = tex_idx;
3310
3311 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3312 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3313
3314 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3315
3316 if (alt_tex_state[sam->cat5.tex] == 0) {
3317 /* assign new alternate/alpha tex state slot: */
3318 alt_tex_state[sam->cat5.tex] = tex_idx++;
3319 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3320 so->astc_srgb.count++;
3321 }
3322
3323 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3324 }
3325 }
3326
3327 static void
3328 fixup_binning_pass(struct ir3_context *ctx)
3329 {
3330 struct ir3_shader_variant *so = ctx->so;
3331 struct ir3 *ir = ctx->ir;
3332 unsigned i, j;
3333
3334 /* first pass, remove unused outputs from the IR level outputs: */
3335 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3336 struct ir3_instruction *out = ir->outputs[i];
3337 assert(out->opc == OPC_META_COLLECT);
3338 unsigned outidx = out->collect.outidx;
3339 unsigned slot = so->outputs[outidx].slot;
3340
3341 /* throw away everything but first position/psize */
3342 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3343 ir->outputs[j] = ir->outputs[i];
3344 j++;
3345 }
3346 }
3347 ir->outputs_count = j;
3348
3349 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3350 * table:
3351 */
3352 for (i = 0, j = 0; i < so->outputs_count; i++) {
3353 unsigned slot = so->outputs[i].slot;
3354
3355 /* throw away everything but first position/psize */
3356 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3357 so->outputs[j] = so->outputs[i];
3358
3359 /* fixup outidx to point to new output table entry: */
3360 struct ir3_instruction *out;
3361 foreach_output (out, ir) {
3362 if (out->collect.outidx == i) {
3363 out->collect.outidx = j;
3364 break;
3365 }
3366 }
3367
3368 j++;
3369 }
3370 }
3371 so->outputs_count = j;
3372 }
3373
3374 static void
3375 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3376 {
3377 unsigned idx = 0;
3378
3379 /* Collect sampling instructions eligible for pre-dispatch. */
3380 foreach_block (block, &ir->block_list) {
3381 foreach_instr_safe (instr, &block->instr_list) {
3382 if (instr->opc == OPC_META_TEX_PREFETCH) {
3383 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3384 struct ir3_sampler_prefetch *fetch =
3385 &ctx->so->sampler_prefetch[idx];
3386 idx++;
3387
3388 if (instr->flags & IR3_INSTR_B) {
3389 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3390 /* In bindless mode, the index is actually the base */
3391 fetch->tex_id = instr->prefetch.tex_base;
3392 fetch->samp_id = instr->prefetch.samp_base;
3393 fetch->tex_bindless_id = instr->prefetch.tex;
3394 fetch->samp_bindless_id = instr->prefetch.samp;
3395 } else {
3396 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3397 fetch->tex_id = instr->prefetch.tex;
3398 fetch->samp_id = instr->prefetch.samp;
3399 }
3400 fetch->wrmask = instr->regs[0]->wrmask;
3401 fetch->dst = instr->regs[0]->num;
3402 fetch->src = instr->prefetch.input_offset;
3403
3404 ctx->so->total_in =
3405 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3406
3407 /* Disable half precision until supported. */
3408 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3409
3410 /* Remove the prefetch placeholder instruction: */
3411 list_delinit(&instr->node);
3412 }
3413 }
3414 }
3415 }
3416
3417 int
3418 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3419 struct ir3_shader_variant *so)
3420 {
3421 struct ir3_context *ctx;
3422 struct ir3 *ir;
3423 int ret = 0, max_bary;
3424
3425 assert(!so->ir);
3426
3427 ctx = ir3_context_init(compiler, so);
3428 if (!ctx) {
3429 DBG("INIT failed!");
3430 ret = -1;
3431 goto out;
3432 }
3433
3434 emit_instructions(ctx);
3435
3436 if (ctx->error) {
3437 DBG("EMIT failed!");
3438 ret = -1;
3439 goto out;
3440 }
3441
3442 ir = so->ir = ctx->ir;
3443
3444 assert((ctx->noutputs % 4) == 0);
3445
3446 /* Setup IR level outputs, which are "collects" that gather
3447 * the scalar components of outputs.
3448 */
3449 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3450 unsigned ncomp = 0;
3451 /* figure out the # of components written:
3452 *
3453 * TODO do we need to handle holes, ie. if .x and .z
3454 * components written, but .y component not written?
3455 */
3456 for (unsigned j = 0; j < 4; j++) {
3457 if (!ctx->outputs[i + j])
3458 break;
3459 ncomp++;
3460 }
3461
3462 /* Note that in some stages, like TCS, store_output is
3463 * lowered to memory writes, so no components of the
3464 * are "written" from the PoV of traditional store-
3465 * output instructions:
3466 */
3467 if (!ncomp)
3468 continue;
3469
3470 struct ir3_instruction *out =
3471 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3472
3473 int outidx = i / 4;
3474 assert(outidx < so->outputs_count);
3475
3476 /* stash index into so->outputs[] so we can map the
3477 * output back to slot/etc later:
3478 */
3479 out->collect.outidx = outidx;
3480
3481 array_insert(ir, ir->outputs, out);
3482 }
3483
3484 /* Set up the gs header as an output for the vertex shader so it won't
3485 * clobber it for the tess ctrl shader.
3486 *
3487 * TODO this could probably be done more cleanly in a nir pass.
3488 */
3489 if (ctx->so->type == MESA_SHADER_VERTEX ||
3490 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3491 if (ctx->primitive_id) {
3492 unsigned n = so->outputs_count++;
3493 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3494
3495 struct ir3_instruction *out =
3496 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3497 out->collect.outidx = n;
3498 array_insert(ir, ir->outputs, out);
3499 }
3500
3501 if (ctx->gs_header) {
3502 unsigned n = so->outputs_count++;
3503 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3504 struct ir3_instruction *out =
3505 ir3_create_collect(ctx, &ctx->gs_header, 1);
3506 out->collect.outidx = n;
3507 array_insert(ir, ir->outputs, out);
3508 }
3509
3510 if (ctx->tcs_header) {
3511 unsigned n = so->outputs_count++;
3512 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3513 struct ir3_instruction *out =
3514 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3515 out->collect.outidx = n;
3516 array_insert(ir, ir->outputs, out);
3517 }
3518 }
3519
3520 /* at this point, for binning pass, throw away unneeded outputs: */
3521 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3522 fixup_binning_pass(ctx);
3523
3524 ir3_debug_print(ir, "BEFORE CF");
3525
3526 ir3_cf(ir);
3527
3528 ir3_debug_print(ir, "BEFORE CP");
3529
3530 ir3_cp(ir, so);
3531
3532 /* at this point, for binning pass, throw away unneeded outputs:
3533 * Note that for a6xx and later, we do this after ir3_cp to ensure
3534 * that the uniform/constant layout for BS and VS matches, so that
3535 * we can re-use same VS_CONST state group.
3536 */
3537 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3538 fixup_binning_pass(ctx);
3539
3540 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3541 * need to make sure not to remove any inputs that are used by
3542 * the nonbinning VS.
3543 */
3544 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3545 so->type == MESA_SHADER_VERTEX) {
3546 for (int i = 0; i < ctx->ninputs; i++) {
3547 struct ir3_instruction *in = ctx->inputs[i];
3548
3549 if (!in)
3550 continue;
3551
3552 unsigned n = i / 4;
3553 unsigned c = i % 4;
3554
3555 debug_assert(n < so->nonbinning->inputs_count);
3556
3557 if (so->nonbinning->inputs[n].sysval)
3558 continue;
3559
3560 /* be sure to keep inputs, even if only used in VS */
3561 if (so->nonbinning->inputs[n].compmask & (1 << c))
3562 array_insert(in->block, in->block->keeps, in);
3563 }
3564 }
3565
3566 ir3_debug_print(ir, "BEFORE GROUPING");
3567
3568 ir3_sched_add_deps(ir);
3569
3570 /* Group left/right neighbors, inserting mov's where needed to
3571 * solve conflicts:
3572 */
3573 ir3_group(ir);
3574
3575 ir3_debug_print(ir, "AFTER GROUPING");
3576
3577 ir3_dce(ir, so);
3578
3579 ir3_debug_print(ir, "AFTER DCE");
3580
3581 /* do Sethi–Ullman numbering before scheduling: */
3582 ir3_sun(ir);
3583
3584 ret = ir3_sched(ir);
3585 if (ret) {
3586 DBG("SCHED failed!");
3587 goto out;
3588 }
3589
3590 ir3_debug_print(ir, "AFTER SCHED");
3591
3592 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3593 * with draw pass VS, so binning and draw pass can both use the
3594 * same VBO state.
3595 *
3596 * Note that VS inputs are expected to be full precision.
3597 */
3598 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3599 (ir->type == MESA_SHADER_VERTEX) &&
3600 so->binning_pass;
3601
3602 if (pre_assign_inputs) {
3603 for (unsigned i = 0; i < ctx->ninputs; i++) {
3604 struct ir3_instruction *instr = ctx->inputs[i];
3605
3606 if (!instr)
3607 continue;
3608
3609 unsigned n = i / 4;
3610 unsigned c = i % 4;
3611 unsigned regid = so->nonbinning->inputs[n].regid + c;
3612
3613 instr->regs[0]->num = regid;
3614 }
3615
3616 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3617 } else if (ctx->tcs_header) {
3618 /* We need to have these values in the same registers between VS and TCS
3619 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3620 */
3621
3622 ctx->tcs_header->regs[0]->num = regid(0, 0);
3623 ctx->primitive_id->regs[0]->num = regid(0, 1);
3624 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3625 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3626 } else if (ctx->gs_header) {
3627 /* We need to have these values in the same registers between producer
3628 * (VS or DS) and GS since the producer chains to GS and doesn't get
3629 * the sysvals redelivered.
3630 */
3631
3632 ctx->gs_header->regs[0]->num = regid(0, 0);
3633 ctx->primitive_id->regs[0]->num = regid(0, 1);
3634 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3635 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3636 } else if (so->num_sampler_prefetch) {
3637 assert(so->type == MESA_SHADER_FRAGMENT);
3638 struct ir3_instruction *instr, *precolor[2];
3639 int idx = 0;
3640
3641 foreach_input (instr, ir) {
3642 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3643 continue;
3644
3645 assert(idx < ARRAY_SIZE(precolor));
3646
3647 precolor[idx] = instr;
3648 instr->regs[0]->num = idx;
3649
3650 idx++;
3651 }
3652 ret = ir3_ra(so, precolor, idx);
3653 } else {
3654 ret = ir3_ra(so, NULL, 0);
3655 }
3656
3657 if (ret) {
3658 DBG("RA failed!");
3659 goto out;
3660 }
3661
3662 ir3_postsched(ctx);
3663 ir3_debug_print(ir, "AFTER POSTSCHED");
3664
3665 if (compiler->gpu_id >= 600) {
3666 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3667 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3668 }
3669 }
3670
3671 if (so->type == MESA_SHADER_FRAGMENT)
3672 pack_inlocs(ctx);
3673
3674 /*
3675 * Fixup inputs/outputs to point to the actual registers assigned:
3676 *
3677 * 1) initialize to r63.x (invalid/unused)
3678 * 2) iterate IR level inputs/outputs and update the variants
3679 * inputs/outputs table based on the assigned registers for
3680 * the remaining inputs/outputs.
3681 */
3682
3683 for (unsigned i = 0; i < so->inputs_count; i++)
3684 so->inputs[i].regid = INVALID_REG;
3685 for (unsigned i = 0; i < so->outputs_count; i++)
3686 so->outputs[i].regid = INVALID_REG;
3687
3688 struct ir3_instruction *out;
3689 foreach_output (out, ir) {
3690 assert(out->opc == OPC_META_COLLECT);
3691 unsigned outidx = out->collect.outidx;
3692
3693 so->outputs[outidx].regid = out->regs[0]->num;
3694 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3695 }
3696
3697 struct ir3_instruction *in;
3698 foreach_input (in, ir) {
3699 assert(in->opc == OPC_META_INPUT);
3700 unsigned inidx = in->input.inidx;
3701
3702 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3703 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3704 compile_assert(ctx, in->regs[0]->num ==
3705 so->nonbinning->inputs[inidx].regid);
3706 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3707 so->nonbinning->inputs[inidx].half);
3708 }
3709 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3710 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3711 } else {
3712 so->inputs[inidx].regid = in->regs[0]->num;
3713 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3714 }
3715 }
3716
3717 if (ctx->astc_srgb)
3718 fixup_astc_srgb(ctx);
3719
3720 /* We need to do legalize after (for frag shader's) the "bary.f"
3721 * offsets (inloc) have been assigned.
3722 */
3723 ir3_legalize(ir, so, &max_bary);
3724
3725 ir3_debug_print(ir, "AFTER LEGALIZE");
3726
3727 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3728 * know what we might have to wait on when coming in from VS chsh.
3729 */
3730 if (so->type == MESA_SHADER_TESS_CTRL ||
3731 so->type == MESA_SHADER_GEOMETRY ) {
3732 foreach_block (block, &ir->block_list) {
3733 foreach_instr (instr, &block->instr_list) {
3734 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3735 break;
3736 }
3737 }
3738 }
3739
3740 so->branchstack = ctx->max_stack;
3741
3742 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3743 if (so->type == MESA_SHADER_FRAGMENT)
3744 so->total_in = max_bary + 1;
3745
3746 so->max_sun = ir->max_sun;
3747
3748 /* Collect sampling instructions eligible for pre-dispatch. */
3749 collect_tex_prefetches(ctx, ir);
3750
3751 if (so->type == MESA_SHADER_FRAGMENT &&
3752 ctx->s->info.fs.needs_helper_invocations)
3753 so->need_pixlod = true;
3754
3755 out:
3756 if (ret) {
3757 if (so->ir)
3758 ir3_destroy(so->ir);
3759 so->ir = NULL;
3760 }
3761 ir3_context_free(ctx);
3762
3763 return ret;
3764 }