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freedreno/ir3: add generic get_barycentric()
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42 void
43 ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
44 {
45 nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
46 if (!intrin)
47 return;
48
49 instr->flags |= IR3_INSTR_B;
50 instr->cat6.base = nir_intrinsic_desc_set(intrin);
51 }
52
53 static struct ir3_instruction *
54 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
55 struct ir3_instruction *address, struct ir3_instruction *collect)
56 {
57 struct ir3_block *block = ctx->block;
58 struct ir3_instruction *mov;
59 struct ir3_register *src;
60
61 mov = ir3_instr_create(block, OPC_MOV);
62 mov->cat1.src_type = TYPE_U32;
63 mov->cat1.dst_type = TYPE_U32;
64 __ssa_dst(mov);
65 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
66 src->size = arrsz;
67 src->array.offset = n;
68
69 ir3_instr_set_address(mov, address);
70
71 return mov;
72 }
73
74 static struct ir3_instruction *
75 create_input(struct ir3_context *ctx, unsigned compmask)
76 {
77 struct ir3_instruction *in;
78
79 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
80 in->input.sysval = ~0;
81 __ssa_dst(in)->wrmask = compmask;
82
83 array_insert(ctx->ir, ctx->ir->inputs, in);
84
85 return in;
86 }
87
88 static struct ir3_instruction *
89 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
90 {
91 struct ir3_block *block = ctx->block;
92 struct ir3_instruction *instr;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction *inloc = create_immed(block, n);
95
96 if (use_ldlv) {
97 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
98 instr->cat6.type = TYPE_U32;
99 instr->cat6.iim_val = 1;
100 } else {
101 instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0);
102 instr->regs[2]->wrmask = 0x3;
103 }
104
105 return instr;
106 }
107
108 static struct ir3_instruction *
109 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
110 {
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
114 unsigned n = const_state->offsets.driver_param;
115 unsigned r = regid(n + dp / 4, dp % 4);
116 return create_uniform(ctx->block, r);
117 }
118
119 /*
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
124 * 0.
125 */
126
127 /*
128 * alu/sfu instructions:
129 */
130
131 static struct ir3_instruction *
132 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
133 unsigned src_bitsize, nir_op op)
134 {
135 type_t src_type, dst_type;
136
137 switch (op) {
138 case nir_op_f2f32:
139 case nir_op_f2f16_rtne:
140 case nir_op_f2f16_rtz:
141 case nir_op_f2f16:
142 case nir_op_f2i32:
143 case nir_op_f2i16:
144 case nir_op_f2i8:
145 case nir_op_f2u32:
146 case nir_op_f2u16:
147 case nir_op_f2u8:
148 switch (src_bitsize) {
149 case 32:
150 src_type = TYPE_F32;
151 break;
152 case 16:
153 src_type = TYPE_F16;
154 break;
155 default:
156 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
157 }
158 break;
159
160 case nir_op_i2f32:
161 case nir_op_i2f16:
162 case nir_op_i2i32:
163 case nir_op_i2i16:
164 case nir_op_i2i8:
165 switch (src_bitsize) {
166 case 32:
167 src_type = TYPE_S32;
168 break;
169 case 16:
170 src_type = TYPE_S16;
171 break;
172 case 8:
173 src_type = TYPE_S8;
174 break;
175 default:
176 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
177 }
178 break;
179
180 case nir_op_u2f32:
181 case nir_op_u2f16:
182 case nir_op_u2u32:
183 case nir_op_u2u16:
184 case nir_op_u2u8:
185 switch (src_bitsize) {
186 case 32:
187 src_type = TYPE_U32;
188 break;
189 case 16:
190 src_type = TYPE_U16;
191 break;
192 case 8:
193 src_type = TYPE_U8;
194 break;
195 default:
196 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
197 }
198 break;
199
200 case nir_op_b2f16:
201 case nir_op_b2f32:
202 case nir_op_b2i8:
203 case nir_op_b2i16:
204 case nir_op_b2i32:
205 src_type = TYPE_U32;
206 break;
207
208 default:
209 ir3_context_error(ctx, "invalid conversion op: %u", op);
210 }
211
212 switch (op) {
213 case nir_op_f2f32:
214 case nir_op_i2f32:
215 case nir_op_u2f32:
216 case nir_op_b2f32:
217 dst_type = TYPE_F32;
218 break;
219
220 case nir_op_f2f16_rtne:
221 case nir_op_f2f16_rtz:
222 case nir_op_f2f16:
223 case nir_op_i2f16:
224 case nir_op_u2f16:
225 case nir_op_b2f16:
226 dst_type = TYPE_F16;
227 break;
228
229 case nir_op_f2i32:
230 case nir_op_i2i32:
231 case nir_op_b2i32:
232 dst_type = TYPE_S32;
233 break;
234
235 case nir_op_f2i16:
236 case nir_op_i2i16:
237 case nir_op_b2i16:
238 dst_type = TYPE_S16;
239 break;
240
241 case nir_op_f2i8:
242 case nir_op_i2i8:
243 case nir_op_b2i8:
244 dst_type = TYPE_S8;
245 break;
246
247 case nir_op_f2u32:
248 case nir_op_u2u32:
249 dst_type = TYPE_U32;
250 break;
251
252 case nir_op_f2u16:
253 case nir_op_u2u16:
254 dst_type = TYPE_U16;
255 break;
256
257 case nir_op_f2u8:
258 case nir_op_u2u8:
259 dst_type = TYPE_U8;
260 break;
261
262 default:
263 ir3_context_error(ctx, "invalid conversion op: %u", op);
264 }
265
266 if (src_type == dst_type)
267 return src;
268
269 struct ir3_instruction *cov =
270 ir3_COV(ctx->block, src, src_type, dst_type);
271
272 if (op == nir_op_f2f16_rtne)
273 cov->regs[0]->flags |= IR3_REG_EVEN;
274
275 return cov;
276 }
277
278 static void
279 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
280 {
281 const nir_op_info *info = &nir_op_infos[alu->op];
282 struct ir3_instruction **dst, *src[info->num_inputs];
283 unsigned bs[info->num_inputs]; /* bit size */
284 struct ir3_block *b = ctx->block;
285 unsigned dst_sz, wrmask;
286 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
287 TYPE_U16 : TYPE_U32;
288
289 if (alu->dest.dest.is_ssa) {
290 dst_sz = alu->dest.dest.ssa.num_components;
291 wrmask = (1 << dst_sz) - 1;
292 } else {
293 dst_sz = alu->dest.dest.reg.reg->num_components;
294 wrmask = alu->dest.write_mask;
295 }
296
297 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
298
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
302 */
303 if ((alu->op == nir_op_vec2) ||
304 (alu->op == nir_op_vec3) ||
305 (alu->op == nir_op_vec4)) {
306
307 for (int i = 0; i < info->num_inputs; i++) {
308 nir_alu_src *asrc = &alu->src[i];
309
310 compile_assert(ctx, !asrc->abs);
311 compile_assert(ctx, !asrc->negate);
312
313 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
314 if (!src[i])
315 src[i] = create_immed_typed(ctx->block, 0, dst_type);
316 dst[i] = ir3_MOV(b, src[i], dst_type);
317 }
318
319 ir3_put_dst(ctx, &alu->dest.dest);
320 return;
321 }
322
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
325 */
326 if (alu->op == nir_op_mov) {
327 nir_alu_src *asrc = &alu->src[0];
328 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
329
330 for (unsigned i = 0; i < dst_sz; i++) {
331 if (wrmask & (1 << i)) {
332 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
333 } else {
334 dst[i] = NULL;
335 }
336 }
337
338 ir3_put_dst(ctx, &alu->dest.dest);
339 return;
340 }
341
342 /* General case: We can just grab the one used channel per src. */
343 for (int i = 0; i < info->num_inputs; i++) {
344 unsigned chan = ffs(alu->dest.write_mask) - 1;
345 nir_alu_src *asrc = &alu->src[i];
346
347 compile_assert(ctx, !asrc->abs);
348 compile_assert(ctx, !asrc->negate);
349
350 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
351 bs[i] = nir_src_bit_size(asrc->src);
352
353 compile_assert(ctx, src[i]);
354 }
355
356 switch (alu->op) {
357 case nir_op_f2f32:
358 case nir_op_f2f16_rtne:
359 case nir_op_f2f16_rtz:
360 case nir_op_f2f16:
361 case nir_op_f2i32:
362 case nir_op_f2i16:
363 case nir_op_f2i8:
364 case nir_op_f2u32:
365 case nir_op_f2u16:
366 case nir_op_f2u8:
367 case nir_op_i2f32:
368 case nir_op_i2f16:
369 case nir_op_i2i32:
370 case nir_op_i2i16:
371 case nir_op_i2i8:
372 case nir_op_u2f32:
373 case nir_op_u2f16:
374 case nir_op_u2u32:
375 case nir_op_u2u16:
376 case nir_op_u2u8:
377 case nir_op_b2f16:
378 case nir_op_b2f32:
379 case nir_op_b2i8:
380 case nir_op_b2i16:
381 case nir_op_b2i32:
382 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
383 break;
384
385 case nir_op_fquantize2f16:
386 dst[0] = create_cov(ctx,
387 create_cov(ctx, src[0], 32, nir_op_f2f16),
388 16, nir_op_f2f32);
389 break;
390 case nir_op_f2b1:
391 dst[0] = ir3_CMPS_F(b,
392 src[0], 0,
393 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
394 dst[0]->cat2.condition = IR3_COND_NE;
395 break;
396
397 case nir_op_i2b1:
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
400 */
401 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
402 dst[0]->cat2.condition = IR3_COND_NE;
403 break;
404
405 case nir_op_b2b1:
406 /* b2b1 will appear when translating from
407 *
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
410 *
411 * A negate can turn those into a 1 or 0 for us.
412 */
413 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
414 break;
415
416 case nir_op_b2b32:
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
418 * argument.
419 *
420 * A negate can turn those into a ~0 for us.
421 */
422 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
423 break;
424
425 case nir_op_fneg:
426 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
427 break;
428 case nir_op_fabs:
429 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
430 break;
431 case nir_op_fmax:
432 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
433 break;
434 case nir_op_fmin:
435 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
436 break;
437 case nir_op_fsat:
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
441 * to eliminate.
442 *
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
445 * everywhere.
446 *
447 * TODO probably opc_cat==4 is ok too
448 */
449 if (alu->src[0].src.is_ssa &&
450 src[0]->opc != OPC_BARY_F &&
451 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
452 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
453 src[0]->flags |= IR3_INSTR_SAT;
454 dst[0] = ir3_MOV(b, src[0], dst_type);
455 } else {
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
458 */
459 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
460 dst[0]->flags |= IR3_INSTR_SAT;
461 }
462 break;
463 case nir_op_fmul:
464 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
465 break;
466 case nir_op_fadd:
467 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
468 break;
469 case nir_op_fsub:
470 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
471 break;
472 case nir_op_ffma:
473 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
474 break;
475 case nir_op_fddx:
476 case nir_op_fddx_coarse:
477 dst[0] = ir3_DSX(b, src[0], 0);
478 dst[0]->cat5.type = TYPE_F32;
479 break;
480 case nir_op_fddx_fine:
481 dst[0] = ir3_DSXPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_fddy:
485 case nir_op_fddy_coarse:
486 dst[0] = ir3_DSY(b, src[0], 0);
487 dst[0]->cat5.type = TYPE_F32;
488 break;
489 break;
490 case nir_op_fddy_fine:
491 dst[0] = ir3_DSYPP_1(b, src[0], 0);
492 dst[0]->cat5.type = TYPE_F32;
493 break;
494 case nir_op_flt:
495 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
496 dst[0]->cat2.condition = IR3_COND_LT;
497 break;
498 case nir_op_fge:
499 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
500 dst[0]->cat2.condition = IR3_COND_GE;
501 break;
502 case nir_op_feq:
503 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
504 dst[0]->cat2.condition = IR3_COND_EQ;
505 break;
506 case nir_op_fne:
507 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
508 dst[0]->cat2.condition = IR3_COND_NE;
509 break;
510 case nir_op_fceil:
511 dst[0] = ir3_CEIL_F(b, src[0], 0);
512 break;
513 case nir_op_ffloor:
514 dst[0] = ir3_FLOOR_F(b, src[0], 0);
515 break;
516 case nir_op_ftrunc:
517 dst[0] = ir3_TRUNC_F(b, src[0], 0);
518 break;
519 case nir_op_fround_even:
520 dst[0] = ir3_RNDNE_F(b, src[0], 0);
521 break;
522 case nir_op_fsign:
523 dst[0] = ir3_SIGN_F(b, src[0], 0);
524 break;
525
526 case nir_op_fsin:
527 dst[0] = ir3_SIN(b, src[0], 0);
528 break;
529 case nir_op_fcos:
530 dst[0] = ir3_COS(b, src[0], 0);
531 break;
532 case nir_op_frsq:
533 dst[0] = ir3_RSQ(b, src[0], 0);
534 break;
535 case nir_op_frcp:
536 dst[0] = ir3_RCP(b, src[0], 0);
537 break;
538 case nir_op_flog2:
539 dst[0] = ir3_LOG2(b, src[0], 0);
540 break;
541 case nir_op_fexp2:
542 dst[0] = ir3_EXP2(b, src[0], 0);
543 break;
544 case nir_op_fsqrt:
545 dst[0] = ir3_SQRT(b, src[0], 0);
546 break;
547
548 case nir_op_iabs:
549 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
550 break;
551 case nir_op_iadd:
552 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_iand:
555 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imax:
558 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umax:
561 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_imin:
564 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_umin:
567 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_umul_low:
570 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_imadsh_mix16:
573 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
574 break;
575 case nir_op_imad24_ir3:
576 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
577 break;
578 case nir_op_imul24:
579 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
580 break;
581 case nir_op_ineg:
582 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
583 break;
584 case nir_op_inot:
585 if (bs[0] == 1) {
586 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
587 } else {
588 dst[0] = ir3_NOT_B(b, src[0], 0);
589 }
590 break;
591 case nir_op_ior:
592 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ishl:
595 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
596 break;
597 case nir_op_ishr:
598 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
599 break;
600 case nir_op_isub:
601 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
602 break;
603 case nir_op_ixor:
604 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
605 break;
606 case nir_op_ushr:
607 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
608 break;
609 case nir_op_ilt:
610 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
611 dst[0]->cat2.condition = IR3_COND_LT;
612 break;
613 case nir_op_ige:
614 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
615 dst[0]->cat2.condition = IR3_COND_GE;
616 break;
617 case nir_op_ieq:
618 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_EQ;
620 break;
621 case nir_op_ine:
622 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
623 dst[0]->cat2.condition = IR3_COND_NE;
624 break;
625 case nir_op_ult:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_LT;
628 break;
629 case nir_op_uge:
630 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
631 dst[0]->cat2.condition = IR3_COND_GE;
632 break;
633
634 case nir_op_bcsel: {
635 struct ir3_instruction *cond = src[0];
636
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
640 */
641 if (cond->opc == OPC_ABSNEG_S &&
642 cond->flags == 0 &&
643 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
644 cond = cond->regs[1]->instr;
645 }
646
647 compile_assert(ctx, bs[1] == bs[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
650 */
651 if (bs[1] == 16) {
652 struct hash_entry *prev_entry =
653 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
654 if (prev_entry) {
655 cond = prev_entry->data;
656 } else {
657 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
658 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
659 }
660 }
661
662 if (bs[1] != 16)
663 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
664 else
665 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
666 break;
667 }
668 case nir_op_bit_count: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction *hi, *lo;
673
674 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
675 TYPE_U32, TYPE_U16);
676 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
677
678 hi = ir3_CBITS_B(b, hi, 0);
679 lo = ir3_CBITS_B(b, lo, 0);
680
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi->regs[0]->flags |= IR3_REG_HALF;
685 lo->regs[0]->flags |= IR3_REG_HALF;
686
687 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
688 dst[0]->regs[0]->flags |= IR3_REG_HALF;
689 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
690 break;
691 }
692 case nir_op_ifind_msb: {
693 struct ir3_instruction *cmp;
694 dst[0] = ir3_CLZ_S(b, src[0], 0);
695 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
696 cmp->cat2.condition = IR3_COND_GE;
697 dst[0] = ir3_SEL_B32(b,
698 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
699 cmp, 0, dst[0], 0);
700 break;
701 }
702 case nir_op_ufind_msb:
703 dst[0] = ir3_CLZ_B(b, src[0], 0);
704 dst[0] = ir3_SEL_B32(b,
705 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
706 src[0], 0, dst[0], 0);
707 break;
708 case nir_op_find_lsb:
709 dst[0] = ir3_BFREV_B(b, src[0], 0);
710 dst[0] = ir3_CLZ_B(b, dst[0], 0);
711 break;
712 case nir_op_bitfield_reverse:
713 dst[0] = ir3_BFREV_B(b, src[0], 0);
714 break;
715
716 default:
717 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
718 nir_op_infos[alu->op].name);
719 break;
720 }
721
722 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
723 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
724 alu->op == nir_op_b2b32);
725 assert(dst_sz == 1);
726 } else {
727 /* 1-bit values stored in 32-bit registers are only valid for certain
728 * ALU ops.
729 */
730 switch (alu->op) {
731 case nir_op_iand:
732 case nir_op_ior:
733 case nir_op_ixor:
734 case nir_op_inot:
735 case nir_op_bcsel:
736 break;
737 default:
738 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
739 }
740 }
741
742 ir3_put_dst(ctx, &alu->dest.dest);
743 }
744
745 static void
746 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
747 struct ir3_instruction **dst)
748 {
749 struct ir3_block *b = ctx->block;
750
751 unsigned ncomp = intr->num_components;
752 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
753 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
754 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
755 ldc->regs[0]->wrmask = MASK(ncomp);
756 ldc->cat6.iim_val = ncomp;
757 ldc->cat6.d = nir_intrinsic_base(intr);
758 ldc->cat6.type = TYPE_U32;
759
760 ir3_handle_bindless_cat6(ldc, intr->src[0]);
761 if (ldc->flags & IR3_INSTR_B)
762 ctx->so->bindless_ubo = true;
763
764 ir3_split_dest(b, dst, ldc, 0, ncomp);
765 }
766
767
768 /* handles direct/indirect UBO reads: */
769 static void
770 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
771 struct ir3_instruction **dst)
772 {
773 struct ir3_block *b = ctx->block;
774 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
775 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
776 unsigned ubo = regid(const_state->offsets.ubo, 0);
777 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
778
779 int off = 0;
780
781 /* First src is ubo index, which could either be an immed or not: */
782 src0 = ir3_get_src(ctx, &intr->src[0])[0];
783 if (is_same_type_mov(src0) &&
784 (src0->regs[1]->flags & IR3_REG_IMMED)) {
785 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
786 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
787 } else {
788 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
789 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
790
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
794 */
795 ctx->so->constlen = MAX2(ctx->so->constlen,
796 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
797 }
798
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
800 addr = base_lo;
801
802 if (nir_src_is_const(intr->src[1])) {
803 off += nir_src_as_uint(intr->src[1]);
804 } else {
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1 = ir3_get_src(ctx, &intr->src[1])[0];
807
808 /* and add offset to addr: */
809 addr = ir3_ADD_S(b, addr, 0, src1, 0);
810 }
811
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off + (intr->num_components * 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
816 */
817 unsigned off2 = off + (intr->num_components * 4) - 1024;
818 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
819 off -= off2;
820 }
821
822 if (ptrsz == 2) {
823 struct ir3_instruction *carry;
824
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
827 * base_hi++
828 */
829 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
830 carry->cat2.condition = IR3_COND_LT;
831 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
832
833 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
834 }
835
836 for (int i = 0; i < intr->num_components; i++) {
837 struct ir3_instruction *load =
838 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
839 create_immed(b, off + i * 4), 0);
840 load->cat6.type = TYPE_U32;
841 dst[i] = load;
842 }
843 }
844
845 /* src[] = { block_index } */
846 static void
847 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
848 struct ir3_instruction **dst)
849 {
850 /* SSBO size stored as a const starting at ssbo_sizes: */
851 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
852 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
853 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
854 const_state->ssbo_size.off[blk_idx];
855
856 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
857
858 dst[0] = create_uniform(ctx->block, idx);
859 }
860
861 /* src[] = { offset }. const_index[] = { base } */
862 static void
863 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
864 struct ir3_instruction **dst)
865 {
866 struct ir3_block *b = ctx->block;
867 struct ir3_instruction *ldl, *offset;
868 unsigned base;
869
870 offset = ir3_get_src(ctx, &intr->src[0])[0];
871 base = nir_intrinsic_base(intr);
872
873 ldl = ir3_LDL(b, offset, 0,
874 create_immed(b, intr->num_components), 0,
875 create_immed(b, base), 0);
876
877 ldl->cat6.type = utype_dst(intr->dest);
878 ldl->regs[0]->wrmask = MASK(intr->num_components);
879
880 ldl->barrier_class = IR3_BARRIER_SHARED_R;
881 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
882
883 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
884 }
885
886 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
887 static void
888 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
889 {
890 struct ir3_block *b = ctx->block;
891 struct ir3_instruction *stl, *offset;
892 struct ir3_instruction * const *value;
893 unsigned base, wrmask, ncomp;
894
895 value = ir3_get_src(ctx, &intr->src[0]);
896 offset = ir3_get_src(ctx, &intr->src[1])[0];
897
898 base = nir_intrinsic_base(intr);
899 wrmask = nir_intrinsic_write_mask(intr);
900 ncomp = ffs(~wrmask) - 1;
901
902 assert(wrmask == BITFIELD_MASK(intr->num_components));
903
904 stl = ir3_STL(b, offset, 0,
905 ir3_create_collect(ctx, value, ncomp), 0,
906 create_immed(b, ncomp), 0);
907 stl->cat6.dst_offset = base;
908 stl->cat6.type = utype_src(intr->src[0]);
909 stl->barrier_class = IR3_BARRIER_SHARED_W;
910 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
911
912 array_insert(b, b->keeps, stl);
913 }
914
915 /* src[] = { offset }. const_index[] = { base } */
916 static void
917 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
918 struct ir3_instruction **dst)
919 {
920 struct ir3_block *b = ctx->block;
921 struct ir3_instruction *load, *offset;
922 unsigned base;
923
924 offset = ir3_get_src(ctx, &intr->src[0])[0];
925 base = nir_intrinsic_base(intr);
926
927 load = ir3_LDLW(b, offset, 0,
928 create_immed(b, intr->num_components), 0,
929 create_immed(b, base), 0);
930
931 load->cat6.type = utype_dst(intr->dest);
932 load->regs[0]->wrmask = MASK(intr->num_components);
933
934 load->barrier_class = IR3_BARRIER_SHARED_R;
935 load->barrier_conflict = IR3_BARRIER_SHARED_W;
936
937 ir3_split_dest(b, dst, load, 0, intr->num_components);
938 }
939
940 /* src[] = { value, offset }. const_index[] = { base } */
941 static void
942 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
943 {
944 struct ir3_block *b = ctx->block;
945 struct ir3_instruction *store, *offset;
946 struct ir3_instruction * const *value;
947
948 value = ir3_get_src(ctx, &intr->src[0]);
949 offset = ir3_get_src(ctx, &intr->src[1])[0];
950
951 store = ir3_STLW(b, offset, 0,
952 ir3_create_collect(ctx, value, intr->num_components), 0,
953 create_immed(b, intr->num_components), 0);
954
955 store->cat6.dst_offset = nir_intrinsic_base(intr);
956 store->cat6.type = utype_src(intr->src[0]);
957 store->barrier_class = IR3_BARRIER_SHARED_W;
958 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
959
960 array_insert(b, b->keeps, store);
961 }
962
963 /*
964 * CS shared variable atomic intrinsics
965 *
966 * All of the shared variable atomic memory operations read a value from
967 * memory, compute a new value using one of the operations below, write the
968 * new value to memory, and return the original value read.
969 *
970 * All operations take 2 sources except CompSwap that takes 3. These
971 * sources represent:
972 *
973 * 0: The offset into the shared variable storage region that the atomic
974 * operation will operate on.
975 * 1: The data parameter to the atomic function (i.e. the value to add
976 * in shared_atomic_add, etc).
977 * 2: For CompSwap only: the second data parameter.
978 */
979 static struct ir3_instruction *
980 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
981 {
982 struct ir3_block *b = ctx->block;
983 struct ir3_instruction *atomic, *src0, *src1;
984 type_t type = TYPE_U32;
985
986 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
987 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
988
989 switch (intr->intrinsic) {
990 case nir_intrinsic_shared_atomic_add:
991 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
992 break;
993 case nir_intrinsic_shared_atomic_imin:
994 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
995 type = TYPE_S32;
996 break;
997 case nir_intrinsic_shared_atomic_umin:
998 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
999 break;
1000 case nir_intrinsic_shared_atomic_imax:
1001 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1002 type = TYPE_S32;
1003 break;
1004 case nir_intrinsic_shared_atomic_umax:
1005 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_and:
1008 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_or:
1011 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1012 break;
1013 case nir_intrinsic_shared_atomic_xor:
1014 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1015 break;
1016 case nir_intrinsic_shared_atomic_exchange:
1017 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1018 break;
1019 case nir_intrinsic_shared_atomic_comp_swap:
1020 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1021 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1022 ir3_get_src(ctx, &intr->src[2])[0],
1023 src1,
1024 }, 2);
1025 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1026 break;
1027 default:
1028 unreachable("boo");
1029 }
1030
1031 atomic->cat6.iim_val = 1;
1032 atomic->cat6.d = 1;
1033 atomic->cat6.type = type;
1034 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1035 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1036
1037 /* even if nothing consume the result, we can't DCE the instruction: */
1038 array_insert(b, b->keeps, atomic);
1039
1040 return atomic;
1041 }
1042
1043 struct tex_src_info {
1044 /* For prefetch */
1045 unsigned tex_base, samp_base, tex_idx, samp_idx;
1046 /* For normal tex instructions */
1047 unsigned base, combined_idx, a1_val, flags;
1048 struct ir3_instruction *samp_tex;
1049 };
1050
1051 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1052 * to handle with the image_mapping table..
1053 */
1054 static struct tex_src_info
1055 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1056 {
1057 struct ir3_block *b = ctx->block;
1058 struct tex_src_info info = { 0 };
1059 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1060 ctx->so->bindless_tex = true;
1061
1062 if (bindless_tex) {
1063 /* Bindless case */
1064 info.flags |= IR3_INSTR_B;
1065
1066 /* Gather information required to determine which encoding to
1067 * choose as well as for prefetch.
1068 */
1069 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1070 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1071 if (tex_const)
1072 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1073 info.samp_idx = 0;
1074
1075 /* Choose encoding. */
1076 if (tex_const && info.tex_idx < 256) {
1077 if (info.tex_idx < 16) {
1078 /* Everything fits within the instruction */
1079 info.base = info.tex_base;
1080 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1081 } else {
1082 info.base = info.tex_base;
1083 info.a1_val = info.tex_idx << 3;
1084 info.combined_idx = 0;
1085 info.flags |= IR3_INSTR_A1EN;
1086 }
1087 info.samp_tex = NULL;
1088 } else {
1089 info.flags |= IR3_INSTR_S2EN;
1090 info.base = info.tex_base;
1091
1092 /* Note: the indirect source is now a vec2 instead of hvec2 */
1093 struct ir3_instruction *texture, *sampler;
1094
1095 texture = ir3_get_src(ctx, &intr->src[0])[0];
1096 sampler = create_immed(b, 0);
1097 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1098 texture,
1099 sampler,
1100 }, 2);
1101 }
1102 } else {
1103 info.flags |= IR3_INSTR_S2EN;
1104 unsigned slot = nir_src_as_uint(intr->src[0]);
1105 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1106 struct ir3_instruction *texture, *sampler;
1107
1108 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1109 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1110
1111 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1112 sampler,
1113 texture,
1114 }, 2);
1115 }
1116
1117 return info;
1118 }
1119
1120 static struct ir3_instruction *
1121 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1122 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1123 struct ir3_instruction *src1)
1124 {
1125 struct ir3_instruction *sam, *addr;
1126 if (info.flags & IR3_INSTR_A1EN) {
1127 addr = ir3_get_addr1(ctx, info.a1_val);
1128 }
1129 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1130 info.samp_tex, src0, src1);
1131 if (info.flags & IR3_INSTR_A1EN) {
1132 ir3_instr_set_address(sam, addr);
1133 }
1134 if (info.flags & IR3_INSTR_B) {
1135 sam->cat5.tex_base = info.base;
1136 sam->cat5.samp = info.combined_idx;
1137 }
1138 return sam;
1139 }
1140
1141 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1142 static void
1143 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1144 struct ir3_instruction **dst)
1145 {
1146 struct ir3_block *b = ctx->block;
1147 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1148 struct ir3_instruction *sam;
1149 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1150 struct ir3_instruction *coords[4];
1151 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1152 type_t type = ir3_get_type_for_image_intrinsic(intr);
1153
1154 /* hmm, this seems a bit odd, but it is what blob does and (at least
1155 * a5xx) just faults on bogus addresses otherwise:
1156 */
1157 if (flags & IR3_INSTR_3D) {
1158 flags &= ~IR3_INSTR_3D;
1159 flags |= IR3_INSTR_A;
1160 }
1161 info.flags |= flags;
1162
1163 for (unsigned i = 0; i < ncoords; i++)
1164 coords[i] = src0[i];
1165
1166 if (ncoords == 1)
1167 coords[ncoords++] = create_immed(b, 0);
1168
1169 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1170 ir3_create_collect(ctx, coords, ncoords), NULL);
1171
1172 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1173 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1174
1175 ir3_split_dest(b, dst, sam, 0, 4);
1176 }
1177
1178 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1179 void
1180 emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1181 struct ir3_instruction **dst)
1182 {
1183 struct ir3_block *b = ctx->block;
1184 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1185 struct ir3_instruction *sam, *lod;
1186 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1187 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1188 TYPE_U16 : TYPE_U32;
1189
1190 info.flags |= flags;
1191 lod = create_immed(b, 0);
1192 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1193
1194 /* Array size actually ends up in .w rather than .z. This doesn't
1195 * matter for miplevel 0, but for higher mips the value in z is
1196 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1197 * returned, which means that we have to add 1 to it for arrays for
1198 * a3xx.
1199 *
1200 * Note use a temporary dst and then copy, since the size of the dst
1201 * array that is passed in is based on nir's understanding of the
1202 * result size, not the hardware's
1203 */
1204 struct ir3_instruction *tmp[4];
1205
1206 ir3_split_dest(b, tmp, sam, 0, 4);
1207
1208 /* get_size instruction returns size in bytes instead of texels
1209 * for imageBuffer, so we need to divide it by the pixel size
1210 * of the image format.
1211 *
1212 * TODO: This is at least true on a5xx. Check other gens.
1213 */
1214 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1215 /* Since all the possible values the divisor can take are
1216 * power-of-two (4, 8, or 16), the division is implemented
1217 * as a shift-right.
1218 * During shader setup, the log2 of the image format's
1219 * bytes-per-pixel should have been emitted in 2nd slot of
1220 * image_dims. See ir3_shader::emit_image_dims().
1221 */
1222 const struct ir3_const_state *const_state =
1223 ir3_const_state(ctx->so);
1224 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1225 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1226 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1227
1228 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1229 }
1230
1231 for (unsigned i = 0; i < ncoords; i++)
1232 dst[i] = tmp[i];
1233
1234 if (flags & IR3_INSTR_A) {
1235 if (ctx->compiler->levels_add_one) {
1236 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1237 } else {
1238 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1239 }
1240 }
1241 }
1242
1243 static void
1244 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1245 {
1246 struct ir3_block *b = ctx->block;
1247 struct ir3_instruction *barrier;
1248
1249 switch (intr->intrinsic) {
1250 case nir_intrinsic_control_barrier:
1251 barrier = ir3_BAR(b);
1252 barrier->cat7.g = true;
1253 barrier->cat7.l = true;
1254 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1255 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1256 break;
1257 case nir_intrinsic_memory_barrier:
1258 barrier = ir3_FENCE(b);
1259 barrier->cat7.g = true;
1260 barrier->cat7.r = true;
1261 barrier->cat7.w = true;
1262 barrier->cat7.l = true;
1263 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1264 IR3_BARRIER_BUFFER_W;
1265 barrier->barrier_conflict =
1266 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1267 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1268 break;
1269 case nir_intrinsic_memory_barrier_buffer:
1270 barrier = ir3_FENCE(b);
1271 barrier->cat7.g = true;
1272 barrier->cat7.r = true;
1273 barrier->cat7.w = true;
1274 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1275 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1276 IR3_BARRIER_BUFFER_W;
1277 break;
1278 case nir_intrinsic_memory_barrier_image:
1279 // TODO double check if this should have .g set
1280 barrier = ir3_FENCE(b);
1281 barrier->cat7.g = true;
1282 barrier->cat7.r = true;
1283 barrier->cat7.w = true;
1284 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1285 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1286 IR3_BARRIER_IMAGE_W;
1287 break;
1288 case nir_intrinsic_memory_barrier_shared:
1289 barrier = ir3_FENCE(b);
1290 barrier->cat7.g = true;
1291 barrier->cat7.l = true;
1292 barrier->cat7.r = true;
1293 barrier->cat7.w = true;
1294 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1295 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1296 IR3_BARRIER_SHARED_W;
1297 break;
1298 case nir_intrinsic_group_memory_barrier:
1299 barrier = ir3_FENCE(b);
1300 barrier->cat7.g = true;
1301 barrier->cat7.l = true;
1302 barrier->cat7.r = true;
1303 barrier->cat7.w = true;
1304 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1305 IR3_BARRIER_IMAGE_W |
1306 IR3_BARRIER_BUFFER_W;
1307 barrier->barrier_conflict =
1308 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1309 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1310 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1311 break;
1312 default:
1313 unreachable("boo");
1314 }
1315
1316 /* make sure barrier doesn't get DCE'd */
1317 array_insert(b, b->keeps, barrier);
1318 }
1319
1320 static void add_sysval_input_compmask(struct ir3_context *ctx,
1321 gl_system_value slot, unsigned compmask,
1322 struct ir3_instruction *instr)
1323 {
1324 struct ir3_shader_variant *so = ctx->so;
1325 unsigned n = so->inputs_count++;
1326
1327 assert(instr->opc == OPC_META_INPUT);
1328 instr->input.inidx = n;
1329 instr->input.sysval = slot;
1330
1331 so->inputs[n].sysval = true;
1332 so->inputs[n].slot = slot;
1333 so->inputs[n].compmask = compmask;
1334 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1335 so->total_in++;
1336 }
1337
1338 static struct ir3_instruction *
1339 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1340 unsigned compmask)
1341 {
1342 assert(compmask);
1343 struct ir3_instruction *sysval = create_input(ctx, compmask);
1344 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1345 return sysval;
1346 }
1347
1348 static struct ir3_instruction *
1349 get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
1350 {
1351 static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1352
1353 STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1354 STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1355 STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1356 STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1357 STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
1358 STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
1359 STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
1360
1361 if (!ctx->ij[bary]) {
1362 struct ir3_instruction *xy[2];
1363 struct ir3_instruction *ij;
1364
1365 ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
1366 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1367
1368 ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
1369 }
1370
1371 return ctx->ij[bary];
1372 }
1373
1374 static struct ir3_instruction *
1375 get_barycentric_centroid(struct ir3_context *ctx)
1376 {
1377 return get_barycentric(ctx, IJ_PERSP_CENTROID);
1378 }
1379
1380 static struct ir3_instruction *
1381 get_barycentric_sample(struct ir3_context *ctx)
1382 {
1383 return get_barycentric(ctx, IJ_PERSP_SAMPLE);
1384 }
1385
1386 static struct ir3_instruction *
1387 get_barycentric_pixel(struct ir3_context *ctx)
1388 {
1389 return get_barycentric(ctx, IJ_PERSP_PIXEL);
1390 }
1391
1392 static struct ir3_instruction *
1393 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1394 {
1395 if (!ctx->frag_coord) {
1396 struct ir3_block *b = ctx->in_block;
1397 struct ir3_instruction *xyzw[4];
1398 struct ir3_instruction *hw_frag_coord;
1399
1400 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1401 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1402
1403 /* for frag_coord.xy, we get unsigned values.. we need
1404 * to subtract (integer) 8 and divide by 16 (right-
1405 * shift by 4) then convert to float:
1406 *
1407 * sub.s tmp, src, 8
1408 * shr.b tmp, tmp, 4
1409 * mov.u32f32 dst, tmp
1410 *
1411 */
1412 for (int i = 0; i < 2; i++) {
1413 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1414 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1415 }
1416
1417 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1418 }
1419
1420 ctx->so->fragcoord_compmask |=
1421 nir_ssa_def_components_read(&intr->dest.ssa);
1422
1423 return ctx->frag_coord;
1424 }
1425
1426 static void
1427 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1428 {
1429 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1430 struct ir3_instruction **dst;
1431 struct ir3_instruction * const *src;
1432 struct ir3_block *b = ctx->block;
1433 unsigned dest_components = nir_intrinsic_dest_components(intr);
1434 int idx, comp;
1435
1436 if (info->has_dest) {
1437 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
1438 } else {
1439 dst = NULL;
1440 }
1441
1442 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
1443 const unsigned primitive_param = const_state->offsets.primitive_param * 4;
1444 const unsigned primitive_map = const_state->offsets.primitive_map * 4;
1445
1446 switch (intr->intrinsic) {
1447 case nir_intrinsic_load_uniform:
1448 idx = nir_intrinsic_base(intr);
1449 if (nir_src_is_const(intr->src[0])) {
1450 idx += nir_src_as_uint(intr->src[0]);
1451 for (int i = 0; i < dest_components; i++) {
1452 dst[i] = create_uniform_typed(b, idx + i,
1453 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1454 }
1455 } else {
1456 src = ir3_get_src(ctx, &intr->src[0]);
1457 for (int i = 0; i < dest_components; i++) {
1458 dst[i] = create_uniform_indirect(b, idx + i,
1459 ir3_get_addr0(ctx, src[0], 1));
1460 }
1461 /* NOTE: if relative addressing is used, we set
1462 * constlen in the compiler (to worst-case value)
1463 * since we don't know in the assembler what the max
1464 * addr reg value can be:
1465 */
1466 ctx->so->constlen = MAX2(ctx->so->constlen,
1467 const_state->ubo_state.size / 16);
1468 }
1469 break;
1470
1471 case nir_intrinsic_load_vs_primitive_stride_ir3:
1472 dst[0] = create_uniform(b, primitive_param + 0);
1473 break;
1474 case nir_intrinsic_load_vs_vertex_stride_ir3:
1475 dst[0] = create_uniform(b, primitive_param + 1);
1476 break;
1477 case nir_intrinsic_load_hs_patch_stride_ir3:
1478 dst[0] = create_uniform(b, primitive_param + 2);
1479 break;
1480 case nir_intrinsic_load_patch_vertices_in:
1481 dst[0] = create_uniform(b, primitive_param + 3);
1482 break;
1483 case nir_intrinsic_load_tess_param_base_ir3:
1484 dst[0] = create_uniform(b, primitive_param + 4);
1485 dst[1] = create_uniform(b, primitive_param + 5);
1486 break;
1487 case nir_intrinsic_load_tess_factor_base_ir3:
1488 dst[0] = create_uniform(b, primitive_param + 6);
1489 dst[1] = create_uniform(b, primitive_param + 7);
1490 break;
1491
1492 case nir_intrinsic_load_primitive_location_ir3:
1493 idx = nir_intrinsic_driver_location(intr);
1494 dst[0] = create_uniform(b, primitive_map + idx);
1495 break;
1496
1497 case nir_intrinsic_load_gs_header_ir3:
1498 dst[0] = ctx->gs_header;
1499 break;
1500 case nir_intrinsic_load_tcs_header_ir3:
1501 dst[0] = ctx->tcs_header;
1502 break;
1503
1504 case nir_intrinsic_load_primitive_id:
1505 dst[0] = ctx->primitive_id;
1506 break;
1507
1508 case nir_intrinsic_load_tess_coord:
1509 if (!ctx->tess_coord) {
1510 ctx->tess_coord =
1511 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1512 }
1513 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1514
1515 /* Unused, but ir3_put_dst() below wants to free something */
1516 dst[2] = create_immed(b, 0);
1517 break;
1518
1519 case nir_intrinsic_end_patch_ir3:
1520 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1521 struct ir3_instruction *end = ir3_PREDE(b);
1522 array_insert(b, b->keeps, end);
1523
1524 end->barrier_class = IR3_BARRIER_EVERYTHING;
1525 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1526 break;
1527
1528 case nir_intrinsic_store_global_ir3: {
1529 struct ir3_instruction *value, *addr, *offset;
1530 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
1531
1532 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1533 ir3_get_src(ctx, &intr->src[1])[0],
1534 ir3_get_src(ctx, &intr->src[1])[1]
1535 }, 2);
1536
1537 offset = ir3_get_src(ctx, &intr->src[2])[0];
1538
1539 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
1540
1541 struct ir3_instruction *stg =
1542 ir3_STG_G(ctx->block, addr, 0, value, 0,
1543 create_immed(ctx->block, ncomp), 0, offset, 0);
1544 stg->cat6.type = TYPE_U32;
1545 stg->cat6.iim_val = 1;
1546
1547 array_insert(b, b->keeps, stg);
1548
1549 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1550 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1551 break;
1552 }
1553
1554 case nir_intrinsic_load_global_ir3: {
1555 struct ir3_instruction *addr, *offset;
1556
1557 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1558 ir3_get_src(ctx, &intr->src[0])[0],
1559 ir3_get_src(ctx, &intr->src[0])[1]
1560 }, 2);
1561
1562 offset = ir3_get_src(ctx, &intr->src[1])[0];
1563
1564 struct ir3_instruction *load =
1565 ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components),
1566 0, offset, 0);
1567 load->cat6.type = TYPE_U32;
1568 load->regs[0]->wrmask = MASK(dest_components);
1569
1570 load->barrier_class = IR3_BARRIER_BUFFER_R;
1571 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1572
1573 ir3_split_dest(b, dst, load, 0, dest_components);
1574 break;
1575 }
1576
1577 case nir_intrinsic_load_ubo:
1578 emit_intrinsic_load_ubo(ctx, intr, dst);
1579 break;
1580 case nir_intrinsic_load_ubo_ir3:
1581 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1582 break;
1583 case nir_intrinsic_load_frag_coord:
1584 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1585 break;
1586 case nir_intrinsic_load_sample_pos_from_id: {
1587 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1588 * but that doesn't seem necessary.
1589 */
1590 struct ir3_instruction *offset =
1591 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1592 offset->regs[0]->wrmask = 0x3;
1593 offset->cat5.type = TYPE_F32;
1594
1595 ir3_split_dest(b, dst, offset, 0, 2);
1596
1597 break;
1598 }
1599 case nir_intrinsic_load_size_ir3:
1600 if (!ctx->ij[IJ_PERSP_SIZE]) {
1601 ctx->ij[IJ_PERSP_SIZE] =
1602 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1603 }
1604 dst[0] = ctx->ij[IJ_PERSP_SIZE];
1605 break;
1606 case nir_intrinsic_load_barycentric_centroid:
1607 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1608 break;
1609 case nir_intrinsic_load_barycentric_sample:
1610 if (ctx->so->key.msaa) {
1611 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1612 } else {
1613 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1614 }
1615 break;
1616 case nir_intrinsic_load_barycentric_pixel:
1617 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1618 break;
1619 case nir_intrinsic_load_interpolated_input:
1620 idx = nir_intrinsic_base(intr);
1621 comp = nir_intrinsic_component(intr);
1622 src = ir3_get_src(ctx, &intr->src[0]);
1623 if (nir_src_is_const(intr->src[1])) {
1624 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1625 idx += nir_src_as_uint(intr->src[1]);
1626 for (int i = 0; i < dest_components; i++) {
1627 unsigned inloc = idx * 4 + i + comp;
1628 if (ctx->so->inputs[idx].bary &&
1629 !ctx->so->inputs[idx].use_ldlv) {
1630 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1631 } else {
1632 /* for non-varyings use the pre-setup input, since
1633 * that is easier than mapping things back to a
1634 * nir_variable to figure out what it is.
1635 */
1636 dst[i] = ctx->inputs[inloc];
1637 compile_assert(ctx, dst[i]);
1638 }
1639 }
1640 } else {
1641 ir3_context_error(ctx, "unhandled");
1642 }
1643 break;
1644 case nir_intrinsic_load_input:
1645 idx = nir_intrinsic_base(intr);
1646 comp = nir_intrinsic_component(intr);
1647 if (nir_src_is_const(intr->src[0])) {
1648 idx += nir_src_as_uint(intr->src[0]);
1649 for (int i = 0; i < dest_components; i++) {
1650 unsigned n = idx * 4 + i + comp;
1651 dst[i] = ctx->inputs[n];
1652 compile_assert(ctx, ctx->inputs[n]);
1653 }
1654 } else {
1655 src = ir3_get_src(ctx, &intr->src[0]);
1656 struct ir3_instruction *collect =
1657 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1658 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1659 for (int i = 0; i < dest_components; i++) {
1660 unsigned n = idx * 4 + i + comp;
1661 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1662 n, addr, collect);
1663 }
1664 }
1665 break;
1666 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1667 * pass and replaced by an ir3-specifc version that adds the
1668 * dword-offset in the last source.
1669 */
1670 case nir_intrinsic_load_ssbo_ir3:
1671 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1672 break;
1673 case nir_intrinsic_store_ssbo_ir3:
1674 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1675 !ctx->s->info.fs.early_fragment_tests)
1676 ctx->so->no_earlyz = true;
1677 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1678 break;
1679 case nir_intrinsic_get_buffer_size:
1680 emit_intrinsic_ssbo_size(ctx, intr, dst);
1681 break;
1682 case nir_intrinsic_ssbo_atomic_add_ir3:
1683 case nir_intrinsic_ssbo_atomic_imin_ir3:
1684 case nir_intrinsic_ssbo_atomic_umin_ir3:
1685 case nir_intrinsic_ssbo_atomic_imax_ir3:
1686 case nir_intrinsic_ssbo_atomic_umax_ir3:
1687 case nir_intrinsic_ssbo_atomic_and_ir3:
1688 case nir_intrinsic_ssbo_atomic_or_ir3:
1689 case nir_intrinsic_ssbo_atomic_xor_ir3:
1690 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1691 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1692 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1693 !ctx->s->info.fs.early_fragment_tests)
1694 ctx->so->no_earlyz = true;
1695 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1696 break;
1697 case nir_intrinsic_load_shared:
1698 emit_intrinsic_load_shared(ctx, intr, dst);
1699 break;
1700 case nir_intrinsic_store_shared:
1701 emit_intrinsic_store_shared(ctx, intr);
1702 break;
1703 case nir_intrinsic_shared_atomic_add:
1704 case nir_intrinsic_shared_atomic_imin:
1705 case nir_intrinsic_shared_atomic_umin:
1706 case nir_intrinsic_shared_atomic_imax:
1707 case nir_intrinsic_shared_atomic_umax:
1708 case nir_intrinsic_shared_atomic_and:
1709 case nir_intrinsic_shared_atomic_or:
1710 case nir_intrinsic_shared_atomic_xor:
1711 case nir_intrinsic_shared_atomic_exchange:
1712 case nir_intrinsic_shared_atomic_comp_swap:
1713 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1714 break;
1715 case nir_intrinsic_image_load:
1716 emit_intrinsic_load_image(ctx, intr, dst);
1717 break;
1718 case nir_intrinsic_bindless_image_load:
1719 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1720 * so using isam doesn't work.
1721 *
1722 * TODO: can we use isam if we fill out more fields?
1723 */
1724 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1725 break;
1726 case nir_intrinsic_image_store:
1727 case nir_intrinsic_bindless_image_store:
1728 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1729 !ctx->s->info.fs.early_fragment_tests)
1730 ctx->so->no_earlyz = true;
1731 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1732 break;
1733 case nir_intrinsic_image_size:
1734 case nir_intrinsic_bindless_image_size:
1735 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
1736 break;
1737 case nir_intrinsic_image_atomic_add:
1738 case nir_intrinsic_bindless_image_atomic_add:
1739 case nir_intrinsic_image_atomic_imin:
1740 case nir_intrinsic_bindless_image_atomic_imin:
1741 case nir_intrinsic_image_atomic_umin:
1742 case nir_intrinsic_bindless_image_atomic_umin:
1743 case nir_intrinsic_image_atomic_imax:
1744 case nir_intrinsic_bindless_image_atomic_imax:
1745 case nir_intrinsic_image_atomic_umax:
1746 case nir_intrinsic_bindless_image_atomic_umax:
1747 case nir_intrinsic_image_atomic_and:
1748 case nir_intrinsic_bindless_image_atomic_and:
1749 case nir_intrinsic_image_atomic_or:
1750 case nir_intrinsic_bindless_image_atomic_or:
1751 case nir_intrinsic_image_atomic_xor:
1752 case nir_intrinsic_bindless_image_atomic_xor:
1753 case nir_intrinsic_image_atomic_exchange:
1754 case nir_intrinsic_bindless_image_atomic_exchange:
1755 case nir_intrinsic_image_atomic_comp_swap:
1756 case nir_intrinsic_bindless_image_atomic_comp_swap:
1757 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1758 !ctx->s->info.fs.early_fragment_tests)
1759 ctx->so->no_earlyz = true;
1760 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1761 break;
1762 case nir_intrinsic_control_barrier:
1763 case nir_intrinsic_memory_barrier:
1764 case nir_intrinsic_group_memory_barrier:
1765 case nir_intrinsic_memory_barrier_buffer:
1766 case nir_intrinsic_memory_barrier_image:
1767 case nir_intrinsic_memory_barrier_shared:
1768 emit_intrinsic_barrier(ctx, intr);
1769 /* note that blk ptr no longer valid, make that obvious: */
1770 b = NULL;
1771 break;
1772 case nir_intrinsic_store_output:
1773 idx = nir_intrinsic_base(intr);
1774 comp = nir_intrinsic_component(intr);
1775 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1776 idx += nir_src_as_uint(intr->src[1]);
1777
1778 src = ir3_get_src(ctx, &intr->src[0]);
1779 for (int i = 0; i < nir_intrinsic_src_components(intr, 0); i++) {
1780 unsigned n = idx * 4 + i + comp;
1781 ctx->outputs[n] = src[i];
1782 }
1783 break;
1784 case nir_intrinsic_load_base_vertex:
1785 case nir_intrinsic_load_first_vertex:
1786 if (!ctx->basevertex) {
1787 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1788 }
1789 dst[0] = ctx->basevertex;
1790 break;
1791 case nir_intrinsic_load_draw_id:
1792 if (!ctx->draw_id) {
1793 ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
1794 }
1795 dst[0] = ctx->draw_id;
1796 break;
1797 case nir_intrinsic_load_base_instance:
1798 if (!ctx->base_instance) {
1799 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1800 }
1801 dst[0] = ctx->base_instance;
1802 break;
1803 case nir_intrinsic_load_vertex_id_zero_base:
1804 case nir_intrinsic_load_vertex_id:
1805 if (!ctx->vertex_id) {
1806 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1807 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1808 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1809 }
1810 dst[0] = ctx->vertex_id;
1811 break;
1812 case nir_intrinsic_load_instance_id:
1813 if (!ctx->instance_id) {
1814 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1815 }
1816 dst[0] = ctx->instance_id;
1817 break;
1818 case nir_intrinsic_load_sample_id:
1819 ctx->so->per_samp = true;
1820 /* fall-thru */
1821 case nir_intrinsic_load_sample_id_no_per_sample:
1822 if (!ctx->samp_id) {
1823 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1824 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1825 }
1826 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1827 break;
1828 case nir_intrinsic_load_sample_mask_in:
1829 if (!ctx->samp_mask_in) {
1830 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1831 }
1832 dst[0] = ctx->samp_mask_in;
1833 break;
1834 case nir_intrinsic_load_user_clip_plane:
1835 idx = nir_intrinsic_ucp_id(intr);
1836 for (int i = 0; i < dest_components; i++) {
1837 unsigned n = idx * 4 + i;
1838 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1839 }
1840 break;
1841 case nir_intrinsic_load_front_face:
1842 if (!ctx->frag_face) {
1843 ctx->so->frag_face = true;
1844 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1845 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1846 }
1847 /* for fragface, we get -1 for back and 0 for front. However this is
1848 * the inverse of what nir expects (where ~0 is true).
1849 */
1850 dst[0] = ir3_CMPS_S(b,
1851 ctx->frag_face, 0,
1852 create_immed_typed(b, 0, TYPE_U16), 0);
1853 dst[0]->cat2.condition = IR3_COND_EQ;
1854 break;
1855 case nir_intrinsic_load_local_invocation_id:
1856 if (!ctx->local_invocation_id) {
1857 ctx->local_invocation_id =
1858 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1859 }
1860 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1861 break;
1862 case nir_intrinsic_load_work_group_id:
1863 if (!ctx->work_group_id) {
1864 ctx->work_group_id =
1865 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1866 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1867 }
1868 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1869 break;
1870 case nir_intrinsic_load_num_work_groups:
1871 for (int i = 0; i < dest_components; i++) {
1872 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1873 }
1874 break;
1875 case nir_intrinsic_load_local_group_size:
1876 for (int i = 0; i < dest_components; i++) {
1877 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1878 }
1879 break;
1880 case nir_intrinsic_discard_if:
1881 case nir_intrinsic_discard: {
1882 struct ir3_instruction *cond, *kill;
1883
1884 if (intr->intrinsic == nir_intrinsic_discard_if) {
1885 /* conditional discard: */
1886 src = ir3_get_src(ctx, &intr->src[0]);
1887 cond = src[0];
1888 } else {
1889 /* unconditional discard: */
1890 cond = create_immed(b, 1);
1891 }
1892
1893 /* NOTE: only cmps.*.* can write p0.x: */
1894 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1895 cond->cat2.condition = IR3_COND_NE;
1896
1897 /* condition always goes in predicate register: */
1898 cond->regs[0]->num = regid(REG_P0, 0);
1899 cond->regs[0]->flags &= ~IR3_REG_SSA;
1900
1901 kill = ir3_KILL(b, cond, 0);
1902 kill->regs[1]->num = regid(REG_P0, 0);
1903 array_insert(ctx->ir, ctx->ir->predicates, kill);
1904
1905 array_insert(b, b->keeps, kill);
1906 ctx->so->has_kill = true;
1907
1908 break;
1909 }
1910
1911 case nir_intrinsic_cond_end_ir3: {
1912 struct ir3_instruction *cond, *kill;
1913
1914 src = ir3_get_src(ctx, &intr->src[0]);
1915 cond = src[0];
1916
1917 /* NOTE: only cmps.*.* can write p0.x: */
1918 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1919 cond->cat2.condition = IR3_COND_NE;
1920
1921 /* condition always goes in predicate register: */
1922 cond->regs[0]->num = regid(REG_P0, 0);
1923
1924 kill = ir3_PREDT(b, cond, 0);
1925
1926 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1927 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1928
1929 array_insert(ctx->ir, ctx->ir->predicates, kill);
1930 array_insert(b, b->keeps, kill);
1931 break;
1932 }
1933
1934 case nir_intrinsic_load_shared_ir3:
1935 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1936 break;
1937 case nir_intrinsic_store_shared_ir3:
1938 emit_intrinsic_store_shared_ir3(ctx, intr);
1939 break;
1940 case nir_intrinsic_bindless_resource_ir3:
1941 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1942 break;
1943 default:
1944 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1945 nir_intrinsic_infos[intr->intrinsic].name);
1946 break;
1947 }
1948
1949 if (info->has_dest)
1950 ir3_put_dst(ctx, &intr->dest);
1951 }
1952
1953 static void
1954 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1955 {
1956 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1957 instr->def.num_components);
1958
1959 if (instr->def.bit_size == 16) {
1960 for (int i = 0; i < instr->def.num_components; i++)
1961 dst[i] = create_immed_typed(ctx->block,
1962 instr->value[i].u16,
1963 TYPE_U16);
1964 } else {
1965 for (int i = 0; i < instr->def.num_components; i++)
1966 dst[i] = create_immed_typed(ctx->block,
1967 instr->value[i].u32,
1968 TYPE_U32);
1969 }
1970
1971 }
1972
1973 static void
1974 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1975 {
1976 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1977 undef->def.num_components);
1978 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
1979
1980 /* backend doesn't want undefined instructions, so just plug
1981 * in 0.0..
1982 */
1983 for (int i = 0; i < undef->def.num_components; i++)
1984 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1985 }
1986
1987 /*
1988 * texture fetch/sample instructions:
1989 */
1990
1991 static type_t
1992 get_tex_dest_type(nir_tex_instr *tex)
1993 {
1994 type_t type;
1995
1996 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1997 case nir_type_invalid:
1998 case nir_type_float:
1999 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2000 break;
2001 case nir_type_int:
2002 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2003 break;
2004 case nir_type_uint:
2005 case nir_type_bool:
2006 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2007 break;
2008 default:
2009 unreachable("bad dest_type");
2010 }
2011
2012 return type;
2013 }
2014
2015 static void
2016 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2017 {
2018 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2019 unsigned flags = 0;
2020
2021 /* note: would use tex->coord_components.. except txs.. also,
2022 * since array index goes after shadow ref, we don't want to
2023 * count it:
2024 */
2025 if (coords == 3)
2026 flags |= IR3_INSTR_3D;
2027
2028 if (tex->is_shadow && tex->op != nir_texop_lod)
2029 flags |= IR3_INSTR_S;
2030
2031 if (tex->is_array && tex->op != nir_texop_lod)
2032 flags |= IR3_INSTR_A;
2033
2034 *flagsp = flags;
2035 *coordsp = coords;
2036 }
2037
2038 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2039 * or immediate (in which case it will get lowered later to a non .s2en
2040 * version of the tex instruction which encode tex/samp as immediates:
2041 */
2042 static struct tex_src_info
2043 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2044 {
2045 struct ir3_block *b = ctx->block;
2046 struct tex_src_info info = { 0 };
2047 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2048 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2049 struct ir3_instruction *texture, *sampler;
2050
2051 if (texture_idx >= 0 || sampler_idx >= 0) {
2052 /* Bindless case */
2053 info.flags |= IR3_INSTR_B;
2054
2055 /* Gather information required to determine which encoding to
2056 * choose as well as for prefetch.
2057 */
2058 nir_intrinsic_instr *bindless_tex = NULL;
2059 bool tex_const;
2060 if (texture_idx >= 0) {
2061 ctx->so->bindless_tex = true;
2062 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2063 assert(bindless_tex);
2064 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2065 tex_const = nir_src_is_const(bindless_tex->src[0]);
2066 if (tex_const)
2067 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2068 } else {
2069 /* To simplify some of the logic below, assume the index is
2070 * constant 0 when it's not enabled.
2071 */
2072 tex_const = true;
2073 info.tex_idx = 0;
2074 }
2075 nir_intrinsic_instr *bindless_samp = NULL;
2076 bool samp_const;
2077 if (sampler_idx >= 0) {
2078 ctx->so->bindless_samp = true;
2079 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2080 assert(bindless_samp);
2081 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2082 samp_const = nir_src_is_const(bindless_samp->src[0]);
2083 if (samp_const)
2084 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2085 } else {
2086 samp_const = true;
2087 info.samp_idx = 0;
2088 }
2089
2090 /* Choose encoding. */
2091 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2092 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2093 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2094 /* Everything fits within the instruction */
2095 info.base = info.tex_base;
2096 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2097 } else {
2098 info.base = info.tex_base;
2099 info.a1_val = info.tex_idx << 3 | info.samp_base;
2100 info.combined_idx = info.samp_idx;
2101 info.flags |= IR3_INSTR_A1EN;
2102 }
2103 info.samp_tex = NULL;
2104 } else {
2105 info.flags |= IR3_INSTR_S2EN;
2106 /* In the indirect case, we only use a1.x to store the sampler
2107 * base if it differs from the texture base.
2108 */
2109 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2110 info.base = info.tex_base;
2111 } else {
2112 info.base = info.tex_base;
2113 info.a1_val = info.samp_base;
2114 info.flags |= IR3_INSTR_A1EN;
2115 }
2116
2117 /* Note: the indirect source is now a vec2 instead of hvec2, and
2118 * for some reason the texture and sampler are swapped.
2119 */
2120 struct ir3_instruction *texture, *sampler;
2121
2122 if (bindless_tex) {
2123 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2124 } else {
2125 texture = create_immed(b, 0);
2126 }
2127
2128 if (bindless_samp) {
2129 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2130 } else {
2131 sampler = create_immed(b, 0);
2132 }
2133 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2134 texture,
2135 sampler,
2136 }, 2);
2137 }
2138 } else {
2139 info.flags |= IR3_INSTR_S2EN;
2140 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2141 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2142 if (texture_idx >= 0) {
2143 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2144 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2145 } else {
2146 /* TODO what to do for dynamic case? I guess we only need the
2147 * max index for astc srgb workaround so maybe not a problem
2148 * to worry about if we don't enable indirect samplers for
2149 * a4xx?
2150 */
2151 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2152 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2153 info.tex_idx = tex->texture_index;
2154 }
2155
2156 if (sampler_idx >= 0) {
2157 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2158 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2159 } else {
2160 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2161 info.samp_idx = tex->texture_index;
2162 }
2163
2164 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2165 sampler,
2166 texture,
2167 }, 2);
2168 }
2169
2170 return info;
2171 }
2172
2173 static void
2174 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2175 {
2176 struct ir3_block *b = ctx->block;
2177 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2178 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2179 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2180 struct tex_src_info info = { 0 };
2181 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2182 unsigned i, coords, flags, ncomp;
2183 unsigned nsrc0 = 0, nsrc1 = 0;
2184 type_t type;
2185 opc_t opc = 0;
2186
2187 ncomp = nir_dest_num_components(tex->dest);
2188
2189 coord = off = ddx = ddy = NULL;
2190 lod = proj = compare = sample_index = NULL;
2191
2192 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2193
2194 for (unsigned i = 0; i < tex->num_srcs; i++) {
2195 switch (tex->src[i].src_type) {
2196 case nir_tex_src_coord:
2197 coord = ir3_get_src(ctx, &tex->src[i].src);
2198 break;
2199 case nir_tex_src_bias:
2200 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2201 has_bias = true;
2202 break;
2203 case nir_tex_src_lod:
2204 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2205 has_lod = true;
2206 break;
2207 case nir_tex_src_comparator: /* shadow comparator */
2208 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2209 break;
2210 case nir_tex_src_projector:
2211 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2212 has_proj = true;
2213 break;
2214 case nir_tex_src_offset:
2215 off = ir3_get_src(ctx, &tex->src[i].src);
2216 has_off = true;
2217 break;
2218 case nir_tex_src_ddx:
2219 ddx = ir3_get_src(ctx, &tex->src[i].src);
2220 break;
2221 case nir_tex_src_ddy:
2222 ddy = ir3_get_src(ctx, &tex->src[i].src);
2223 break;
2224 case nir_tex_src_ms_index:
2225 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2226 break;
2227 case nir_tex_src_texture_offset:
2228 case nir_tex_src_sampler_offset:
2229 case nir_tex_src_texture_handle:
2230 case nir_tex_src_sampler_handle:
2231 /* handled in get_tex_samp_src() */
2232 break;
2233 default:
2234 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2235 tex->src[i].src_type);
2236 return;
2237 }
2238 }
2239
2240 switch (tex->op) {
2241 case nir_texop_tex_prefetch:
2242 compile_assert(ctx, !has_bias);
2243 compile_assert(ctx, !has_lod);
2244 compile_assert(ctx, !compare);
2245 compile_assert(ctx, !has_proj);
2246 compile_assert(ctx, !has_off);
2247 compile_assert(ctx, !ddx);
2248 compile_assert(ctx, !ddy);
2249 compile_assert(ctx, !sample_index);
2250 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2251 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2252
2253 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2254 opc = OPC_META_TEX_PREFETCH;
2255 ctx->so->num_sampler_prefetch++;
2256 break;
2257 }
2258 /* fallthru */
2259 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2260 case nir_texop_txb: opc = OPC_SAMB; break;
2261 case nir_texop_txl: opc = OPC_SAML; break;
2262 case nir_texop_txd: opc = OPC_SAMGQ; break;
2263 case nir_texop_txf: opc = OPC_ISAML; break;
2264 case nir_texop_lod: opc = OPC_GETLOD; break;
2265 case nir_texop_tg4:
2266 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2267 * what blob does, seems gather is broken?), and a3xx did
2268 * not support it (but probably could also emulate).
2269 */
2270 switch (tex->component) {
2271 case 0: opc = OPC_GATHER4R; break;
2272 case 1: opc = OPC_GATHER4G; break;
2273 case 2: opc = OPC_GATHER4B; break;
2274 case 3: opc = OPC_GATHER4A; break;
2275 }
2276 break;
2277 case nir_texop_txf_ms_fb:
2278 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2279 default:
2280 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2281 return;
2282 }
2283
2284 tex_info(tex, &flags, &coords);
2285
2286 /*
2287 * lay out the first argument in the proper order:
2288 * - actual coordinates first
2289 * - shadow reference
2290 * - array index
2291 * - projection w
2292 * - starting at offset 4, dpdx.xy, dpdy.xy
2293 *
2294 * bias/lod go into the second arg
2295 */
2296
2297 /* insert tex coords: */
2298 for (i = 0; i < coords; i++)
2299 src0[i] = coord[i];
2300
2301 nsrc0 = i;
2302
2303 /* scale up integer coords for TXF based on the LOD */
2304 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2305 assert(has_lod);
2306 for (i = 0; i < coords; i++)
2307 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2308 }
2309
2310 if (coords == 1) {
2311 /* hw doesn't do 1d, so we treat it as 2d with
2312 * height of 1, and patch up the y coord.
2313 */
2314 if (is_isam(opc)) {
2315 src0[nsrc0++] = create_immed(b, 0);
2316 } else {
2317 src0[nsrc0++] = create_immed(b, fui(0.5));
2318 }
2319 }
2320
2321 if (tex->is_shadow && tex->op != nir_texop_lod)
2322 src0[nsrc0++] = compare;
2323
2324 if (tex->is_array && tex->op != nir_texop_lod) {
2325 struct ir3_instruction *idx = coord[coords];
2326
2327 /* the array coord for cube arrays needs 0.5 added to it */
2328 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2329 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2330
2331 src0[nsrc0++] = idx;
2332 }
2333
2334 if (has_proj) {
2335 src0[nsrc0++] = proj;
2336 flags |= IR3_INSTR_P;
2337 }
2338
2339 /* pad to 4, then ddx/ddy: */
2340 if (tex->op == nir_texop_txd) {
2341 while (nsrc0 < 4)
2342 src0[nsrc0++] = create_immed(b, fui(0.0));
2343 for (i = 0; i < coords; i++)
2344 src0[nsrc0++] = ddx[i];
2345 if (coords < 2)
2346 src0[nsrc0++] = create_immed(b, fui(0.0));
2347 for (i = 0; i < coords; i++)
2348 src0[nsrc0++] = ddy[i];
2349 if (coords < 2)
2350 src0[nsrc0++] = create_immed(b, fui(0.0));
2351 }
2352
2353 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2354 * with scaled x coord according to requested sample:
2355 */
2356 if (opc == OPC_ISAMM) {
2357 if (ctx->compiler->txf_ms_with_isaml) {
2358 /* the samples are laid out in x dimension as
2359 * 0 1 2 3
2360 * x_ms = (x << ms) + sample_index;
2361 */
2362 struct ir3_instruction *ms;
2363 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2364
2365 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2366 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2367
2368 opc = OPC_ISAML;
2369 } else {
2370 src0[nsrc0++] = sample_index;
2371 }
2372 }
2373
2374 /*
2375 * second argument (if applicable):
2376 * - offsets
2377 * - lod
2378 * - bias
2379 */
2380 if (has_off | has_lod | has_bias) {
2381 if (has_off) {
2382 unsigned off_coords = coords;
2383 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2384 off_coords--;
2385 for (i = 0; i < off_coords; i++)
2386 src1[nsrc1++] = off[i];
2387 if (off_coords < 2)
2388 src1[nsrc1++] = create_immed(b, fui(0.0));
2389 flags |= IR3_INSTR_O;
2390 }
2391
2392 if (has_lod | has_bias)
2393 src1[nsrc1++] = lod;
2394 }
2395
2396 type = get_tex_dest_type(tex);
2397
2398 if (opc == OPC_GETLOD)
2399 type = TYPE_S32;
2400
2401
2402 if (tex->op == nir_texop_txf_ms_fb) {
2403 /* only expect a single txf_ms_fb per shader: */
2404 compile_assert(ctx, !ctx->so->fb_read);
2405 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2406
2407 ctx->so->fb_read = true;
2408 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2409 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2410 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2411 }, 2);
2412 info.flags = IR3_INSTR_S2EN;
2413
2414 ctx->so->num_samp++;
2415 } else {
2416 info = get_tex_samp_tex_src(ctx, tex);
2417 }
2418
2419 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2420 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2421
2422 if (opc == OPC_META_TEX_PREFETCH) {
2423 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2424
2425 compile_assert(ctx, tex->src[idx].src.is_ssa);
2426
2427 sam = ir3_META_TEX_PREFETCH(b);
2428 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2429 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2430 sam->prefetch.input_offset =
2431 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2432 /* make sure not to add irrelevant flags like S2EN */
2433 sam->flags = flags | (info.flags & IR3_INSTR_B);
2434 sam->prefetch.tex = info.tex_idx;
2435 sam->prefetch.samp = info.samp_idx;
2436 sam->prefetch.tex_base = info.tex_base;
2437 sam->prefetch.samp_base = info.samp_base;
2438 } else {
2439 info.flags |= flags;
2440 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2441 }
2442
2443 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2444 assert(opc != OPC_META_TEX_PREFETCH);
2445
2446 /* only need first 3 components: */
2447 sam->regs[0]->wrmask = 0x7;
2448 ir3_split_dest(b, dst, sam, 0, 3);
2449
2450 /* we need to sample the alpha separately with a non-ASTC
2451 * texture state:
2452 */
2453 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2454 info.samp_tex, col0, col1);
2455
2456 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2457
2458 /* fixup .w component: */
2459 ir3_split_dest(b, &dst[3], sam, 3, 1);
2460 } else {
2461 /* normal (non-workaround) case: */
2462 ir3_split_dest(b, dst, sam, 0, ncomp);
2463 }
2464
2465 /* GETLOD returns results in 4.8 fixed point */
2466 if (opc == OPC_GETLOD) {
2467 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2468
2469 compile_assert(ctx, tex->dest_type == nir_type_float);
2470 for (i = 0; i < 2; i++) {
2471 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2472 factor, 0);
2473 }
2474 }
2475
2476 ir3_put_dst(ctx, &tex->dest);
2477 }
2478
2479 static void
2480 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2481 {
2482 struct ir3_block *b = ctx->block;
2483 struct ir3_instruction **dst, *sam;
2484 type_t dst_type = get_tex_dest_type(tex);
2485 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2486
2487 dst = ir3_get_dst(ctx, &tex->dest, 1);
2488
2489 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2490
2491 /* even though there is only one component, since it ends
2492 * up in .y/.z/.w rather than .x, we need a split_dest()
2493 */
2494 ir3_split_dest(b, dst, sam, idx, 1);
2495
2496 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2497 * the value in TEX_CONST_0 is zero-based.
2498 */
2499 if (ctx->compiler->levels_add_one)
2500 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2501
2502 ir3_put_dst(ctx, &tex->dest);
2503 }
2504
2505 static void
2506 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2507 {
2508 struct ir3_block *b = ctx->block;
2509 struct ir3_instruction **dst, *sam;
2510 struct ir3_instruction *lod;
2511 unsigned flags, coords;
2512 type_t dst_type = get_tex_dest_type(tex);
2513 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2514
2515 tex_info(tex, &flags, &coords);
2516 info.flags |= flags;
2517
2518 /* Actually we want the number of dimensions, not coordinates. This
2519 * distinction only matters for cubes.
2520 */
2521 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2522 coords = 2;
2523
2524 dst = ir3_get_dst(ctx, &tex->dest, 4);
2525
2526 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2527 compile_assert(ctx, lod_idx >= 0);
2528
2529 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2530
2531 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2532 ir3_split_dest(b, dst, sam, 0, 4);
2533
2534 /* Array size actually ends up in .w rather than .z. This doesn't
2535 * matter for miplevel 0, but for higher mips the value in z is
2536 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2537 * returned, which means that we have to add 1 to it for arrays.
2538 */
2539 if (tex->is_array) {
2540 if (ctx->compiler->levels_add_one) {
2541 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2542 } else {
2543 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2544 }
2545 }
2546
2547 ir3_put_dst(ctx, &tex->dest);
2548 }
2549
2550 static void
2551 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2552 {
2553 switch (jump->type) {
2554 case nir_jump_break:
2555 case nir_jump_continue:
2556 case nir_jump_return:
2557 /* I *think* we can simply just ignore this, and use the
2558 * successor block link to figure out where we need to
2559 * jump to for break/continue
2560 */
2561 break;
2562 default:
2563 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2564 break;
2565 }
2566 }
2567
2568 static void
2569 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2570 {
2571 switch (instr->type) {
2572 case nir_instr_type_alu:
2573 emit_alu(ctx, nir_instr_as_alu(instr));
2574 break;
2575 case nir_instr_type_deref:
2576 /* ignored, handled as part of the intrinsic they are src to */
2577 break;
2578 case nir_instr_type_intrinsic:
2579 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2580 break;
2581 case nir_instr_type_load_const:
2582 emit_load_const(ctx, nir_instr_as_load_const(instr));
2583 break;
2584 case nir_instr_type_ssa_undef:
2585 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2586 break;
2587 case nir_instr_type_tex: {
2588 nir_tex_instr *tex = nir_instr_as_tex(instr);
2589 /* couple tex instructions get special-cased:
2590 */
2591 switch (tex->op) {
2592 case nir_texop_txs:
2593 emit_tex_txs(ctx, tex);
2594 break;
2595 case nir_texop_query_levels:
2596 emit_tex_info(ctx, tex, 2);
2597 break;
2598 case nir_texop_texture_samples:
2599 emit_tex_info(ctx, tex, 3);
2600 break;
2601 default:
2602 emit_tex(ctx, tex);
2603 break;
2604 }
2605 break;
2606 }
2607 case nir_instr_type_jump:
2608 emit_jump(ctx, nir_instr_as_jump(instr));
2609 break;
2610 case nir_instr_type_phi:
2611 /* we have converted phi webs to regs in NIR by now */
2612 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2613 break;
2614 case nir_instr_type_call:
2615 case nir_instr_type_parallel_copy:
2616 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2617 break;
2618 }
2619 }
2620
2621 static struct ir3_block *
2622 get_block(struct ir3_context *ctx, const nir_block *nblock)
2623 {
2624 struct ir3_block *block;
2625 struct hash_entry *hentry;
2626
2627 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2628 if (hentry)
2629 return hentry->data;
2630
2631 block = ir3_block_create(ctx->ir);
2632 block->nblock = nblock;
2633 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2634
2635 set_foreach(nblock->predecessors, sentry) {
2636 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2637 }
2638
2639 return block;
2640 }
2641
2642 static void
2643 emit_block(struct ir3_context *ctx, nir_block *nblock)
2644 {
2645 struct ir3_block *block = get_block(ctx, nblock);
2646
2647 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2648 if (nblock->successors[i]) {
2649 block->successors[i] =
2650 get_block(ctx, nblock->successors[i]);
2651 }
2652 }
2653
2654 ctx->block = block;
2655 list_addtail(&block->node, &ctx->ir->block_list);
2656
2657 /* re-emit addr register in each block if needed: */
2658 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2659 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2660 ctx->addr0_ht[i] = NULL;
2661 }
2662
2663 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2664 ctx->addr1_ht = NULL;
2665
2666 nir_foreach_instr (instr, nblock) {
2667 ctx->cur_instr = instr;
2668 emit_instr(ctx, instr);
2669 ctx->cur_instr = NULL;
2670 if (ctx->error)
2671 return;
2672 }
2673
2674 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2675 }
2676
2677 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2678
2679 static void
2680 emit_if(struct ir3_context *ctx, nir_if *nif)
2681 {
2682 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2683
2684 ctx->block->condition = ir3_get_predicate(ctx, condition);
2685
2686 emit_cf_list(ctx, &nif->then_list);
2687 emit_cf_list(ctx, &nif->else_list);
2688 }
2689
2690 static void
2691 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2692 {
2693 emit_cf_list(ctx, &nloop->body);
2694 ctx->so->loops++;
2695 }
2696
2697 static void
2698 stack_push(struct ir3_context *ctx)
2699 {
2700 ctx->stack++;
2701 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2702 }
2703
2704 static void
2705 stack_pop(struct ir3_context *ctx)
2706 {
2707 compile_assert(ctx, ctx->stack > 0);
2708 ctx->stack--;
2709 }
2710
2711 static void
2712 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2713 {
2714 foreach_list_typed (nir_cf_node, node, node, list) {
2715 switch (node->type) {
2716 case nir_cf_node_block:
2717 emit_block(ctx, nir_cf_node_as_block(node));
2718 break;
2719 case nir_cf_node_if:
2720 stack_push(ctx);
2721 emit_if(ctx, nir_cf_node_as_if(node));
2722 stack_pop(ctx);
2723 break;
2724 case nir_cf_node_loop:
2725 stack_push(ctx);
2726 emit_loop(ctx, nir_cf_node_as_loop(node));
2727 stack_pop(ctx);
2728 break;
2729 case nir_cf_node_function:
2730 ir3_context_error(ctx, "TODO\n");
2731 break;
2732 }
2733 }
2734 }
2735
2736 /* emit stream-out code. At this point, the current block is the original
2737 * (nir) end block, and nir ensures that all flow control paths terminate
2738 * into the end block. We re-purpose the original end block to generate
2739 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2740 * block holding stream-out write instructions, followed by the new end
2741 * block:
2742 *
2743 * blockOrigEnd {
2744 * p0.x = (vtxcnt < maxvtxcnt)
2745 * // succs: blockStreamOut, blockNewEnd
2746 * }
2747 * blockStreamOut {
2748 * // preds: blockOrigEnd
2749 * ... stream-out instructions ...
2750 * // succs: blockNewEnd
2751 * }
2752 * blockNewEnd {
2753 * // preds: blockOrigEnd, blockStreamOut
2754 * }
2755 */
2756 static void
2757 emit_stream_out(struct ir3_context *ctx)
2758 {
2759 struct ir3 *ir = ctx->ir;
2760 struct ir3_stream_output_info *strmout =
2761 &ctx->so->shader->stream_output;
2762 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2763 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2764 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2765
2766 /* create vtxcnt input in input block at top of shader,
2767 * so that it is seen as live over the entire duration
2768 * of the shader:
2769 */
2770 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2771 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2772
2773 /* at this point, we are at the original 'end' block,
2774 * re-purpose this block to stream-out condition, then
2775 * append stream-out block and new-end block
2776 */
2777 orig_end_block = ctx->block;
2778
2779 // maybe w/ store_global intrinsic, we could do this
2780 // stuff in nir->nir pass
2781
2782 stream_out_block = ir3_block_create(ir);
2783 list_addtail(&stream_out_block->node, &ir->block_list);
2784
2785 new_end_block = ir3_block_create(ir);
2786 list_addtail(&new_end_block->node, &ir->block_list);
2787
2788 orig_end_block->successors[0] = stream_out_block;
2789 orig_end_block->successors[1] = new_end_block;
2790
2791 stream_out_block->successors[0] = new_end_block;
2792 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2793
2794 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2795 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2796
2797 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2798 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2799 cond->regs[0]->num = regid(REG_P0, 0);
2800 cond->regs[0]->flags &= ~IR3_REG_SSA;
2801 cond->cat2.condition = IR3_COND_LT;
2802
2803 /* condition goes on previous block to the conditional,
2804 * since it is used to pick which of the two successor
2805 * paths to take:
2806 */
2807 orig_end_block->condition = cond;
2808
2809 /* switch to stream_out_block to generate the stream-out
2810 * instructions:
2811 */
2812 ctx->block = stream_out_block;
2813
2814 /* Calculate base addresses based on vtxcnt. Instructions
2815 * generated for bases not used in following loop will be
2816 * stripped out in the backend.
2817 */
2818 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2819 const struct ir3_const_state *const_state =
2820 ir3_const_state(ctx->so);
2821 unsigned stride = strmout->stride[i];
2822 struct ir3_instruction *base, *off;
2823
2824 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2825
2826 /* 24-bit should be enough: */
2827 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2828 create_immed(ctx->block, stride * 4), 0);
2829
2830 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2831 }
2832
2833 /* Generate the per-output store instructions: */
2834 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2835 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2836 unsigned c = j + strmout->output[i].start_component;
2837 struct ir3_instruction *base, *out, *stg;
2838
2839 base = bases[strmout->output[i].output_buffer];
2840 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2841
2842 stg = ir3_STG(ctx->block, base, 0, out, 0,
2843 create_immed(ctx->block, 1), 0);
2844 stg->cat6.type = TYPE_U32;
2845 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2846
2847 array_insert(ctx->block, ctx->block->keeps, stg);
2848 }
2849 }
2850
2851 /* and finally switch to the new_end_block: */
2852 ctx->block = new_end_block;
2853 }
2854
2855 static void
2856 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2857 {
2858 nir_metadata_require(impl, nir_metadata_block_index);
2859
2860 compile_assert(ctx, ctx->stack == 0);
2861
2862 emit_cf_list(ctx, &impl->body);
2863 emit_block(ctx, impl->end_block);
2864
2865 compile_assert(ctx, ctx->stack == 0);
2866
2867 /* at this point, we should have a single empty block,
2868 * into which we emit the 'end' instruction.
2869 */
2870 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2871
2872 /* If stream-out (aka transform-feedback) enabled, emit the
2873 * stream-out instructions, followed by a new empty block (into
2874 * which the 'end' instruction lands).
2875 *
2876 * NOTE: it is done in this order, rather than inserting before
2877 * we emit end_block, because NIR guarantees that all blocks
2878 * flow into end_block, and that end_block has no successors.
2879 * So by re-purposing end_block as the first block of stream-
2880 * out, we guarantee that all exit paths flow into the stream-
2881 * out instructions.
2882 */
2883 if ((ctx->compiler->gpu_id < 500) &&
2884 (ctx->so->shader->stream_output.num_outputs > 0) &&
2885 !ctx->so->binning_pass) {
2886 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2887 emit_stream_out(ctx);
2888 }
2889
2890 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2891 * NOP and has an epilogue that writes the VS outputs to local storage, to
2892 * be read by the HS. Then it resets execution mask (chmask) and chains
2893 * to the next shader (chsh).
2894 */
2895 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2896 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2897 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2898 struct ir3_instruction *chmask =
2899 ir3_CHMASK(ctx->block);
2900 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2901 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2902
2903 struct ir3_instruction *chsh =
2904 ir3_CHSH(ctx->block);
2905 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2906 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2907 } else {
2908 ir3_END(ctx->block);
2909 }
2910 }
2911
2912 static void
2913 setup_input(struct ir3_context *ctx, nir_variable *in)
2914 {
2915 struct ir3_shader_variant *so = ctx->so;
2916 unsigned ncomp = glsl_get_components(in->type);
2917 unsigned n = in->data.driver_location;
2918 unsigned frac = in->data.location_frac;
2919 unsigned slot = in->data.location;
2920
2921 /* Inputs are loaded using ldlw or ldg for these stages. */
2922 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2923 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2924 ctx->so->type == MESA_SHADER_GEOMETRY)
2925 return;
2926
2927 /* skip unread inputs, we could end up with (for example), unsplit
2928 * matrix/etc inputs in the case they are not read, so just silently
2929 * skip these.
2930 */
2931 if (ncomp > 4)
2932 return;
2933
2934 so->inputs[n].slot = slot;
2935 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2936 so->inputs_count = MAX2(so->inputs_count, n + 1);
2937 so->inputs[n].interpolate = in->data.interpolation;
2938
2939 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2940
2941 /* if any varyings have 'sample' qualifer, that triggers us
2942 * to run in per-sample mode:
2943 */
2944 so->per_samp |= in->data.sample;
2945
2946 for (int i = 0; i < ncomp; i++) {
2947 struct ir3_instruction *instr = NULL;
2948 unsigned idx = (n * 4) + i + frac;
2949
2950 if (slot == VARYING_SLOT_POS) {
2951 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2952 } else {
2953 /* detect the special case for front/back colors where
2954 * we need to do flat vs smooth shading depending on
2955 * rast state:
2956 */
2957 if (in->data.interpolation == INTERP_MODE_NONE) {
2958 switch (slot) {
2959 case VARYING_SLOT_COL0:
2960 case VARYING_SLOT_COL1:
2961 case VARYING_SLOT_BFC0:
2962 case VARYING_SLOT_BFC1:
2963 so->inputs[n].rasterflat = true;
2964 break;
2965 default:
2966 break;
2967 }
2968 }
2969
2970 if (ctx->compiler->flat_bypass) {
2971 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2972 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2973 so->inputs[n].use_ldlv = true;
2974 }
2975
2976 so->inputs[n].bary = true;
2977
2978 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2979 }
2980
2981 compile_assert(ctx, idx < ctx->ninputs);
2982
2983 ctx->inputs[idx] = instr;
2984 }
2985 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2986 struct ir3_instruction *input = NULL;
2987 struct ir3_instruction *components[4];
2988 unsigned mask = (1 << (ncomp + frac)) - 1;
2989
2990 foreach_input (in, ctx->ir) {
2991 if (in->input.inidx == n) {
2992 input = in;
2993 break;
2994 }
2995 }
2996
2997 if (!input) {
2998 input = create_input(ctx, mask);
2999 input->input.inidx = n;
3000 } else {
3001 /* For aliased inputs, just append to the wrmask.. ie. if we
3002 * first see a vec2 index at slot N, and then later a vec4,
3003 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3004 *
3005 * If the new input that aliases a previously processed input
3006 * sets no new bits, then just bail as there is nothing to see
3007 * here.
3008 *
3009 * Note that we don't expect to get an input w/ frac!=0, if we
3010 * did we'd have to adjust ncomp and frac to cover the entire
3011 * merged input.
3012 */
3013 if (!(mask & ~input->regs[0]->wrmask))
3014 return;
3015 input->regs[0]->wrmask |= mask;
3016 }
3017
3018 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3019
3020 for (int i = 0; i < ncomp; i++) {
3021 unsigned idx = (n * 4) + i + frac;
3022 compile_assert(ctx, idx < ctx->ninputs);
3023
3024 /* With aliased inputs, since we add to the wrmask above, we
3025 * can end up with stale meta:split instructions in the inputs
3026 * table. This is basically harmless, since eventually they
3027 * will get swept away by DCE, but the mismatch wrmask (since
3028 * they would be using the previous wrmask before we OR'd in
3029 * more bits) angers ir3_validate. So just preemptively clean
3030 * them up. See:
3031 *
3032 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3033 *
3034 * Note however that split_dest() will return the src if it is
3035 * scalar, so the previous ctx->inputs[idx] could be the input
3036 * itself (which we don't want to remove)
3037 */
3038 if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) {
3039 list_del(&ctx->inputs[idx]->node);
3040 }
3041
3042 ctx->inputs[idx] = components[i];
3043 }
3044 } else {
3045 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3046 }
3047
3048 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3049 so->total_in += ncomp;
3050 }
3051 }
3052
3053 /* Initially we assign non-packed inloc's for varyings, as we don't really
3054 * know up-front which components will be unused. After all the compilation
3055 * stages we scan the shader to see which components are actually used, and
3056 * re-pack the inlocs to eliminate unneeded varyings.
3057 */
3058 static void
3059 pack_inlocs(struct ir3_context *ctx)
3060 {
3061 struct ir3_shader_variant *so = ctx->so;
3062 uint8_t used_components[so->inputs_count];
3063
3064 memset(used_components, 0, sizeof(used_components));
3065
3066 /*
3067 * First Step: scan shader to find which bary.f/ldlv remain:
3068 */
3069
3070 foreach_block (block, &ctx->ir->block_list) {
3071 foreach_instr (instr, &block->instr_list) {
3072 if (is_input(instr)) {
3073 unsigned inloc = instr->regs[1]->iim_val;
3074 unsigned i = inloc / 4;
3075 unsigned j = inloc % 4;
3076
3077 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3078 compile_assert(ctx, i < so->inputs_count);
3079
3080 used_components[i] |= 1 << j;
3081 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3082 for (int n = 0; n < 2; n++) {
3083 unsigned inloc = instr->prefetch.input_offset + n;
3084 unsigned i = inloc / 4;
3085 unsigned j = inloc % 4;
3086
3087 compile_assert(ctx, i < so->inputs_count);
3088
3089 used_components[i] |= 1 << j;
3090 }
3091 }
3092 }
3093 }
3094
3095 /*
3096 * Second Step: reassign varying inloc/slots:
3097 */
3098
3099 unsigned actual_in = 0;
3100 unsigned inloc = 0;
3101
3102 for (unsigned i = 0; i < so->inputs_count; i++) {
3103 unsigned compmask = 0, maxcomp = 0;
3104
3105 so->inputs[i].inloc = inloc;
3106 so->inputs[i].bary = false;
3107
3108 for (unsigned j = 0; j < 4; j++) {
3109 if (!(used_components[i] & (1 << j)))
3110 continue;
3111
3112 compmask |= (1 << j);
3113 actual_in++;
3114 maxcomp = j + 1;
3115
3116 /* at this point, since used_components[i] mask is only
3117 * considering varyings (ie. not sysvals) we know this
3118 * is a varying:
3119 */
3120 so->inputs[i].bary = true;
3121 }
3122
3123 if (so->inputs[i].bary) {
3124 so->varying_in++;
3125 so->inputs[i].compmask = (1 << maxcomp) - 1;
3126 inloc += maxcomp;
3127 }
3128 }
3129
3130 /*
3131 * Third Step: reassign packed inloc's:
3132 */
3133
3134 foreach_block (block, &ctx->ir->block_list) {
3135 foreach_instr (instr, &block->instr_list) {
3136 if (is_input(instr)) {
3137 unsigned inloc = instr->regs[1]->iim_val;
3138 unsigned i = inloc / 4;
3139 unsigned j = inloc % 4;
3140
3141 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3142 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3143 unsigned i = instr->prefetch.input_offset / 4;
3144 unsigned j = instr->prefetch.input_offset % 4;
3145 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3146 }
3147 }
3148 }
3149 }
3150
3151 static void
3152 setup_output(struct ir3_context *ctx, nir_variable *out)
3153 {
3154 struct ir3_shader_variant *so = ctx->so;
3155 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3156 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3157 unsigned n = out->data.driver_location;
3158 unsigned frac = out->data.location_frac;
3159 unsigned slot = out->data.location;
3160
3161 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3162 switch (slot) {
3163 case FRAG_RESULT_DEPTH:
3164 so->writes_pos = true;
3165 break;
3166 case FRAG_RESULT_COLOR:
3167 so->color0_mrt = 1;
3168 break;
3169 case FRAG_RESULT_SAMPLE_MASK:
3170 so->writes_smask = true;
3171 break;
3172 default:
3173 slot += out->data.index; /* For dual-src blend */
3174 if (slot >= FRAG_RESULT_DATA0)
3175 break;
3176 ir3_context_error(ctx, "unknown FS output name: %s\n",
3177 gl_frag_result_name(slot));
3178 }
3179 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3180 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3181 ctx->so->type == MESA_SHADER_GEOMETRY) {
3182 switch (slot) {
3183 case VARYING_SLOT_POS:
3184 so->writes_pos = true;
3185 break;
3186 case VARYING_SLOT_PSIZ:
3187 so->writes_psize = true;
3188 break;
3189 case VARYING_SLOT_PRIMITIVE_ID:
3190 case VARYING_SLOT_LAYER:
3191 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3192 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3193 /* fall through */
3194 case VARYING_SLOT_COL0:
3195 case VARYING_SLOT_COL1:
3196 case VARYING_SLOT_BFC0:
3197 case VARYING_SLOT_BFC1:
3198 case VARYING_SLOT_FOGC:
3199 case VARYING_SLOT_CLIP_DIST0:
3200 case VARYING_SLOT_CLIP_DIST1:
3201 case VARYING_SLOT_CLIP_VERTEX:
3202 break;
3203 default:
3204 if (slot >= VARYING_SLOT_VAR0)
3205 break;
3206 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3207 break;
3208 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3209 _mesa_shader_stage_to_string(ctx->so->type),
3210 gl_varying_slot_name(slot));
3211 }
3212 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3213 /* output lowered to buffer writes. */
3214 return;
3215 } else {
3216 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3217 }
3218
3219
3220 so->outputs_count = out->data.driver_location + slots;
3221 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3222
3223 for (int i = 0; i < slots; i++) {
3224 int slot_base = n + i;
3225 so->outputs[slot_base].slot = slot + i;
3226
3227 for (int i = 0; i < ncomp; i++) {
3228 unsigned idx = (slot_base * 4) + i + frac;
3229 compile_assert(ctx, idx < ctx->noutputs);
3230 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3231 }
3232
3233 /* if varying packing doesn't happen, we could end up in a situation
3234 * with "holes" in the output, and since the per-generation code that
3235 * sets up varying linkage registers doesn't expect to have more than
3236 * one varying per vec4 slot, pad the holes.
3237 *
3238 * Note that this should probably generate a performance warning of
3239 * some sort.
3240 */
3241 for (int i = 0; i < frac; i++) {
3242 unsigned idx = (slot_base * 4) + i;
3243 if (!ctx->outputs[idx]) {
3244 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3245 }
3246 }
3247 }
3248 }
3249
3250 static void
3251 emit_instructions(struct ir3_context *ctx)
3252 {
3253 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3254
3255 ctx->ninputs = ctx->s->num_inputs * 4;
3256 ctx->noutputs = ctx->s->num_outputs * 4;
3257 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3258 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3259
3260 ctx->ir = ir3_create(ctx->compiler, ctx->so);
3261
3262 /* Create inputs in first block: */
3263 ctx->block = get_block(ctx, nir_start_block(fxn));
3264 ctx->in_block = ctx->block;
3265
3266 /* for fragment shader, the vcoord input register is used as the
3267 * base for bary.f varying fetch instrs:
3268 *
3269 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3270 * until emit_intrinsic when we know they are actually needed.
3271 * For now, we defer creating ctx->ij_centroid, etc, since we
3272 * only need ij_pixel for "old style" varying inputs (ie.
3273 * tgsi_to_nir)
3274 */
3275 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3276 ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3);
3277 }
3278
3279 /* Setup inputs: */
3280 nir_foreach_variable (var, &ctx->s->inputs) {
3281 setup_input(ctx, var);
3282 }
3283
3284 /* Defer add_sysval_input() stuff until after setup_inputs(),
3285 * because sysvals need to be appended after varyings:
3286 */
3287 if (ctx->ij[IJ_PERSP_PIXEL]) {
3288 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3289 0x3, ctx->ij[IJ_PERSP_PIXEL]);
3290 }
3291
3292
3293 /* Tesselation shaders always need primitive ID for indexing the
3294 * BO. Geometry shaders don't always need it but when they do it has be
3295 * delivered and unclobbered in the VS. To make things easy, we always
3296 * make room for it in VS/DS.
3297 */
3298 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3299 bool has_gs = ctx->so->key.has_gs;
3300 switch (ctx->so->type) {
3301 case MESA_SHADER_VERTEX:
3302 if (has_tess) {
3303 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3304 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3305 } else if (has_gs) {
3306 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3307 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3308 }
3309 break;
3310 case MESA_SHADER_TESS_CTRL:
3311 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3312 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3313 break;
3314 case MESA_SHADER_TESS_EVAL:
3315 if (has_gs)
3316 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3317 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3318 break;
3319 case MESA_SHADER_GEOMETRY:
3320 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3321 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3322 break;
3323 default:
3324 break;
3325 }
3326
3327 /* Setup outputs: */
3328 nir_foreach_variable (var, &ctx->s->outputs) {
3329 setup_output(ctx, var);
3330 }
3331
3332 /* Find # of samplers. Just assume that we'll be reading from images.. if
3333 * it is write-only we don't have to count it, but after lowering derefs
3334 * is too late to compact indices for that.
3335 */
3336 ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images;
3337
3338 /* NOTE: need to do something more clever when we support >1 fxn */
3339 nir_foreach_register (reg, &fxn->registers) {
3340 ir3_declare_array(ctx, reg);
3341 }
3342 /* And emit the body: */
3343 ctx->impl = fxn;
3344 emit_function(ctx, fxn);
3345 }
3346
3347 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3348 * need to assign the tex state indexes for these after we know the
3349 * max tex index.
3350 */
3351 static void
3352 fixup_astc_srgb(struct ir3_context *ctx)
3353 {
3354 struct ir3_shader_variant *so = ctx->so;
3355 /* indexed by original tex idx, value is newly assigned alpha sampler
3356 * state tex idx. Zero is invalid since there is at least one sampler
3357 * if we get here.
3358 */
3359 unsigned alt_tex_state[16] = {0};
3360 unsigned tex_idx = ctx->max_texture_index + 1;
3361 unsigned idx = 0;
3362
3363 so->astc_srgb.base = tex_idx;
3364
3365 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3366 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3367
3368 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3369
3370 if (alt_tex_state[sam->cat5.tex] == 0) {
3371 /* assign new alternate/alpha tex state slot: */
3372 alt_tex_state[sam->cat5.tex] = tex_idx++;
3373 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3374 so->astc_srgb.count++;
3375 }
3376
3377 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3378 }
3379 }
3380
3381 static void
3382 fixup_binning_pass(struct ir3_context *ctx)
3383 {
3384 struct ir3_shader_variant *so = ctx->so;
3385 struct ir3 *ir = ctx->ir;
3386 unsigned i, j;
3387
3388 /* first pass, remove unused outputs from the IR level outputs: */
3389 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3390 struct ir3_instruction *out = ir->outputs[i];
3391 assert(out->opc == OPC_META_COLLECT);
3392 unsigned outidx = out->collect.outidx;
3393 unsigned slot = so->outputs[outidx].slot;
3394
3395 /* throw away everything but first position/psize */
3396 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3397 ir->outputs[j] = ir->outputs[i];
3398 j++;
3399 }
3400 }
3401 ir->outputs_count = j;
3402
3403 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3404 * table:
3405 */
3406 for (i = 0, j = 0; i < so->outputs_count; i++) {
3407 unsigned slot = so->outputs[i].slot;
3408
3409 /* throw away everything but first position/psize */
3410 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3411 so->outputs[j] = so->outputs[i];
3412
3413 /* fixup outidx to point to new output table entry: */
3414 foreach_output (out, ir) {
3415 if (out->collect.outidx == i) {
3416 out->collect.outidx = j;
3417 break;
3418 }
3419 }
3420
3421 j++;
3422 }
3423 }
3424 so->outputs_count = j;
3425 }
3426
3427 static void
3428 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3429 {
3430 unsigned idx = 0;
3431
3432 /* Collect sampling instructions eligible for pre-dispatch. */
3433 foreach_block (block, &ir->block_list) {
3434 foreach_instr_safe (instr, &block->instr_list) {
3435 if (instr->opc == OPC_META_TEX_PREFETCH) {
3436 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3437 struct ir3_sampler_prefetch *fetch =
3438 &ctx->so->sampler_prefetch[idx];
3439 idx++;
3440
3441 if (instr->flags & IR3_INSTR_B) {
3442 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3443 /* In bindless mode, the index is actually the base */
3444 fetch->tex_id = instr->prefetch.tex_base;
3445 fetch->samp_id = instr->prefetch.samp_base;
3446 fetch->tex_bindless_id = instr->prefetch.tex;
3447 fetch->samp_bindless_id = instr->prefetch.samp;
3448 } else {
3449 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3450 fetch->tex_id = instr->prefetch.tex;
3451 fetch->samp_id = instr->prefetch.samp;
3452 }
3453 fetch->wrmask = instr->regs[0]->wrmask;
3454 fetch->dst = instr->regs[0]->num;
3455 fetch->src = instr->prefetch.input_offset;
3456
3457 /* These are the limits on a5xx/a6xx, we might need to
3458 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3459 */
3460 assert(fetch->dst <= 0x3f);
3461 assert(fetch->tex_id <= 0x1f);
3462 assert(fetch->samp_id < 0xf);
3463
3464 ctx->so->total_in =
3465 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3466
3467 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3468
3469 /* Remove the prefetch placeholder instruction: */
3470 list_delinit(&instr->node);
3471 }
3472 }
3473 }
3474 }
3475
3476 int
3477 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3478 struct ir3_shader_variant *so)
3479 {
3480 struct ir3_context *ctx;
3481 struct ir3 *ir;
3482 int ret = 0, max_bary;
3483 bool progress;
3484
3485 assert(!so->ir);
3486
3487 ctx = ir3_context_init(compiler, so);
3488 if (!ctx) {
3489 DBG("INIT failed!");
3490 ret = -1;
3491 goto out;
3492 }
3493
3494 emit_instructions(ctx);
3495
3496 if (ctx->error) {
3497 DBG("EMIT failed!");
3498 ret = -1;
3499 goto out;
3500 }
3501
3502 ir = so->ir = ctx->ir;
3503
3504 assert((ctx->noutputs % 4) == 0);
3505
3506 /* Setup IR level outputs, which are "collects" that gather
3507 * the scalar components of outputs.
3508 */
3509 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3510 unsigned ncomp = 0;
3511 /* figure out the # of components written:
3512 *
3513 * TODO do we need to handle holes, ie. if .x and .z
3514 * components written, but .y component not written?
3515 */
3516 for (unsigned j = 0; j < 4; j++) {
3517 if (!ctx->outputs[i + j])
3518 break;
3519 ncomp++;
3520 }
3521
3522 /* Note that in some stages, like TCS, store_output is
3523 * lowered to memory writes, so no components of the
3524 * are "written" from the PoV of traditional store-
3525 * output instructions:
3526 */
3527 if (!ncomp)
3528 continue;
3529
3530 struct ir3_instruction *out =
3531 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3532
3533 int outidx = i / 4;
3534 assert(outidx < so->outputs_count);
3535
3536 /* stash index into so->outputs[] so we can map the
3537 * output back to slot/etc later:
3538 */
3539 out->collect.outidx = outidx;
3540
3541 array_insert(ir, ir->outputs, out);
3542 }
3543
3544 /* Set up the gs header as an output for the vertex shader so it won't
3545 * clobber it for the tess ctrl shader.
3546 *
3547 * TODO this could probably be done more cleanly in a nir pass.
3548 */
3549 if (ctx->so->type == MESA_SHADER_VERTEX ||
3550 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3551 if (ctx->primitive_id) {
3552 unsigned n = so->outputs_count++;
3553 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3554
3555 struct ir3_instruction *out =
3556 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3557 out->collect.outidx = n;
3558 array_insert(ir, ir->outputs, out);
3559 }
3560
3561 if (ctx->gs_header) {
3562 unsigned n = so->outputs_count++;
3563 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3564 struct ir3_instruction *out =
3565 ir3_create_collect(ctx, &ctx->gs_header, 1);
3566 out->collect.outidx = n;
3567 array_insert(ir, ir->outputs, out);
3568 }
3569
3570 if (ctx->tcs_header) {
3571 unsigned n = so->outputs_count++;
3572 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3573 struct ir3_instruction *out =
3574 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3575 out->collect.outidx = n;
3576 array_insert(ir, ir->outputs, out);
3577 }
3578 }
3579
3580 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3581 * need to make sure not to remove any inputs that are used by
3582 * the nonbinning VS.
3583 */
3584 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3585 so->type == MESA_SHADER_VERTEX) {
3586 for (int i = 0; i < ctx->ninputs; i++) {
3587 struct ir3_instruction *in = ctx->inputs[i];
3588
3589 if (!in)
3590 continue;
3591
3592 unsigned n = i / 4;
3593 unsigned c = i % 4;
3594
3595 debug_assert(n < so->nonbinning->inputs_count);
3596
3597 if (so->nonbinning->inputs[n].sysval)
3598 continue;
3599
3600 /* be sure to keep inputs, even if only used in VS */
3601 if (so->nonbinning->inputs[n].compmask & (1 << c))
3602 array_insert(in->block, in->block->keeps, in);
3603 }
3604 }
3605
3606 /* at this point, for binning pass, throw away unneeded outputs: */
3607 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3608 fixup_binning_pass(ctx);
3609
3610 ir3_debug_print(ir, "AFTER: nir->ir3");
3611 ir3_validate(ir);
3612
3613 do {
3614 progress = false;
3615
3616 progress |= IR3_PASS(ir, ir3_cf);
3617 progress |= IR3_PASS(ir, ir3_cp, so);
3618 progress |= IR3_PASS(ir, ir3_dce, so);
3619 } while (progress);
3620
3621 /* at this point, for binning pass, throw away unneeded outputs:
3622 * Note that for a6xx and later, we do this after ir3_cp to ensure
3623 * that the uniform/constant layout for BS and VS matches, so that
3624 * we can re-use same VS_CONST state group.
3625 */
3626 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
3627 fixup_binning_pass(ctx);
3628 /* cleanup the result of removing unneeded outputs: */
3629 while (IR3_PASS(ir, ir3_dce, so)) {}
3630 }
3631
3632 IR3_PASS(ir, ir3_sched_add_deps);
3633
3634 /* Group left/right neighbors, inserting mov's where needed to
3635 * solve conflicts:
3636 */
3637 IR3_PASS(ir, ir3_group);
3638
3639 /* At this point, all the dead code should be long gone: */
3640 assert(!IR3_PASS(ir, ir3_dce, so));
3641
3642 ret = ir3_sched(ir);
3643 if (ret) {
3644 DBG("SCHED failed!");
3645 goto out;
3646 }
3647
3648 ir3_debug_print(ir, "AFTER: ir3_sched");
3649
3650 if (IR3_PASS(ir, ir3_cp_postsched)) {
3651 /* cleanup the result of removing unneeded mov's: */
3652 while (IR3_PASS(ir, ir3_dce, so)) {}
3653 }
3654
3655 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3656 * with draw pass VS, so binning and draw pass can both use the
3657 * same VBO state.
3658 *
3659 * Note that VS inputs are expected to be full precision.
3660 */
3661 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3662 (ir->type == MESA_SHADER_VERTEX) &&
3663 so->binning_pass;
3664
3665 if (pre_assign_inputs) {
3666 for (unsigned i = 0; i < ctx->ninputs; i++) {
3667 struct ir3_instruction *instr = ctx->inputs[i];
3668
3669 if (!instr)
3670 continue;
3671
3672 unsigned n = i / 4;
3673 unsigned c = i % 4;
3674 unsigned regid = so->nonbinning->inputs[n].regid + c;
3675
3676 instr->regs[0]->num = regid;
3677 }
3678
3679 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3680 } else if (ctx->tcs_header) {
3681 /* We need to have these values in the same registers between VS and TCS
3682 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3683 */
3684
3685 ctx->tcs_header->regs[0]->num = regid(0, 0);
3686 ctx->primitive_id->regs[0]->num = regid(0, 1);
3687 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3688 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3689 } else if (ctx->gs_header) {
3690 /* We need to have these values in the same registers between producer
3691 * (VS or DS) and GS since the producer chains to GS and doesn't get
3692 * the sysvals redelivered.
3693 */
3694
3695 ctx->gs_header->regs[0]->num = regid(0, 0);
3696 ctx->primitive_id->regs[0]->num = regid(0, 1);
3697 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3698 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3699 } else if (so->num_sampler_prefetch) {
3700 assert(so->type == MESA_SHADER_FRAGMENT);
3701 struct ir3_instruction *precolor[2];
3702 int idx = 0;
3703
3704 foreach_input (instr, ir) {
3705 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3706 continue;
3707
3708 assert(idx < ARRAY_SIZE(precolor));
3709
3710 precolor[idx] = instr;
3711 instr->regs[0]->num = idx;
3712
3713 idx++;
3714 }
3715 ret = ir3_ra(so, precolor, idx);
3716 } else {
3717 ret = ir3_ra(so, NULL, 0);
3718 }
3719
3720 if (ret) {
3721 DBG("RA failed!");
3722 goto out;
3723 }
3724
3725 IR3_PASS(ir, ir3_postsched, so);
3726
3727 if (compiler->gpu_id >= 600) {
3728 IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
3729 }
3730
3731 if (so->type == MESA_SHADER_FRAGMENT)
3732 pack_inlocs(ctx);
3733
3734 /*
3735 * Fixup inputs/outputs to point to the actual registers assigned:
3736 *
3737 * 1) initialize to r63.x (invalid/unused)
3738 * 2) iterate IR level inputs/outputs and update the variants
3739 * inputs/outputs table based on the assigned registers for
3740 * the remaining inputs/outputs.
3741 */
3742
3743 for (unsigned i = 0; i < so->inputs_count; i++)
3744 so->inputs[i].regid = INVALID_REG;
3745 for (unsigned i = 0; i < so->outputs_count; i++)
3746 so->outputs[i].regid = INVALID_REG;
3747
3748 foreach_output (out, ir) {
3749 assert(out->opc == OPC_META_COLLECT);
3750 unsigned outidx = out->collect.outidx;
3751
3752 so->outputs[outidx].regid = out->regs[0]->num;
3753 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3754 }
3755
3756 foreach_input (in, ir) {
3757 assert(in->opc == OPC_META_INPUT);
3758 unsigned inidx = in->input.inidx;
3759
3760 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3761 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3762 compile_assert(ctx, in->regs[0]->num ==
3763 so->nonbinning->inputs[inidx].regid);
3764 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3765 so->nonbinning->inputs[inidx].half);
3766 }
3767 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3768 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3769 } else {
3770 so->inputs[inidx].regid = in->regs[0]->num;
3771 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3772 }
3773 }
3774
3775 if (ctx->astc_srgb)
3776 fixup_astc_srgb(ctx);
3777
3778 /* We need to do legalize after (for frag shader's) the "bary.f"
3779 * offsets (inloc) have been assigned.
3780 */
3781 IR3_PASS(ir, ir3_legalize, so, &max_bary);
3782
3783 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3784 * know what we might have to wait on when coming in from VS chsh.
3785 */
3786 if (so->type == MESA_SHADER_TESS_CTRL ||
3787 so->type == MESA_SHADER_GEOMETRY ) {
3788 foreach_block (block, &ir->block_list) {
3789 foreach_instr (instr, &block->instr_list) {
3790 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3791 break;
3792 }
3793 }
3794 }
3795
3796 so->branchstack = ctx->max_stack;
3797
3798 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3799 if (so->type == MESA_SHADER_FRAGMENT)
3800 so->total_in = max_bary + 1;
3801
3802 /* Collect sampling instructions eligible for pre-dispatch. */
3803 collect_tex_prefetches(ctx, ir);
3804
3805 if (so->type == MESA_SHADER_FRAGMENT &&
3806 ctx->s->info.fs.needs_helper_invocations)
3807 so->need_pixlod = true;
3808
3809 out:
3810 if (ret) {
3811 if (so->ir)
3812 ir3_destroy(so->ir);
3813 so->ir = NULL;
3814 }
3815 ir3_context_free(ctx);
3816
3817 return ret;
3818 }