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freedreno/ir3: Plumb the ir3_shader_variant into legalize.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddy:
471 case nir_op_fddy_coarse:
472 dst[0] = ir3_DSY(b, src[0], 0);
473 dst[0]->cat5.type = TYPE_F32;
474 break;
475 break;
476 case nir_op_flt16:
477 case nir_op_flt32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_LT;
480 break;
481 case nir_op_fge16:
482 case nir_op_fge32:
483 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
484 dst[0]->cat2.condition = IR3_COND_GE;
485 break;
486 case nir_op_feq16:
487 case nir_op_feq32:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne16:
492 case nir_op_fne32:
493 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
494 dst[0]->cat2.condition = IR3_COND_NE;
495 break;
496 case nir_op_fceil:
497 dst[0] = ir3_CEIL_F(b, src[0], 0);
498 break;
499 case nir_op_ffloor:
500 dst[0] = ir3_FLOOR_F(b, src[0], 0);
501 break;
502 case nir_op_ftrunc:
503 dst[0] = ir3_TRUNC_F(b, src[0], 0);
504 break;
505 case nir_op_fround_even:
506 dst[0] = ir3_RNDNE_F(b, src[0], 0);
507 break;
508 case nir_op_fsign:
509 dst[0] = ir3_SIGN_F(b, src[0], 0);
510 break;
511
512 case nir_op_fsin:
513 dst[0] = ir3_SIN(b, src[0], 0);
514 break;
515 case nir_op_fcos:
516 dst[0] = ir3_COS(b, src[0], 0);
517 break;
518 case nir_op_frsq:
519 dst[0] = ir3_RSQ(b, src[0], 0);
520 break;
521 case nir_op_frcp:
522 dst[0] = ir3_RCP(b, src[0], 0);
523 break;
524 case nir_op_flog2:
525 dst[0] = ir3_LOG2(b, src[0], 0);
526 break;
527 case nir_op_fexp2:
528 dst[0] = ir3_EXP2(b, src[0], 0);
529 break;
530 case nir_op_fsqrt:
531 dst[0] = ir3_SQRT(b, src[0], 0);
532 break;
533
534 case nir_op_iabs:
535 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
536 break;
537 case nir_op_iadd:
538 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_iand:
541 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_imax:
544 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_umax:
547 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_imin:
550 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umin:
553 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_umul_low:
556 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
557 break;
558 case nir_op_imadsh_mix16:
559 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
560 break;
561 case nir_op_imad24_ir3:
562 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
563 break;
564 case nir_op_imul24:
565 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ineg:
568 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
569 break;
570 case nir_op_inot:
571 dst[0] = ir3_NOT_B(b, src[0], 0);
572 break;
573 case nir_op_ior:
574 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ishl:
577 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishr:
580 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_isub:
583 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ixor:
586 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ushr:
589 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ilt16:
592 case nir_op_ilt32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_LT;
595 break;
596 case nir_op_ige16:
597 case nir_op_ige32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_GE;
600 break;
601 case nir_op_ieq16:
602 case nir_op_ieq32:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine16:
607 case nir_op_ine32:
608 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_NE;
610 break;
611 case nir_op_ult16:
612 case nir_op_ult32:
613 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
614 dst[0]->cat2.condition = IR3_COND_LT;
615 break;
616 case nir_op_uge16:
617 case nir_op_uge32:
618 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_GE;
620 break;
621
622 case nir_op_b16csel:
623 case nir_op_b32csel: {
624 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
625
626 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
627 cond->regs[0]->flags |= IR3_REG_HALF;
628
629 compile_assert(ctx, bs[1] == bs[2]);
630 /* Make sure the boolean condition has the same bit size as the other
631 * two arguments, adding a conversion if necessary.
632 */
633 if (bs[1] < bs[0])
634 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
635 else if (bs[1] > bs[0])
636 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
637
638 if (bs[1] > 16)
639 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
640 else
641 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
642 break;
643 }
644 case nir_op_bit_count: {
645 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
646 // double check on earlier gen's. Once half-precision support is
647 // in place, this should probably move to a NIR lowering pass:
648 struct ir3_instruction *hi, *lo;
649
650 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
651 TYPE_U32, TYPE_U16);
652 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
653
654 hi = ir3_CBITS_B(b, hi, 0);
655 lo = ir3_CBITS_B(b, lo, 0);
656
657 // TODO maybe the builders should default to making dst half-precision
658 // if the src's were half precision, to make this less awkward.. otoh
659 // we should probably just do this lowering in NIR.
660 hi->regs[0]->flags |= IR3_REG_HALF;
661 lo->regs[0]->flags |= IR3_REG_HALF;
662
663 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
664 dst[0]->regs[0]->flags |= IR3_REG_HALF;
665 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
666 break;
667 }
668 case nir_op_ifind_msb: {
669 struct ir3_instruction *cmp;
670 dst[0] = ir3_CLZ_S(b, src[0], 0);
671 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
672 cmp->cat2.condition = IR3_COND_GE;
673 dst[0] = ir3_SEL_B32(b,
674 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
675 cmp, 0, dst[0], 0);
676 break;
677 }
678 case nir_op_ufind_msb:
679 dst[0] = ir3_CLZ_B(b, src[0], 0);
680 dst[0] = ir3_SEL_B32(b,
681 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
682 src[0], 0, dst[0], 0);
683 break;
684 case nir_op_find_lsb:
685 dst[0] = ir3_BFREV_B(b, src[0], 0);
686 dst[0] = ir3_CLZ_B(b, dst[0], 0);
687 break;
688 case nir_op_bitfield_reverse:
689 dst[0] = ir3_BFREV_B(b, src[0], 0);
690 break;
691
692 default:
693 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
694 nir_op_infos[alu->op].name);
695 break;
696 }
697
698 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
699 assert(dst_sz == 1);
700
701 if (nir_dest_bit_size(alu->dest.dest) < 32)
702 dst[0]->regs[0]->flags |= IR3_REG_HALF;
703
704 dst[0] = ir3_n2b(b, dst[0]);
705 }
706
707 if (nir_dest_bit_size(alu->dest.dest) < 32) {
708 for (unsigned i = 0; i < dst_sz; i++) {
709 dst[i]->regs[0]->flags |= IR3_REG_HALF;
710 }
711 }
712
713 ir3_put_dst(ctx, &alu->dest.dest);
714 }
715
716 /* handles direct/indirect UBO reads: */
717 static void
718 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
719 struct ir3_instruction **dst)
720 {
721 struct ir3_block *b = ctx->block;
722 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
723 /* UBO addresses are the first driver params, but subtract 2 here to
724 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
725 * is the uniforms: */
726 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
727 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
728 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
729
730 int off = 0;
731
732 /* First src is ubo index, which could either be an immed or not: */
733 src0 = ir3_get_src(ctx, &intr->src[0])[0];
734 if (is_same_type_mov(src0) &&
735 (src0->regs[1]->flags & IR3_REG_IMMED)) {
736 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
737 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
738 } else {
739 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
740 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
741
742 /* NOTE: since relative addressing is used, make sure constlen is
743 * at least big enough to cover all the UBO addresses, since the
744 * assembler won't know what the max address reg is.
745 */
746 ctx->so->constlen = MAX2(ctx->so->constlen,
747 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
748 }
749
750 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
751 addr = base_lo;
752
753 if (nir_src_is_const(intr->src[1])) {
754 off += nir_src_as_uint(intr->src[1]);
755 } else {
756 /* For load_ubo_indirect, second src is indirect offset: */
757 src1 = ir3_get_src(ctx, &intr->src[1])[0];
758
759 /* and add offset to addr: */
760 addr = ir3_ADD_S(b, addr, 0, src1, 0);
761 }
762
763 /* if offset is to large to encode in the ldg, split it out: */
764 if ((off + (intr->num_components * 4)) > 1024) {
765 /* split out the minimal amount to improve the odds that
766 * cp can fit the immediate in the add.s instruction:
767 */
768 unsigned off2 = off + (intr->num_components * 4) - 1024;
769 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
770 off -= off2;
771 }
772
773 if (ptrsz == 2) {
774 struct ir3_instruction *carry;
775
776 /* handle 32b rollover, ie:
777 * if (addr < base_lo)
778 * base_hi++
779 */
780 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
781 carry->cat2.condition = IR3_COND_LT;
782 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
783
784 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
785 }
786
787 for (int i = 0; i < intr->num_components; i++) {
788 struct ir3_instruction *load =
789 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
790 create_immed(b, off + i * 4), 0);
791 load->cat6.type = TYPE_U32;
792 dst[i] = load;
793 }
794 }
795
796 /* src[] = { block_index } */
797 static void
798 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
799 struct ir3_instruction **dst)
800 {
801 /* SSBO size stored as a const starting at ssbo_sizes: */
802 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
803 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
804 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
805 const_state->ssbo_size.off[blk_idx];
806
807 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
808
809 dst[0] = create_uniform(ctx->block, idx);
810 }
811
812 /* src[] = { offset }. const_index[] = { base } */
813 static void
814 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
815 struct ir3_instruction **dst)
816 {
817 struct ir3_block *b = ctx->block;
818 struct ir3_instruction *ldl, *offset;
819 unsigned base;
820
821 offset = ir3_get_src(ctx, &intr->src[0])[0];
822 base = nir_intrinsic_base(intr);
823
824 ldl = ir3_LDL(b, offset, 0,
825 create_immed(b, intr->num_components), 0,
826 create_immed(b, base), 0);
827
828 ldl->cat6.type = utype_dst(intr->dest);
829 ldl->regs[0]->wrmask = MASK(intr->num_components);
830
831 ldl->barrier_class = IR3_BARRIER_SHARED_R;
832 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
833
834 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
835 }
836
837 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
838 static void
839 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
840 {
841 struct ir3_block *b = ctx->block;
842 struct ir3_instruction *stl, *offset;
843 struct ir3_instruction * const *value;
844 unsigned base, wrmask;
845
846 value = ir3_get_src(ctx, &intr->src[0]);
847 offset = ir3_get_src(ctx, &intr->src[1])[0];
848
849 base = nir_intrinsic_base(intr);
850 wrmask = nir_intrinsic_write_mask(intr);
851
852 /* Combine groups of consecutive enabled channels in one write
853 * message. We use ffs to find the first enabled channel and then ffs on
854 * the bit-inverse, down-shifted writemask to determine the length of
855 * the block of enabled bits.
856 *
857 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
858 */
859 while (wrmask) {
860 unsigned first_component = ffs(wrmask) - 1;
861 unsigned length = ffs(~(wrmask >> first_component)) - 1;
862
863 stl = ir3_STL(b, offset, 0,
864 ir3_create_collect(ctx, &value[first_component], length), 0,
865 create_immed(b, length), 0);
866 stl->cat6.dst_offset = first_component + base;
867 stl->cat6.type = utype_src(intr->src[0]);
868 stl->barrier_class = IR3_BARRIER_SHARED_W;
869 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
870
871 array_insert(b, b->keeps, stl);
872
873 /* Clear the bits in the writemask that we just wrote, then try
874 * again to see if more channels are left.
875 */
876 wrmask &= (15 << (first_component + length));
877 }
878 }
879
880 /* src[] = { offset }. const_index[] = { base } */
881 static void
882 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
883 struct ir3_instruction **dst)
884 {
885 struct ir3_block *b = ctx->block;
886 struct ir3_instruction *load, *offset;
887 unsigned base;
888
889 offset = ir3_get_src(ctx, &intr->src[0])[0];
890 base = nir_intrinsic_base(intr);
891
892 load = ir3_LDLW(b, offset, 0,
893 create_immed(b, intr->num_components), 0,
894 create_immed(b, base), 0);
895
896 load->cat6.type = utype_dst(intr->dest);
897 load->regs[0]->wrmask = MASK(intr->num_components);
898
899 load->barrier_class = IR3_BARRIER_SHARED_R;
900 load->barrier_conflict = IR3_BARRIER_SHARED_W;
901
902 ir3_split_dest(b, dst, load, 0, intr->num_components);
903 }
904
905 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
906 static void
907 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
908 {
909 struct ir3_block *b = ctx->block;
910 struct ir3_instruction *store, *offset;
911 struct ir3_instruction * const *value;
912 unsigned base, wrmask;
913
914 value = ir3_get_src(ctx, &intr->src[0]);
915 offset = ir3_get_src(ctx, &intr->src[1])[0];
916
917 base = nir_intrinsic_base(intr);
918 wrmask = nir_intrinsic_write_mask(intr);
919
920 /* Combine groups of consecutive enabled channels in one write
921 * message. We use ffs to find the first enabled channel and then ffs on
922 * the bit-inverse, down-shifted writemask to determine the length of
923 * the block of enabled bits.
924 *
925 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
926 */
927 while (wrmask) {
928 unsigned first_component = ffs(wrmask) - 1;
929 unsigned length = ffs(~(wrmask >> first_component)) - 1;
930
931 store = ir3_STLW(b, offset, 0,
932 ir3_create_collect(ctx, &value[first_component], length), 0,
933 create_immed(b, length), 0);
934
935 store->cat6.dst_offset = first_component + base;
936 store->cat6.type = utype_src(intr->src[0]);
937 store->barrier_class = IR3_BARRIER_SHARED_W;
938 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
939
940 array_insert(b, b->keeps, store);
941
942 /* Clear the bits in the writemask that we just wrote, then try
943 * again to see if more channels are left.
944 */
945 wrmask &= (15 << (first_component + length));
946 }
947 }
948
949 /*
950 * CS shared variable atomic intrinsics
951 *
952 * All of the shared variable atomic memory operations read a value from
953 * memory, compute a new value using one of the operations below, write the
954 * new value to memory, and return the original value read.
955 *
956 * All operations take 2 sources except CompSwap that takes 3. These
957 * sources represent:
958 *
959 * 0: The offset into the shared variable storage region that the atomic
960 * operation will operate on.
961 * 1: The data parameter to the atomic function (i.e. the value to add
962 * in shared_atomic_add, etc).
963 * 2: For CompSwap only: the second data parameter.
964 */
965 static struct ir3_instruction *
966 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
967 {
968 struct ir3_block *b = ctx->block;
969 struct ir3_instruction *atomic, *src0, *src1;
970 type_t type = TYPE_U32;
971
972 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
973 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
974
975 switch (intr->intrinsic) {
976 case nir_intrinsic_shared_atomic_add:
977 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
978 break;
979 case nir_intrinsic_shared_atomic_imin:
980 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
981 type = TYPE_S32;
982 break;
983 case nir_intrinsic_shared_atomic_umin:
984 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
985 break;
986 case nir_intrinsic_shared_atomic_imax:
987 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
988 type = TYPE_S32;
989 break;
990 case nir_intrinsic_shared_atomic_umax:
991 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
992 break;
993 case nir_intrinsic_shared_atomic_and:
994 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
995 break;
996 case nir_intrinsic_shared_atomic_or:
997 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
998 break;
999 case nir_intrinsic_shared_atomic_xor:
1000 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1001 break;
1002 case nir_intrinsic_shared_atomic_exchange:
1003 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1004 break;
1005 case nir_intrinsic_shared_atomic_comp_swap:
1006 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1007 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1008 ir3_get_src(ctx, &intr->src[2])[0],
1009 src1,
1010 }, 2);
1011 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1012 break;
1013 default:
1014 unreachable("boo");
1015 }
1016
1017 atomic->cat6.iim_val = 1;
1018 atomic->cat6.d = 1;
1019 atomic->cat6.type = type;
1020 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1021 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1022
1023 /* even if nothing consume the result, we can't DCE the instruction: */
1024 array_insert(b, b->keeps, atomic);
1025
1026 return atomic;
1027 }
1028
1029 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1030 * to handle with the image_mapping table..
1031 */
1032 static struct ir3_instruction *
1033 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1034 {
1035 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1036 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1037 struct ir3_instruction *texture, *sampler;
1038
1039 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1040 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1041
1042 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1043 sampler,
1044 texture,
1045 }, 2);
1046 }
1047
1048 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1049 static void
1050 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1051 struct ir3_instruction **dst)
1052 {
1053 struct ir3_block *b = ctx->block;
1054 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1055 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1056 struct ir3_instruction *sam;
1057 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1058 struct ir3_instruction *coords[4];
1059 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1060 type_t type = ir3_get_image_type(var);
1061
1062 /* hmm, this seems a bit odd, but it is what blob does and (at least
1063 * a5xx) just faults on bogus addresses otherwise:
1064 */
1065 if (flags & IR3_INSTR_3D) {
1066 flags &= ~IR3_INSTR_3D;
1067 flags |= IR3_INSTR_A;
1068 }
1069
1070 for (unsigned i = 0; i < ncoords; i++)
1071 coords[i] = src0[i];
1072
1073 if (ncoords == 1)
1074 coords[ncoords++] = create_immed(b, 0);
1075
1076 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1077 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1078
1079 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1080 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1081
1082 ir3_split_dest(b, dst, sam, 0, 4);
1083 }
1084
1085 static void
1086 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1087 struct ir3_instruction **dst)
1088 {
1089 struct ir3_block *b = ctx->block;
1090 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1091 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1092 struct ir3_instruction *sam, *lod;
1093 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1094 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1095 TYPE_U16 : TYPE_U32;
1096
1097 lod = create_immed(b, 0);
1098 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1099 samp_tex, lod, NULL);
1100
1101 /* Array size actually ends up in .w rather than .z. This doesn't
1102 * matter for miplevel 0, but for higher mips the value in z is
1103 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1104 * returned, which means that we have to add 1 to it for arrays for
1105 * a3xx.
1106 *
1107 * Note use a temporary dst and then copy, since the size of the dst
1108 * array that is passed in is based on nir's understanding of the
1109 * result size, not the hardware's
1110 */
1111 struct ir3_instruction *tmp[4];
1112
1113 ir3_split_dest(b, tmp, sam, 0, 4);
1114
1115 /* get_size instruction returns size in bytes instead of texels
1116 * for imageBuffer, so we need to divide it by the pixel size
1117 * of the image format.
1118 *
1119 * TODO: This is at least true on a5xx. Check other gens.
1120 */
1121 enum glsl_sampler_dim dim =
1122 glsl_get_sampler_dim(glsl_without_array(var->type));
1123 if (dim == GLSL_SAMPLER_DIM_BUF) {
1124 /* Since all the possible values the divisor can take are
1125 * power-of-two (4, 8, or 16), the division is implemented
1126 * as a shift-right.
1127 * During shader setup, the log2 of the image format's
1128 * bytes-per-pixel should have been emitted in 2nd slot of
1129 * image_dims. See ir3_shader::emit_image_dims().
1130 */
1131 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1132 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1133 const_state->image_dims.off[var->data.driver_location];
1134 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1135
1136 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1137 }
1138
1139 for (unsigned i = 0; i < ncoords; i++)
1140 dst[i] = tmp[i];
1141
1142 if (flags & IR3_INSTR_A) {
1143 if (ctx->compiler->levels_add_one) {
1144 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1145 } else {
1146 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1147 }
1148 }
1149 }
1150
1151 static void
1152 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1153 {
1154 struct ir3_block *b = ctx->block;
1155 struct ir3_instruction *barrier;
1156
1157 switch (intr->intrinsic) {
1158 case nir_intrinsic_control_barrier:
1159 barrier = ir3_BAR(b);
1160 barrier->cat7.g = true;
1161 barrier->cat7.l = true;
1162 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1163 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1164 break;
1165 case nir_intrinsic_memory_barrier:
1166 barrier = ir3_FENCE(b);
1167 barrier->cat7.g = true;
1168 barrier->cat7.r = true;
1169 barrier->cat7.w = true;
1170 barrier->cat7.l = true;
1171 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1172 IR3_BARRIER_BUFFER_W;
1173 barrier->barrier_conflict =
1174 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1175 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1176 break;
1177 case nir_intrinsic_memory_barrier_buffer:
1178 barrier = ir3_FENCE(b);
1179 barrier->cat7.g = true;
1180 barrier->cat7.r = true;
1181 barrier->cat7.w = true;
1182 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1183 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1184 IR3_BARRIER_BUFFER_W;
1185 break;
1186 case nir_intrinsic_memory_barrier_image:
1187 // TODO double check if this should have .g set
1188 barrier = ir3_FENCE(b);
1189 barrier->cat7.g = true;
1190 barrier->cat7.r = true;
1191 barrier->cat7.w = true;
1192 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1193 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1194 IR3_BARRIER_IMAGE_W;
1195 break;
1196 case nir_intrinsic_memory_barrier_shared:
1197 barrier = ir3_FENCE(b);
1198 barrier->cat7.g = true;
1199 barrier->cat7.l = true;
1200 barrier->cat7.r = true;
1201 barrier->cat7.w = true;
1202 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1203 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1204 IR3_BARRIER_SHARED_W;
1205 break;
1206 case nir_intrinsic_group_memory_barrier:
1207 barrier = ir3_FENCE(b);
1208 barrier->cat7.g = true;
1209 barrier->cat7.l = true;
1210 barrier->cat7.r = true;
1211 barrier->cat7.w = true;
1212 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1213 IR3_BARRIER_IMAGE_W |
1214 IR3_BARRIER_BUFFER_W;
1215 barrier->barrier_conflict =
1216 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1217 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1218 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1219 break;
1220 default:
1221 unreachable("boo");
1222 }
1223
1224 /* make sure barrier doesn't get DCE'd */
1225 array_insert(b, b->keeps, barrier);
1226 }
1227
1228 static void add_sysval_input_compmask(struct ir3_context *ctx,
1229 gl_system_value slot, unsigned compmask,
1230 struct ir3_instruction *instr)
1231 {
1232 struct ir3_shader_variant *so = ctx->so;
1233 unsigned n = so->inputs_count++;
1234
1235 assert(instr->opc == OPC_META_INPUT);
1236 instr->input.inidx = n;
1237 instr->input.sysval = slot;
1238
1239 so->inputs[n].sysval = true;
1240 so->inputs[n].slot = slot;
1241 so->inputs[n].compmask = compmask;
1242 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1243 so->total_in++;
1244 }
1245
1246 static struct ir3_instruction *
1247 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1248 unsigned compmask)
1249 {
1250 assert(compmask);
1251 struct ir3_instruction *sysval = create_input(ctx, compmask);
1252 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1253 return sysval;
1254 }
1255
1256 static struct ir3_instruction *
1257 get_barycentric_centroid(struct ir3_context *ctx)
1258 {
1259 if (!ctx->ij_centroid) {
1260 struct ir3_instruction *xy[2];
1261 struct ir3_instruction *ij;
1262
1263 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1264 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1265
1266 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1267 }
1268
1269 return ctx->ij_centroid;
1270 }
1271
1272 static struct ir3_instruction *
1273 get_barycentric_sample(struct ir3_context *ctx)
1274 {
1275 if (!ctx->ij_sample) {
1276 struct ir3_instruction *xy[2];
1277 struct ir3_instruction *ij;
1278
1279 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1280 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1281
1282 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1283 }
1284
1285 return ctx->ij_sample;
1286 }
1287
1288 static struct ir3_instruction *
1289 get_barycentric_pixel(struct ir3_context *ctx)
1290 {
1291 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1292 * this to create ij_pixel only on demand:
1293 */
1294 return ctx->ij_pixel;
1295 }
1296
1297 static struct ir3_instruction *
1298 get_frag_coord(struct ir3_context *ctx)
1299 {
1300 if (!ctx->frag_coord) {
1301 struct ir3_block *b = ctx->block;
1302 struct ir3_instruction *xyzw[4];
1303 struct ir3_instruction *hw_frag_coord;
1304
1305 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1306 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1307
1308 /* for frag_coord.xy, we get unsigned values.. we need
1309 * to subtract (integer) 8 and divide by 16 (right-
1310 * shift by 4) then convert to float:
1311 *
1312 * sub.s tmp, src, 8
1313 * shr.b tmp, tmp, 4
1314 * mov.u32f32 dst, tmp
1315 *
1316 */
1317 for (int i = 0; i < 2; i++) {
1318 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1319 create_immed(b, 8), 0);
1320 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1321 create_immed(b, 4), 0);
1322 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1323 }
1324
1325 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1326 ctx->so->frag_coord = true;
1327 }
1328
1329 return ctx->frag_coord;
1330 }
1331
1332 static void
1333 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1334 {
1335 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1336 struct ir3_instruction **dst;
1337 struct ir3_instruction * const *src;
1338 struct ir3_block *b = ctx->block;
1339 int idx, comp;
1340
1341 if (info->has_dest) {
1342 unsigned n = nir_intrinsic_dest_components(intr);
1343 dst = ir3_get_dst(ctx, &intr->dest, n);
1344 } else {
1345 dst = NULL;
1346 }
1347
1348 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1349 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1350
1351 switch (intr->intrinsic) {
1352 case nir_intrinsic_load_uniform:
1353 idx = nir_intrinsic_base(intr);
1354 if (nir_src_is_const(intr->src[0])) {
1355 idx += nir_src_as_uint(intr->src[0]);
1356 for (int i = 0; i < intr->num_components; i++) {
1357 dst[i] = create_uniform_typed(b, idx + i,
1358 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1359 }
1360 } else {
1361 src = ir3_get_src(ctx, &intr->src[0]);
1362 for (int i = 0; i < intr->num_components; i++) {
1363 dst[i] = create_uniform_indirect(b, idx + i,
1364 ir3_get_addr(ctx, src[0], 1));
1365 }
1366 /* NOTE: if relative addressing is used, we set
1367 * constlen in the compiler (to worst-case value)
1368 * since we don't know in the assembler what the max
1369 * addr reg value can be:
1370 */
1371 ctx->so->constlen = MAX2(ctx->so->constlen,
1372 ctx->so->shader->ubo_state.size / 16);
1373 }
1374 break;
1375
1376 case nir_intrinsic_load_vs_primitive_stride_ir3:
1377 dst[0] = create_uniform(b, primitive_param + 0);
1378 break;
1379 case nir_intrinsic_load_vs_vertex_stride_ir3:
1380 dst[0] = create_uniform(b, primitive_param + 1);
1381 break;
1382 case nir_intrinsic_load_hs_patch_stride_ir3:
1383 dst[0] = create_uniform(b, primitive_param + 2);
1384 break;
1385 case nir_intrinsic_load_patch_vertices_in:
1386 dst[0] = create_uniform(b, primitive_param + 3);
1387 break;
1388 case nir_intrinsic_load_tess_param_base_ir3:
1389 dst[0] = create_uniform(b, primitive_param + 4);
1390 dst[1] = create_uniform(b, primitive_param + 5);
1391 break;
1392 case nir_intrinsic_load_tess_factor_base_ir3:
1393 dst[0] = create_uniform(b, primitive_param + 6);
1394 dst[1] = create_uniform(b, primitive_param + 7);
1395 break;
1396
1397 case nir_intrinsic_load_primitive_location_ir3:
1398 idx = nir_intrinsic_driver_location(intr);
1399 dst[0] = create_uniform(b, primitive_map + idx);
1400 break;
1401
1402 case nir_intrinsic_load_gs_header_ir3:
1403 dst[0] = ctx->gs_header;
1404 break;
1405 case nir_intrinsic_load_tcs_header_ir3:
1406 dst[0] = ctx->tcs_header;
1407 break;
1408
1409 case nir_intrinsic_load_primitive_id:
1410 dst[0] = ctx->primitive_id;
1411 break;
1412
1413 case nir_intrinsic_load_tess_coord:
1414 if (!ctx->tess_coord) {
1415 ctx->tess_coord =
1416 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1417 }
1418 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1419
1420 /* Unused, but ir3_put_dst() below wants to free something */
1421 dst[2] = create_immed(b, 0);
1422 break;
1423
1424 case nir_intrinsic_end_patch_ir3:
1425 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1426 struct ir3_instruction *end = ir3_ENDIF(b);
1427 array_insert(b, b->keeps, end);
1428
1429 end->barrier_class = IR3_BARRIER_EVERYTHING;
1430 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1431 break;
1432
1433 case nir_intrinsic_store_global_ir3: {
1434 struct ir3_instruction *value, *addr, *offset;
1435
1436 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1437 ir3_get_src(ctx, &intr->src[1])[0],
1438 ir3_get_src(ctx, &intr->src[1])[1]
1439 }, 2);
1440
1441 offset = ir3_get_src(ctx, &intr->src[2])[0];
1442
1443 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1444 intr->num_components);
1445
1446 struct ir3_instruction *stg =
1447 ir3_STG_G(ctx->block, addr, 0, value, 0,
1448 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1449 stg->cat6.type = TYPE_U32;
1450 stg->cat6.iim_val = 1;
1451
1452 array_insert(b, b->keeps, stg);
1453
1454 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1455 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1456 break;
1457 }
1458
1459 case nir_intrinsic_load_global_ir3: {
1460 struct ir3_instruction *addr, *offset;
1461
1462 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1463 ir3_get_src(ctx, &intr->src[0])[0],
1464 ir3_get_src(ctx, &intr->src[0])[1]
1465 }, 2);
1466
1467 offset = ir3_get_src(ctx, &intr->src[1])[0];
1468
1469 struct ir3_instruction *load =
1470 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1471 0, offset, 0);
1472 load->cat6.type = TYPE_U32;
1473 load->regs[0]->wrmask = MASK(intr->num_components);
1474
1475 load->barrier_class = IR3_BARRIER_BUFFER_R;
1476 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1477
1478 ir3_split_dest(b, dst, load, 0, intr->num_components);
1479 break;
1480 }
1481
1482 case nir_intrinsic_load_ubo:
1483 emit_intrinsic_load_ubo(ctx, intr, dst);
1484 break;
1485 case nir_intrinsic_load_frag_coord:
1486 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1487 break;
1488 case nir_intrinsic_load_sample_pos_from_id: {
1489 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1490 * but that doesn't seem necessary.
1491 */
1492 struct ir3_instruction *offset =
1493 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1494 offset->regs[0]->wrmask = 0x3;
1495 offset->cat5.type = TYPE_F32;
1496
1497 ir3_split_dest(b, dst, offset, 0, 2);
1498
1499 break;
1500 }
1501 case nir_intrinsic_load_size_ir3:
1502 if (!ctx->ij_size) {
1503 ctx->ij_size =
1504 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1505 }
1506 dst[0] = ctx->ij_size;
1507 break;
1508 case nir_intrinsic_load_barycentric_centroid:
1509 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1510 break;
1511 case nir_intrinsic_load_barycentric_sample:
1512 if (ctx->so->key.msaa) {
1513 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1514 } else {
1515 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1516 }
1517 break;
1518 case nir_intrinsic_load_barycentric_pixel:
1519 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1520 break;
1521 case nir_intrinsic_load_interpolated_input:
1522 idx = nir_intrinsic_base(intr);
1523 comp = nir_intrinsic_component(intr);
1524 src = ir3_get_src(ctx, &intr->src[0]);
1525 if (nir_src_is_const(intr->src[1])) {
1526 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1527 idx += nir_src_as_uint(intr->src[1]);
1528 for (int i = 0; i < intr->num_components; i++) {
1529 unsigned inloc = idx * 4 + i + comp;
1530 if (ctx->so->inputs[idx].bary &&
1531 !ctx->so->inputs[idx].use_ldlv) {
1532 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1533 } else {
1534 /* for non-varyings use the pre-setup input, since
1535 * that is easier than mapping things back to a
1536 * nir_variable to figure out what it is.
1537 */
1538 dst[i] = ctx->inputs[inloc];
1539 }
1540 }
1541 } else {
1542 ir3_context_error(ctx, "unhandled");
1543 }
1544 break;
1545 case nir_intrinsic_load_input:
1546 idx = nir_intrinsic_base(intr);
1547 comp = nir_intrinsic_component(intr);
1548 if (nir_src_is_const(intr->src[0])) {
1549 idx += nir_src_as_uint(intr->src[0]);
1550 for (int i = 0; i < intr->num_components; i++) {
1551 unsigned n = idx * 4 + i + comp;
1552 dst[i] = ctx->inputs[n];
1553 compile_assert(ctx, ctx->inputs[n]);
1554 }
1555 } else {
1556 src = ir3_get_src(ctx, &intr->src[0]);
1557 struct ir3_instruction *collect =
1558 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1559 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1560 for (int i = 0; i < intr->num_components; i++) {
1561 unsigned n = idx * 4 + i + comp;
1562 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1563 n, addr, collect);
1564 }
1565 }
1566 break;
1567 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1568 * pass and replaced by an ir3-specifc version that adds the
1569 * dword-offset in the last source.
1570 */
1571 case nir_intrinsic_load_ssbo_ir3:
1572 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1573 break;
1574 case nir_intrinsic_store_ssbo_ir3:
1575 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1576 !ctx->s->info.fs.early_fragment_tests)
1577 ctx->so->no_earlyz = true;
1578 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1579 break;
1580 case nir_intrinsic_get_buffer_size:
1581 emit_intrinsic_ssbo_size(ctx, intr, dst);
1582 break;
1583 case nir_intrinsic_ssbo_atomic_add_ir3:
1584 case nir_intrinsic_ssbo_atomic_imin_ir3:
1585 case nir_intrinsic_ssbo_atomic_umin_ir3:
1586 case nir_intrinsic_ssbo_atomic_imax_ir3:
1587 case nir_intrinsic_ssbo_atomic_umax_ir3:
1588 case nir_intrinsic_ssbo_atomic_and_ir3:
1589 case nir_intrinsic_ssbo_atomic_or_ir3:
1590 case nir_intrinsic_ssbo_atomic_xor_ir3:
1591 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1592 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1593 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1594 !ctx->s->info.fs.early_fragment_tests)
1595 ctx->so->no_earlyz = true;
1596 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1597 break;
1598 case nir_intrinsic_load_shared:
1599 emit_intrinsic_load_shared(ctx, intr, dst);
1600 break;
1601 case nir_intrinsic_store_shared:
1602 emit_intrinsic_store_shared(ctx, intr);
1603 break;
1604 case nir_intrinsic_shared_atomic_add:
1605 case nir_intrinsic_shared_atomic_imin:
1606 case nir_intrinsic_shared_atomic_umin:
1607 case nir_intrinsic_shared_atomic_imax:
1608 case nir_intrinsic_shared_atomic_umax:
1609 case nir_intrinsic_shared_atomic_and:
1610 case nir_intrinsic_shared_atomic_or:
1611 case nir_intrinsic_shared_atomic_xor:
1612 case nir_intrinsic_shared_atomic_exchange:
1613 case nir_intrinsic_shared_atomic_comp_swap:
1614 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1615 break;
1616 case nir_intrinsic_image_deref_load:
1617 emit_intrinsic_load_image(ctx, intr, dst);
1618 break;
1619 case nir_intrinsic_image_deref_store:
1620 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1621 !ctx->s->info.fs.early_fragment_tests)
1622 ctx->so->no_earlyz = true;
1623 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1624 break;
1625 case nir_intrinsic_image_deref_size:
1626 emit_intrinsic_image_size(ctx, intr, dst);
1627 break;
1628 case nir_intrinsic_image_deref_atomic_add:
1629 case nir_intrinsic_image_deref_atomic_imin:
1630 case nir_intrinsic_image_deref_atomic_umin:
1631 case nir_intrinsic_image_deref_atomic_imax:
1632 case nir_intrinsic_image_deref_atomic_umax:
1633 case nir_intrinsic_image_deref_atomic_and:
1634 case nir_intrinsic_image_deref_atomic_or:
1635 case nir_intrinsic_image_deref_atomic_xor:
1636 case nir_intrinsic_image_deref_atomic_exchange:
1637 case nir_intrinsic_image_deref_atomic_comp_swap:
1638 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1639 !ctx->s->info.fs.early_fragment_tests)
1640 ctx->so->no_earlyz = true;
1641 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1642 break;
1643 case nir_intrinsic_control_barrier:
1644 case nir_intrinsic_memory_barrier:
1645 case nir_intrinsic_group_memory_barrier:
1646 case nir_intrinsic_memory_barrier_buffer:
1647 case nir_intrinsic_memory_barrier_image:
1648 case nir_intrinsic_memory_barrier_shared:
1649 emit_intrinsic_barrier(ctx, intr);
1650 /* note that blk ptr no longer valid, make that obvious: */
1651 b = NULL;
1652 break;
1653 case nir_intrinsic_store_output:
1654 idx = nir_intrinsic_base(intr);
1655 comp = nir_intrinsic_component(intr);
1656 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1657 idx += nir_src_as_uint(intr->src[1]);
1658
1659 src = ir3_get_src(ctx, &intr->src[0]);
1660 for (int i = 0; i < intr->num_components; i++) {
1661 unsigned n = idx * 4 + i + comp;
1662 ctx->outputs[n] = src[i];
1663 }
1664 break;
1665 case nir_intrinsic_load_base_vertex:
1666 case nir_intrinsic_load_first_vertex:
1667 if (!ctx->basevertex) {
1668 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1669 }
1670 dst[0] = ctx->basevertex;
1671 break;
1672 case nir_intrinsic_load_base_instance:
1673 if (!ctx->base_instance) {
1674 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1675 }
1676 dst[0] = ctx->base_instance;
1677 break;
1678 case nir_intrinsic_load_vertex_id_zero_base:
1679 case nir_intrinsic_load_vertex_id:
1680 if (!ctx->vertex_id) {
1681 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1682 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1683 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1684 }
1685 dst[0] = ctx->vertex_id;
1686 break;
1687 case nir_intrinsic_load_instance_id:
1688 if (!ctx->instance_id) {
1689 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1690 }
1691 dst[0] = ctx->instance_id;
1692 break;
1693 case nir_intrinsic_load_sample_id:
1694 ctx->so->per_samp = true;
1695 /* fall-thru */
1696 case nir_intrinsic_load_sample_id_no_per_sample:
1697 if (!ctx->samp_id) {
1698 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1699 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1700 }
1701 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1702 break;
1703 case nir_intrinsic_load_sample_mask_in:
1704 if (!ctx->samp_mask_in) {
1705 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1706 }
1707 dst[0] = ctx->samp_mask_in;
1708 break;
1709 case nir_intrinsic_load_user_clip_plane:
1710 idx = nir_intrinsic_ucp_id(intr);
1711 for (int i = 0; i < intr->num_components; i++) {
1712 unsigned n = idx * 4 + i;
1713 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1714 }
1715 break;
1716 case nir_intrinsic_load_front_face:
1717 if (!ctx->frag_face) {
1718 ctx->so->frag_face = true;
1719 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1720 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1721 }
1722 /* for fragface, we get -1 for back and 0 for front. However this is
1723 * the inverse of what nir expects (where ~0 is true).
1724 */
1725 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1726 dst[0] = ir3_NOT_B(b, dst[0], 0);
1727 break;
1728 case nir_intrinsic_load_local_invocation_id:
1729 if (!ctx->local_invocation_id) {
1730 ctx->local_invocation_id =
1731 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1732 }
1733 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1734 break;
1735 case nir_intrinsic_load_work_group_id:
1736 if (!ctx->work_group_id) {
1737 ctx->work_group_id =
1738 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1739 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1740 }
1741 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1742 break;
1743 case nir_intrinsic_load_num_work_groups:
1744 for (int i = 0; i < intr->num_components; i++) {
1745 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1746 }
1747 break;
1748 case nir_intrinsic_load_local_group_size:
1749 for (int i = 0; i < intr->num_components; i++) {
1750 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1751 }
1752 break;
1753 case nir_intrinsic_discard_if:
1754 case nir_intrinsic_discard: {
1755 struct ir3_instruction *cond, *kill;
1756
1757 if (intr->intrinsic == nir_intrinsic_discard_if) {
1758 /* conditional discard: */
1759 src = ir3_get_src(ctx, &intr->src[0]);
1760 cond = ir3_b2n(b, src[0]);
1761 } else {
1762 /* unconditional discard: */
1763 cond = create_immed(b, 1);
1764 }
1765
1766 /* NOTE: only cmps.*.* can write p0.x: */
1767 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1768 cond->cat2.condition = IR3_COND_NE;
1769
1770 /* condition always goes in predicate register: */
1771 cond->regs[0]->num = regid(REG_P0, 0);
1772 cond->regs[0]->flags &= ~IR3_REG_SSA;
1773
1774 kill = ir3_KILL(b, cond, 0);
1775 array_insert(ctx->ir, ctx->ir->predicates, kill);
1776
1777 array_insert(b, b->keeps, kill);
1778 ctx->so->no_earlyz = true;
1779
1780 break;
1781 }
1782
1783 case nir_intrinsic_cond_end_ir3: {
1784 struct ir3_instruction *cond, *kill;
1785
1786 src = ir3_get_src(ctx, &intr->src[0]);
1787 cond = ir3_b2n(b, src[0]);
1788
1789 /* NOTE: only cmps.*.* can write p0.x: */
1790 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1791 cond->cat2.condition = IR3_COND_NE;
1792
1793 /* condition always goes in predicate register: */
1794 cond->regs[0]->num = regid(REG_P0, 0);
1795
1796 kill = ir3_IF(b, cond, 0);
1797
1798 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1799 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1800
1801 array_insert(ctx->ir, ctx->ir->predicates, kill);
1802 array_insert(b, b->keeps, kill);
1803 break;
1804 }
1805
1806 case nir_intrinsic_load_shared_ir3:
1807 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1808 break;
1809 case nir_intrinsic_store_shared_ir3:
1810 emit_intrinsic_store_shared_ir3(ctx, intr);
1811 break;
1812 default:
1813 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1814 nir_intrinsic_infos[intr->intrinsic].name);
1815 break;
1816 }
1817
1818 if (info->has_dest)
1819 ir3_put_dst(ctx, &intr->dest);
1820 }
1821
1822 static void
1823 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1824 {
1825 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1826 instr->def.num_components);
1827
1828 if (instr->def.bit_size < 32) {
1829 for (int i = 0; i < instr->def.num_components; i++)
1830 dst[i] = create_immed_typed(ctx->block,
1831 instr->value[i].u16,
1832 TYPE_U16);
1833 } else {
1834 for (int i = 0; i < instr->def.num_components; i++)
1835 dst[i] = create_immed_typed(ctx->block,
1836 instr->value[i].u32,
1837 TYPE_U32);
1838 }
1839
1840 }
1841
1842 static void
1843 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1844 {
1845 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1846 undef->def.num_components);
1847 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1848
1849 /* backend doesn't want undefined instructions, so just plug
1850 * in 0.0..
1851 */
1852 for (int i = 0; i < undef->def.num_components; i++)
1853 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1854 }
1855
1856 /*
1857 * texture fetch/sample instructions:
1858 */
1859
1860 static type_t
1861 get_tex_dest_type(nir_tex_instr *tex)
1862 {
1863 type_t type;
1864
1865 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1866 case nir_type_invalid:
1867 case nir_type_float:
1868 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1869 break;
1870 case nir_type_int:
1871 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1872 break;
1873 case nir_type_uint:
1874 case nir_type_bool:
1875 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1876 break;
1877 default:
1878 unreachable("bad dest_type");
1879 }
1880
1881 return type;
1882 }
1883
1884 static void
1885 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1886 {
1887 unsigned coords, flags = 0;
1888
1889 /* note: would use tex->coord_components.. except txs.. also,
1890 * since array index goes after shadow ref, we don't want to
1891 * count it:
1892 */
1893 switch (tex->sampler_dim) {
1894 case GLSL_SAMPLER_DIM_1D:
1895 case GLSL_SAMPLER_DIM_BUF:
1896 coords = 1;
1897 break;
1898 case GLSL_SAMPLER_DIM_2D:
1899 case GLSL_SAMPLER_DIM_RECT:
1900 case GLSL_SAMPLER_DIM_EXTERNAL:
1901 case GLSL_SAMPLER_DIM_MS:
1902 case GLSL_SAMPLER_DIM_SUBPASS:
1903 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1904 coords = 2;
1905 break;
1906 case GLSL_SAMPLER_DIM_3D:
1907 case GLSL_SAMPLER_DIM_CUBE:
1908 coords = 3;
1909 flags |= IR3_INSTR_3D;
1910 break;
1911 default:
1912 unreachable("bad sampler_dim");
1913 }
1914
1915 if (tex->is_shadow && tex->op != nir_texop_lod)
1916 flags |= IR3_INSTR_S;
1917
1918 if (tex->is_array && tex->op != nir_texop_lod)
1919 flags |= IR3_INSTR_A;
1920
1921 *flagsp = flags;
1922 *coordsp = coords;
1923 }
1924
1925 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1926 * or immediate (in which case it will get lowered later to a non .s2en
1927 * version of the tex instruction which encode tex/samp as immediates:
1928 */
1929 static struct ir3_instruction *
1930 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1931 {
1932 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1933 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1934 struct ir3_instruction *texture, *sampler;
1935
1936 if (texture_idx >= 0) {
1937 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1938 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1939 } else {
1940 /* TODO what to do for dynamic case? I guess we only need the
1941 * max index for astc srgb workaround so maybe not a problem
1942 * to worry about if we don't enable indirect samplers for
1943 * a4xx?
1944 */
1945 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1946 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1947 }
1948
1949 if (sampler_idx >= 0) {
1950 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1951 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1952 } else {
1953 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1954 }
1955
1956 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1957 sampler,
1958 texture,
1959 }, 2);
1960 }
1961
1962 static void
1963 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1964 {
1965 struct ir3_block *b = ctx->block;
1966 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1967 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1968 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1969 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1970 unsigned i, coords, flags, ncomp;
1971 unsigned nsrc0 = 0, nsrc1 = 0;
1972 type_t type;
1973 opc_t opc = 0;
1974
1975 ncomp = nir_dest_num_components(tex->dest);
1976
1977 coord = off = ddx = ddy = NULL;
1978 lod = proj = compare = sample_index = NULL;
1979
1980 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1981
1982 for (unsigned i = 0; i < tex->num_srcs; i++) {
1983 switch (tex->src[i].src_type) {
1984 case nir_tex_src_coord:
1985 coord = ir3_get_src(ctx, &tex->src[i].src);
1986 break;
1987 case nir_tex_src_bias:
1988 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1989 has_bias = true;
1990 break;
1991 case nir_tex_src_lod:
1992 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1993 has_lod = true;
1994 break;
1995 case nir_tex_src_comparator: /* shadow comparator */
1996 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1997 break;
1998 case nir_tex_src_projector:
1999 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2000 has_proj = true;
2001 break;
2002 case nir_tex_src_offset:
2003 off = ir3_get_src(ctx, &tex->src[i].src);
2004 has_off = true;
2005 break;
2006 case nir_tex_src_ddx:
2007 ddx = ir3_get_src(ctx, &tex->src[i].src);
2008 break;
2009 case nir_tex_src_ddy:
2010 ddy = ir3_get_src(ctx, &tex->src[i].src);
2011 break;
2012 case nir_tex_src_ms_index:
2013 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2014 break;
2015 case nir_tex_src_texture_offset:
2016 case nir_tex_src_sampler_offset:
2017 /* handled in get_tex_samp_src() */
2018 break;
2019 default:
2020 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2021 tex->src[i].src_type);
2022 return;
2023 }
2024 }
2025
2026 switch (tex->op) {
2027 case nir_texop_tex_prefetch:
2028 compile_assert(ctx, !has_bias);
2029 compile_assert(ctx, !has_lod);
2030 compile_assert(ctx, !compare);
2031 compile_assert(ctx, !has_proj);
2032 compile_assert(ctx, !has_off);
2033 compile_assert(ctx, !ddx);
2034 compile_assert(ctx, !ddy);
2035 compile_assert(ctx, !sample_index);
2036 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2037 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2038
2039 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2040 opc = OPC_META_TEX_PREFETCH;
2041 ctx->so->num_sampler_prefetch++;
2042 break;
2043 }
2044 /* fallthru */
2045 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2046 case nir_texop_txb: opc = OPC_SAMB; break;
2047 case nir_texop_txl: opc = OPC_SAML; break;
2048 case nir_texop_txd: opc = OPC_SAMGQ; break;
2049 case nir_texop_txf: opc = OPC_ISAML; break;
2050 case nir_texop_lod: opc = OPC_GETLOD; break;
2051 case nir_texop_tg4:
2052 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2053 * what blob does, seems gather is broken?), and a3xx did
2054 * not support it (but probably could also emulate).
2055 */
2056 switch (tex->component) {
2057 case 0: opc = OPC_GATHER4R; break;
2058 case 1: opc = OPC_GATHER4G; break;
2059 case 2: opc = OPC_GATHER4B; break;
2060 case 3: opc = OPC_GATHER4A; break;
2061 }
2062 break;
2063 case nir_texop_txf_ms_fb:
2064 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2065 default:
2066 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2067 return;
2068 }
2069
2070 tex_info(tex, &flags, &coords);
2071
2072 /*
2073 * lay out the first argument in the proper order:
2074 * - actual coordinates first
2075 * - shadow reference
2076 * - array index
2077 * - projection w
2078 * - starting at offset 4, dpdx.xy, dpdy.xy
2079 *
2080 * bias/lod go into the second arg
2081 */
2082
2083 /* insert tex coords: */
2084 for (i = 0; i < coords; i++)
2085 src0[i] = coord[i];
2086
2087 nsrc0 = i;
2088
2089 /* scale up integer coords for TXF based on the LOD */
2090 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2091 assert(has_lod);
2092 for (i = 0; i < coords; i++)
2093 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2094 }
2095
2096 if (coords == 1) {
2097 /* hw doesn't do 1d, so we treat it as 2d with
2098 * height of 1, and patch up the y coord.
2099 */
2100 if (is_isam(opc)) {
2101 src0[nsrc0++] = create_immed(b, 0);
2102 } else {
2103 src0[nsrc0++] = create_immed(b, fui(0.5));
2104 }
2105 }
2106
2107 if (tex->is_shadow && tex->op != nir_texop_lod)
2108 src0[nsrc0++] = compare;
2109
2110 if (tex->is_array && tex->op != nir_texop_lod) {
2111 struct ir3_instruction *idx = coord[coords];
2112
2113 /* the array coord for cube arrays needs 0.5 added to it */
2114 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2115 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2116
2117 src0[nsrc0++] = idx;
2118 }
2119
2120 if (has_proj) {
2121 src0[nsrc0++] = proj;
2122 flags |= IR3_INSTR_P;
2123 }
2124
2125 /* pad to 4, then ddx/ddy: */
2126 if (tex->op == nir_texop_txd) {
2127 while (nsrc0 < 4)
2128 src0[nsrc0++] = create_immed(b, fui(0.0));
2129 for (i = 0; i < coords; i++)
2130 src0[nsrc0++] = ddx[i];
2131 if (coords < 2)
2132 src0[nsrc0++] = create_immed(b, fui(0.0));
2133 for (i = 0; i < coords; i++)
2134 src0[nsrc0++] = ddy[i];
2135 if (coords < 2)
2136 src0[nsrc0++] = create_immed(b, fui(0.0));
2137 }
2138
2139 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2140 * with scaled x coord according to requested sample:
2141 */
2142 if (opc == OPC_ISAMM) {
2143 if (ctx->compiler->txf_ms_with_isaml) {
2144 /* the samples are laid out in x dimension as
2145 * 0 1 2 3
2146 * x_ms = (x << ms) + sample_index;
2147 */
2148 struct ir3_instruction *ms;
2149 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2150
2151 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2152 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2153
2154 opc = OPC_ISAML;
2155 } else {
2156 src0[nsrc0++] = sample_index;
2157 }
2158 }
2159
2160 /*
2161 * second argument (if applicable):
2162 * - offsets
2163 * - lod
2164 * - bias
2165 */
2166 if (has_off | has_lod | has_bias) {
2167 if (has_off) {
2168 unsigned off_coords = coords;
2169 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2170 off_coords--;
2171 for (i = 0; i < off_coords; i++)
2172 src1[nsrc1++] = off[i];
2173 if (off_coords < 2)
2174 src1[nsrc1++] = create_immed(b, fui(0.0));
2175 flags |= IR3_INSTR_O;
2176 }
2177
2178 if (has_lod | has_bias)
2179 src1[nsrc1++] = lod;
2180 }
2181
2182 type = get_tex_dest_type(tex);
2183
2184 if (opc == OPC_GETLOD)
2185 type = TYPE_S32;
2186
2187 struct ir3_instruction *samp_tex;
2188
2189 if (tex->op == nir_texop_txf_ms_fb) {
2190 /* only expect a single txf_ms_fb per shader: */
2191 compile_assert(ctx, !ctx->so->fb_read);
2192 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2193
2194 ctx->so->fb_read = true;
2195 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2196 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2197 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2198 }, 2);
2199
2200 ctx->so->num_samp++;
2201 } else {
2202 samp_tex = get_tex_samp_tex_src(ctx, tex);
2203 }
2204
2205 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2206 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2207
2208 if (opc == OPC_META_TEX_PREFETCH) {
2209 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2210
2211 compile_assert(ctx, tex->src[idx].src.is_ssa);
2212
2213 sam = ir3_META_TEX_PREFETCH(b);
2214 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2215 sam->prefetch.input_offset =
2216 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2217 sam->prefetch.tex = tex->texture_index;
2218 sam->prefetch.samp = tex->sampler_index;
2219 } else {
2220 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2221 samp_tex, col0, col1);
2222 }
2223
2224 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2225 assert(opc != OPC_META_TEX_PREFETCH);
2226
2227 /* only need first 3 components: */
2228 sam->regs[0]->wrmask = 0x7;
2229 ir3_split_dest(b, dst, sam, 0, 3);
2230
2231 /* we need to sample the alpha separately with a non-ASTC
2232 * texture state:
2233 */
2234 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2235 samp_tex, col0, col1);
2236
2237 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2238
2239 /* fixup .w component: */
2240 ir3_split_dest(b, &dst[3], sam, 3, 1);
2241 } else {
2242 /* normal (non-workaround) case: */
2243 ir3_split_dest(b, dst, sam, 0, ncomp);
2244 }
2245
2246 /* GETLOD returns results in 4.8 fixed point */
2247 if (opc == OPC_GETLOD) {
2248 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2249
2250 compile_assert(ctx, tex->dest_type == nir_type_float);
2251 for (i = 0; i < 2; i++) {
2252 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2253 factor, 0);
2254 }
2255 }
2256
2257 ir3_put_dst(ctx, &tex->dest);
2258 }
2259
2260 static void
2261 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2262 {
2263 struct ir3_block *b = ctx->block;
2264 struct ir3_instruction **dst, *sam;
2265 type_t dst_type = get_tex_dest_type(tex);
2266
2267 dst = ir3_get_dst(ctx, &tex->dest, 1);
2268
2269 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2270 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2271
2272 /* even though there is only one component, since it ends
2273 * up in .y/.z/.w rather than .x, we need a split_dest()
2274 */
2275 if (idx)
2276 ir3_split_dest(b, dst, sam, 0, idx + 1);
2277
2278 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2279 * the value in TEX_CONST_0 is zero-based.
2280 */
2281 if (ctx->compiler->levels_add_one)
2282 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2283
2284 ir3_put_dst(ctx, &tex->dest);
2285 }
2286
2287 static void
2288 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2289 {
2290 struct ir3_block *b = ctx->block;
2291 struct ir3_instruction **dst, *sam;
2292 struct ir3_instruction *lod;
2293 unsigned flags, coords;
2294 type_t dst_type = get_tex_dest_type(tex);
2295
2296 tex_info(tex, &flags, &coords);
2297
2298 /* Actually we want the number of dimensions, not coordinates. This
2299 * distinction only matters for cubes.
2300 */
2301 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2302 coords = 2;
2303
2304 dst = ir3_get_dst(ctx, &tex->dest, 4);
2305
2306 compile_assert(ctx, tex->num_srcs == 1);
2307 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2308
2309 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2310
2311 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2312 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2313
2314 ir3_split_dest(b, dst, sam, 0, 4);
2315
2316 /* Array size actually ends up in .w rather than .z. This doesn't
2317 * matter for miplevel 0, but for higher mips the value in z is
2318 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2319 * returned, which means that we have to add 1 to it for arrays.
2320 */
2321 if (tex->is_array) {
2322 if (ctx->compiler->levels_add_one) {
2323 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2324 } else {
2325 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2326 }
2327 }
2328
2329 ir3_put_dst(ctx, &tex->dest);
2330 }
2331
2332 static void
2333 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2334 {
2335 switch (jump->type) {
2336 case nir_jump_break:
2337 case nir_jump_continue:
2338 case nir_jump_return:
2339 /* I *think* we can simply just ignore this, and use the
2340 * successor block link to figure out where we need to
2341 * jump to for break/continue
2342 */
2343 break;
2344 default:
2345 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2346 break;
2347 }
2348 }
2349
2350 static void
2351 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2352 {
2353 switch (instr->type) {
2354 case nir_instr_type_alu:
2355 emit_alu(ctx, nir_instr_as_alu(instr));
2356 break;
2357 case nir_instr_type_deref:
2358 /* ignored, handled as part of the intrinsic they are src to */
2359 break;
2360 case nir_instr_type_intrinsic:
2361 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2362 break;
2363 case nir_instr_type_load_const:
2364 emit_load_const(ctx, nir_instr_as_load_const(instr));
2365 break;
2366 case nir_instr_type_ssa_undef:
2367 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2368 break;
2369 case nir_instr_type_tex: {
2370 nir_tex_instr *tex = nir_instr_as_tex(instr);
2371 /* couple tex instructions get special-cased:
2372 */
2373 switch (tex->op) {
2374 case nir_texop_txs:
2375 emit_tex_txs(ctx, tex);
2376 break;
2377 case nir_texop_query_levels:
2378 emit_tex_info(ctx, tex, 2);
2379 break;
2380 case nir_texop_texture_samples:
2381 emit_tex_info(ctx, tex, 3);
2382 break;
2383 default:
2384 emit_tex(ctx, tex);
2385 break;
2386 }
2387 break;
2388 }
2389 case nir_instr_type_jump:
2390 emit_jump(ctx, nir_instr_as_jump(instr));
2391 break;
2392 case nir_instr_type_phi:
2393 /* we have converted phi webs to regs in NIR by now */
2394 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2395 break;
2396 case nir_instr_type_call:
2397 case nir_instr_type_parallel_copy:
2398 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2399 break;
2400 }
2401 }
2402
2403 static struct ir3_block *
2404 get_block(struct ir3_context *ctx, const nir_block *nblock)
2405 {
2406 struct ir3_block *block;
2407 struct hash_entry *hentry;
2408
2409 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2410 if (hentry)
2411 return hentry->data;
2412
2413 block = ir3_block_create(ctx->ir);
2414 block->nblock = nblock;
2415 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2416
2417 block->predecessors = _mesa_pointer_set_create(block);
2418 set_foreach(nblock->predecessors, sentry) {
2419 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2420 }
2421
2422 return block;
2423 }
2424
2425 static void
2426 emit_block(struct ir3_context *ctx, nir_block *nblock)
2427 {
2428 struct ir3_block *block = get_block(ctx, nblock);
2429
2430 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2431 if (nblock->successors[i]) {
2432 block->successors[i] =
2433 get_block(ctx, nblock->successors[i]);
2434 }
2435 }
2436
2437 ctx->block = block;
2438 list_addtail(&block->node, &ctx->ir->block_list);
2439
2440 /* re-emit addr register in each block if needed: */
2441 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2442 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2443 ctx->addr_ht[i] = NULL;
2444 }
2445
2446 nir_foreach_instr(instr, nblock) {
2447 ctx->cur_instr = instr;
2448 emit_instr(ctx, instr);
2449 ctx->cur_instr = NULL;
2450 if (ctx->error)
2451 return;
2452 }
2453 }
2454
2455 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2456
2457 static void
2458 emit_if(struct ir3_context *ctx, nir_if *nif)
2459 {
2460 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2461
2462 ctx->block->condition =
2463 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2464
2465 emit_cf_list(ctx, &nif->then_list);
2466 emit_cf_list(ctx, &nif->else_list);
2467 }
2468
2469 static void
2470 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2471 {
2472 emit_cf_list(ctx, &nloop->body);
2473 ctx->so->loops++;
2474 }
2475
2476 static void
2477 stack_push(struct ir3_context *ctx)
2478 {
2479 ctx->stack++;
2480 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2481 }
2482
2483 static void
2484 stack_pop(struct ir3_context *ctx)
2485 {
2486 compile_assert(ctx, ctx->stack > 0);
2487 ctx->stack--;
2488 }
2489
2490 static void
2491 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2492 {
2493 foreach_list_typed(nir_cf_node, node, node, list) {
2494 switch (node->type) {
2495 case nir_cf_node_block:
2496 emit_block(ctx, nir_cf_node_as_block(node));
2497 break;
2498 case nir_cf_node_if:
2499 stack_push(ctx);
2500 emit_if(ctx, nir_cf_node_as_if(node));
2501 stack_pop(ctx);
2502 break;
2503 case nir_cf_node_loop:
2504 stack_push(ctx);
2505 emit_loop(ctx, nir_cf_node_as_loop(node));
2506 stack_pop(ctx);
2507 break;
2508 case nir_cf_node_function:
2509 ir3_context_error(ctx, "TODO\n");
2510 break;
2511 }
2512 }
2513 }
2514
2515 /* emit stream-out code. At this point, the current block is the original
2516 * (nir) end block, and nir ensures that all flow control paths terminate
2517 * into the end block. We re-purpose the original end block to generate
2518 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2519 * block holding stream-out write instructions, followed by the new end
2520 * block:
2521 *
2522 * blockOrigEnd {
2523 * p0.x = (vtxcnt < maxvtxcnt)
2524 * // succs: blockStreamOut, blockNewEnd
2525 * }
2526 * blockStreamOut {
2527 * ... stream-out instructions ...
2528 * // succs: blockNewEnd
2529 * }
2530 * blockNewEnd {
2531 * }
2532 */
2533 static void
2534 emit_stream_out(struct ir3_context *ctx)
2535 {
2536 struct ir3 *ir = ctx->ir;
2537 struct ir3_stream_output_info *strmout =
2538 &ctx->so->shader->stream_output;
2539 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2540 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2541 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2542
2543 /* create vtxcnt input in input block at top of shader,
2544 * so that it is seen as live over the entire duration
2545 * of the shader:
2546 */
2547 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2548 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2549
2550 /* at this point, we are at the original 'end' block,
2551 * re-purpose this block to stream-out condition, then
2552 * append stream-out block and new-end block
2553 */
2554 orig_end_block = ctx->block;
2555
2556 // TODO these blocks need to update predecessors..
2557 // maybe w/ store_global intrinsic, we could do this
2558 // stuff in nir->nir pass
2559
2560 stream_out_block = ir3_block_create(ir);
2561 list_addtail(&stream_out_block->node, &ir->block_list);
2562
2563 new_end_block = ir3_block_create(ir);
2564 list_addtail(&new_end_block->node, &ir->block_list);
2565
2566 orig_end_block->successors[0] = stream_out_block;
2567 orig_end_block->successors[1] = new_end_block;
2568 stream_out_block->successors[0] = new_end_block;
2569
2570 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2571 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2572 cond->regs[0]->num = regid(REG_P0, 0);
2573 cond->regs[0]->flags &= ~IR3_REG_SSA;
2574 cond->cat2.condition = IR3_COND_LT;
2575
2576 /* condition goes on previous block to the conditional,
2577 * since it is used to pick which of the two successor
2578 * paths to take:
2579 */
2580 orig_end_block->condition = cond;
2581
2582 /* switch to stream_out_block to generate the stream-out
2583 * instructions:
2584 */
2585 ctx->block = stream_out_block;
2586
2587 /* Calculate base addresses based on vtxcnt. Instructions
2588 * generated for bases not used in following loop will be
2589 * stripped out in the backend.
2590 */
2591 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2592 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2593 unsigned stride = strmout->stride[i];
2594 struct ir3_instruction *base, *off;
2595
2596 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2597
2598 /* 24-bit should be enough: */
2599 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2600 create_immed(ctx->block, stride * 4), 0);
2601
2602 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2603 }
2604
2605 /* Generate the per-output store instructions: */
2606 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2607 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2608 unsigned c = j + strmout->output[i].start_component;
2609 struct ir3_instruction *base, *out, *stg;
2610
2611 base = bases[strmout->output[i].output_buffer];
2612 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2613
2614 stg = ir3_STG(ctx->block, base, 0, out, 0,
2615 create_immed(ctx->block, 1), 0);
2616 stg->cat6.type = TYPE_U32;
2617 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2618
2619 array_insert(ctx->block, ctx->block->keeps, stg);
2620 }
2621 }
2622
2623 /* and finally switch to the new_end_block: */
2624 ctx->block = new_end_block;
2625 }
2626
2627 static void
2628 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2629 {
2630 nir_metadata_require(impl, nir_metadata_block_index);
2631
2632 compile_assert(ctx, ctx->stack == 0);
2633
2634 emit_cf_list(ctx, &impl->body);
2635 emit_block(ctx, impl->end_block);
2636
2637 compile_assert(ctx, ctx->stack == 0);
2638
2639 /* at this point, we should have a single empty block,
2640 * into which we emit the 'end' instruction.
2641 */
2642 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2643
2644 /* If stream-out (aka transform-feedback) enabled, emit the
2645 * stream-out instructions, followed by a new empty block (into
2646 * which the 'end' instruction lands).
2647 *
2648 * NOTE: it is done in this order, rather than inserting before
2649 * we emit end_block, because NIR guarantees that all blocks
2650 * flow into end_block, and that end_block has no successors.
2651 * So by re-purposing end_block as the first block of stream-
2652 * out, we guarantee that all exit paths flow into the stream-
2653 * out instructions.
2654 */
2655 if ((ctx->compiler->gpu_id < 500) &&
2656 (ctx->so->shader->stream_output.num_outputs > 0) &&
2657 !ctx->so->binning_pass) {
2658 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2659 emit_stream_out(ctx);
2660 }
2661
2662 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2663 * NOP and has an epilogue that writes the VS outputs to local storage, to
2664 * be read by the HS. Then it resets execution mask (chmask) and chains
2665 * to the next shader (chsh).
2666 */
2667 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2668 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2669 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2670 struct ir3_instruction *chmask =
2671 ir3_CHMASK(ctx->block);
2672 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2673 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2674
2675 struct ir3_instruction *chsh =
2676 ir3_CHSH(ctx->block);
2677 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2678 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2679 } else {
2680 ir3_END(ctx->block);
2681 }
2682 }
2683
2684 static void
2685 setup_input(struct ir3_context *ctx, nir_variable *in)
2686 {
2687 struct ir3_shader_variant *so = ctx->so;
2688 unsigned ncomp = glsl_get_components(in->type);
2689 unsigned n = in->data.driver_location;
2690 unsigned frac = in->data.location_frac;
2691 unsigned slot = in->data.location;
2692
2693 /* Inputs are loaded using ldlw or ldg for these stages. */
2694 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2695 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2696 ctx->so->type == MESA_SHADER_GEOMETRY)
2697 return;
2698
2699 /* skip unread inputs, we could end up with (for example), unsplit
2700 * matrix/etc inputs in the case they are not read, so just silently
2701 * skip these.
2702 */
2703 if (ncomp > 4)
2704 return;
2705
2706 so->inputs[n].slot = slot;
2707 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2708 so->inputs_count = MAX2(so->inputs_count, n + 1);
2709 so->inputs[n].interpolate = in->data.interpolation;
2710
2711 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2712
2713 /* if any varyings have 'sample' qualifer, that triggers us
2714 * to run in per-sample mode:
2715 */
2716 so->per_samp |= in->data.sample;
2717
2718 for (int i = 0; i < ncomp; i++) {
2719 struct ir3_instruction *instr = NULL;
2720 unsigned idx = (n * 4) + i + frac;
2721
2722 if (slot == VARYING_SLOT_POS) {
2723 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2724 } else if (slot == VARYING_SLOT_PNTC) {
2725 /* see for example st_nir_fixup_varying_slots().. this is
2726 * maybe a bit mesa/st specific. But we need things to line
2727 * up for this in fdN_program:
2728 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2729 * if (emit->sprite_coord_enable & texmask) {
2730 * ...
2731 * }
2732 */
2733 so->inputs[n].slot = VARYING_SLOT_VAR8;
2734 so->inputs[n].bary = true;
2735 instr = create_frag_input(ctx, false, idx);
2736 } else {
2737 /* detect the special case for front/back colors where
2738 * we need to do flat vs smooth shading depending on
2739 * rast state:
2740 */
2741 if (in->data.interpolation == INTERP_MODE_NONE) {
2742 switch (slot) {
2743 case VARYING_SLOT_COL0:
2744 case VARYING_SLOT_COL1:
2745 case VARYING_SLOT_BFC0:
2746 case VARYING_SLOT_BFC1:
2747 so->inputs[n].rasterflat = true;
2748 break;
2749 default:
2750 break;
2751 }
2752 }
2753
2754 if (ctx->compiler->flat_bypass) {
2755 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2756 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2757 so->inputs[n].use_ldlv = true;
2758 }
2759
2760 so->inputs[n].bary = true;
2761
2762 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2763 }
2764
2765 compile_assert(ctx, idx < ctx->ninputs);
2766
2767 ctx->inputs[idx] = instr;
2768 }
2769 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2770 struct ir3_instruction *input = NULL, *in;
2771 struct ir3_instruction *components[4];
2772 unsigned mask = (1 << (ncomp + frac)) - 1;
2773
2774 foreach_input(in, ctx->ir) {
2775 if (in->input.inidx == n) {
2776 input = in;
2777 break;
2778 }
2779 }
2780
2781 if (!input) {
2782 input = create_input(ctx, mask);
2783 input->input.inidx = n;
2784 } else {
2785 input->regs[0]->wrmask |= mask;
2786 }
2787
2788 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2789
2790 for (int i = 0; i < ncomp; i++) {
2791 unsigned idx = (n * 4) + i + frac;
2792 compile_assert(ctx, idx < ctx->ninputs);
2793 ctx->inputs[idx] = components[i];
2794 }
2795 } else {
2796 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2797 }
2798
2799 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2800 so->total_in += ncomp;
2801 }
2802 }
2803
2804 /* Initially we assign non-packed inloc's for varyings, as we don't really
2805 * know up-front which components will be unused. After all the compilation
2806 * stages we scan the shader to see which components are actually used, and
2807 * re-pack the inlocs to eliminate unneeded varyings.
2808 */
2809 static void
2810 pack_inlocs(struct ir3_context *ctx)
2811 {
2812 struct ir3_shader_variant *so = ctx->so;
2813 uint8_t used_components[so->inputs_count];
2814
2815 memset(used_components, 0, sizeof(used_components));
2816
2817 /*
2818 * First Step: scan shader to find which bary.f/ldlv remain:
2819 */
2820
2821 foreach_block (block, &ctx->ir->block_list) {
2822 foreach_instr (instr, &block->instr_list) {
2823 if (is_input(instr)) {
2824 unsigned inloc = instr->regs[1]->iim_val;
2825 unsigned i = inloc / 4;
2826 unsigned j = inloc % 4;
2827
2828 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2829 compile_assert(ctx, i < so->inputs_count);
2830
2831 used_components[i] |= 1 << j;
2832 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2833 for (int n = 0; n < 2; n++) {
2834 unsigned inloc = instr->prefetch.input_offset + n;
2835 unsigned i = inloc / 4;
2836 unsigned j = inloc % 4;
2837
2838 compile_assert(ctx, i < so->inputs_count);
2839
2840 used_components[i] |= 1 << j;
2841 }
2842 }
2843 }
2844 }
2845
2846 /*
2847 * Second Step: reassign varying inloc/slots:
2848 */
2849
2850 unsigned actual_in = 0;
2851 unsigned inloc = 0;
2852
2853 for (unsigned i = 0; i < so->inputs_count; i++) {
2854 unsigned compmask = 0, maxcomp = 0;
2855
2856 so->inputs[i].inloc = inloc;
2857 so->inputs[i].bary = false;
2858
2859 for (unsigned j = 0; j < 4; j++) {
2860 if (!(used_components[i] & (1 << j)))
2861 continue;
2862
2863 compmask |= (1 << j);
2864 actual_in++;
2865 maxcomp = j + 1;
2866
2867 /* at this point, since used_components[i] mask is only
2868 * considering varyings (ie. not sysvals) we know this
2869 * is a varying:
2870 */
2871 so->inputs[i].bary = true;
2872 }
2873
2874 if (so->inputs[i].bary) {
2875 so->varying_in++;
2876 so->inputs[i].compmask = (1 << maxcomp) - 1;
2877 inloc += maxcomp;
2878 }
2879 }
2880
2881 /*
2882 * Third Step: reassign packed inloc's:
2883 */
2884
2885 foreach_block (block, &ctx->ir->block_list) {
2886 foreach_instr (instr, &block->instr_list) {
2887 if (is_input(instr)) {
2888 unsigned inloc = instr->regs[1]->iim_val;
2889 unsigned i = inloc / 4;
2890 unsigned j = inloc % 4;
2891
2892 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2893 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2894 unsigned i = instr->prefetch.input_offset / 4;
2895 unsigned j = instr->prefetch.input_offset % 4;
2896 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2897 }
2898 }
2899 }
2900 }
2901
2902 static void
2903 setup_output(struct ir3_context *ctx, nir_variable *out)
2904 {
2905 struct ir3_shader_variant *so = ctx->so;
2906 unsigned ncomp = glsl_get_components(out->type);
2907 unsigned n = out->data.driver_location;
2908 unsigned frac = out->data.location_frac;
2909 unsigned slot = out->data.location;
2910 unsigned comp = 0;
2911
2912 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2913 switch (slot) {
2914 case FRAG_RESULT_DEPTH:
2915 comp = 2; /* tgsi will write to .z component */
2916 so->writes_pos = true;
2917 break;
2918 case FRAG_RESULT_COLOR:
2919 so->color0_mrt = 1;
2920 break;
2921 case FRAG_RESULT_SAMPLE_MASK:
2922 so->writes_smask = true;
2923 break;
2924 default:
2925 if (slot >= FRAG_RESULT_DATA0)
2926 break;
2927 ir3_context_error(ctx, "unknown FS output name: %s\n",
2928 gl_frag_result_name(slot));
2929 }
2930 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2931 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2932 ctx->so->type == MESA_SHADER_GEOMETRY) {
2933 switch (slot) {
2934 case VARYING_SLOT_POS:
2935 so->writes_pos = true;
2936 break;
2937 case VARYING_SLOT_PSIZ:
2938 so->writes_psize = true;
2939 break;
2940 case VARYING_SLOT_PRIMITIVE_ID:
2941 case VARYING_SLOT_LAYER:
2942 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2943 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2944 /* fall through */
2945 case VARYING_SLOT_COL0:
2946 case VARYING_SLOT_COL1:
2947 case VARYING_SLOT_BFC0:
2948 case VARYING_SLOT_BFC1:
2949 case VARYING_SLOT_FOGC:
2950 case VARYING_SLOT_CLIP_DIST0:
2951 case VARYING_SLOT_CLIP_DIST1:
2952 case VARYING_SLOT_CLIP_VERTEX:
2953 break;
2954 default:
2955 if (slot >= VARYING_SLOT_VAR0)
2956 break;
2957 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2958 break;
2959 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2960 _mesa_shader_stage_to_string(ctx->so->type),
2961 gl_varying_slot_name(slot));
2962 }
2963 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2964 /* output lowered to buffer writes. */
2965 return;
2966 } else {
2967 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2968 }
2969
2970 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2971
2972 so->outputs[n].slot = slot;
2973 so->outputs[n].regid = regid(n, comp);
2974 so->outputs_count = MAX2(so->outputs_count, n + 1);
2975
2976 for (int i = 0; i < ncomp; i++) {
2977 unsigned idx = (n * 4) + i + frac;
2978 compile_assert(ctx, idx < ctx->noutputs);
2979 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2980 }
2981
2982 /* if varying packing doesn't happen, we could end up in a situation
2983 * with "holes" in the output, and since the per-generation code that
2984 * sets up varying linkage registers doesn't expect to have more than
2985 * one varying per vec4 slot, pad the holes.
2986 *
2987 * Note that this should probably generate a performance warning of
2988 * some sort.
2989 */
2990 for (int i = 0; i < frac; i++) {
2991 unsigned idx = (n * 4) + i;
2992 if (!ctx->outputs[idx]) {
2993 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2994 }
2995 }
2996 }
2997
2998 static int
2999 max_drvloc(struct exec_list *vars)
3000 {
3001 int drvloc = -1;
3002 nir_foreach_variable(var, vars) {
3003 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3004 }
3005 return drvloc;
3006 }
3007
3008 static void
3009 emit_instructions(struct ir3_context *ctx)
3010 {
3011 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3012
3013 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3014 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3015
3016 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3017 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3018
3019 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3020
3021 /* Create inputs in first block: */
3022 ctx->block = get_block(ctx, nir_start_block(fxn));
3023 ctx->in_block = ctx->block;
3024 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3025
3026 /* for fragment shader, the vcoord input register is used as the
3027 * base for bary.f varying fetch instrs:
3028 *
3029 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3030 * until emit_intrinsic when we know they are actually needed.
3031 * For now, we defer creating ctx->ij_centroid, etc, since we
3032 * only need ij_pixel for "old style" varying inputs (ie.
3033 * tgsi_to_nir)
3034 */
3035 struct ir3_instruction *vcoord = NULL;
3036 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3037 struct ir3_instruction *xy[2];
3038
3039 vcoord = create_input(ctx, 0x3);
3040 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3041
3042 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3043 }
3044
3045 /* Setup inputs: */
3046 nir_foreach_variable(var, &ctx->s->inputs) {
3047 setup_input(ctx, var);
3048 }
3049
3050 /* Defer add_sysval_input() stuff until after setup_inputs(),
3051 * because sysvals need to be appended after varyings:
3052 */
3053 if (vcoord) {
3054 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
3055 0x3, vcoord);
3056 }
3057
3058
3059 /* Tesselation shaders always need primitive ID for indexing the
3060 * BO. Geometry shaders don't always need it but when they do it has be
3061 * delivered and unclobbered in the VS. To make things easy, we always
3062 * make room for it in VS/DS.
3063 */
3064 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3065 bool has_gs = ctx->so->key.has_gs;
3066 switch (ctx->so->type) {
3067 case MESA_SHADER_VERTEX:
3068 if (has_tess) {
3069 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3070 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3071 } else if (has_gs) {
3072 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3073 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3074 }
3075 break;
3076 case MESA_SHADER_TESS_CTRL:
3077 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3078 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3079 break;
3080 case MESA_SHADER_TESS_EVAL:
3081 if (has_gs)
3082 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3083 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3084 break;
3085 case MESA_SHADER_GEOMETRY:
3086 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3087 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3088 break;
3089 default:
3090 break;
3091 }
3092
3093 /* Setup outputs: */
3094 nir_foreach_variable(var, &ctx->s->outputs) {
3095 setup_output(ctx, var);
3096 }
3097
3098 /* Find # of samplers: */
3099 nir_foreach_variable(var, &ctx->s->uniforms) {
3100 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3101 /* just assume that we'll be reading from images.. if it
3102 * is write-only we don't have to count it, but not sure
3103 * if there is a good way to know?
3104 */
3105 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3106 }
3107
3108 /* NOTE: need to do something more clever when we support >1 fxn */
3109 nir_foreach_register(reg, &fxn->registers) {
3110 ir3_declare_array(ctx, reg);
3111 }
3112 /* And emit the body: */
3113 ctx->impl = fxn;
3114 emit_function(ctx, fxn);
3115 }
3116
3117 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3118 * need to assign the tex state indexes for these after we know the
3119 * max tex index.
3120 */
3121 static void
3122 fixup_astc_srgb(struct ir3_context *ctx)
3123 {
3124 struct ir3_shader_variant *so = ctx->so;
3125 /* indexed by original tex idx, value is newly assigned alpha sampler
3126 * state tex idx. Zero is invalid since there is at least one sampler
3127 * if we get here.
3128 */
3129 unsigned alt_tex_state[16] = {0};
3130 unsigned tex_idx = ctx->max_texture_index + 1;
3131 unsigned idx = 0;
3132
3133 so->astc_srgb.base = tex_idx;
3134
3135 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3136 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3137
3138 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3139
3140 if (alt_tex_state[sam->cat5.tex] == 0) {
3141 /* assign new alternate/alpha tex state slot: */
3142 alt_tex_state[sam->cat5.tex] = tex_idx++;
3143 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3144 so->astc_srgb.count++;
3145 }
3146
3147 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3148 }
3149 }
3150
3151 static void
3152 fixup_binning_pass(struct ir3_context *ctx)
3153 {
3154 struct ir3_shader_variant *so = ctx->so;
3155 struct ir3 *ir = ctx->ir;
3156 unsigned i, j;
3157
3158 /* first pass, remove unused outputs from the IR level outputs: */
3159 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3160 struct ir3_instruction *out = ir->outputs[i];
3161 assert(out->opc == OPC_META_COLLECT);
3162 unsigned outidx = out->collect.outidx;
3163 unsigned slot = so->outputs[outidx].slot;
3164
3165 /* throw away everything but first position/psize */
3166 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3167 ir->outputs[j] = ir->outputs[i];
3168 j++;
3169 }
3170 }
3171 ir->outputs_count = j;
3172
3173 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3174 * table:
3175 */
3176 for (i = 0, j = 0; i < so->outputs_count; i++) {
3177 unsigned slot = so->outputs[i].slot;
3178
3179 /* throw away everything but first position/psize */
3180 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3181 so->outputs[j] = so->outputs[i];
3182
3183 /* fixup outidx to point to new output table entry: */
3184 struct ir3_instruction *out;
3185 foreach_output(out, ir) {
3186 if (out->collect.outidx == i) {
3187 out->collect.outidx = j;
3188 break;
3189 }
3190 }
3191
3192 j++;
3193 }
3194 }
3195 so->outputs_count = j;
3196 }
3197
3198 static void
3199 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3200 {
3201 unsigned idx = 0;
3202
3203 /* Collect sampling instructions eligible for pre-dispatch. */
3204 foreach_block (block, &ir->block_list) {
3205 foreach_instr_safe (instr, &block->instr_list) {
3206 if (instr->opc == OPC_META_TEX_PREFETCH) {
3207 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3208 struct ir3_sampler_prefetch *fetch =
3209 &ctx->so->sampler_prefetch[idx];
3210 idx++;
3211
3212 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3213 fetch->wrmask = instr->regs[0]->wrmask;
3214 fetch->tex_id = instr->prefetch.tex;
3215 fetch->samp_id = instr->prefetch.samp;
3216 fetch->dst = instr->regs[0]->num;
3217 fetch->src = instr->prefetch.input_offset;
3218
3219 ctx->so->total_in =
3220 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3221
3222 /* Disable half precision until supported. */
3223 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3224
3225 /* Remove the prefetch placeholder instruction: */
3226 list_delinit(&instr->node);
3227 }
3228 }
3229 }
3230 }
3231
3232 int
3233 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3234 struct ir3_shader_variant *so)
3235 {
3236 struct ir3_context *ctx;
3237 struct ir3 *ir;
3238 int ret = 0, max_bary;
3239
3240 assert(!so->ir);
3241
3242 ctx = ir3_context_init(compiler, so);
3243 if (!ctx) {
3244 DBG("INIT failed!");
3245 ret = -1;
3246 goto out;
3247 }
3248
3249 emit_instructions(ctx);
3250
3251 if (ctx->error) {
3252 DBG("EMIT failed!");
3253 ret = -1;
3254 goto out;
3255 }
3256
3257 ir = so->ir = ctx->ir;
3258
3259 assert((ctx->noutputs % 4) == 0);
3260
3261 /* Setup IR level outputs, which are "collects" that gather
3262 * the scalar components of outputs.
3263 */
3264 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3265 unsigned ncomp = 0;
3266 /* figure out the # of components written:
3267 *
3268 * TODO do we need to handle holes, ie. if .x and .z
3269 * components written, but .y component not written?
3270 */
3271 for (unsigned j = 0; j < 4; j++) {
3272 if (!ctx->outputs[i + j])
3273 break;
3274 ncomp++;
3275 }
3276
3277 /* Note that in some stages, like TCS, store_output is
3278 * lowered to memory writes, so no components of the
3279 * are "written" from the PoV of traditional store-
3280 * output instructions:
3281 */
3282 if (!ncomp)
3283 continue;
3284
3285 struct ir3_instruction *out =
3286 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3287
3288 int outidx = i / 4;
3289 assert(outidx < so->outputs_count);
3290
3291 /* stash index into so->outputs[] so we can map the
3292 * output back to slot/etc later:
3293 */
3294 out->collect.outidx = outidx;
3295
3296 array_insert(ir, ir->outputs, out);
3297 }
3298
3299 /* Set up the gs header as an output for the vertex shader so it won't
3300 * clobber it for the tess ctrl shader.
3301 *
3302 * TODO this could probably be done more cleanly in a nir pass.
3303 */
3304 if (ctx->so->type == MESA_SHADER_VERTEX ||
3305 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3306 if (ctx->primitive_id) {
3307 unsigned n = so->outputs_count++;
3308 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3309
3310 struct ir3_instruction *out =
3311 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3312 out->collect.outidx = n;
3313 array_insert(ir, ir->outputs, out);
3314 }
3315
3316 if (ctx->gs_header) {
3317 unsigned n = so->outputs_count++;
3318 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3319 struct ir3_instruction *out =
3320 ir3_create_collect(ctx, &ctx->gs_header, 1);
3321 out->collect.outidx = n;
3322 array_insert(ir, ir->outputs, out);
3323 }
3324
3325 if (ctx->tcs_header) {
3326 unsigned n = so->outputs_count++;
3327 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3328 struct ir3_instruction *out =
3329 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3330 out->collect.outidx = n;
3331 array_insert(ir, ir->outputs, out);
3332 }
3333 }
3334
3335 /* at this point, for binning pass, throw away unneeded outputs: */
3336 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3337 fixup_binning_pass(ctx);
3338
3339 ir3_debug_print(ir, "BEFORE CP");
3340
3341 ir3_cp(ir, so);
3342
3343 /* at this point, for binning pass, throw away unneeded outputs:
3344 * Note that for a6xx and later, we do this after ir3_cp to ensure
3345 * that the uniform/constant layout for BS and VS matches, so that
3346 * we can re-use same VS_CONST state group.
3347 */
3348 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3349 fixup_binning_pass(ctx);
3350
3351 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3352 * need to make sure not to remove any inputs that are used by
3353 * the nonbinning VS.
3354 */
3355 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3356 so->type == MESA_SHADER_VERTEX) {
3357 for (int i = 0; i < ctx->ninputs; i++) {
3358 struct ir3_instruction *in = ctx->inputs[i];
3359
3360 if (!in)
3361 continue;
3362
3363 unsigned n = i / 4;
3364 unsigned c = i % 4;
3365
3366 debug_assert(n < so->nonbinning->inputs_count);
3367
3368 if (so->nonbinning->inputs[n].sysval)
3369 continue;
3370
3371 /* be sure to keep inputs, even if only used in VS */
3372 if (so->nonbinning->inputs[n].compmask & (1 << c))
3373 array_insert(in->block, in->block->keeps, in);
3374 }
3375 }
3376
3377 ir3_debug_print(ir, "BEFORE GROUPING");
3378
3379 ir3_sched_add_deps(ir);
3380
3381 /* Group left/right neighbors, inserting mov's where needed to
3382 * solve conflicts:
3383 */
3384 ir3_group(ir);
3385
3386 ir3_debug_print(ir, "AFTER GROUPING");
3387
3388 ir3_depth(ir, so);
3389
3390 ir3_debug_print(ir, "AFTER DEPTH");
3391
3392 /* do Sethi–Ullman numbering before scheduling: */
3393 ir3_sun(ir);
3394
3395 ret = ir3_sched(ir);
3396 if (ret) {
3397 DBG("SCHED failed!");
3398 goto out;
3399 }
3400
3401 if (compiler->gpu_id >= 600) {
3402 ir3_a6xx_fixup_atomic_dests(ir, so);
3403 }
3404
3405 ir3_debug_print(ir, "AFTER SCHED");
3406
3407 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3408 * with draw pass VS, so binning and draw pass can both use the
3409 * same VBO state.
3410 *
3411 * Note that VS inputs are expected to be full precision.
3412 */
3413 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3414 (ir->type == MESA_SHADER_VERTEX) &&
3415 so->binning_pass;
3416
3417 if (pre_assign_inputs) {
3418 for (unsigned i = 0; i < ctx->ninputs; i++) {
3419 struct ir3_instruction *instr = ctx->inputs[i];
3420
3421 if (!instr)
3422 continue;
3423
3424 unsigned n = i / 4;
3425 unsigned c = i % 4;
3426 unsigned regid = so->nonbinning->inputs[n].regid + c;
3427
3428 instr->regs[0]->num = regid;
3429 }
3430
3431 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3432 } else if (ctx->tcs_header) {
3433 /* We need to have these values in the same registers between VS and TCS
3434 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3435 */
3436
3437 ctx->tcs_header->regs[0]->num = regid(0, 0);
3438 ctx->primitive_id->regs[0]->num = regid(0, 1);
3439 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3440 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3441 } else if (ctx->gs_header) {
3442 /* We need to have these values in the same registers between producer
3443 * (VS or DS) and GS since the producer chains to GS and doesn't get
3444 * the sysvals redelivered.
3445 */
3446
3447 ctx->gs_header->regs[0]->num = regid(0, 0);
3448 ctx->primitive_id->regs[0]->num = regid(0, 1);
3449 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3450 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3451 } else if (so->num_sampler_prefetch) {
3452 assert(so->type == MESA_SHADER_FRAGMENT);
3453 struct ir3_instruction *instr, *precolor[2];
3454 int idx = 0;
3455
3456 foreach_input(instr, ir) {
3457 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3458 continue;
3459
3460 assert(idx < ARRAY_SIZE(precolor));
3461
3462 precolor[idx] = instr;
3463 instr->regs[0]->num = idx;
3464
3465 idx++;
3466 }
3467 ret = ir3_ra(so, precolor, idx);
3468 } else {
3469 ret = ir3_ra(so, NULL, 0);
3470 }
3471
3472 if (ret) {
3473 DBG("RA failed!");
3474 goto out;
3475 }
3476
3477 ir3_debug_print(ir, "AFTER RA");
3478
3479 if (so->type == MESA_SHADER_FRAGMENT)
3480 pack_inlocs(ctx);
3481
3482 /*
3483 * Fixup inputs/outputs to point to the actual registers assigned:
3484 *
3485 * 1) initialize to r63.x (invalid/unused)
3486 * 2) iterate IR level inputs/outputs and update the variants
3487 * inputs/outputs table based on the assigned registers for
3488 * the remaining inputs/outputs.
3489 */
3490
3491 for (unsigned i = 0; i < so->inputs_count; i++)
3492 so->inputs[i].regid = INVALID_REG;
3493 for (unsigned i = 0; i < so->outputs_count; i++)
3494 so->outputs[i].regid = INVALID_REG;
3495
3496 struct ir3_instruction *out;
3497 foreach_output(out, ir) {
3498 assert(out->opc == OPC_META_COLLECT);
3499 unsigned outidx = out->collect.outidx;
3500
3501 so->outputs[outidx].regid = out->regs[0]->num;
3502 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3503 }
3504
3505 struct ir3_instruction *in;
3506 foreach_input(in, ir) {
3507 assert(in->opc == OPC_META_INPUT);
3508 unsigned inidx = in->input.inidx;
3509
3510 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3511 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3512 compile_assert(ctx, in->regs[0]->num ==
3513 so->nonbinning->inputs[inidx].regid);
3514 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3515 so->nonbinning->inputs[inidx].half);
3516 }
3517 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3518 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3519 } else {
3520 so->inputs[inidx].regid = in->regs[0]->num;
3521 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3522 }
3523 }
3524
3525 if (ctx->astc_srgb)
3526 fixup_astc_srgb(ctx);
3527
3528 /* We need to do legalize after (for frag shader's) the "bary.f"
3529 * offsets (inloc) have been assigned.
3530 */
3531 ir3_legalize(ir, so, &max_bary);
3532
3533 ir3_debug_print(ir, "AFTER LEGALIZE");
3534
3535 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3536 * know what we might have to wait on when coming in from VS chsh.
3537 */
3538 if (so->type == MESA_SHADER_TESS_CTRL ||
3539 so->type == MESA_SHADER_GEOMETRY ) {
3540 foreach_block (block, &ir->block_list) {
3541 foreach_instr (instr, &block->instr_list) {
3542 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3543 break;
3544 }
3545 }
3546 }
3547
3548 so->branchstack = ctx->max_stack;
3549
3550 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3551 if (so->type == MESA_SHADER_FRAGMENT)
3552 so->total_in = max_bary + 1;
3553
3554 so->max_sun = ir->max_sun;
3555
3556 /* Collect sampling instructions eligible for pre-dispatch. */
3557 collect_tex_prefetches(ctx, ir);
3558
3559 out:
3560 if (ret) {
3561 if (so->ir)
3562 ir3_destroy(so->ir);
3563 so->ir = NULL;
3564 }
3565 ir3_context_free(ctx);
3566
3567 return ret;
3568 }