2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
55 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
57 src
->array
.offset
= n
;
59 ir3_instr_set_address(mov
, address
);
64 static struct ir3_instruction
*
65 create_input(struct ir3_context
*ctx
, unsigned compmask
)
67 struct ir3_instruction
*in
;
69 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
70 in
->input
.sysval
= ~0;
71 __ssa_dst(in
)->wrmask
= compmask
;
73 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
78 static struct ir3_instruction
*
79 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
81 struct ir3_block
*block
= ctx
->block
;
82 struct ir3_instruction
*instr
;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction
*inloc
= create_immed(block
, n
);
87 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
88 instr
->cat6
.type
= TYPE_U32
;
89 instr
->cat6
.iim_val
= 1;
91 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
92 instr
->regs
[2]->wrmask
= 0x3;
98 static struct ir3_instruction
*
99 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
104 unsigned n
= const_state
->offsets
.driver_param
;
105 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
106 return create_uniform(ctx
->block
, r
);
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
116 * -------+---------+-------+-
120 * To convert from an adreno bool (uint) to nir, use:
122 * absneg.s dst, (neg)src
124 * To convert back in the other direction:
126 * absneg.s dst, (abs)arc
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction
*
140 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
142 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction
*
147 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
153 * alu/sfu instructions:
156 static struct ir3_instruction
*
157 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
158 unsigned src_bitsize
, nir_op op
)
160 type_t src_type
, dst_type
;
164 case nir_op_f2f16_rtne
:
165 case nir_op_f2f16_rtz
:
173 switch (src_bitsize
) {
181 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
190 switch (src_bitsize
) {
201 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
210 switch (src_bitsize
) {
221 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
226 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
236 case nir_op_f2f16_rtne
:
237 case nir_op_f2f16_rtz
:
239 /* TODO how to handle rounding mode? */
276 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
279 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
283 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
285 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
286 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
287 unsigned bs
[info
->num_inputs
]; /* bit size */
288 struct ir3_block
*b
= ctx
->block
;
289 unsigned dst_sz
, wrmask
;
290 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
293 if (alu
->dest
.dest
.is_ssa
) {
294 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
295 wrmask
= (1 << dst_sz
) - 1;
297 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
298 wrmask
= alu
->dest
.write_mask
;
301 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
307 if ((alu
->op
== nir_op_vec2
) ||
308 (alu
->op
== nir_op_vec3
) ||
309 (alu
->op
== nir_op_vec4
)) {
311 for (int i
= 0; i
< info
->num_inputs
; i
++) {
312 nir_alu_src
*asrc
= &alu
->src
[i
];
314 compile_assert(ctx
, !asrc
->abs
);
315 compile_assert(ctx
, !asrc
->negate
);
317 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
319 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
320 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
323 ir3_put_dst(ctx
, &alu
->dest
.dest
);
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
330 if (alu
->op
== nir_op_mov
) {
331 nir_alu_src
*asrc
= &alu
->src
[0];
332 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
334 for (unsigned i
= 0; i
< dst_sz
; i
++) {
335 if (wrmask
& (1 << i
)) {
336 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
342 ir3_put_dst(ctx
, &alu
->dest
.dest
);
346 /* General case: We can just grab the one used channel per src. */
347 for (int i
= 0; i
< info
->num_inputs
; i
++) {
348 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
349 nir_alu_src
*asrc
= &alu
->src
[i
];
351 compile_assert(ctx
, !asrc
->abs
);
352 compile_assert(ctx
, !asrc
->negate
);
354 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
355 bs
[i
] = nir_src_bit_size(asrc
->src
);
357 compile_assert(ctx
, src
[i
]);
362 case nir_op_f2f16_rtne
:
363 case nir_op_f2f16_rtz
:
381 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
383 case nir_op_fquantize2f16
:
384 dst
[0] = create_cov(ctx
,
385 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
389 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_F16
);
390 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, zero
, 0);
391 dst
[0]->cat2
.condition
= IR3_COND_NE
;
395 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
396 dst
[0]->cat2
.condition
= IR3_COND_NE
;
399 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
402 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
407 dst
[0] = ir3_b2n(b
, src
[0]);
410 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_S16
);
411 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, zero
, 0);
412 dst
[0]->cat2
.condition
= IR3_COND_NE
;
416 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
417 dst
[0]->cat2
.condition
= IR3_COND_NE
;
421 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
424 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
427 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
430 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
438 * TODO probably opc_cat==4 is ok too
440 if (alu
->src
[0].src
.is_ssa
&&
441 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
442 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
443 src
[0]->flags
|= IR3_INSTR_SAT
;
444 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
449 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
450 dst
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
460 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
463 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
466 case nir_op_fddx_coarse
:
467 dst
[0] = ir3_DSX(b
, src
[0], 0);
468 dst
[0]->cat5
.type
= TYPE_F32
;
471 case nir_op_fddy_coarse
:
472 dst
[0] = ir3_DSY(b
, src
[0], 0);
473 dst
[0]->cat5
.type
= TYPE_F32
;
478 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
479 dst
[0]->cat2
.condition
= IR3_COND_LT
;
483 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
484 dst
[0]->cat2
.condition
= IR3_COND_GE
;
488 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
489 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
493 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
494 dst
[0]->cat2
.condition
= IR3_COND_NE
;
497 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
500 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
503 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
505 case nir_op_fround_even
:
506 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
509 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
513 dst
[0] = ir3_SIN(b
, src
[0], 0);
516 dst
[0] = ir3_COS(b
, src
[0], 0);
519 dst
[0] = ir3_RSQ(b
, src
[0], 0);
522 dst
[0] = ir3_RCP(b
, src
[0], 0);
525 dst
[0] = ir3_LOG2(b
, src
[0], 0);
528 dst
[0] = ir3_EXP2(b
, src
[0], 0);
531 dst
[0] = ir3_SQRT(b
, src
[0], 0);
535 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
538 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
541 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
544 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
547 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
550 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
553 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
555 case nir_op_umul_low
:
556 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
558 case nir_op_imadsh_mix16
:
559 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
561 case nir_op_imad24_ir3
:
562 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
565 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
568 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
571 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
574 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
577 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
580 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
583 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
586 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
589 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
593 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
594 dst
[0]->cat2
.condition
= IR3_COND_LT
;
598 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
599 dst
[0]->cat2
.condition
= IR3_COND_GE
;
603 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
604 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
608 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
609 dst
[0]->cat2
.condition
= IR3_COND_NE
;
613 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
614 dst
[0]->cat2
.condition
= IR3_COND_LT
;
618 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
619 dst
[0]->cat2
.condition
= IR3_COND_GE
;
623 case nir_op_b32csel
: {
624 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
626 if ((src
[0]->regs
[0]->flags
& IR3_REG_HALF
))
627 cond
->regs
[0]->flags
|= IR3_REG_HALF
;
629 compile_assert(ctx
, bs
[1] == bs
[2]);
630 /* Make sure the boolean condition has the same bit size as the other
631 * two arguments, adding a conversion if necessary.
634 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
635 else if (bs
[1] > bs
[0])
636 cond
= ir3_COV(b
, cond
, TYPE_U16
, TYPE_U32
);
639 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
641 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
644 case nir_op_bit_count
: {
645 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
646 // double check on earlier gen's. Once half-precision support is
647 // in place, this should probably move to a NIR lowering pass:
648 struct ir3_instruction
*hi
, *lo
;
650 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
652 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
654 hi
= ir3_CBITS_B(b
, hi
, 0);
655 lo
= ir3_CBITS_B(b
, lo
, 0);
657 // TODO maybe the builders should default to making dst half-precision
658 // if the src's were half precision, to make this less awkward.. otoh
659 // we should probably just do this lowering in NIR.
660 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
661 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
663 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
664 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
665 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
668 case nir_op_ifind_msb
: {
669 struct ir3_instruction
*cmp
;
670 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
671 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
672 cmp
->cat2
.condition
= IR3_COND_GE
;
673 dst
[0] = ir3_SEL_B32(b
,
674 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
678 case nir_op_ufind_msb
:
679 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
680 dst
[0] = ir3_SEL_B32(b
,
681 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
682 src
[0], 0, dst
[0], 0);
684 case nir_op_find_lsb
:
685 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
686 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
688 case nir_op_bitfield_reverse
:
689 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
693 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
694 nir_op_infos
[alu
->op
].name
);
698 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
701 if (nir_dest_bit_size(alu
->dest
.dest
) < 32)
702 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
704 dst
[0] = ir3_n2b(b
, dst
[0]);
707 if (nir_dest_bit_size(alu
->dest
.dest
) < 32) {
708 for (unsigned i
= 0; i
< dst_sz
; i
++) {
709 dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
713 ir3_put_dst(ctx
, &alu
->dest
.dest
);
716 /* handles direct/indirect UBO reads: */
718 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
719 struct ir3_instruction
**dst
)
721 struct ir3_block
*b
= ctx
->block
;
722 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
723 /* UBO addresses are the first driver params, but subtract 2 here to
724 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
725 * is the uniforms: */
726 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
727 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
728 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
732 /* First src is ubo index, which could either be an immed or not: */
733 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
734 if (is_same_type_mov(src0
) &&
735 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
736 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
737 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
739 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, ptrsz
));
740 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, ptrsz
));
742 /* NOTE: since relative addressing is used, make sure constlen is
743 * at least big enough to cover all the UBO addresses, since the
744 * assembler won't know what the max address reg is.
746 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
747 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
750 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
753 if (nir_src_is_const(intr
->src
[1])) {
754 off
+= nir_src_as_uint(intr
->src
[1]);
756 /* For load_ubo_indirect, second src is indirect offset: */
757 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
759 /* and add offset to addr: */
760 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
763 /* if offset is to large to encode in the ldg, split it out: */
764 if ((off
+ (intr
->num_components
* 4)) > 1024) {
765 /* split out the minimal amount to improve the odds that
766 * cp can fit the immediate in the add.s instruction:
768 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
769 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
774 struct ir3_instruction
*carry
;
776 /* handle 32b rollover, ie:
777 * if (addr < base_lo)
780 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
781 carry
->cat2
.condition
= IR3_COND_LT
;
782 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
784 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
787 for (int i
= 0; i
< intr
->num_components
; i
++) {
788 struct ir3_instruction
*load
=
789 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
790 create_immed(b
, off
+ i
* 4), 0);
791 load
->cat6
.type
= TYPE_U32
;
796 /* src[] = { block_index } */
798 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
799 struct ir3_instruction
**dst
)
801 /* SSBO size stored as a const starting at ssbo_sizes: */
802 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
803 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
804 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
805 const_state
->ssbo_size
.off
[blk_idx
];
807 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
809 dst
[0] = create_uniform(ctx
->block
, idx
);
812 /* src[] = { offset }. const_index[] = { base } */
814 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
815 struct ir3_instruction
**dst
)
817 struct ir3_block
*b
= ctx
->block
;
818 struct ir3_instruction
*ldl
, *offset
;
821 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
822 base
= nir_intrinsic_base(intr
);
824 ldl
= ir3_LDL(b
, offset
, 0,
825 create_immed(b
, intr
->num_components
), 0,
826 create_immed(b
, base
), 0);
828 ldl
->cat6
.type
= utype_dst(intr
->dest
);
829 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
831 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
832 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
834 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
837 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
839 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
841 struct ir3_block
*b
= ctx
->block
;
842 struct ir3_instruction
*stl
, *offset
;
843 struct ir3_instruction
* const *value
;
844 unsigned base
, wrmask
;
846 value
= ir3_get_src(ctx
, &intr
->src
[0]);
847 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
849 base
= nir_intrinsic_base(intr
);
850 wrmask
= nir_intrinsic_write_mask(intr
);
852 /* Combine groups of consecutive enabled channels in one write
853 * message. We use ffs to find the first enabled channel and then ffs on
854 * the bit-inverse, down-shifted writemask to determine the length of
855 * the block of enabled bits.
857 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
860 unsigned first_component
= ffs(wrmask
) - 1;
861 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
863 stl
= ir3_STL(b
, offset
, 0,
864 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
865 create_immed(b
, length
), 0);
866 stl
->cat6
.dst_offset
= first_component
+ base
;
867 stl
->cat6
.type
= utype_src(intr
->src
[0]);
868 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
869 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
871 array_insert(b
, b
->keeps
, stl
);
873 /* Clear the bits in the writemask that we just wrote, then try
874 * again to see if more channels are left.
876 wrmask
&= (15 << (first_component
+ length
));
880 /* src[] = { offset }. const_index[] = { base } */
882 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
883 struct ir3_instruction
**dst
)
885 struct ir3_block
*b
= ctx
->block
;
886 struct ir3_instruction
*load
, *offset
;
889 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
890 base
= nir_intrinsic_base(intr
);
892 load
= ir3_LDLW(b
, offset
, 0,
893 create_immed(b
, intr
->num_components
), 0,
894 create_immed(b
, base
), 0);
896 load
->cat6
.type
= utype_dst(intr
->dest
);
897 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
899 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
900 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
902 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
905 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
907 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
909 struct ir3_block
*b
= ctx
->block
;
910 struct ir3_instruction
*store
, *offset
;
911 struct ir3_instruction
* const *value
;
912 unsigned base
, wrmask
;
914 value
= ir3_get_src(ctx
, &intr
->src
[0]);
915 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
917 base
= nir_intrinsic_base(intr
);
918 wrmask
= nir_intrinsic_write_mask(intr
);
920 /* Combine groups of consecutive enabled channels in one write
921 * message. We use ffs to find the first enabled channel and then ffs on
922 * the bit-inverse, down-shifted writemask to determine the length of
923 * the block of enabled bits.
925 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
928 unsigned first_component
= ffs(wrmask
) - 1;
929 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
931 store
= ir3_STLW(b
, offset
, 0,
932 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
933 create_immed(b
, length
), 0);
935 store
->cat6
.dst_offset
= first_component
+ base
;
936 store
->cat6
.type
= utype_src(intr
->src
[0]);
937 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
938 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
940 array_insert(b
, b
->keeps
, store
);
942 /* Clear the bits in the writemask that we just wrote, then try
943 * again to see if more channels are left.
945 wrmask
&= (15 << (first_component
+ length
));
950 * CS shared variable atomic intrinsics
952 * All of the shared variable atomic memory operations read a value from
953 * memory, compute a new value using one of the operations below, write the
954 * new value to memory, and return the original value read.
956 * All operations take 2 sources except CompSwap that takes 3. These
959 * 0: The offset into the shared variable storage region that the atomic
960 * operation will operate on.
961 * 1: The data parameter to the atomic function (i.e. the value to add
962 * in shared_atomic_add, etc).
963 * 2: For CompSwap only: the second data parameter.
965 static struct ir3_instruction
*
966 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
968 struct ir3_block
*b
= ctx
->block
;
969 struct ir3_instruction
*atomic
, *src0
, *src1
;
970 type_t type
= TYPE_U32
;
972 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
973 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
975 switch (intr
->intrinsic
) {
976 case nir_intrinsic_shared_atomic_add
:
977 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
979 case nir_intrinsic_shared_atomic_imin
:
980 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
983 case nir_intrinsic_shared_atomic_umin
:
984 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
986 case nir_intrinsic_shared_atomic_imax
:
987 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
990 case nir_intrinsic_shared_atomic_umax
:
991 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
993 case nir_intrinsic_shared_atomic_and
:
994 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
996 case nir_intrinsic_shared_atomic_or
:
997 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
999 case nir_intrinsic_shared_atomic_xor
:
1000 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1002 case nir_intrinsic_shared_atomic_exchange
:
1003 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1005 case nir_intrinsic_shared_atomic_comp_swap
:
1006 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1007 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1008 ir3_get_src(ctx
, &intr
->src
[2])[0],
1011 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1017 atomic
->cat6
.iim_val
= 1;
1019 atomic
->cat6
.type
= type
;
1020 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1021 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1023 /* even if nothing consume the result, we can't DCE the instruction: */
1024 array_insert(b
, b
->keeps
, atomic
);
1029 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1030 * to handle with the image_mapping table..
1032 static struct ir3_instruction
*
1033 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1035 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
1036 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1037 struct ir3_instruction
*texture
, *sampler
;
1039 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1040 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1042 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1048 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1050 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1051 struct ir3_instruction
**dst
)
1053 struct ir3_block
*b
= ctx
->block
;
1054 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1055 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1056 struct ir3_instruction
*sam
;
1057 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1058 struct ir3_instruction
*coords
[4];
1059 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1060 type_t type
= ir3_get_image_type(var
);
1062 /* hmm, this seems a bit odd, but it is what blob does and (at least
1063 * a5xx) just faults on bogus addresses otherwise:
1065 if (flags
& IR3_INSTR_3D
) {
1066 flags
&= ~IR3_INSTR_3D
;
1067 flags
|= IR3_INSTR_A
;
1070 for (unsigned i
= 0; i
< ncoords
; i
++)
1071 coords
[i
] = src0
[i
];
1074 coords
[ncoords
++] = create_immed(b
, 0);
1076 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
1077 samp_tex
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1079 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1080 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1082 ir3_split_dest(b
, dst
, sam
, 0, 4);
1086 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1087 struct ir3_instruction
**dst
)
1089 struct ir3_block
*b
= ctx
->block
;
1090 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1091 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1092 struct ir3_instruction
*sam
, *lod
;
1093 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1094 type_t dst_type
= nir_dest_bit_size(intr
->dest
) < 32 ?
1095 TYPE_U16
: TYPE_U32
;
1097 lod
= create_immed(b
, 0);
1098 sam
= ir3_SAM(b
, OPC_GETSIZE
, dst_type
, 0b1111, flags
,
1099 samp_tex
, lod
, NULL
);
1101 /* Array size actually ends up in .w rather than .z. This doesn't
1102 * matter for miplevel 0, but for higher mips the value in z is
1103 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1104 * returned, which means that we have to add 1 to it for arrays for
1107 * Note use a temporary dst and then copy, since the size of the dst
1108 * array that is passed in is based on nir's understanding of the
1109 * result size, not the hardware's
1111 struct ir3_instruction
*tmp
[4];
1113 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1115 /* get_size instruction returns size in bytes instead of texels
1116 * for imageBuffer, so we need to divide it by the pixel size
1117 * of the image format.
1119 * TODO: This is at least true on a5xx. Check other gens.
1121 enum glsl_sampler_dim dim
=
1122 glsl_get_sampler_dim(glsl_without_array(var
->type
));
1123 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
1124 /* Since all the possible values the divisor can take are
1125 * power-of-two (4, 8, or 16), the division is implemented
1127 * During shader setup, the log2 of the image format's
1128 * bytes-per-pixel should have been emitted in 2nd slot of
1129 * image_dims. See ir3_shader::emit_image_dims().
1131 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1132 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1133 const_state
->image_dims
.off
[var
->data
.driver_location
];
1134 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1136 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1139 for (unsigned i
= 0; i
< ncoords
; i
++)
1142 if (flags
& IR3_INSTR_A
) {
1143 if (ctx
->compiler
->levels_add_one
) {
1144 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1146 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1152 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1154 struct ir3_block
*b
= ctx
->block
;
1155 struct ir3_instruction
*barrier
;
1157 switch (intr
->intrinsic
) {
1158 case nir_intrinsic_barrier
:
1159 barrier
= ir3_BAR(b
);
1160 barrier
->cat7
.g
= true;
1161 barrier
->cat7
.l
= true;
1162 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1163 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1165 case nir_intrinsic_memory_barrier
:
1166 barrier
= ir3_FENCE(b
);
1167 barrier
->cat7
.g
= true;
1168 barrier
->cat7
.r
= true;
1169 barrier
->cat7
.w
= true;
1170 barrier
->cat7
.l
= true;
1171 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1172 IR3_BARRIER_BUFFER_W
;
1173 barrier
->barrier_conflict
=
1174 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1175 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1177 case nir_intrinsic_memory_barrier_atomic_counter
:
1178 case nir_intrinsic_memory_barrier_buffer
:
1179 barrier
= ir3_FENCE(b
);
1180 barrier
->cat7
.g
= true;
1181 barrier
->cat7
.r
= true;
1182 barrier
->cat7
.w
= true;
1183 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1184 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1185 IR3_BARRIER_BUFFER_W
;
1187 case nir_intrinsic_memory_barrier_image
:
1188 // TODO double check if this should have .g set
1189 barrier
= ir3_FENCE(b
);
1190 barrier
->cat7
.g
= true;
1191 barrier
->cat7
.r
= true;
1192 barrier
->cat7
.w
= true;
1193 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1194 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1195 IR3_BARRIER_IMAGE_W
;
1197 case nir_intrinsic_memory_barrier_shared
:
1198 barrier
= ir3_FENCE(b
);
1199 barrier
->cat7
.g
= true;
1200 barrier
->cat7
.l
= true;
1201 barrier
->cat7
.r
= true;
1202 barrier
->cat7
.w
= true;
1203 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1204 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1205 IR3_BARRIER_SHARED_W
;
1207 case nir_intrinsic_group_memory_barrier
:
1208 barrier
= ir3_FENCE(b
);
1209 barrier
->cat7
.g
= true;
1210 barrier
->cat7
.l
= true;
1211 barrier
->cat7
.r
= true;
1212 barrier
->cat7
.w
= true;
1213 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1214 IR3_BARRIER_IMAGE_W
|
1215 IR3_BARRIER_BUFFER_W
;
1216 barrier
->barrier_conflict
=
1217 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1218 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1219 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1225 /* make sure barrier doesn't get DCE'd */
1226 array_insert(b
, b
->keeps
, barrier
);
1229 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1230 gl_system_value slot
, unsigned compmask
,
1231 struct ir3_instruction
*instr
)
1233 struct ir3_shader_variant
*so
= ctx
->so
;
1234 unsigned n
= so
->inputs_count
++;
1236 assert(instr
->opc
== OPC_META_INPUT
);
1237 instr
->input
.inidx
= n
;
1238 instr
->input
.sysval
= slot
;
1240 so
->inputs
[n
].sysval
= true;
1241 so
->inputs
[n
].slot
= slot
;
1242 so
->inputs
[n
].compmask
= compmask
;
1243 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1247 static struct ir3_instruction
*
1248 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1252 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1253 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1257 static struct ir3_instruction
*
1258 get_barycentric_centroid(struct ir3_context
*ctx
)
1260 if (!ctx
->ij_centroid
) {
1261 struct ir3_instruction
*xy
[2];
1262 struct ir3_instruction
*ij
;
1264 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
, 0x3);
1265 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1267 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1270 return ctx
->ij_centroid
;
1273 static struct ir3_instruction
*
1274 get_barycentric_sample(struct ir3_context
*ctx
)
1276 if (!ctx
->ij_sample
) {
1277 struct ir3_instruction
*xy
[2];
1278 struct ir3_instruction
*ij
;
1280 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
, 0x3);
1281 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1283 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1286 return ctx
->ij_sample
;
1289 static struct ir3_instruction
*
1290 get_barycentric_pixel(struct ir3_context
*ctx
)
1292 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1293 * this to create ij_pixel only on demand:
1295 return ctx
->ij_pixel
;
1298 static struct ir3_instruction
*
1299 get_frag_coord(struct ir3_context
*ctx
)
1301 if (!ctx
->frag_coord
) {
1302 struct ir3_block
*b
= ctx
->block
;
1303 struct ir3_instruction
*xyzw
[4];
1304 struct ir3_instruction
*hw_frag_coord
;
1306 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1307 ir3_split_dest(ctx
->block
, xyzw
, hw_frag_coord
, 0, 4);
1309 /* for frag_coord.xy, we get unsigned values.. we need
1310 * to subtract (integer) 8 and divide by 16 (right-
1311 * shift by 4) then convert to float:
1315 * mov.u32f32 dst, tmp
1318 for (int i
= 0; i
< 2; i
++) {
1319 xyzw
[i
] = ir3_SUB_S(b
, xyzw
[i
], 0,
1320 create_immed(b
, 8), 0);
1321 xyzw
[i
] = ir3_SHR_B(b
, xyzw
[i
], 0,
1322 create_immed(b
, 4), 0);
1323 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1326 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1327 ctx
->so
->frag_coord
= true;
1330 return ctx
->frag_coord
;
1334 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1336 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1337 struct ir3_instruction
**dst
;
1338 struct ir3_instruction
* const *src
;
1339 struct ir3_block
*b
= ctx
->block
;
1342 if (info
->has_dest
) {
1343 unsigned n
= nir_intrinsic_dest_components(intr
);
1344 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1349 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1350 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1352 switch (intr
->intrinsic
) {
1353 case nir_intrinsic_load_uniform
:
1354 idx
= nir_intrinsic_base(intr
);
1355 if (nir_src_is_const(intr
->src
[0])) {
1356 idx
+= nir_src_as_uint(intr
->src
[0]);
1357 for (int i
= 0; i
< intr
->num_components
; i
++) {
1358 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1359 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1362 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1363 for (int i
= 0; i
< intr
->num_components
; i
++) {
1364 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1365 ir3_get_addr(ctx
, src
[0], 1));
1367 /* NOTE: if relative addressing is used, we set
1368 * constlen in the compiler (to worst-case value)
1369 * since we don't know in the assembler what the max
1370 * addr reg value can be:
1372 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1373 ctx
->so
->shader
->ubo_state
.size
/ 16);
1377 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1378 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1380 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1381 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1383 case nir_intrinsic_load_hs_patch_stride_ir3
:
1384 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1386 case nir_intrinsic_load_patch_vertices_in
:
1387 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1389 case nir_intrinsic_load_tess_param_base_ir3
:
1390 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1391 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1393 case nir_intrinsic_load_tess_factor_base_ir3
:
1394 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1395 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1398 case nir_intrinsic_load_primitive_location_ir3
:
1399 idx
= nir_intrinsic_driver_location(intr
);
1400 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1403 case nir_intrinsic_load_gs_header_ir3
:
1404 dst
[0] = ctx
->gs_header
;
1406 case nir_intrinsic_load_tcs_header_ir3
:
1407 dst
[0] = ctx
->tcs_header
;
1410 case nir_intrinsic_load_primitive_id
:
1411 dst
[0] = ctx
->primitive_id
;
1414 case nir_intrinsic_load_tess_coord
:
1415 if (!ctx
->tess_coord
) {
1417 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1419 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1421 /* Unused, but ir3_put_dst() below wants to free something */
1422 dst
[2] = create_immed(b
, 0);
1425 case nir_intrinsic_end_patch_ir3
:
1426 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1427 struct ir3_instruction
*end
= ir3_ENDPATCH(b
);
1428 array_insert(b
, b
->keeps
, end
);
1430 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1431 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1434 case nir_intrinsic_store_global_ir3
: {
1435 struct ir3_instruction
*value
, *addr
, *offset
;
1437 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1438 ir3_get_src(ctx
, &intr
->src
[1])[0],
1439 ir3_get_src(ctx
, &intr
->src
[1])[1]
1442 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1444 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]),
1445 intr
->num_components
);
1447 struct ir3_instruction
*stg
=
1448 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1449 create_immed(ctx
->block
, intr
->num_components
), 0, offset
, 0);
1450 stg
->cat6
.type
= TYPE_U32
;
1451 stg
->cat6
.iim_val
= 1;
1453 array_insert(b
, b
->keeps
, stg
);
1455 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1456 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1460 case nir_intrinsic_load_global_ir3
: {
1461 struct ir3_instruction
*addr
, *offset
;
1463 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1464 ir3_get_src(ctx
, &intr
->src
[0])[0],
1465 ir3_get_src(ctx
, &intr
->src
[0])[1]
1468 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1470 struct ir3_instruction
*load
=
1471 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, intr
->num_components
),
1473 load
->cat6
.type
= TYPE_U32
;
1474 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1476 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1477 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1479 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
1483 case nir_intrinsic_load_ubo
:
1484 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1486 case nir_intrinsic_load_frag_coord
:
1487 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1489 case nir_intrinsic_load_sample_pos_from_id
: {
1490 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1491 * but that doesn't seem necessary.
1493 struct ir3_instruction
*offset
=
1494 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1495 offset
->regs
[0]->wrmask
= 0x3;
1496 offset
->cat5
.type
= TYPE_F32
;
1498 ir3_split_dest(b
, dst
, offset
, 0, 2);
1502 case nir_intrinsic_load_size_ir3
:
1503 if (!ctx
->ij_size
) {
1505 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SIZE
, 0x1);
1507 dst
[0] = ctx
->ij_size
;
1509 case nir_intrinsic_load_barycentric_centroid
:
1510 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1512 case nir_intrinsic_load_barycentric_sample
:
1513 if (ctx
->so
->key
.msaa
) {
1514 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1516 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1519 case nir_intrinsic_load_barycentric_pixel
:
1520 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1522 case nir_intrinsic_load_interpolated_input
:
1523 idx
= nir_intrinsic_base(intr
);
1524 comp
= nir_intrinsic_component(intr
);
1525 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1526 if (nir_src_is_const(intr
->src
[1])) {
1527 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1528 idx
+= nir_src_as_uint(intr
->src
[1]);
1529 for (int i
= 0; i
< intr
->num_components
; i
++) {
1530 unsigned inloc
= idx
* 4 + i
+ comp
;
1531 if (ctx
->so
->inputs
[idx
].bary
&&
1532 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1533 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1535 /* for non-varyings use the pre-setup input, since
1536 * that is easier than mapping things back to a
1537 * nir_variable to figure out what it is.
1539 dst
[i
] = ctx
->ir
->inputs
[inloc
];
1543 ir3_context_error(ctx
, "unhandled");
1546 case nir_intrinsic_load_input
:
1547 idx
= nir_intrinsic_base(intr
);
1548 comp
= nir_intrinsic_component(intr
);
1549 if (nir_src_is_const(intr
->src
[0])) {
1550 idx
+= nir_src_as_uint(intr
->src
[0]);
1551 for (int i
= 0; i
< intr
->num_components
; i
++) {
1552 unsigned n
= idx
* 4 + i
+ comp
;
1553 dst
[i
] = ctx
->inputs
[n
];
1554 compile_assert(ctx
, ctx
->inputs
[n
]);
1557 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1558 struct ir3_instruction
*collect
=
1559 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1560 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1561 for (int i
= 0; i
< intr
->num_components
; i
++) {
1562 unsigned n
= idx
* 4 + i
+ comp
;
1563 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1568 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1569 * pass and replaced by an ir3-specifc version that adds the
1570 * dword-offset in the last source.
1572 case nir_intrinsic_load_ssbo_ir3
:
1573 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1575 case nir_intrinsic_store_ssbo_ir3
:
1576 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1577 !ctx
->s
->info
.fs
.early_fragment_tests
)
1578 ctx
->so
->no_earlyz
= true;
1579 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1581 case nir_intrinsic_get_buffer_size
:
1582 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1584 case nir_intrinsic_ssbo_atomic_add_ir3
:
1585 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1586 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1587 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1588 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1589 case nir_intrinsic_ssbo_atomic_and_ir3
:
1590 case nir_intrinsic_ssbo_atomic_or_ir3
:
1591 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1592 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1593 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1594 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1595 !ctx
->s
->info
.fs
.early_fragment_tests
)
1596 ctx
->so
->no_earlyz
= true;
1597 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1599 case nir_intrinsic_load_shared
:
1600 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1602 case nir_intrinsic_store_shared
:
1603 emit_intrinsic_store_shared(ctx
, intr
);
1605 case nir_intrinsic_shared_atomic_add
:
1606 case nir_intrinsic_shared_atomic_imin
:
1607 case nir_intrinsic_shared_atomic_umin
:
1608 case nir_intrinsic_shared_atomic_imax
:
1609 case nir_intrinsic_shared_atomic_umax
:
1610 case nir_intrinsic_shared_atomic_and
:
1611 case nir_intrinsic_shared_atomic_or
:
1612 case nir_intrinsic_shared_atomic_xor
:
1613 case nir_intrinsic_shared_atomic_exchange
:
1614 case nir_intrinsic_shared_atomic_comp_swap
:
1615 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1617 case nir_intrinsic_image_deref_load
:
1618 emit_intrinsic_load_image(ctx
, intr
, dst
);
1620 case nir_intrinsic_image_deref_store
:
1621 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1622 !ctx
->s
->info
.fs
.early_fragment_tests
)
1623 ctx
->so
->no_earlyz
= true;
1624 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1626 case nir_intrinsic_image_deref_size
:
1627 emit_intrinsic_image_size(ctx
, intr
, dst
);
1629 case nir_intrinsic_image_deref_atomic_add
:
1630 case nir_intrinsic_image_deref_atomic_imin
:
1631 case nir_intrinsic_image_deref_atomic_umin
:
1632 case nir_intrinsic_image_deref_atomic_imax
:
1633 case nir_intrinsic_image_deref_atomic_umax
:
1634 case nir_intrinsic_image_deref_atomic_and
:
1635 case nir_intrinsic_image_deref_atomic_or
:
1636 case nir_intrinsic_image_deref_atomic_xor
:
1637 case nir_intrinsic_image_deref_atomic_exchange
:
1638 case nir_intrinsic_image_deref_atomic_comp_swap
:
1639 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1640 !ctx
->s
->info
.fs
.early_fragment_tests
)
1641 ctx
->so
->no_earlyz
= true;
1642 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1644 case nir_intrinsic_barrier
:
1645 case nir_intrinsic_memory_barrier
:
1646 case nir_intrinsic_group_memory_barrier
:
1647 case nir_intrinsic_memory_barrier_atomic_counter
:
1648 case nir_intrinsic_memory_barrier_buffer
:
1649 case nir_intrinsic_memory_barrier_image
:
1650 case nir_intrinsic_memory_barrier_shared
:
1651 emit_intrinsic_barrier(ctx
, intr
);
1652 /* note that blk ptr no longer valid, make that obvious: */
1655 case nir_intrinsic_store_output
:
1656 idx
= nir_intrinsic_base(intr
);
1657 comp
= nir_intrinsic_component(intr
);
1658 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1659 idx
+= nir_src_as_uint(intr
->src
[1]);
1661 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1662 for (int i
= 0; i
< intr
->num_components
; i
++) {
1663 unsigned n
= idx
* 4 + i
+ comp
;
1664 ctx
->outputs
[n
] = src
[i
];
1667 case nir_intrinsic_load_base_vertex
:
1668 case nir_intrinsic_load_first_vertex
:
1669 if (!ctx
->basevertex
) {
1670 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1672 dst
[0] = ctx
->basevertex
;
1674 case nir_intrinsic_load_vertex_id_zero_base
:
1675 case nir_intrinsic_load_vertex_id
:
1676 if (!ctx
->vertex_id
) {
1677 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1678 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1679 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1681 dst
[0] = ctx
->vertex_id
;
1683 case nir_intrinsic_load_instance_id
:
1684 if (!ctx
->instance_id
) {
1685 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1687 dst
[0] = ctx
->instance_id
;
1689 case nir_intrinsic_load_sample_id
:
1690 ctx
->so
->per_samp
= true;
1692 case nir_intrinsic_load_sample_id_no_per_sample
:
1693 if (!ctx
->samp_id
) {
1694 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1695 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1697 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1699 case nir_intrinsic_load_sample_mask_in
:
1700 if (!ctx
->samp_mask_in
) {
1701 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1703 dst
[0] = ctx
->samp_mask_in
;
1705 case nir_intrinsic_load_user_clip_plane
:
1706 idx
= nir_intrinsic_ucp_id(intr
);
1707 for (int i
= 0; i
< intr
->num_components
; i
++) {
1708 unsigned n
= idx
* 4 + i
;
1709 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1712 case nir_intrinsic_load_front_face
:
1713 if (!ctx
->frag_face
) {
1714 ctx
->so
->frag_face
= true;
1715 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1716 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1718 /* for fragface, we get -1 for back and 0 for front. However this is
1719 * the inverse of what nir expects (where ~0 is true).
1721 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1722 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1724 case nir_intrinsic_load_local_invocation_id
:
1725 if (!ctx
->local_invocation_id
) {
1726 ctx
->local_invocation_id
=
1727 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1729 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1731 case nir_intrinsic_load_work_group_id
:
1732 if (!ctx
->work_group_id
) {
1733 ctx
->work_group_id
=
1734 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1735 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1737 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1739 case nir_intrinsic_load_num_work_groups
:
1740 for (int i
= 0; i
< intr
->num_components
; i
++) {
1741 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1744 case nir_intrinsic_load_local_group_size
:
1745 for (int i
= 0; i
< intr
->num_components
; i
++) {
1746 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1749 case nir_intrinsic_discard_if
:
1750 case nir_intrinsic_discard
: {
1751 struct ir3_instruction
*cond
, *kill
;
1753 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1754 /* conditional discard: */
1755 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1756 cond
= ir3_b2n(b
, src
[0]);
1758 /* unconditional discard: */
1759 cond
= create_immed(b
, 1);
1762 /* NOTE: only cmps.*.* can write p0.x: */
1763 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1764 cond
->cat2
.condition
= IR3_COND_NE
;
1766 /* condition always goes in predicate register: */
1767 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1768 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1770 kill
= ir3_KILL(b
, cond
, 0);
1771 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1773 array_insert(b
, b
->keeps
, kill
);
1774 ctx
->so
->no_earlyz
= true;
1779 case nir_intrinsic_cond_end_ir3
: {
1780 struct ir3_instruction
*cond
, *kill
;
1782 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1783 cond
= ir3_b2n(b
, src
[0]);
1785 /* NOTE: only cmps.*.* can write p0.x: */
1786 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1787 cond
->cat2
.condition
= IR3_COND_NE
;
1789 /* condition always goes in predicate register: */
1790 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1792 kill
= ir3_CONDEND(b
, cond
, 0);
1794 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1795 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1797 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1798 array_insert(b
, b
->keeps
, kill
);
1802 case nir_intrinsic_load_shared_ir3
:
1803 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1805 case nir_intrinsic_store_shared_ir3
:
1806 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1809 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1810 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1815 ir3_put_dst(ctx
, &intr
->dest
);
1819 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1821 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1822 instr
->def
.num_components
);
1824 if (instr
->def
.bit_size
< 32) {
1825 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1826 dst
[i
] = create_immed_typed(ctx
->block
,
1827 instr
->value
[i
].u16
,
1830 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1831 dst
[i
] = create_immed_typed(ctx
->block
,
1832 instr
->value
[i
].u32
,
1839 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1841 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1842 undef
->def
.num_components
);
1843 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1845 /* backend doesn't want undefined instructions, so just plug
1848 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1849 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1853 * texture fetch/sample instructions:
1857 get_tex_dest_type(nir_tex_instr
*tex
)
1861 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
1862 case nir_type_invalid
:
1863 case nir_type_float
:
1864 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_F16
: TYPE_F32
;
1867 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_S16
: TYPE_S32
;
1871 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_U16
: TYPE_U32
;
1874 unreachable("bad dest_type");
1881 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1883 unsigned coords
, flags
= 0;
1885 /* note: would use tex->coord_components.. except txs.. also,
1886 * since array index goes after shadow ref, we don't want to
1889 switch (tex
->sampler_dim
) {
1890 case GLSL_SAMPLER_DIM_1D
:
1891 case GLSL_SAMPLER_DIM_BUF
:
1894 case GLSL_SAMPLER_DIM_2D
:
1895 case GLSL_SAMPLER_DIM_RECT
:
1896 case GLSL_SAMPLER_DIM_EXTERNAL
:
1897 case GLSL_SAMPLER_DIM_MS
:
1900 case GLSL_SAMPLER_DIM_3D
:
1901 case GLSL_SAMPLER_DIM_CUBE
:
1903 flags
|= IR3_INSTR_3D
;
1906 unreachable("bad sampler_dim");
1909 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1910 flags
|= IR3_INSTR_S
;
1912 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1913 flags
|= IR3_INSTR_A
;
1919 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1920 * or immediate (in which case it will get lowered later to a non .s2en
1921 * version of the tex instruction which encode tex/samp as immediates:
1923 static struct ir3_instruction
*
1924 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1926 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
1927 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
1928 struct ir3_instruction
*texture
, *sampler
;
1930 if (texture_idx
>= 0) {
1931 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
1932 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
1934 /* TODO what to do for dynamic case? I guess we only need the
1935 * max index for astc srgb workaround so maybe not a problem
1936 * to worry about if we don't enable indirect samplers for
1939 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
1940 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
1943 if (sampler_idx
>= 0) {
1944 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
1945 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
1947 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
1950 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1957 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1959 struct ir3_block
*b
= ctx
->block
;
1960 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1961 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1962 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1963 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1964 unsigned i
, coords
, flags
, ncomp
;
1965 unsigned nsrc0
= 0, nsrc1
= 0;
1969 ncomp
= nir_dest_num_components(tex
->dest
);
1971 coord
= off
= ddx
= ddy
= NULL
;
1972 lod
= proj
= compare
= sample_index
= NULL
;
1974 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1976 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1977 switch (tex
->src
[i
].src_type
) {
1978 case nir_tex_src_coord
:
1979 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1981 case nir_tex_src_bias
:
1982 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1985 case nir_tex_src_lod
:
1986 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1989 case nir_tex_src_comparator
: /* shadow comparator */
1990 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1992 case nir_tex_src_projector
:
1993 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1996 case nir_tex_src_offset
:
1997 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2000 case nir_tex_src_ddx
:
2001 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2003 case nir_tex_src_ddy
:
2004 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2006 case nir_tex_src_ms_index
:
2007 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2009 case nir_tex_src_texture_offset
:
2010 case nir_tex_src_sampler_offset
:
2011 /* handled in get_tex_samp_src() */
2014 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2015 tex
->src
[i
].src_type
);
2021 case nir_texop_tex_prefetch
:
2022 compile_assert(ctx
, !has_bias
);
2023 compile_assert(ctx
, !has_lod
);
2024 compile_assert(ctx
, !compare
);
2025 compile_assert(ctx
, !has_proj
);
2026 compile_assert(ctx
, !has_off
);
2027 compile_assert(ctx
, !ddx
);
2028 compile_assert(ctx
, !ddy
);
2029 compile_assert(ctx
, !sample_index
);
2030 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2031 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2033 if (ctx
->so
->num_sampler_prefetch
< IR3_MAX_SAMPLER_PREFETCH
) {
2034 opc
= OPC_META_TEX_PREFETCH
;
2035 ctx
->so
->num_sampler_prefetch
++;
2039 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2040 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2041 case nir_texop_txl
: opc
= OPC_SAML
; break;
2042 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2043 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2044 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2046 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2047 * what blob does, seems gather is broken?), and a3xx did
2048 * not support it (but probably could also emulate).
2050 switch (tex
->component
) {
2051 case 0: opc
= OPC_GATHER4R
; break;
2052 case 1: opc
= OPC_GATHER4G
; break;
2053 case 2: opc
= OPC_GATHER4B
; break;
2054 case 3: opc
= OPC_GATHER4A
; break;
2057 case nir_texop_txf_ms_fb
:
2058 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2060 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2064 tex_info(tex
, &flags
, &coords
);
2067 * lay out the first argument in the proper order:
2068 * - actual coordinates first
2069 * - shadow reference
2072 * - starting at offset 4, dpdx.xy, dpdy.xy
2074 * bias/lod go into the second arg
2077 /* insert tex coords: */
2078 for (i
= 0; i
< coords
; i
++)
2083 /* scale up integer coords for TXF based on the LOD */
2084 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2086 for (i
= 0; i
< coords
; i
++)
2087 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2091 /* hw doesn't do 1d, so we treat it as 2d with
2092 * height of 1, and patch up the y coord.
2095 src0
[nsrc0
++] = create_immed(b
, 0);
2097 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2101 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2102 src0
[nsrc0
++] = compare
;
2104 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2105 struct ir3_instruction
*idx
= coord
[coords
];
2107 /* the array coord for cube arrays needs 0.5 added to it */
2108 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2109 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2111 src0
[nsrc0
++] = idx
;
2115 src0
[nsrc0
++] = proj
;
2116 flags
|= IR3_INSTR_P
;
2119 /* pad to 4, then ddx/ddy: */
2120 if (tex
->op
== nir_texop_txd
) {
2122 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2123 for (i
= 0; i
< coords
; i
++)
2124 src0
[nsrc0
++] = ddx
[i
];
2126 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2127 for (i
= 0; i
< coords
; i
++)
2128 src0
[nsrc0
++] = ddy
[i
];
2130 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2133 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2134 * with scaled x coord according to requested sample:
2136 if (opc
== OPC_ISAMM
) {
2137 if (ctx
->compiler
->txf_ms_with_isaml
) {
2138 /* the samples are laid out in x dimension as
2140 * x_ms = (x << ms) + sample_index;
2142 struct ir3_instruction
*ms
;
2143 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2145 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2146 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2150 src0
[nsrc0
++] = sample_index
;
2155 * second argument (if applicable):
2160 if (has_off
| has_lod
| has_bias
) {
2162 unsigned off_coords
= coords
;
2163 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2165 for (i
= 0; i
< off_coords
; i
++)
2166 src1
[nsrc1
++] = off
[i
];
2168 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2169 flags
|= IR3_INSTR_O
;
2172 if (has_lod
| has_bias
)
2173 src1
[nsrc1
++] = lod
;
2176 type
= get_tex_dest_type(tex
);
2178 if (opc
== OPC_GETLOD
)
2181 struct ir3_instruction
*samp_tex
;
2183 if (tex
->op
== nir_texop_txf_ms_fb
) {
2184 /* only expect a single txf_ms_fb per shader: */
2185 compile_assert(ctx
, !ctx
->so
->fb_read
);
2186 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2188 ctx
->so
->fb_read
= true;
2189 samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2190 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2191 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2194 ctx
->so
->num_samp
++;
2196 samp_tex
= get_tex_samp_tex_src(ctx
, tex
);
2199 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2200 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2202 if (opc
== OPC_META_TEX_PREFETCH
) {
2203 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2205 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2207 sam
= ir3_META_TEX_PREFETCH(b
);
2208 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2209 sam
->prefetch
.input_offset
=
2210 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2211 sam
->prefetch
.tex
= tex
->texture_index
;
2212 sam
->prefetch
.samp
= tex
->sampler_index
;
2214 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
2215 samp_tex
, col0
, col1
);
2218 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2219 assert(opc
!= OPC_META_TEX_PREFETCH
);
2221 /* only need first 3 components: */
2222 sam
->regs
[0]->wrmask
= 0x7;
2223 ir3_split_dest(b
, dst
, sam
, 0, 3);
2225 /* we need to sample the alpha separately with a non-ASTC
2228 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
2229 samp_tex
, col0
, col1
);
2231 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2233 /* fixup .w component: */
2234 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2236 /* normal (non-workaround) case: */
2237 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2240 /* GETLOD returns results in 4.8 fixed point */
2241 if (opc
== OPC_GETLOD
) {
2242 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2244 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2245 for (i
= 0; i
< 2; i
++) {
2246 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2251 ir3_put_dst(ctx
, &tex
->dest
);
2255 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2257 struct ir3_block
*b
= ctx
->block
;
2258 struct ir3_instruction
**dst
, *sam
;
2259 type_t dst_type
= get_tex_dest_type(tex
);
2261 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2263 sam
= ir3_SAM(b
, OPC_GETINFO
, dst_type
, 1 << idx
, 0,
2264 get_tex_samp_tex_src(ctx
, tex
), NULL
, NULL
);
2266 /* even though there is only one component, since it ends
2267 * up in .y/.z/.w rather than .x, we need a split_dest()
2270 ir3_split_dest(b
, dst
, sam
, 0, idx
+ 1);
2272 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2273 * the value in TEX_CONST_0 is zero-based.
2275 if (ctx
->compiler
->levels_add_one
)
2276 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2278 ir3_put_dst(ctx
, &tex
->dest
);
2282 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2284 struct ir3_block
*b
= ctx
->block
;
2285 struct ir3_instruction
**dst
, *sam
;
2286 struct ir3_instruction
*lod
;
2287 unsigned flags
, coords
;
2288 type_t dst_type
= get_tex_dest_type(tex
);
2290 tex_info(tex
, &flags
, &coords
);
2292 /* Actually we want the number of dimensions, not coordinates. This
2293 * distinction only matters for cubes.
2295 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2298 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2300 compile_assert(ctx
, tex
->num_srcs
== 1);
2301 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2303 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2305 sam
= ir3_SAM(b
, OPC_GETSIZE
, dst_type
, 0b1111, flags
,
2306 get_tex_samp_tex_src(ctx
, tex
), lod
, NULL
);
2308 ir3_split_dest(b
, dst
, sam
, 0, 4);
2310 /* Array size actually ends up in .w rather than .z. This doesn't
2311 * matter for miplevel 0, but for higher mips the value in z is
2312 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2313 * returned, which means that we have to add 1 to it for arrays.
2315 if (tex
->is_array
) {
2316 if (ctx
->compiler
->levels_add_one
) {
2317 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2319 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2323 ir3_put_dst(ctx
, &tex
->dest
);
2327 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2329 switch (jump
->type
) {
2330 case nir_jump_break
:
2331 case nir_jump_continue
:
2332 case nir_jump_return
:
2333 /* I *think* we can simply just ignore this, and use the
2334 * successor block link to figure out where we need to
2335 * jump to for break/continue
2339 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2345 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2347 switch (instr
->type
) {
2348 case nir_instr_type_alu
:
2349 emit_alu(ctx
, nir_instr_as_alu(instr
));
2351 case nir_instr_type_deref
:
2352 /* ignored, handled as part of the intrinsic they are src to */
2354 case nir_instr_type_intrinsic
:
2355 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2357 case nir_instr_type_load_const
:
2358 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2360 case nir_instr_type_ssa_undef
:
2361 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2363 case nir_instr_type_tex
: {
2364 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2365 /* couple tex instructions get special-cased:
2369 emit_tex_txs(ctx
, tex
);
2371 case nir_texop_query_levels
:
2372 emit_tex_info(ctx
, tex
, 2);
2374 case nir_texop_texture_samples
:
2375 emit_tex_info(ctx
, tex
, 3);
2383 case nir_instr_type_jump
:
2384 emit_jump(ctx
, nir_instr_as_jump(instr
));
2386 case nir_instr_type_phi
:
2387 /* we have converted phi webs to regs in NIR by now */
2388 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2390 case nir_instr_type_call
:
2391 case nir_instr_type_parallel_copy
:
2392 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2397 static struct ir3_block
*
2398 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2400 struct ir3_block
*block
;
2401 struct hash_entry
*hentry
;
2403 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2405 return hentry
->data
;
2407 block
= ir3_block_create(ctx
->ir
);
2408 block
->nblock
= nblock
;
2409 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2411 block
->predecessors
= _mesa_pointer_set_create(block
);
2412 set_foreach(nblock
->predecessors
, sentry
) {
2413 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2420 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2422 struct ir3_block
*block
= get_block(ctx
, nblock
);
2424 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2425 if (nblock
->successors
[i
]) {
2426 block
->successors
[i
] =
2427 get_block(ctx
, nblock
->successors
[i
]);
2432 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2434 /* re-emit addr register in each block if needed: */
2435 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2436 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2437 ctx
->addr_ht
[i
] = NULL
;
2440 nir_foreach_instr(instr
, nblock
) {
2441 ctx
->cur_instr
= instr
;
2442 emit_instr(ctx
, instr
);
2443 ctx
->cur_instr
= NULL
;
2449 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2452 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2454 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2456 ctx
->block
->condition
=
2457 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2459 emit_cf_list(ctx
, &nif
->then_list
);
2460 emit_cf_list(ctx
, &nif
->else_list
);
2464 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2466 emit_cf_list(ctx
, &nloop
->body
);
2471 stack_push(struct ir3_context
*ctx
)
2474 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2478 stack_pop(struct ir3_context
*ctx
)
2480 compile_assert(ctx
, ctx
->stack
> 0);
2485 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2487 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2488 switch (node
->type
) {
2489 case nir_cf_node_block
:
2490 emit_block(ctx
, nir_cf_node_as_block(node
));
2492 case nir_cf_node_if
:
2494 emit_if(ctx
, nir_cf_node_as_if(node
));
2497 case nir_cf_node_loop
:
2499 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2502 case nir_cf_node_function
:
2503 ir3_context_error(ctx
, "TODO\n");
2509 /* emit stream-out code. At this point, the current block is the original
2510 * (nir) end block, and nir ensures that all flow control paths terminate
2511 * into the end block. We re-purpose the original end block to generate
2512 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2513 * block holding stream-out write instructions, followed by the new end
2517 * p0.x = (vtxcnt < maxvtxcnt)
2518 * // succs: blockStreamOut, blockNewEnd
2521 * ... stream-out instructions ...
2522 * // succs: blockNewEnd
2528 emit_stream_out(struct ir3_context
*ctx
)
2530 struct ir3
*ir
= ctx
->ir
;
2531 struct ir3_stream_output_info
*strmout
=
2532 &ctx
->so
->shader
->stream_output
;
2533 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2534 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2535 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2537 /* create vtxcnt input in input block at top of shader,
2538 * so that it is seen as live over the entire duration
2541 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2542 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2544 /* at this point, we are at the original 'end' block,
2545 * re-purpose this block to stream-out condition, then
2546 * append stream-out block and new-end block
2548 orig_end_block
= ctx
->block
;
2550 // TODO these blocks need to update predecessors..
2551 // maybe w/ store_global intrinsic, we could do this
2552 // stuff in nir->nir pass
2554 stream_out_block
= ir3_block_create(ir
);
2555 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2557 new_end_block
= ir3_block_create(ir
);
2558 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2560 orig_end_block
->successors
[0] = stream_out_block
;
2561 orig_end_block
->successors
[1] = new_end_block
;
2562 stream_out_block
->successors
[0] = new_end_block
;
2564 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2565 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2566 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2567 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2568 cond
->cat2
.condition
= IR3_COND_LT
;
2570 /* condition goes on previous block to the conditional,
2571 * since it is used to pick which of the two successor
2574 orig_end_block
->condition
= cond
;
2576 /* switch to stream_out_block to generate the stream-out
2579 ctx
->block
= stream_out_block
;
2581 /* Calculate base addresses based on vtxcnt. Instructions
2582 * generated for bases not used in following loop will be
2583 * stripped out in the backend.
2585 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2586 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2587 unsigned stride
= strmout
->stride
[i
];
2588 struct ir3_instruction
*base
, *off
;
2590 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2592 /* 24-bit should be enough: */
2593 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2594 create_immed(ctx
->block
, stride
* 4), 0);
2596 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2599 /* Generate the per-output store instructions: */
2600 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2601 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2602 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2603 struct ir3_instruction
*base
, *out
, *stg
;
2605 base
= bases
[strmout
->output
[i
].output_buffer
];
2606 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2608 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2609 create_immed(ctx
->block
, 1), 0);
2610 stg
->cat6
.type
= TYPE_U32
;
2611 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2613 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2617 /* and finally switch to the new_end_block: */
2618 ctx
->block
= new_end_block
;
2622 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2624 nir_metadata_require(impl
, nir_metadata_block_index
);
2626 compile_assert(ctx
, ctx
->stack
== 0);
2628 emit_cf_list(ctx
, &impl
->body
);
2629 emit_block(ctx
, impl
->end_block
);
2631 compile_assert(ctx
, ctx
->stack
== 0);
2633 /* at this point, we should have a single empty block,
2634 * into which we emit the 'end' instruction.
2636 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2638 /* If stream-out (aka transform-feedback) enabled, emit the
2639 * stream-out instructions, followed by a new empty block (into
2640 * which the 'end' instruction lands).
2642 * NOTE: it is done in this order, rather than inserting before
2643 * we emit end_block, because NIR guarantees that all blocks
2644 * flow into end_block, and that end_block has no successors.
2645 * So by re-purposing end_block as the first block of stream-
2646 * out, we guarantee that all exit paths flow into the stream-
2649 if ((ctx
->compiler
->gpu_id
< 500) &&
2650 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2651 !ctx
->so
->binning_pass
) {
2652 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2653 emit_stream_out(ctx
);
2656 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2657 * NOP and has an epilogue that writes the VS outputs to local storage, to
2658 * be read by the HS. Then it resets execution mask (chmask) and chains
2659 * to the next shader (chsh).
2661 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2662 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2663 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2664 struct ir3_instruction
*chmask
=
2665 ir3_CHMASK(ctx
->block
);
2666 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2667 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2669 struct ir3_instruction
*chsh
=
2670 ir3_CHSH(ctx
->block
);
2671 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2672 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2674 ir3_END(ctx
->block
);
2679 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2681 struct ir3_shader_variant
*so
= ctx
->so
;
2682 unsigned ncomp
= glsl_get_components(in
->type
);
2683 unsigned n
= in
->data
.driver_location
;
2684 unsigned frac
= in
->data
.location_frac
;
2685 unsigned slot
= in
->data
.location
;
2687 /* Inputs are loaded using ldlw or ldg for these stages. */
2688 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2689 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2690 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2693 /* skip unread inputs, we could end up with (for example), unsplit
2694 * matrix/etc inputs in the case they are not read, so just silently
2700 so
->inputs
[n
].slot
= slot
;
2701 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2702 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2703 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2705 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2707 /* if any varyings have 'sample' qualifer, that triggers us
2708 * to run in per-sample mode:
2710 so
->per_samp
|= in
->data
.sample
;
2712 for (int i
= 0; i
< ncomp
; i
++) {
2713 struct ir3_instruction
*instr
= NULL
;
2714 unsigned idx
= (n
* 4) + i
+ frac
;
2716 if (slot
== VARYING_SLOT_POS
) {
2717 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2718 } else if (slot
== VARYING_SLOT_PNTC
) {
2719 /* see for example st_nir_fixup_varying_slots().. this is
2720 * maybe a bit mesa/st specific. But we need things to line
2721 * up for this in fdN_program:
2722 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2723 * if (emit->sprite_coord_enable & texmask) {
2727 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2728 so
->inputs
[n
].bary
= true;
2729 instr
= create_frag_input(ctx
, false, idx
);
2731 /* detect the special case for front/back colors where
2732 * we need to do flat vs smooth shading depending on
2735 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2737 case VARYING_SLOT_COL0
:
2738 case VARYING_SLOT_COL1
:
2739 case VARYING_SLOT_BFC0
:
2740 case VARYING_SLOT_BFC1
:
2741 so
->inputs
[n
].rasterflat
= true;
2748 if (ctx
->compiler
->flat_bypass
) {
2749 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2750 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2751 so
->inputs
[n
].use_ldlv
= true;
2754 so
->inputs
[n
].bary
= true;
2756 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2759 compile_assert(ctx
, idx
< ctx
->ninputs
);
2761 ctx
->inputs
[idx
] = instr
;
2763 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2764 /* We shouldn't have fractional input for VS input.. that only shows
2765 * up with varying packing
2769 struct ir3_instruction
*input
= create_input(ctx
, (1 << ncomp
) - 1);
2770 struct ir3_instruction
*components
[ncomp
];
2772 input
->input
.inidx
= n
;
2774 ir3_split_dest(ctx
->block
, components
, input
, 0, ncomp
);
2776 for (int i
= 0; i
< ncomp
; i
++) {
2777 unsigned idx
= (n
* 4) + i
+ frac
;
2778 compile_assert(ctx
, idx
< ctx
->ninputs
);
2779 ctx
->inputs
[idx
] = components
[i
];
2782 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2785 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2786 so
->total_in
+= ncomp
;
2790 /* Initially we assign non-packed inloc's for varyings, as we don't really
2791 * know up-front which components will be unused. After all the compilation
2792 * stages we scan the shader to see which components are actually used, and
2793 * re-pack the inlocs to eliminate unneeded varyings.
2796 pack_inlocs(struct ir3_context
*ctx
)
2798 struct ir3_shader_variant
*so
= ctx
->so
;
2799 uint8_t used_components
[so
->inputs_count
];
2801 memset(used_components
, 0, sizeof(used_components
));
2804 * First Step: scan shader to find which bary.f/ldlv remain:
2807 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2808 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2809 if (is_input(instr
)) {
2810 unsigned inloc
= instr
->regs
[1]->iim_val
;
2811 unsigned i
= inloc
/ 4;
2812 unsigned j
= inloc
% 4;
2814 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
2815 compile_assert(ctx
, i
< so
->inputs_count
);
2817 used_components
[i
] |= 1 << j
;
2818 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
2819 for (int n
= 0; n
< 2; n
++) {
2820 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
2821 unsigned i
= inloc
/ 4;
2822 unsigned j
= inloc
% 4;
2824 compile_assert(ctx
, i
< so
->inputs_count
);
2826 used_components
[i
] |= 1 << j
;
2833 * Second Step: reassign varying inloc/slots:
2836 unsigned actual_in
= 0;
2839 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
2840 unsigned compmask
= 0, maxcomp
= 0;
2842 so
->inputs
[i
].inloc
= inloc
;
2843 so
->inputs
[i
].bary
= false;
2845 for (unsigned j
= 0; j
< 4; j
++) {
2846 if (!(used_components
[i
] & (1 << j
)))
2849 compmask
|= (1 << j
);
2853 /* at this point, since used_components[i] mask is only
2854 * considering varyings (ie. not sysvals) we know this
2857 so
->inputs
[i
].bary
= true;
2860 if (so
->inputs
[i
].bary
) {
2862 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2868 * Third Step: reassign packed inloc's:
2871 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2872 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2873 if (is_input(instr
)) {
2874 unsigned inloc
= instr
->regs
[1]->iim_val
;
2875 unsigned i
= inloc
/ 4;
2876 unsigned j
= inloc
% 4;
2878 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
2885 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2887 struct ir3_shader_variant
*so
= ctx
->so
;
2888 unsigned ncomp
= glsl_get_components(out
->type
);
2889 unsigned n
= out
->data
.driver_location
;
2890 unsigned frac
= out
->data
.location_frac
;
2891 unsigned slot
= out
->data
.location
;
2894 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2896 case FRAG_RESULT_DEPTH
:
2897 comp
= 2; /* tgsi will write to .z component */
2898 so
->writes_pos
= true;
2900 case FRAG_RESULT_COLOR
:
2903 case FRAG_RESULT_SAMPLE_MASK
:
2904 so
->writes_smask
= true;
2907 if (slot
>= FRAG_RESULT_DATA0
)
2909 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2910 gl_frag_result_name(slot
));
2912 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
2913 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2914 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
2916 case VARYING_SLOT_POS
:
2917 so
->writes_pos
= true;
2919 case VARYING_SLOT_PSIZ
:
2920 so
->writes_psize
= true;
2922 case VARYING_SLOT_PRIMITIVE_ID
:
2923 case VARYING_SLOT_LAYER
:
2924 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
2925 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
2927 case VARYING_SLOT_COL0
:
2928 case VARYING_SLOT_COL1
:
2929 case VARYING_SLOT_BFC0
:
2930 case VARYING_SLOT_BFC1
:
2931 case VARYING_SLOT_FOGC
:
2932 case VARYING_SLOT_CLIP_DIST0
:
2933 case VARYING_SLOT_CLIP_DIST1
:
2934 case VARYING_SLOT_CLIP_VERTEX
:
2937 if (slot
>= VARYING_SLOT_VAR0
)
2939 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2941 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
2942 _mesa_shader_stage_to_string(ctx
->so
->type
),
2943 gl_varying_slot_name(slot
));
2945 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
2946 /* output lowered to buffer writes. */
2949 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2952 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2954 so
->outputs
[n
].slot
= slot
;
2955 so
->outputs
[n
].regid
= regid(n
, comp
);
2956 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2958 for (int i
= 0; i
< ncomp
; i
++) {
2959 unsigned idx
= (n
* 4) + i
+ frac
;
2960 compile_assert(ctx
, idx
< ctx
->noutputs
);
2961 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2964 /* if varying packing doesn't happen, we could end up in a situation
2965 * with "holes" in the output, and since the per-generation code that
2966 * sets up varying linkage registers doesn't expect to have more than
2967 * one varying per vec4 slot, pad the holes.
2969 * Note that this should probably generate a performance warning of
2972 for (int i
= 0; i
< frac
; i
++) {
2973 unsigned idx
= (n
* 4) + i
;
2974 if (!ctx
->outputs
[idx
]) {
2975 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2981 max_drvloc(struct exec_list
*vars
)
2984 nir_foreach_variable(var
, vars
) {
2985 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2991 emit_instructions(struct ir3_context
*ctx
)
2993 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2995 ctx
->ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2996 ctx
->noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2998 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
2999 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3001 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3003 /* Create inputs in first block: */
3004 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3005 ctx
->in_block
= ctx
->block
;
3006 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3008 /* for fragment shader, the vcoord input register is used as the
3009 * base for bary.f varying fetch instrs:
3011 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3012 * until emit_intrinsic when we know they are actually needed.
3013 * For now, we defer creating ctx->ij_centroid, etc, since we
3014 * only need ij_pixel for "old style" varying inputs (ie.
3017 struct ir3_instruction
*vcoord
= NULL
;
3018 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3019 struct ir3_instruction
*xy
[2];
3021 vcoord
= create_input(ctx
, 0x3);
3022 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
3024 ctx
->ij_pixel
= ir3_create_collect(ctx
, xy
, 2);
3028 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3029 setup_input(ctx
, var
);
3032 /* Defer add_sysval_input() stuff until after setup_inputs(),
3033 * because sysvals need to be appended after varyings:
3036 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
,
3041 /* Tesselation shaders always need primitive ID for indexing the
3042 * BO. Geometry shaders don't always need it but when they do it has be
3043 * delivered and unclobbered in the VS. To make things easy, we always
3044 * make room for it in VS/DS.
3046 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3047 bool has_gs
= ctx
->so
->key
.has_gs
;
3048 switch (ctx
->so
->type
) {
3049 case MESA_SHADER_VERTEX
:
3051 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3052 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3053 } else if (has_gs
) {
3054 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3055 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3058 case MESA_SHADER_TESS_CTRL
:
3059 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3060 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3062 case MESA_SHADER_TESS_EVAL
:
3064 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3065 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3067 case MESA_SHADER_GEOMETRY
:
3068 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3069 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3075 /* Setup outputs: */
3076 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3077 setup_output(ctx
, var
);
3080 /* Find # of samplers: */
3081 nir_foreach_variable(var
, &ctx
->s
->uniforms
) {
3082 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
3083 /* just assume that we'll be reading from images.. if it
3084 * is write-only we don't have to count it, but not sure
3085 * if there is a good way to know?
3087 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
3090 /* NOTE: need to do something more clever when we support >1 fxn */
3091 nir_foreach_register(reg
, &fxn
->registers
) {
3092 ir3_declare_array(ctx
, reg
);
3094 /* And emit the body: */
3096 emit_function(ctx
, fxn
);
3099 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3100 * need to assign the tex state indexes for these after we know the
3104 fixup_astc_srgb(struct ir3_context
*ctx
)
3106 struct ir3_shader_variant
*so
= ctx
->so
;
3107 /* indexed by original tex idx, value is newly assigned alpha sampler
3108 * state tex idx. Zero is invalid since there is at least one sampler
3111 unsigned alt_tex_state
[16] = {0};
3112 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3115 so
->astc_srgb
.base
= tex_idx
;
3117 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3118 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3120 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3122 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3123 /* assign new alternate/alpha tex state slot: */
3124 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3125 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3126 so
->astc_srgb
.count
++;
3129 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3134 fixup_binning_pass(struct ir3_context
*ctx
)
3136 struct ir3_shader_variant
*so
= ctx
->so
;
3137 struct ir3
*ir
= ctx
->ir
;
3140 /* first pass, remove unused outputs from the IR level outputs: */
3141 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3142 struct ir3_instruction
*out
= ir
->outputs
[i
];
3143 assert(out
->opc
== OPC_META_COLLECT
);
3144 unsigned outidx
= out
->collect
.outidx
;
3145 unsigned slot
= so
->outputs
[outidx
].slot
;
3147 /* throw away everything but first position/psize */
3148 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3149 ir
->outputs
[j
] = ir
->outputs
[i
];
3153 ir
->outputs_count
= j
;
3155 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3158 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3159 unsigned slot
= so
->outputs
[i
].slot
;
3161 /* throw away everything but first position/psize */
3162 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3163 so
->outputs
[j
] = so
->outputs
[i
];
3165 /* fixup outidx to point to new output table entry: */
3166 struct ir3_instruction
*out
;
3167 foreach_output(out
, ir
) {
3168 if (out
->collect
.outidx
== i
) {
3169 out
->collect
.outidx
= j
;
3177 so
->outputs_count
= j
;
3181 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3185 /* Collect sampling instructions eligible for pre-dispatch. */
3186 list_for_each_entry(struct ir3_block
, block
, &ir
->block_list
, node
) {
3187 list_for_each_entry_safe(struct ir3_instruction
, instr
,
3188 &block
->instr_list
, node
) {
3189 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3190 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3191 struct ir3_sampler_prefetch
*fetch
=
3192 &ctx
->so
->sampler_prefetch
[idx
];
3195 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3196 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3197 fetch
->tex_id
= instr
->prefetch
.tex
;
3198 fetch
->samp_id
= instr
->prefetch
.samp
;
3199 fetch
->dst
= instr
->regs
[0]->num
;
3200 fetch
->src
= instr
->prefetch
.input_offset
;
3203 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3205 /* Disable half precision until supported. */
3206 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3208 /* Remove the prefetch placeholder instruction: */
3209 list_delinit(&instr
->node
);
3216 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3217 struct ir3_shader_variant
*so
)
3219 struct ir3_context
*ctx
;
3221 int ret
= 0, max_bary
;
3225 ctx
= ir3_context_init(compiler
, so
);
3227 DBG("INIT failed!");
3232 emit_instructions(ctx
);
3235 DBG("EMIT failed!");
3240 ir
= so
->ir
= ctx
->ir
;
3242 assert((ctx
->noutputs
% 4) == 0);
3244 /* Setup IR level outputs, which are "collects" that gather
3245 * the scalar components of outputs.
3247 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3249 /* figure out the # of components written:
3251 * TODO do we need to handle holes, ie. if .x and .z
3252 * components written, but .y component not written?
3254 for (unsigned j
= 0; j
< 4; j
++) {
3255 if (!ctx
->outputs
[i
+ j
])
3260 /* Note that in some stages, like TCS, store_output is
3261 * lowered to memory writes, so no components of the
3262 * are "written" from the PoV of traditional store-
3263 * output instructions:
3268 struct ir3_instruction
*out
=
3269 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3272 assert(outidx
< so
->outputs_count
);
3274 /* stash index into so->outputs[] so we can map the
3275 * output back to slot/etc later:
3277 out
->collect
.outidx
= outidx
;
3279 array_insert(ir
, ir
->outputs
, out
);
3282 /* Set up the gs header as an output for the vertex shader so it won't
3283 * clobber it for the tess ctrl shader.
3285 * TODO this could probably be done more cleanly in a nir pass.
3287 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3288 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3289 if (ctx
->primitive_id
) {
3290 unsigned n
= so
->outputs_count
++;
3291 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3293 struct ir3_instruction
*out
=
3294 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3295 out
->collect
.outidx
= n
;
3296 array_insert(ir
, ir
->outputs
, out
);
3299 if (ctx
->gs_header
) {
3300 unsigned n
= so
->outputs_count
++;
3301 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3302 struct ir3_instruction
*out
=
3303 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3304 out
->collect
.outidx
= n
;
3305 array_insert(ir
, ir
->outputs
, out
);
3308 if (ctx
->tcs_header
) {
3309 unsigned n
= so
->outputs_count
++;
3310 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3311 struct ir3_instruction
*out
=
3312 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3313 out
->collect
.outidx
= n
;
3314 array_insert(ir
, ir
->outputs
, out
);
3318 /* at this point, for binning pass, throw away unneeded outputs: */
3319 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3320 fixup_binning_pass(ctx
);
3322 ir3_debug_print(ir
, "BEFORE CP");
3326 /* at this point, for binning pass, throw away unneeded outputs:
3327 * Note that for a6xx and later, we do this after ir3_cp to ensure
3328 * that the uniform/constant layout for BS and VS matches, so that
3329 * we can re-use same VS_CONST state group.
3331 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3332 fixup_binning_pass(ctx
);
3334 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3335 * need to make sure not to remove any inputs that are used by
3336 * the nonbinning VS.
3338 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3339 so
->type
== MESA_SHADER_VERTEX
) {
3340 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3341 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3349 debug_assert(n
< so
->nonbinning
->inputs_count
);
3351 if (so
->nonbinning
->inputs
[n
].sysval
)
3354 /* be sure to keep inputs, even if only used in VS */
3355 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3356 array_insert(in
->block
, in
->block
->keeps
, in
);
3360 ir3_debug_print(ir
, "BEFORE GROUPING");
3362 ir3_sched_add_deps(ir
);
3364 /* Group left/right neighbors, inserting mov's where needed to
3369 ir3_debug_print(ir
, "AFTER GROUPING");
3373 ir3_debug_print(ir
, "AFTER DEPTH");
3375 /* do Sethi–Ullman numbering before scheduling: */
3378 ret
= ir3_sched(ir
);
3380 DBG("SCHED failed!");
3384 if (compiler
->gpu_id
>= 600) {
3385 ir3_a6xx_fixup_atomic_dests(ir
, so
);
3388 ir3_debug_print(ir
, "AFTER SCHED");
3390 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3391 * with draw pass VS, so binning and draw pass can both use the
3394 * Note that VS inputs are expected to be full precision.
3396 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3397 (ir
->type
== MESA_SHADER_VERTEX
) &&
3400 if (pre_assign_inputs
) {
3401 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3402 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3409 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3411 instr
->regs
[0]->num
= regid
;
3414 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3415 } else if (ctx
->tcs_header
) {
3416 /* We need to have these values in the same registers between VS and TCS
3417 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3420 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3421 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3422 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3423 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3424 } else if (ctx
->gs_header
) {
3425 /* We need to have these values in the same registers between producer
3426 * (VS or DS) and GS since the producer chains to GS and doesn't get
3427 * the sysvals redelivered.
3430 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3431 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3432 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3433 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3434 } else if (so
->num_sampler_prefetch
) {
3435 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3436 struct ir3_instruction
*instr
, *precolor
[2];
3439 foreach_input(instr
, ir
) {
3440 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PIXEL
)
3443 assert(idx
< ARRAY_SIZE(precolor
));
3445 precolor
[idx
] = instr
;
3446 instr
->regs
[0]->num
= idx
;
3450 ret
= ir3_ra(so
, precolor
, idx
);
3452 ret
= ir3_ra(so
, NULL
, 0);
3460 ir3_debug_print(ir
, "AFTER RA");
3462 if (so
->type
== MESA_SHADER_FRAGMENT
)
3466 * Fixup inputs/outputs to point to the actual registers assigned:
3468 * 1) initialize to r63.x (invalid/unused)
3469 * 2) iterate IR level inputs/outputs and update the variants
3470 * inputs/outputs table based on the assigned registers for
3471 * the remaining inputs/outputs.
3474 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3475 so
->inputs
[i
].regid
= INVALID_REG
;
3476 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3477 so
->outputs
[i
].regid
= INVALID_REG
;
3479 struct ir3_instruction
*out
;
3480 foreach_output(out
, ir
) {
3481 assert(out
->opc
== OPC_META_COLLECT
);
3482 unsigned outidx
= out
->collect
.outidx
;
3484 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3485 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3488 struct ir3_instruction
*in
;
3489 foreach_input(in
, ir
) {
3490 assert(in
->opc
== OPC_META_INPUT
);
3491 unsigned inidx
= in
->input
.inidx
;
3493 if (pre_assign_inputs
) {
3494 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3495 compile_assert(ctx
, in
->regs
[0]->num
==
3496 so
->nonbinning
->inputs
[inidx
].regid
);
3497 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3498 so
->nonbinning
->inputs
[inidx
].half
);
3500 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3501 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3503 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3504 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3509 fixup_astc_srgb(ctx
);
3511 /* We need to do legalize after (for frag shader's) the "bary.f"
3512 * offsets (inloc) have been assigned.
3514 ir3_legalize(ir
, &so
->has_ssbo
, &so
->need_pixlod
, &max_bary
);
3516 ir3_debug_print(ir
, "AFTER LEGALIZE");
3518 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3519 * know what we might have to wait on when coming in from VS chsh.
3521 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3522 so
->type
== MESA_SHADER_GEOMETRY
) {
3523 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
3524 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
3525 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3531 so
->branchstack
= ctx
->max_stack
;
3533 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3534 if (so
->type
== MESA_SHADER_FRAGMENT
)
3535 so
->total_in
= max_bary
+ 1;
3537 so
->max_sun
= ir
->max_sun
;
3539 /* Collect sampling instructions eligible for pre-dispatch. */
3540 collect_tex_prefetches(ctx
, ir
);
3545 ir3_destroy(so
->ir
);
3548 ir3_context_free(ctx
);