2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
54 ir3_reg_create(mov
, 0, 0);
55 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
58 src
->array
.offset
= n
;
60 ir3_instr_set_address(mov
, address
);
65 static struct ir3_instruction
*
66 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
68 struct ir3_instruction
*in
;
70 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
71 in
->inout
.block
= ctx
->in_block
;
72 ir3_reg_create(in
, n
, 0);
74 in
->regs
[0]->wrmask
= compmask
;
79 static struct ir3_instruction
*
80 create_input(struct ir3_context
*ctx
, unsigned n
)
82 return create_input_compmask(ctx
, n
, 0x1);
85 static struct ir3_instruction
*
86 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
88 struct ir3_block
*block
= ctx
->block
;
89 struct ir3_instruction
*instr
;
90 /* actual inloc is assigned and fixed up later: */
91 struct ir3_instruction
*inloc
= create_immed(block
, 0);
94 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
95 instr
->cat6
.type
= TYPE_U32
;
96 instr
->cat6
.iim_val
= 1;
98 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_vcoord
, 0);
99 instr
->regs
[2]->wrmask
= 0x3;
105 static struct ir3_instruction
*
106 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n
= ctx
->so
->constbase
.driver_param
;
111 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
112 return create_uniform(ctx
->block
, r
);
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
122 * -------+---------+-------+-
126 * To convert from an adreno bool (uint) to nir, use:
128 * absneg.s dst, (neg)src
130 * To convert back in the other direction:
132 * absneg.s dst, (abs)arc
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction
*
146 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
148 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction
*
153 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
155 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
159 * alu/sfu instructions:
162 static struct ir3_instruction
*
163 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
164 unsigned src_bitsize
, nir_op op
)
166 type_t src_type
, dst_type
;
170 case nir_op_f2f16_rtne
:
171 case nir_op_f2f16_rtz
:
179 switch (src_bitsize
) {
187 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
196 switch (src_bitsize
) {
207 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
216 switch (src_bitsize
) {
227 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
232 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
242 case nir_op_f2f16_rtne
:
243 case nir_op_f2f16_rtz
:
245 /* TODO how to handle rounding mode? */
282 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
285 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
289 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
291 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
292 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
293 unsigned bs
[info
->num_inputs
]; /* bit size */
294 struct ir3_block
*b
= ctx
->block
;
295 unsigned dst_sz
, wrmask
;
297 if (alu
->dest
.dest
.is_ssa
) {
298 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
299 wrmask
= (1 << dst_sz
) - 1;
301 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
302 wrmask
= alu
->dest
.write_mask
;
305 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
311 if ((alu
->op
== nir_op_vec2
) ||
312 (alu
->op
== nir_op_vec3
) ||
313 (alu
->op
== nir_op_vec4
)) {
315 for (int i
= 0; i
< info
->num_inputs
; i
++) {
316 nir_alu_src
*asrc
= &alu
->src
[i
];
318 compile_assert(ctx
, !asrc
->abs
);
319 compile_assert(ctx
, !asrc
->negate
);
321 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
323 src
[i
] = create_immed(ctx
->block
, 0);
324 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
327 ir3_put_dst(ctx
, &alu
->dest
.dest
);
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
334 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
335 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
336 nir_alu_src
*asrc
= &alu
->src
[0];
337 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
339 for (unsigned i
= 0; i
< dst_sz
; i
++) {
340 if (wrmask
& (1 << i
)) {
341 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
347 ir3_put_dst(ctx
, &alu
->dest
.dest
);
351 /* General case: We can just grab the one used channel per src. */
352 for (int i
= 0; i
< info
->num_inputs
; i
++) {
353 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
354 nir_alu_src
*asrc
= &alu
->src
[i
];
356 compile_assert(ctx
, !asrc
->abs
);
357 compile_assert(ctx
, !asrc
->negate
);
359 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
360 bs
[i
] = nir_src_bit_size(asrc
->src
);
362 compile_assert(ctx
, src
[i
]);
367 case nir_op_f2f16_rtne
:
368 case nir_op_f2f16_rtz
:
386 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
389 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
390 dst
[0]->cat2
.condition
= IR3_COND_NE
;
391 dst
[0] = ir3_n2b(b
, dst
[0]);
395 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
400 dst
[0] = ir3_b2n(b
, src
[0]);
403 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
404 dst
[0]->cat2
.condition
= IR3_COND_NE
;
405 dst
[0] = ir3_n2b(b
, dst
[0]);
409 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
412 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
415 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
418 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
426 * TODO probably opc_cat==4 is ok too
428 if (alu
->src
[0].src
.is_ssa
&&
429 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
430 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
431 src
[0]->flags
|= IR3_INSTR_SAT
;
432 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
437 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
438 dst
[0]->flags
|= IR3_INSTR_SAT
;
442 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
445 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
448 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
451 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
454 dst
[0] = ir3_DSX(b
, src
[0], 0);
455 dst
[0]->cat5
.type
= TYPE_F32
;
458 dst
[0] = ir3_DSY(b
, src
[0], 0);
459 dst
[0]->cat5
.type
= TYPE_F32
;
463 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
464 dst
[0]->cat2
.condition
= IR3_COND_LT
;
465 dst
[0] = ir3_n2b(b
, dst
[0]);
468 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
469 dst
[0]->cat2
.condition
= IR3_COND_GE
;
470 dst
[0] = ir3_n2b(b
, dst
[0]);
473 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
474 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
475 dst
[0] = ir3_n2b(b
, dst
[0]);
478 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
479 dst
[0]->cat2
.condition
= IR3_COND_NE
;
480 dst
[0] = ir3_n2b(b
, dst
[0]);
483 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
486 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
489 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
491 case nir_op_fround_even
:
492 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
495 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
499 dst
[0] = ir3_SIN(b
, src
[0], 0);
502 dst
[0] = ir3_COS(b
, src
[0], 0);
505 dst
[0] = ir3_RSQ(b
, src
[0], 0);
508 dst
[0] = ir3_RCP(b
, src
[0], 0);
511 dst
[0] = ir3_LOG2(b
, src
[0], 0);
514 dst
[0] = ir3_EXP2(b
, src
[0], 0);
517 dst
[0] = ir3_SQRT(b
, src
[0], 0);
521 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
524 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
527 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
530 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
533 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
536 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
539 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
548 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
549 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
550 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
553 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
556 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
559 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
562 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
565 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
568 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
571 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
574 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
577 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
578 dst
[0]->cat2
.condition
= IR3_COND_LT
;
579 dst
[0] = ir3_n2b(b
, dst
[0]);
582 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
583 dst
[0]->cat2
.condition
= IR3_COND_GE
;
584 dst
[0] = ir3_n2b(b
, dst
[0]);
587 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
588 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
589 dst
[0] = ir3_n2b(b
, dst
[0]);
592 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
593 dst
[0]->cat2
.condition
= IR3_COND_NE
;
594 dst
[0] = ir3_n2b(b
, dst
[0]);
597 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
598 dst
[0]->cat2
.condition
= IR3_COND_LT
;
599 dst
[0] = ir3_n2b(b
, dst
[0]);
602 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
603 dst
[0]->cat2
.condition
= IR3_COND_GE
;
604 dst
[0] = ir3_n2b(b
, dst
[0]);
607 case nir_op_b32csel
: {
608 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
609 compile_assert(ctx
, bs
[1] == bs
[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
615 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
616 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
619 case nir_op_bit_count
:
620 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
622 case nir_op_ifind_msb
: {
623 struct ir3_instruction
*cmp
;
624 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
625 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
626 cmp
->cat2
.condition
= IR3_COND_GE
;
627 dst
[0] = ir3_SEL_B32(b
,
628 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
632 case nir_op_ufind_msb
:
633 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
634 dst
[0] = ir3_SEL_B32(b
,
635 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
636 src
[0], 0, dst
[0], 0);
638 case nir_op_find_lsb
:
639 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
640 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
642 case nir_op_bitfield_reverse
:
643 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
647 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
648 nir_op_infos
[alu
->op
].name
);
652 ir3_put_dst(ctx
, &alu
->dest
.dest
);
655 /* handles direct/indirect UBO reads: */
657 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
658 struct ir3_instruction
**dst
)
660 struct ir3_block
*b
= ctx
->block
;
661 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
662 nir_const_value
*const_offset
;
663 /* UBO addresses are the first driver params: */
664 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
665 const unsigned ptrsz
= ir3_pointer_size(ctx
);
669 /* First src is ubo index, which could either be an immed or not: */
670 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
671 if (is_same_type_mov(src0
) &&
672 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
673 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
674 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
676 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, 4));
677 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, 4));
680 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
683 const_offset
= nir_src_as_const_value(intr
->src
[1]);
685 off
+= const_offset
->u32
[0];
687 /* For load_ubo_indirect, second src is indirect offset: */
688 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
690 /* and add offset to addr: */
691 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
694 /* if offset is to large to encode in the ldg, split it out: */
695 if ((off
+ (intr
->num_components
* 4)) > 1024) {
696 /* split out the minimal amount to improve the odds that
697 * cp can fit the immediate in the add.s instruction:
699 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
700 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
705 struct ir3_instruction
*carry
;
707 /* handle 32b rollover, ie:
708 * if (addr < base_lo)
711 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
712 carry
->cat2
.condition
= IR3_COND_LT
;
713 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
715 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
718 for (int i
= 0; i
< intr
->num_components
; i
++) {
719 struct ir3_instruction
*load
=
720 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
721 load
->cat6
.type
= TYPE_U32
;
722 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
727 /* src[] = { block_index } */
729 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
730 struct ir3_instruction
**dst
)
732 /* SSBO size stored as a const starting at ssbo_sizes: */
733 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
734 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
735 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
737 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
739 dst
[0] = create_uniform(ctx
->block
, idx
);
742 /* src[] = { offset }. const_index[] = { base } */
744 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
745 struct ir3_instruction
**dst
)
747 struct ir3_block
*b
= ctx
->block
;
748 struct ir3_instruction
*ldl
, *offset
;
751 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
752 base
= nir_intrinsic_base(intr
);
754 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
755 ldl
->cat6
.src_offset
= base
;
756 ldl
->cat6
.type
= utype_dst(intr
->dest
);
757 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
759 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
760 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
762 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
765 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
767 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
769 struct ir3_block
*b
= ctx
->block
;
770 struct ir3_instruction
*stl
, *offset
;
771 struct ir3_instruction
* const *value
;
772 unsigned base
, wrmask
;
774 value
= ir3_get_src(ctx
, &intr
->src
[0]);
775 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
777 base
= nir_intrinsic_base(intr
);
778 wrmask
= nir_intrinsic_write_mask(intr
);
780 /* Combine groups of consecutive enabled channels in one write
781 * message. We use ffs to find the first enabled channel and then ffs on
782 * the bit-inverse, down-shifted writemask to determine the length of
783 * the block of enabled bits.
785 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
788 unsigned first_component
= ffs(wrmask
) - 1;
789 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
791 stl
= ir3_STL(b
, offset
, 0,
792 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
793 create_immed(b
, length
), 0);
794 stl
->cat6
.dst_offset
= first_component
+ base
;
795 stl
->cat6
.type
= utype_src(intr
->src
[0]);
796 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
797 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
799 array_insert(b
, b
->keeps
, stl
);
801 /* Clear the bits in the writemask that we just wrote, then try
802 * again to see if more channels are left.
804 wrmask
&= (15 << (first_component
+ length
));
809 * CS shared variable atomic intrinsics
811 * All of the shared variable atomic memory operations read a value from
812 * memory, compute a new value using one of the operations below, write the
813 * new value to memory, and return the original value read.
815 * All operations take 2 sources except CompSwap that takes 3. These
818 * 0: The offset into the shared variable storage region that the atomic
819 * operation will operate on.
820 * 1: The data parameter to the atomic function (i.e. the value to add
821 * in shared_atomic_add, etc).
822 * 2: For CompSwap only: the second data parameter.
824 static struct ir3_instruction
*
825 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
827 struct ir3_block
*b
= ctx
->block
;
828 struct ir3_instruction
*atomic
, *src0
, *src1
;
829 type_t type
= TYPE_U32
;
831 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
832 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
834 switch (intr
->intrinsic
) {
835 case nir_intrinsic_shared_atomic_add
:
836 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
838 case nir_intrinsic_shared_atomic_imin
:
839 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
842 case nir_intrinsic_shared_atomic_umin
:
843 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
845 case nir_intrinsic_shared_atomic_imax
:
846 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
849 case nir_intrinsic_shared_atomic_umax
:
850 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
852 case nir_intrinsic_shared_atomic_and
:
853 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
855 case nir_intrinsic_shared_atomic_or
:
856 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
858 case nir_intrinsic_shared_atomic_xor
:
859 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
861 case nir_intrinsic_shared_atomic_exchange
:
862 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
864 case nir_intrinsic_shared_atomic_comp_swap
:
865 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
866 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
867 ir3_get_src(ctx
, &intr
->src
[2])[0],
870 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
876 atomic
->cat6
.iim_val
= 1;
878 atomic
->cat6
.type
= type
;
879 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
880 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
882 /* even if nothing consume the result, we can't DCE the instruction: */
883 array_insert(b
, b
->keeps
, atomic
);
888 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
890 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
891 struct ir3_instruction
**dst
)
893 struct ir3_block
*b
= ctx
->block
;
894 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
895 struct ir3_instruction
*sam
;
896 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
897 struct ir3_instruction
*coords
[4];
898 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
899 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
900 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
901 type_t type
= ir3_get_image_type(var
);
903 /* hmm, this seems a bit odd, but it is what blob does and (at least
904 * a5xx) just faults on bogus addresses otherwise:
906 if (flags
& IR3_INSTR_3D
) {
907 flags
&= ~IR3_INSTR_3D
;
908 flags
|= IR3_INSTR_A
;
911 for (unsigned i
= 0; i
< ncoords
; i
++)
915 coords
[ncoords
++] = create_immed(b
, 0);
917 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
918 tex_idx
, tex_idx
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
920 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
921 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
923 ir3_split_dest(b
, dst
, sam
, 0, 4);
927 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
928 struct ir3_instruction
**dst
)
930 struct ir3_block
*b
= ctx
->block
;
931 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
932 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
933 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
934 struct ir3_instruction
*sam
, *lod
;
935 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
937 lod
= create_immed(b
, 0);
938 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
939 tex_idx
, tex_idx
, lod
, NULL
);
941 /* Array size actually ends up in .w rather than .z. This doesn't
942 * matter for miplevel 0, but for higher mips the value in z is
943 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
944 * returned, which means that we have to add 1 to it for arrays for
947 * Note use a temporary dst and then copy, since the size of the dst
948 * array that is passed in is based on nir's understanding of the
949 * result size, not the hardware's
951 struct ir3_instruction
*tmp
[4];
953 ir3_split_dest(b
, tmp
, sam
, 0, 4);
955 /* get_size instruction returns size in bytes instead of texels
956 * for imageBuffer, so we need to divide it by the pixel size
957 * of the image format.
959 * TODO: This is at least true on a5xx. Check other gens.
961 enum glsl_sampler_dim dim
=
962 glsl_get_sampler_dim(glsl_without_array(var
->type
));
963 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
964 /* Since all the possible values the divisor can take are
965 * power-of-two (4, 8, or 16), the division is implemented
967 * During shader setup, the log2 of the image format's
968 * bytes-per-pixel should have been emitted in 2nd slot of
969 * image_dims. See ir3_shader::emit_image_dims().
971 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
972 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
973 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
975 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
978 for (unsigned i
= 0; i
< ncoords
; i
++)
981 if (flags
& IR3_INSTR_A
) {
982 if (ctx
->compiler
->levels_add_one
) {
983 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
985 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
991 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
993 struct ir3_block
*b
= ctx
->block
;
994 struct ir3_instruction
*barrier
;
996 switch (intr
->intrinsic
) {
997 case nir_intrinsic_barrier
:
998 barrier
= ir3_BAR(b
);
999 barrier
->cat7
.g
= true;
1000 barrier
->cat7
.l
= true;
1001 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1002 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1004 case nir_intrinsic_memory_barrier
:
1005 barrier
= ir3_FENCE(b
);
1006 barrier
->cat7
.g
= true;
1007 barrier
->cat7
.r
= true;
1008 barrier
->cat7
.w
= true;
1009 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1010 IR3_BARRIER_BUFFER_W
;
1011 barrier
->barrier_conflict
=
1012 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1013 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1015 case nir_intrinsic_memory_barrier_atomic_counter
:
1016 case nir_intrinsic_memory_barrier_buffer
:
1017 barrier
= ir3_FENCE(b
);
1018 barrier
->cat7
.g
= true;
1019 barrier
->cat7
.r
= true;
1020 barrier
->cat7
.w
= true;
1021 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1022 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1023 IR3_BARRIER_BUFFER_W
;
1025 case nir_intrinsic_memory_barrier_image
:
1026 // TODO double check if this should have .g set
1027 barrier
= ir3_FENCE(b
);
1028 barrier
->cat7
.g
= true;
1029 barrier
->cat7
.r
= true;
1030 barrier
->cat7
.w
= true;
1031 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1032 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1033 IR3_BARRIER_IMAGE_W
;
1035 case nir_intrinsic_memory_barrier_shared
:
1036 barrier
= ir3_FENCE(b
);
1037 barrier
->cat7
.g
= true;
1038 barrier
->cat7
.l
= true;
1039 barrier
->cat7
.r
= true;
1040 barrier
->cat7
.w
= true;
1041 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1042 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1043 IR3_BARRIER_SHARED_W
;
1045 case nir_intrinsic_group_memory_barrier
:
1046 barrier
= ir3_FENCE(b
);
1047 barrier
->cat7
.g
= true;
1048 barrier
->cat7
.l
= true;
1049 barrier
->cat7
.r
= true;
1050 barrier
->cat7
.w
= true;
1051 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1052 IR3_BARRIER_IMAGE_W
|
1053 IR3_BARRIER_BUFFER_W
;
1054 barrier
->barrier_conflict
=
1055 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1056 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1057 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1063 /* make sure barrier doesn't get DCE'd */
1064 array_insert(b
, b
->keeps
, barrier
);
1067 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1068 gl_system_value slot
, unsigned compmask
,
1069 struct ir3_instruction
*instr
)
1071 struct ir3_shader_variant
*so
= ctx
->so
;
1072 unsigned r
= regid(so
->inputs_count
, 0);
1073 unsigned n
= so
->inputs_count
++;
1075 so
->inputs
[n
].sysval
= true;
1076 so
->inputs
[n
].slot
= slot
;
1077 so
->inputs
[n
].compmask
= compmask
;
1078 so
->inputs
[n
].regid
= r
;
1079 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1082 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1083 ctx
->ir
->inputs
[r
] = instr
;
1086 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1087 struct ir3_instruction
*instr
)
1089 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1093 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1095 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1096 struct ir3_instruction
**dst
;
1097 struct ir3_instruction
* const *src
;
1098 struct ir3_block
*b
= ctx
->block
;
1099 nir_const_value
*const_offset
;
1102 if (info
->has_dest
) {
1103 unsigned n
= nir_intrinsic_dest_components(intr
);
1104 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1109 switch (intr
->intrinsic
) {
1110 case nir_intrinsic_load_uniform
:
1111 idx
= nir_intrinsic_base(intr
);
1112 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1114 idx
+= const_offset
->u32
[0];
1115 for (int i
= 0; i
< intr
->num_components
; i
++) {
1116 unsigned n
= idx
* 4 + i
;
1117 dst
[i
] = create_uniform(b
, n
);
1120 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1121 for (int i
= 0; i
< intr
->num_components
; i
++) {
1122 int n
= idx
* 4 + i
;
1123 dst
[i
] = create_uniform_indirect(b
, n
,
1124 ir3_get_addr(ctx
, src
[0], 4));
1126 /* NOTE: if relative addressing is used, we set
1127 * constlen in the compiler (to worst-case value)
1128 * since we don't know in the assembler what the max
1129 * addr reg value can be:
1131 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1134 case nir_intrinsic_load_ubo
:
1135 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1137 case nir_intrinsic_load_input
:
1138 idx
= nir_intrinsic_base(intr
);
1139 comp
= nir_intrinsic_component(intr
);
1140 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1142 idx
+= const_offset
->u32
[0];
1143 for (int i
= 0; i
< intr
->num_components
; i
++) {
1144 unsigned n
= idx
* 4 + i
+ comp
;
1145 dst
[i
] = ctx
->ir
->inputs
[n
];
1148 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1149 struct ir3_instruction
*collect
=
1150 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1151 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1152 for (int i
= 0; i
< intr
->num_components
; i
++) {
1153 unsigned n
= idx
* 4 + i
+ comp
;
1154 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1159 case nir_intrinsic_load_ssbo
:
1160 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1162 case nir_intrinsic_store_ssbo
:
1163 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1165 case nir_intrinsic_get_buffer_size
:
1166 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1168 case nir_intrinsic_ssbo_atomic_add
:
1169 case nir_intrinsic_ssbo_atomic_imin
:
1170 case nir_intrinsic_ssbo_atomic_umin
:
1171 case nir_intrinsic_ssbo_atomic_imax
:
1172 case nir_intrinsic_ssbo_atomic_umax
:
1173 case nir_intrinsic_ssbo_atomic_and
:
1174 case nir_intrinsic_ssbo_atomic_or
:
1175 case nir_intrinsic_ssbo_atomic_xor
:
1176 case nir_intrinsic_ssbo_atomic_exchange
:
1177 case nir_intrinsic_ssbo_atomic_comp_swap
:
1178 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1180 case nir_intrinsic_load_shared
:
1181 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1183 case nir_intrinsic_store_shared
:
1184 emit_intrinsic_store_shared(ctx
, intr
);
1186 case nir_intrinsic_shared_atomic_add
:
1187 case nir_intrinsic_shared_atomic_imin
:
1188 case nir_intrinsic_shared_atomic_umin
:
1189 case nir_intrinsic_shared_atomic_imax
:
1190 case nir_intrinsic_shared_atomic_umax
:
1191 case nir_intrinsic_shared_atomic_and
:
1192 case nir_intrinsic_shared_atomic_or
:
1193 case nir_intrinsic_shared_atomic_xor
:
1194 case nir_intrinsic_shared_atomic_exchange
:
1195 case nir_intrinsic_shared_atomic_comp_swap
:
1196 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1198 case nir_intrinsic_image_deref_load
:
1199 emit_intrinsic_load_image(ctx
, intr
, dst
);
1201 case nir_intrinsic_image_deref_store
:
1202 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1204 case nir_intrinsic_image_deref_size
:
1205 emit_intrinsic_image_size(ctx
, intr
, dst
);
1207 case nir_intrinsic_image_deref_atomic_add
:
1208 case nir_intrinsic_image_deref_atomic_min
:
1209 case nir_intrinsic_image_deref_atomic_max
:
1210 case nir_intrinsic_image_deref_atomic_and
:
1211 case nir_intrinsic_image_deref_atomic_or
:
1212 case nir_intrinsic_image_deref_atomic_xor
:
1213 case nir_intrinsic_image_deref_atomic_exchange
:
1214 case nir_intrinsic_image_deref_atomic_comp_swap
:
1215 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1217 case nir_intrinsic_barrier
:
1218 case nir_intrinsic_memory_barrier
:
1219 case nir_intrinsic_group_memory_barrier
:
1220 case nir_intrinsic_memory_barrier_atomic_counter
:
1221 case nir_intrinsic_memory_barrier_buffer
:
1222 case nir_intrinsic_memory_barrier_image
:
1223 case nir_intrinsic_memory_barrier_shared
:
1224 emit_intrinsic_barrier(ctx
, intr
);
1225 /* note that blk ptr no longer valid, make that obvious: */
1228 case nir_intrinsic_store_output
:
1229 idx
= nir_intrinsic_base(intr
);
1230 comp
= nir_intrinsic_component(intr
);
1231 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1232 compile_assert(ctx
, const_offset
!= NULL
);
1233 idx
+= const_offset
->u32
[0];
1235 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1236 for (int i
= 0; i
< intr
->num_components
; i
++) {
1237 unsigned n
= idx
* 4 + i
+ comp
;
1238 ctx
->ir
->outputs
[n
] = src
[i
];
1241 case nir_intrinsic_load_base_vertex
:
1242 case nir_intrinsic_load_first_vertex
:
1243 if (!ctx
->basevertex
) {
1244 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1245 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
1247 dst
[0] = ctx
->basevertex
;
1249 case nir_intrinsic_load_vertex_id_zero_base
:
1250 case nir_intrinsic_load_vertex_id
:
1251 if (!ctx
->vertex_id
) {
1252 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1253 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1254 ctx
->vertex_id
= create_input(ctx
, 0);
1255 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1257 dst
[0] = ctx
->vertex_id
;
1259 case nir_intrinsic_load_instance_id
:
1260 if (!ctx
->instance_id
) {
1261 ctx
->instance_id
= create_input(ctx
, 0);
1262 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1265 dst
[0] = ctx
->instance_id
;
1267 case nir_intrinsic_load_sample_id
:
1268 case nir_intrinsic_load_sample_id_no_per_sample
:
1269 if (!ctx
->samp_id
) {
1270 ctx
->samp_id
= create_input(ctx
, 0);
1271 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1272 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
1275 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1277 case nir_intrinsic_load_sample_mask_in
:
1278 if (!ctx
->samp_mask_in
) {
1279 ctx
->samp_mask_in
= create_input(ctx
, 0);
1280 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
1283 dst
[0] = ctx
->samp_mask_in
;
1285 case nir_intrinsic_load_user_clip_plane
:
1286 idx
= nir_intrinsic_ucp_id(intr
);
1287 for (int i
= 0; i
< intr
->num_components
; i
++) {
1288 unsigned n
= idx
* 4 + i
;
1289 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1292 case nir_intrinsic_load_front_face
:
1293 if (!ctx
->frag_face
) {
1294 ctx
->so
->frag_face
= true;
1295 ctx
->frag_face
= create_input(ctx
, 0);
1296 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
1297 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1299 /* for fragface, we get -1 for back and 0 for front. However this is
1300 * the inverse of what nir expects (where ~0 is true).
1302 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1303 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1305 case nir_intrinsic_load_local_invocation_id
:
1306 if (!ctx
->local_invocation_id
) {
1307 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
1308 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1309 0x7, ctx
->local_invocation_id
);
1311 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1313 case nir_intrinsic_load_work_group_id
:
1314 if (!ctx
->work_group_id
) {
1315 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
1316 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1317 0x7, ctx
->work_group_id
);
1318 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1320 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1322 case nir_intrinsic_load_num_work_groups
:
1323 for (int i
= 0; i
< intr
->num_components
; i
++) {
1324 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1327 case nir_intrinsic_load_local_group_size
:
1328 for (int i
= 0; i
< intr
->num_components
; i
++) {
1329 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1332 case nir_intrinsic_discard_if
:
1333 case nir_intrinsic_discard
: {
1334 struct ir3_instruction
*cond
, *kill
;
1336 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1337 /* conditional discard: */
1338 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1339 cond
= ir3_b2n(b
, src
[0]);
1341 /* unconditional discard: */
1342 cond
= create_immed(b
, 1);
1345 /* NOTE: only cmps.*.* can write p0.x: */
1346 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1347 cond
->cat2
.condition
= IR3_COND_NE
;
1349 /* condition always goes in predicate register: */
1350 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1352 kill
= ir3_KILL(b
, cond
, 0);
1353 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1355 array_insert(b
, b
->keeps
, kill
);
1356 ctx
->so
->has_kill
= true;
1361 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1362 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1367 ir3_put_dst(ctx
, &intr
->dest
);
1371 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1373 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1374 instr
->def
.num_components
);
1375 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1377 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1378 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
1382 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1384 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1385 undef
->def
.num_components
);
1386 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1388 /* backend doesn't want undefined instructions, so just plug
1391 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1392 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1396 * texture fetch/sample instructions:
1400 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1402 unsigned coords
, flags
= 0;
1404 /* note: would use tex->coord_components.. except txs.. also,
1405 * since array index goes after shadow ref, we don't want to
1408 switch (tex
->sampler_dim
) {
1409 case GLSL_SAMPLER_DIM_1D
:
1410 case GLSL_SAMPLER_DIM_BUF
:
1413 case GLSL_SAMPLER_DIM_2D
:
1414 case GLSL_SAMPLER_DIM_RECT
:
1415 case GLSL_SAMPLER_DIM_EXTERNAL
:
1416 case GLSL_SAMPLER_DIM_MS
:
1419 case GLSL_SAMPLER_DIM_3D
:
1420 case GLSL_SAMPLER_DIM_CUBE
:
1422 flags
|= IR3_INSTR_3D
;
1425 unreachable("bad sampler_dim");
1428 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1429 flags
|= IR3_INSTR_S
;
1431 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1432 flags
|= IR3_INSTR_A
;
1439 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1441 struct ir3_block
*b
= ctx
->block
;
1442 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1443 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1444 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1445 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1446 unsigned i
, coords
, flags
, ncomp
;
1447 unsigned nsrc0
= 0, nsrc1
= 0;
1451 ncomp
= nir_dest_num_components(tex
->dest
);
1453 coord
= off
= ddx
= ddy
= NULL
;
1454 lod
= proj
= compare
= sample_index
= NULL
;
1456 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1458 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1459 switch (tex
->src
[i
].src_type
) {
1460 case nir_tex_src_coord
:
1461 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1463 case nir_tex_src_bias
:
1464 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1467 case nir_tex_src_lod
:
1468 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1471 case nir_tex_src_comparator
: /* shadow comparator */
1472 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1474 case nir_tex_src_projector
:
1475 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1478 case nir_tex_src_offset
:
1479 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1482 case nir_tex_src_ddx
:
1483 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1485 case nir_tex_src_ddy
:
1486 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1488 case nir_tex_src_ms_index
:
1489 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1492 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
1493 tex
->src
[i
].src_type
);
1499 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
1500 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1501 case nir_texop_txl
: opc
= OPC_SAML
; break;
1502 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1503 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1504 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1506 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1507 * what blob does, seems gather is broken?), and a3xx did
1508 * not support it (but probably could also emulate).
1510 switch (tex
->component
) {
1511 case 0: opc
= OPC_GATHER4R
; break;
1512 case 1: opc
= OPC_GATHER4G
; break;
1513 case 2: opc
= OPC_GATHER4B
; break;
1514 case 3: opc
= OPC_GATHER4A
; break;
1517 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
1519 case nir_texop_query_levels
:
1520 case nir_texop_texture_samples
:
1521 case nir_texop_samples_identical
:
1522 case nir_texop_txf_ms_mcs
:
1523 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1527 tex_info(tex
, &flags
, &coords
);
1530 * lay out the first argument in the proper order:
1531 * - actual coordinates first
1532 * - shadow reference
1535 * - starting at offset 4, dpdx.xy, dpdy.xy
1537 * bias/lod go into the second arg
1540 /* insert tex coords: */
1541 for (i
= 0; i
< coords
; i
++)
1546 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1547 * with scaled x coord according to requested sample:
1549 if (tex
->op
== nir_texop_txf_ms
) {
1550 if (ctx
->compiler
->txf_ms_with_isaml
) {
1551 /* the samples are laid out in x dimension as
1553 * x_ms = (x << ms) + sample_index;
1555 struct ir3_instruction
*ms
;
1556 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
1558 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
1559 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
1563 src0
[nsrc0
++] = sample_index
;
1567 /* scale up integer coords for TXF based on the LOD */
1568 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1570 for (i
= 0; i
< coords
; i
++)
1571 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1575 /* hw doesn't do 1d, so we treat it as 2d with
1576 * height of 1, and patch up the y coord.
1582 /* These instructions expect integer coord: */
1583 src0
[nsrc0
++] = create_immed(b
, 0);
1586 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1591 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1592 src0
[nsrc0
++] = compare
;
1594 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1595 struct ir3_instruction
*idx
= coord
[coords
];
1597 /* the array coord for cube arrays needs 0.5 added to it */
1598 if (ctx
->compiler
->array_index_add_half
&& (opc
!= OPC_ISAML
))
1599 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1601 src0
[nsrc0
++] = idx
;
1605 src0
[nsrc0
++] = proj
;
1606 flags
|= IR3_INSTR_P
;
1609 /* pad to 4, then ddx/ddy: */
1610 if (tex
->op
== nir_texop_txd
) {
1612 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1613 for (i
= 0; i
< coords
; i
++)
1614 src0
[nsrc0
++] = ddx
[i
];
1616 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1617 for (i
= 0; i
< coords
; i
++)
1618 src0
[nsrc0
++] = ddy
[i
];
1620 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1624 * second argument (if applicable):
1629 if (has_off
| has_lod
| has_bias
) {
1631 unsigned off_coords
= coords
;
1632 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1634 for (i
= 0; i
< off_coords
; i
++)
1635 src1
[nsrc1
++] = off
[i
];
1637 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1638 flags
|= IR3_INSTR_O
;
1641 if (has_lod
| has_bias
)
1642 src1
[nsrc1
++] = lod
;
1645 switch (tex
->dest_type
) {
1646 case nir_type_invalid
:
1647 case nir_type_float
:
1658 unreachable("bad dest_type");
1661 if (opc
== OPC_GETLOD
)
1664 unsigned tex_idx
= tex
->texture_index
;
1666 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1668 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
1669 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
1671 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
1672 tex_idx
, tex_idx
, col0
, col1
);
1674 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1675 /* only need first 3 components: */
1676 sam
->regs
[0]->wrmask
= 0x7;
1677 ir3_split_dest(b
, dst
, sam
, 0, 3);
1679 /* we need to sample the alpha separately with a non-ASTC
1682 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
1683 tex_idx
, tex_idx
, col0
, col1
);
1685 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1687 /* fixup .w component: */
1688 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
1690 /* normal (non-workaround) case: */
1691 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
1694 /* GETLOD returns results in 4.8 fixed point */
1695 if (opc
== OPC_GETLOD
) {
1696 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1698 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1699 for (i
= 0; i
< 2; i
++) {
1700 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1705 ir3_put_dst(ctx
, &tex
->dest
);
1709 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1711 struct ir3_block
*b
= ctx
->block
;
1712 struct ir3_instruction
**dst
, *sam
;
1714 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
1716 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, 0b0100, 0,
1717 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1719 /* even though there is only one component, since it ends
1720 * up in .z rather than .x, we need a split_dest()
1722 ir3_split_dest(b
, dst
, sam
, 0, 3);
1724 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1725 * the value in TEX_CONST_0 is zero-based.
1727 if (ctx
->compiler
->levels_add_one
)
1728 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1730 ir3_put_dst(ctx
, &tex
->dest
);
1734 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1736 struct ir3_block
*b
= ctx
->block
;
1737 struct ir3_instruction
**dst
, *sam
;
1738 struct ir3_instruction
*lod
;
1739 unsigned flags
, coords
;
1741 tex_info(tex
, &flags
, &coords
);
1743 /* Actually we want the number of dimensions, not coordinates. This
1744 * distinction only matters for cubes.
1746 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1749 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
1751 compile_assert(ctx
, tex
->num_srcs
== 1);
1752 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1754 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
1756 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
1757 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1759 ir3_split_dest(b
, dst
, sam
, 0, 4);
1761 /* Array size actually ends up in .w rather than .z. This doesn't
1762 * matter for miplevel 0, but for higher mips the value in z is
1763 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1764 * returned, which means that we have to add 1 to it for arrays.
1766 if (tex
->is_array
) {
1767 if (ctx
->compiler
->levels_add_one
) {
1768 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1770 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1774 ir3_put_dst(ctx
, &tex
->dest
);
1778 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
1780 switch (jump
->type
) {
1781 case nir_jump_break
:
1782 case nir_jump_continue
:
1783 case nir_jump_return
:
1784 /* I *think* we can simply just ignore this, and use the
1785 * successor block link to figure out where we need to
1786 * jump to for break/continue
1790 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1796 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
1798 switch (instr
->type
) {
1799 case nir_instr_type_alu
:
1800 emit_alu(ctx
, nir_instr_as_alu(instr
));
1802 case nir_instr_type_deref
:
1803 /* ignored, handled as part of the intrinsic they are src to */
1805 case nir_instr_type_intrinsic
:
1806 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1808 case nir_instr_type_load_const
:
1809 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1811 case nir_instr_type_ssa_undef
:
1812 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1814 case nir_instr_type_tex
: {
1815 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1816 /* couple tex instructions get special-cased:
1820 emit_tex_txs(ctx
, tex
);
1822 case nir_texop_query_levels
:
1823 emit_tex_query_levels(ctx
, tex
);
1831 case nir_instr_type_jump
:
1832 emit_jump(ctx
, nir_instr_as_jump(instr
));
1834 case nir_instr_type_phi
:
1835 /* we have converted phi webs to regs in NIR by now */
1836 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
1838 case nir_instr_type_call
:
1839 case nir_instr_type_parallel_copy
:
1840 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1845 static struct ir3_block
*
1846 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
1848 struct ir3_block
*block
;
1849 struct hash_entry
*hentry
;
1852 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1854 return hentry
->data
;
1856 block
= ir3_block_create(ctx
->ir
);
1857 block
->nblock
= nblock
;
1858 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1860 block
->predecessors_count
= nblock
->predecessors
->entries
;
1861 block
->predecessors
= ralloc_array_size(block
,
1862 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
1864 set_foreach(nblock
->predecessors
, sentry
) {
1865 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
1872 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
1874 struct ir3_block
*block
= get_block(ctx
, nblock
);
1876 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1877 if (nblock
->successors
[i
]) {
1878 block
->successors
[i
] =
1879 get_block(ctx
, nblock
->successors
[i
]);
1884 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1886 /* re-emit addr register in each block if needed: */
1887 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
1888 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
1889 ctx
->addr_ht
[i
] = NULL
;
1892 nir_foreach_instr(instr
, nblock
) {
1893 ctx
->cur_instr
= instr
;
1894 emit_instr(ctx
, instr
);
1895 ctx
->cur_instr
= NULL
;
1901 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
1904 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
1906 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
1908 ctx
->block
->condition
=
1909 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1911 emit_cf_list(ctx
, &nif
->then_list
);
1912 emit_cf_list(ctx
, &nif
->else_list
);
1916 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
1918 emit_cf_list(ctx
, &nloop
->body
);
1922 stack_push(struct ir3_context
*ctx
)
1925 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
1929 stack_pop(struct ir3_context
*ctx
)
1931 compile_assert(ctx
, ctx
->stack
> 0);
1936 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
1938 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1939 switch (node
->type
) {
1940 case nir_cf_node_block
:
1941 emit_block(ctx
, nir_cf_node_as_block(node
));
1943 case nir_cf_node_if
:
1945 emit_if(ctx
, nir_cf_node_as_if(node
));
1948 case nir_cf_node_loop
:
1950 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1953 case nir_cf_node_function
:
1954 ir3_context_error(ctx
, "TODO\n");
1960 /* emit stream-out code. At this point, the current block is the original
1961 * (nir) end block, and nir ensures that all flow control paths terminate
1962 * into the end block. We re-purpose the original end block to generate
1963 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1964 * block holding stream-out write instructions, followed by the new end
1968 * p0.x = (vtxcnt < maxvtxcnt)
1969 * // succs: blockStreamOut, blockNewEnd
1972 * ... stream-out instructions ...
1973 * // succs: blockNewEnd
1979 emit_stream_out(struct ir3_context
*ctx
)
1981 struct ir3_shader_variant
*v
= ctx
->so
;
1982 struct ir3
*ir
= ctx
->ir
;
1983 struct ir3_stream_output_info
*strmout
=
1984 &ctx
->so
->shader
->stream_output
;
1985 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
1986 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
1987 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
1989 /* create vtxcnt input in input block at top of shader,
1990 * so that it is seen as live over the entire duration
1993 vtxcnt
= create_input(ctx
, 0);
1994 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
1996 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
1998 /* at this point, we are at the original 'end' block,
1999 * re-purpose this block to stream-out condition, then
2000 * append stream-out block and new-end block
2002 orig_end_block
= ctx
->block
;
2004 // TODO these blocks need to update predecessors..
2005 // maybe w/ store_global intrinsic, we could do this
2006 // stuff in nir->nir pass
2008 stream_out_block
= ir3_block_create(ir
);
2009 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2011 new_end_block
= ir3_block_create(ir
);
2012 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2014 orig_end_block
->successors
[0] = stream_out_block
;
2015 orig_end_block
->successors
[1] = new_end_block
;
2016 stream_out_block
->successors
[0] = new_end_block
;
2018 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2019 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2020 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2021 cond
->cat2
.condition
= IR3_COND_LT
;
2023 /* condition goes on previous block to the conditional,
2024 * since it is used to pick which of the two successor
2027 orig_end_block
->condition
= cond
;
2029 /* switch to stream_out_block to generate the stream-out
2032 ctx
->block
= stream_out_block
;
2034 /* Calculate base addresses based on vtxcnt. Instructions
2035 * generated for bases not used in following loop will be
2036 * stripped out in the backend.
2038 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2039 unsigned stride
= strmout
->stride
[i
];
2040 struct ir3_instruction
*base
, *off
;
2042 base
= create_uniform(ctx
->block
, regid(v
->constbase
.tfbo
, i
));
2044 /* 24-bit should be enough: */
2045 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2046 create_immed(ctx
->block
, stride
* 4), 0);
2048 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2051 /* Generate the per-output store instructions: */
2052 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2053 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2054 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2055 struct ir3_instruction
*base
, *out
, *stg
;
2057 base
= bases
[strmout
->output
[i
].output_buffer
];
2058 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2060 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2061 create_immed(ctx
->block
, 1), 0);
2062 stg
->cat6
.type
= TYPE_U32
;
2063 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2065 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2069 /* and finally switch to the new_end_block: */
2070 ctx
->block
= new_end_block
;
2074 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2076 nir_metadata_require(impl
, nir_metadata_block_index
);
2078 compile_assert(ctx
, ctx
->stack
== 0);
2080 emit_cf_list(ctx
, &impl
->body
);
2081 emit_block(ctx
, impl
->end_block
);
2083 compile_assert(ctx
, ctx
->stack
== 0);
2085 /* at this point, we should have a single empty block,
2086 * into which we emit the 'end' instruction.
2088 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2090 /* If stream-out (aka transform-feedback) enabled, emit the
2091 * stream-out instructions, followed by a new empty block (into
2092 * which the 'end' instruction lands).
2094 * NOTE: it is done in this order, rather than inserting before
2095 * we emit end_block, because NIR guarantees that all blocks
2096 * flow into end_block, and that end_block has no successors.
2097 * So by re-purposing end_block as the first block of stream-
2098 * out, we guarantee that all exit paths flow into the stream-
2101 if ((ctx
->compiler
->gpu_id
< 500) &&
2102 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2103 !ctx
->so
->binning_pass
) {
2104 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2105 emit_stream_out(ctx
);
2108 ir3_END(ctx
->block
);
2111 static struct ir3_instruction
*
2112 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
2114 struct ir3_block
*block
= ctx
->block
;
2115 struct ir3_instruction
*instr
;
2117 if (!ctx
->frag_coord
) {
2118 ctx
->frag_coord
= create_input_compmask(ctx
, 0, 0xf);
2119 /* defer add_sysval_input() until after all inputs created */
2122 ir3_split_dest(block
, &instr
, ctx
->frag_coord
, comp
, 1);
2127 /* for frag_coord, we get unsigned values.. we need
2128 * to subtract (integer) 8 and divide by 16 (right-
2129 * shift by 4) then convert to float:
2133 * mov.u32f32 dst, tmp
2136 instr
= ir3_SUB_S(block
, instr
, 0,
2137 create_immed(block
, 8), 0);
2138 instr
= ir3_SHR_B(block
, instr
, 0,
2139 create_immed(block
, 4), 0);
2140 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
2146 /* seems that we can use these as-is: */
2152 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2154 struct ir3_shader_variant
*so
= ctx
->so
;
2155 unsigned ncomp
= glsl_get_components(in
->type
);
2156 unsigned n
= in
->data
.driver_location
;
2157 unsigned frac
= in
->data
.location_frac
;
2158 unsigned slot
= in
->data
.location
;
2160 /* skip unread inputs, we could end up with (for example), unsplit
2161 * matrix/etc inputs in the case they are not read, so just silently
2167 so
->inputs
[n
].slot
= slot
;
2168 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2169 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2170 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2172 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2173 for (int i
= 0; i
< ncomp
; i
++) {
2174 struct ir3_instruction
*instr
= NULL
;
2175 unsigned idx
= (n
* 4) + i
+ frac
;
2177 if (slot
== VARYING_SLOT_POS
) {
2178 so
->inputs
[n
].bary
= false;
2179 so
->frag_coord
= true;
2180 instr
= create_frag_coord(ctx
, i
);
2181 } else if (slot
== VARYING_SLOT_PNTC
) {
2182 /* see for example st_nir_fixup_varying_slots().. this is
2183 * maybe a bit mesa/st specific. But we need things to line
2184 * up for this in fdN_program:
2185 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2186 * if (emit->sprite_coord_enable & texmask) {
2190 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2191 so
->inputs
[n
].bary
= true;
2192 instr
= create_frag_input(ctx
, false);
2194 bool use_ldlv
= false;
2196 /* detect the special case for front/back colors where
2197 * we need to do flat vs smooth shading depending on
2200 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2202 case VARYING_SLOT_COL0
:
2203 case VARYING_SLOT_COL1
:
2204 case VARYING_SLOT_BFC0
:
2205 case VARYING_SLOT_BFC1
:
2206 so
->inputs
[n
].rasterflat
= true;
2213 if (ctx
->compiler
->flat_bypass
) {
2214 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2215 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2219 so
->inputs
[n
].bary
= true;
2221 instr
= create_frag_input(ctx
, use_ldlv
);
2224 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2226 ctx
->ir
->inputs
[idx
] = instr
;
2228 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2229 for (int i
= 0; i
< ncomp
; i
++) {
2230 unsigned idx
= (n
* 4) + i
+ frac
;
2231 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2232 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
2235 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2238 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2239 so
->total_in
+= ncomp
;
2244 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2246 struct ir3_shader_variant
*so
= ctx
->so
;
2247 unsigned ncomp
= glsl_get_components(out
->type
);
2248 unsigned n
= out
->data
.driver_location
;
2249 unsigned frac
= out
->data
.location_frac
;
2250 unsigned slot
= out
->data
.location
;
2253 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2255 case FRAG_RESULT_DEPTH
:
2256 comp
= 2; /* tgsi will write to .z component */
2257 so
->writes_pos
= true;
2259 case FRAG_RESULT_COLOR
:
2263 if (slot
>= FRAG_RESULT_DATA0
)
2265 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2266 gl_frag_result_name(slot
));
2268 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2270 case VARYING_SLOT_POS
:
2271 so
->writes_pos
= true;
2273 case VARYING_SLOT_PSIZ
:
2274 so
->writes_psize
= true;
2276 case VARYING_SLOT_COL0
:
2277 case VARYING_SLOT_COL1
:
2278 case VARYING_SLOT_BFC0
:
2279 case VARYING_SLOT_BFC1
:
2280 case VARYING_SLOT_FOGC
:
2281 case VARYING_SLOT_CLIP_DIST0
:
2282 case VARYING_SLOT_CLIP_DIST1
:
2283 case VARYING_SLOT_CLIP_VERTEX
:
2286 if (slot
>= VARYING_SLOT_VAR0
)
2288 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2290 ir3_context_error(ctx
, "unknown VS output name: %s\n",
2291 gl_varying_slot_name(slot
));
2294 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2297 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2299 so
->outputs
[n
].slot
= slot
;
2300 so
->outputs
[n
].regid
= regid(n
, comp
);
2301 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2303 for (int i
= 0; i
< ncomp
; i
++) {
2304 unsigned idx
= (n
* 4) + i
+ frac
;
2305 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2306 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2309 /* if varying packing doesn't happen, we could end up in a situation
2310 * with "holes" in the output, and since the per-generation code that
2311 * sets up varying linkage registers doesn't expect to have more than
2312 * one varying per vec4 slot, pad the holes.
2314 * Note that this should probably generate a performance warning of
2317 for (int i
= 0; i
< frac
; i
++) {
2318 unsigned idx
= (n
* 4) + i
;
2319 if (!ctx
->ir
->outputs
[idx
]) {
2320 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2326 max_drvloc(struct exec_list
*vars
)
2329 nir_foreach_variable(var
, vars
) {
2330 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2335 static const unsigned max_sysvals
[] = {
2336 [MESA_SHADER_FRAGMENT
] = 24, // TODO
2337 [MESA_SHADER_VERTEX
] = 16,
2338 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2339 [MESA_SHADER_KERNEL
] = 16, // TODO how many do we actually need?
2343 emit_instructions(struct ir3_context
*ctx
)
2345 unsigned ninputs
, noutputs
;
2346 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2348 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2349 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2351 /* we need to leave room for sysvals:
2353 ninputs
+= max_sysvals
[ctx
->so
->type
];
2355 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2357 /* Create inputs in first block: */
2358 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2359 ctx
->in_block
= ctx
->block
;
2360 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2362 ninputs
-= max_sysvals
[ctx
->so
->type
];
2364 /* for fragment shader, the vcoord input register is used as the
2365 * base for bary.f varying fetch instrs:
2367 struct ir3_instruction
*vcoord
= NULL
;
2368 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2369 struct ir3_instruction
*xy
[2];
2371 vcoord
= create_input_compmask(ctx
, 0, 0x3);
2372 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
2374 ctx
->frag_vcoord
= ir3_create_collect(ctx
, xy
, 2);
2378 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2379 setup_input(ctx
, var
);
2382 /* Defer add_sysval_input() stuff until after setup_inputs(),
2383 * because sysvals need to be appended after varyings:
2386 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_VARYING_COORD
,
2390 if (ctx
->frag_coord
) {
2391 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_FRAG_COORD
,
2392 0xf, ctx
->frag_coord
);
2395 /* Setup outputs: */
2396 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2397 setup_output(ctx
, var
);
2400 /* Setup registers (which should only be arrays): */
2401 nir_foreach_register(reg
, &ctx
->s
->registers
) {
2402 ir3_declare_array(ctx
, reg
);
2405 /* NOTE: need to do something more clever when we support >1 fxn */
2406 nir_foreach_register(reg
, &fxn
->registers
) {
2407 ir3_declare_array(ctx
, reg
);
2409 /* And emit the body: */
2411 emit_function(ctx
, fxn
);
2414 /* from NIR perspective, we actually have varying inputs. But the varying
2415 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2416 * only actual inputs are the sysvals.
2419 fixup_frag_inputs(struct ir3_context
*ctx
)
2421 struct ir3_shader_variant
*so
= ctx
->so
;
2422 struct ir3
*ir
= ctx
->ir
;
2425 /* sysvals should appear at the end of the inputs, drop everything else: */
2426 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
2429 /* at IR level, inputs are always blocks of 4 scalars: */
2432 ir
->inputs
= &ir
->inputs
[i
];
2436 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2437 * need to assign the tex state indexes for these after we know the
2441 fixup_astc_srgb(struct ir3_context
*ctx
)
2443 struct ir3_shader_variant
*so
= ctx
->so
;
2444 /* indexed by original tex idx, value is newly assigned alpha sampler
2445 * state tex idx. Zero is invalid since there is at least one sampler
2448 unsigned alt_tex_state
[16] = {0};
2449 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2452 so
->astc_srgb
.base
= tex_idx
;
2454 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2455 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2457 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2459 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2460 /* assign new alternate/alpha tex state slot: */
2461 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2462 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2463 so
->astc_srgb
.count
++;
2466 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2471 fixup_binning_pass(struct ir3_context
*ctx
)
2473 struct ir3_shader_variant
*so
= ctx
->so
;
2474 struct ir3
*ir
= ctx
->ir
;
2477 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2478 unsigned slot
= so
->outputs
[i
].slot
;
2480 /* throw away everything but first position/psize */
2481 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2483 so
->outputs
[j
] = so
->outputs
[i
];
2484 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2485 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2486 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2487 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2492 so
->outputs_count
= j
;
2493 ir
->noutputs
= j
* 4;
2497 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2498 struct ir3_shader_variant
*so
)
2500 struct ir3_context
*ctx
;
2502 struct ir3_instruction
**inputs
;
2503 unsigned i
, actual_in
, inloc
;
2504 int ret
= 0, max_bary
;
2508 ctx
= ir3_context_init(compiler
, so
);
2510 DBG("INIT failed!");
2515 emit_instructions(ctx
);
2518 DBG("EMIT failed!");
2523 ir
= so
->ir
= ctx
->ir
;
2525 /* keep track of the inputs from TGSI perspective.. */
2526 inputs
= ir
->inputs
;
2528 /* but fixup actual inputs for frag shader: */
2529 if (so
->type
== MESA_SHADER_FRAGMENT
)
2530 fixup_frag_inputs(ctx
);
2532 /* at this point, for binning pass, throw away unneeded outputs: */
2533 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
2534 fixup_binning_pass(ctx
);
2536 /* if we want half-precision outputs, mark the output registers
2539 if (so
->key
.half_precision
) {
2540 for (i
= 0; i
< ir
->noutputs
; i
++) {
2541 struct ir3_instruction
*out
= ir
->outputs
[i
];
2546 /* if frag shader writes z, that needs to be full precision: */
2547 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2550 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2551 /* output could be a fanout (ie. texture fetch output)
2552 * in which case we need to propagate the half-reg flag
2553 * up to the definer so that RA sees it:
2555 if (out
->opc
== OPC_META_FO
) {
2556 out
= out
->regs
[1]->instr
;
2557 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2560 if (out
->opc
== OPC_MOV
) {
2561 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2566 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2567 printf("BEFORE CP:\n");
2573 /* at this point, for binning pass, throw away unneeded outputs:
2574 * Note that for a6xx and later, we do this after ir3_cp to ensure
2575 * that the uniform/constant layout for BS and VS matches, so that
2576 * we can re-use same VS_CONST state group.
2578 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
2579 fixup_binning_pass(ctx
);
2581 /* Insert mov if there's same instruction for each output.
2582 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2584 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
2585 if (!ir
->outputs
[i
])
2587 for (unsigned j
= 0; j
< i
; j
++) {
2588 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
2590 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
2595 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2596 printf("BEFORE GROUPING:\n");
2600 ir3_sched_add_deps(ir
);
2602 /* Group left/right neighbors, inserting mov's where needed to
2607 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2608 printf("AFTER GROUPING:\n");
2614 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2615 printf("AFTER DEPTH:\n");
2619 ret
= ir3_sched(ir
);
2621 DBG("SCHED failed!");
2625 if (compiler
->gpu_id
>= 600) {
2626 ir3_a6xx_fixup_atomic_dests(ir
, so
);
2629 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2630 printf("AFTER SCHED:\n");
2634 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2640 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2641 printf("AFTER RA:\n");
2645 /* fixup input/outputs: */
2646 for (i
= 0; i
< so
->outputs_count
; i
++) {
2647 /* sometimes we get outputs that don't write the .x coord, like:
2649 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2651 * Presumably the result of varying packing and then eliminating
2652 * some unneeded varyings? Just skip head to the first valid
2653 * component of the output.
2655 for (unsigned j
= 0; j
< 4; j
++) {
2656 struct ir3_instruction
*instr
= ir
->outputs
[(i
*4) + j
];
2658 so
->outputs
[i
].regid
= instr
->regs
[0]->num
;
2664 /* Note that some or all channels of an input may be unused: */
2667 for (i
= 0; i
< so
->inputs_count
; i
++) {
2668 unsigned j
, reg
= regid(63,0), compmask
= 0, maxcomp
= 0;
2669 so
->inputs
[i
].ncomp
= 0;
2670 so
->inputs
[i
].inloc
= inloc
;
2671 for (j
= 0; j
< 4; j
++) {
2672 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2673 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2674 compmask
|= (1 << j
);
2675 reg
= in
->regs
[0]->num
- j
;
2677 so
->inputs
[i
].ncomp
++;
2678 if ((so
->type
== MESA_SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2680 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2681 in
->regs
[1]->iim_val
= inloc
+ j
;
2686 if ((so
->type
== MESA_SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
2688 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2690 } else if (!so
->inputs
[i
].sysval
) {
2691 so
->inputs
[i
].compmask
= compmask
;
2693 so
->inputs
[i
].regid
= reg
;
2697 fixup_astc_srgb(ctx
);
2699 /* We need to do legalize after (for frag shader's) the "bary.f"
2700 * offsets (inloc) have been assigned.
2702 ir3_legalize(ir
, &so
->num_samp
, &so
->has_ssbo
, &max_bary
);
2704 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2705 printf("AFTER LEGALIZE:\n");
2709 so
->branchstack
= ctx
->max_stack
;
2711 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2712 if (so
->type
== MESA_SHADER_VERTEX
)
2713 so
->total_in
= actual_in
;
2715 so
->total_in
= max_bary
+ 1;
2720 ir3_destroy(so
->ir
);
2723 ir3_context_free(ctx
);