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freedreno/ir3: re-work shader inputs/outputs
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
395 break;
396 case nir_op_b2f32:
397 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
398 break;
399 case nir_op_b2i8:
400 case nir_op_b2i16:
401 case nir_op_b2i32:
402 dst[0] = ir3_b2n(b, src[0]);
403 break;
404 case nir_op_i2b32:
405 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
406 dst[0]->cat2.condition = IR3_COND_NE;
407 dst[0] = ir3_n2b(b, dst[0]);
408 break;
409
410 case nir_op_fneg:
411 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
412 break;
413 case nir_op_fabs:
414 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
415 break;
416 case nir_op_fmax:
417 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
418 break;
419 case nir_op_fmin:
420 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
421 break;
422 case nir_op_fsat:
423 /* if there is just a single use of the src, and it supports
424 * (sat) bit, we can just fold the (sat) flag back to the
425 * src instruction and create a mov. This is easier for cp
426 * to eliminate.
427 *
428 * TODO probably opc_cat==4 is ok too
429 */
430 if (alu->src[0].src.is_ssa &&
431 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
432 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
433 src[0]->flags |= IR3_INSTR_SAT;
434 dst[0] = ir3_MOV(b, src[0], dst_type);
435 } else {
436 /* otherwise generate a max.f that saturates.. blob does
437 * similar (generating a cat2 mov using max.f)
438 */
439 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
440 dst[0]->flags |= IR3_INSTR_SAT;
441 }
442 break;
443 case nir_op_fmul:
444 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
445 break;
446 case nir_op_fadd:
447 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
448 break;
449 case nir_op_fsub:
450 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
451 break;
452 case nir_op_ffma:
453 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
454 break;
455 case nir_op_fddx:
456 case nir_op_fddx_coarse:
457 dst[0] = ir3_DSX(b, src[0], 0);
458 dst[0]->cat5.type = TYPE_F32;
459 break;
460 case nir_op_fddy:
461 case nir_op_fddy_coarse:
462 dst[0] = ir3_DSY(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 break;
466 case nir_op_flt32:
467 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
468 dst[0]->cat2.condition = IR3_COND_LT;
469 dst[0] = ir3_n2b(b, dst[0]);
470 break;
471 case nir_op_fge32:
472 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
473 dst[0]->cat2.condition = IR3_COND_GE;
474 dst[0] = ir3_n2b(b, dst[0]);
475 break;
476 case nir_op_feq32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_EQ;
479 dst[0] = ir3_n2b(b, dst[0]);
480 break;
481 case nir_op_fne32:
482 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
483 dst[0]->cat2.condition = IR3_COND_NE;
484 dst[0] = ir3_n2b(b, dst[0]);
485 break;
486 case nir_op_fceil:
487 dst[0] = ir3_CEIL_F(b, src[0], 0);
488 break;
489 case nir_op_ffloor:
490 dst[0] = ir3_FLOOR_F(b, src[0], 0);
491 break;
492 case nir_op_ftrunc:
493 dst[0] = ir3_TRUNC_F(b, src[0], 0);
494 break;
495 case nir_op_fround_even:
496 dst[0] = ir3_RNDNE_F(b, src[0], 0);
497 break;
498 case nir_op_fsign:
499 dst[0] = ir3_SIGN_F(b, src[0], 0);
500 break;
501
502 case nir_op_fsin:
503 dst[0] = ir3_SIN(b, src[0], 0);
504 break;
505 case nir_op_fcos:
506 dst[0] = ir3_COS(b, src[0], 0);
507 break;
508 case nir_op_frsq:
509 dst[0] = ir3_RSQ(b, src[0], 0);
510 break;
511 case nir_op_frcp:
512 dst[0] = ir3_RCP(b, src[0], 0);
513 break;
514 case nir_op_flog2:
515 dst[0] = ir3_LOG2(b, src[0], 0);
516 break;
517 case nir_op_fexp2:
518 dst[0] = ir3_EXP2(b, src[0], 0);
519 break;
520 case nir_op_fsqrt:
521 dst[0] = ir3_SQRT(b, src[0], 0);
522 break;
523
524 case nir_op_iabs:
525 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
526 break;
527 case nir_op_iadd:
528 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
529 break;
530 case nir_op_iand:
531 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
532 break;
533 case nir_op_imax:
534 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
535 break;
536 case nir_op_umax:
537 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_imin:
540 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_umin:
543 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umul_low:
546 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_imadsh_mix16:
549 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
550 break;
551 case nir_op_imad24_ir3:
552 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
553 break;
554 case nir_op_imul24:
555 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_ineg:
558 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
559 break;
560 case nir_op_inot:
561 dst[0] = ir3_NOT_B(b, src[0], 0);
562 break;
563 case nir_op_ior:
564 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_ishl:
567 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_ishr:
570 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_isub:
573 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ixor:
576 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
577 break;
578 case nir_op_ushr:
579 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
580 break;
581 case nir_op_ilt32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_LT;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ige32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_GE;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ieq32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_EQ;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ine32:
597 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_NE;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_ult32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_LT;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606 case nir_op_uge32:
607 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
608 dst[0]->cat2.condition = IR3_COND_GE;
609 dst[0] = ir3_n2b(b, dst[0]);
610 break;
611
612 case nir_op_b32csel: {
613 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
614 compile_assert(ctx, bs[1] == bs[2]);
615 /* the boolean condition is 32b even if src[1] and src[2] are
616 * half-precision, but sel.b16 wants all three src's to be the
617 * same type.
618 */
619 if (bs[1] < 32)
620 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
621 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
622 break;
623 }
624 case nir_op_bit_count: {
625 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
626 // double check on earlier gen's. Once half-precision support is
627 // in place, this should probably move to a NIR lowering pass:
628 struct ir3_instruction *hi, *lo;
629
630 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
631 TYPE_U32, TYPE_U16);
632 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
633
634 hi = ir3_CBITS_B(b, hi, 0);
635 lo = ir3_CBITS_B(b, lo, 0);
636
637 // TODO maybe the builders should default to making dst half-precision
638 // if the src's were half precision, to make this less awkward.. otoh
639 // we should probably just do this lowering in NIR.
640 hi->regs[0]->flags |= IR3_REG_HALF;
641 lo->regs[0]->flags |= IR3_REG_HALF;
642
643 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
644 dst[0]->regs[0]->flags |= IR3_REG_HALF;
645 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
646 break;
647 }
648 case nir_op_ifind_msb: {
649 struct ir3_instruction *cmp;
650 dst[0] = ir3_CLZ_S(b, src[0], 0);
651 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
652 cmp->cat2.condition = IR3_COND_GE;
653 dst[0] = ir3_SEL_B32(b,
654 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
655 cmp, 0, dst[0], 0);
656 break;
657 }
658 case nir_op_ufind_msb:
659 dst[0] = ir3_CLZ_B(b, src[0], 0);
660 dst[0] = ir3_SEL_B32(b,
661 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
662 src[0], 0, dst[0], 0);
663 break;
664 case nir_op_find_lsb:
665 dst[0] = ir3_BFREV_B(b, src[0], 0);
666 dst[0] = ir3_CLZ_B(b, dst[0], 0);
667 break;
668 case nir_op_bitfield_reverse:
669 dst[0] = ir3_BFREV_B(b, src[0], 0);
670 break;
671
672 default:
673 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
674 nir_op_infos[alu->op].name);
675 break;
676 }
677
678 ir3_put_dst(ctx, &alu->dest.dest);
679 }
680
681 /* handles direct/indirect UBO reads: */
682 static void
683 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
684 struct ir3_instruction **dst)
685 {
686 struct ir3_block *b = ctx->block;
687 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
688 /* UBO addresses are the first driver params, but subtract 2 here to
689 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
690 * is the uniforms: */
691 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
692 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
693 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
694
695 int off = 0;
696
697 /* First src is ubo index, which could either be an immed or not: */
698 src0 = ir3_get_src(ctx, &intr->src[0])[0];
699 if (is_same_type_mov(src0) &&
700 (src0->regs[1]->flags & IR3_REG_IMMED)) {
701 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
702 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
703 } else {
704 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
705 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
706
707 /* NOTE: since relative addressing is used, make sure constlen is
708 * at least big enough to cover all the UBO addresses, since the
709 * assembler won't know what the max address reg is.
710 */
711 ctx->so->constlen = MAX2(ctx->so->constlen,
712 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
713 }
714
715 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
716 addr = base_lo;
717
718 if (nir_src_is_const(intr->src[1])) {
719 off += nir_src_as_uint(intr->src[1]);
720 } else {
721 /* For load_ubo_indirect, second src is indirect offset: */
722 src1 = ir3_get_src(ctx, &intr->src[1])[0];
723
724 /* and add offset to addr: */
725 addr = ir3_ADD_S(b, addr, 0, src1, 0);
726 }
727
728 /* if offset is to large to encode in the ldg, split it out: */
729 if ((off + (intr->num_components * 4)) > 1024) {
730 /* split out the minimal amount to improve the odds that
731 * cp can fit the immediate in the add.s instruction:
732 */
733 unsigned off2 = off + (intr->num_components * 4) - 1024;
734 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
735 off -= off2;
736 }
737
738 if (ptrsz == 2) {
739 struct ir3_instruction *carry;
740
741 /* handle 32b rollover, ie:
742 * if (addr < base_lo)
743 * base_hi++
744 */
745 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
746 carry->cat2.condition = IR3_COND_LT;
747 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
748
749 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
750 }
751
752 for (int i = 0; i < intr->num_components; i++) {
753 struct ir3_instruction *load =
754 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
755 create_immed(b, off + i * 4), 0);
756 load->cat6.type = TYPE_U32;
757 dst[i] = load;
758 }
759 }
760
761 /* src[] = { block_index } */
762 static void
763 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
764 struct ir3_instruction **dst)
765 {
766 /* SSBO size stored as a const starting at ssbo_sizes: */
767 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
768 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
769 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
770 const_state->ssbo_size.off[blk_idx];
771
772 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
773
774 dst[0] = create_uniform(ctx->block, idx);
775 }
776
777 /* src[] = { offset }. const_index[] = { base } */
778 static void
779 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
780 struct ir3_instruction **dst)
781 {
782 struct ir3_block *b = ctx->block;
783 struct ir3_instruction *ldl, *offset;
784 unsigned base;
785
786 offset = ir3_get_src(ctx, &intr->src[0])[0];
787 base = nir_intrinsic_base(intr);
788
789 ldl = ir3_LDL(b, offset, 0,
790 create_immed(b, intr->num_components), 0,
791 create_immed(b, base), 0);
792
793 ldl->cat6.type = utype_dst(intr->dest);
794 ldl->regs[0]->wrmask = MASK(intr->num_components);
795
796 ldl->barrier_class = IR3_BARRIER_SHARED_R;
797 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
798
799 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
800 }
801
802 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
803 static void
804 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
805 {
806 struct ir3_block *b = ctx->block;
807 struct ir3_instruction *stl, *offset;
808 struct ir3_instruction * const *value;
809 unsigned base, wrmask;
810
811 value = ir3_get_src(ctx, &intr->src[0]);
812 offset = ir3_get_src(ctx, &intr->src[1])[0];
813
814 base = nir_intrinsic_base(intr);
815 wrmask = nir_intrinsic_write_mask(intr);
816
817 /* Combine groups of consecutive enabled channels in one write
818 * message. We use ffs to find the first enabled channel and then ffs on
819 * the bit-inverse, down-shifted writemask to determine the length of
820 * the block of enabled bits.
821 *
822 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
823 */
824 while (wrmask) {
825 unsigned first_component = ffs(wrmask) - 1;
826 unsigned length = ffs(~(wrmask >> first_component)) - 1;
827
828 stl = ir3_STL(b, offset, 0,
829 ir3_create_collect(ctx, &value[first_component], length), 0,
830 create_immed(b, length), 0);
831 stl->cat6.dst_offset = first_component + base;
832 stl->cat6.type = utype_src(intr->src[0]);
833 stl->barrier_class = IR3_BARRIER_SHARED_W;
834 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
835
836 array_insert(b, b->keeps, stl);
837
838 /* Clear the bits in the writemask that we just wrote, then try
839 * again to see if more channels are left.
840 */
841 wrmask &= (15 << (first_component + length));
842 }
843 }
844
845 /* src[] = { offset }. const_index[] = { base } */
846 static void
847 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
848 struct ir3_instruction **dst)
849 {
850 struct ir3_block *b = ctx->block;
851 struct ir3_instruction *load, *offset;
852 unsigned base;
853
854 offset = ir3_get_src(ctx, &intr->src[0])[0];
855 base = nir_intrinsic_base(intr);
856
857 load = ir3_LDLW(b, offset, 0,
858 create_immed(b, intr->num_components), 0,
859 create_immed(b, base), 0);
860
861 load->cat6.type = utype_dst(intr->dest);
862 load->regs[0]->wrmask = MASK(intr->num_components);
863
864 load->barrier_class = IR3_BARRIER_SHARED_R;
865 load->barrier_conflict = IR3_BARRIER_SHARED_W;
866
867 ir3_split_dest(b, dst, load, 0, intr->num_components);
868 }
869
870 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
871 static void
872 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
873 {
874 struct ir3_block *b = ctx->block;
875 struct ir3_instruction *store, *offset;
876 struct ir3_instruction * const *value;
877 unsigned base, wrmask;
878
879 value = ir3_get_src(ctx, &intr->src[0]);
880 offset = ir3_get_src(ctx, &intr->src[1])[0];
881
882 base = nir_intrinsic_base(intr);
883 wrmask = nir_intrinsic_write_mask(intr);
884
885 /* Combine groups of consecutive enabled channels in one write
886 * message. We use ffs to find the first enabled channel and then ffs on
887 * the bit-inverse, down-shifted writemask to determine the length of
888 * the block of enabled bits.
889 *
890 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
891 */
892 while (wrmask) {
893 unsigned first_component = ffs(wrmask) - 1;
894 unsigned length = ffs(~(wrmask >> first_component)) - 1;
895
896 store = ir3_STLW(b, offset, 0,
897 ir3_create_collect(ctx, &value[first_component], length), 0,
898 create_immed(b, length), 0);
899
900 store->cat6.dst_offset = first_component + base;
901 store->cat6.type = utype_src(intr->src[0]);
902 store->barrier_class = IR3_BARRIER_SHARED_W;
903 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
904
905 array_insert(b, b->keeps, store);
906
907 /* Clear the bits in the writemask that we just wrote, then try
908 * again to see if more channels are left.
909 */
910 wrmask &= (15 << (first_component + length));
911 }
912 }
913
914 /*
915 * CS shared variable atomic intrinsics
916 *
917 * All of the shared variable atomic memory operations read a value from
918 * memory, compute a new value using one of the operations below, write the
919 * new value to memory, and return the original value read.
920 *
921 * All operations take 2 sources except CompSwap that takes 3. These
922 * sources represent:
923 *
924 * 0: The offset into the shared variable storage region that the atomic
925 * operation will operate on.
926 * 1: The data parameter to the atomic function (i.e. the value to add
927 * in shared_atomic_add, etc).
928 * 2: For CompSwap only: the second data parameter.
929 */
930 static struct ir3_instruction *
931 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
932 {
933 struct ir3_block *b = ctx->block;
934 struct ir3_instruction *atomic, *src0, *src1;
935 type_t type = TYPE_U32;
936
937 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
938 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
939
940 switch (intr->intrinsic) {
941 case nir_intrinsic_shared_atomic_add:
942 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
943 break;
944 case nir_intrinsic_shared_atomic_imin:
945 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
946 type = TYPE_S32;
947 break;
948 case nir_intrinsic_shared_atomic_umin:
949 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
950 break;
951 case nir_intrinsic_shared_atomic_imax:
952 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
953 type = TYPE_S32;
954 break;
955 case nir_intrinsic_shared_atomic_umax:
956 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
957 break;
958 case nir_intrinsic_shared_atomic_and:
959 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
960 break;
961 case nir_intrinsic_shared_atomic_or:
962 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
963 break;
964 case nir_intrinsic_shared_atomic_xor:
965 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
966 break;
967 case nir_intrinsic_shared_atomic_exchange:
968 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
969 break;
970 case nir_intrinsic_shared_atomic_comp_swap:
971 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
972 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
973 ir3_get_src(ctx, &intr->src[2])[0],
974 src1,
975 }, 2);
976 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
977 break;
978 default:
979 unreachable("boo");
980 }
981
982 atomic->cat6.iim_val = 1;
983 atomic->cat6.d = 1;
984 atomic->cat6.type = type;
985 atomic->barrier_class = IR3_BARRIER_SHARED_W;
986 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
987
988 /* even if nothing consume the result, we can't DCE the instruction: */
989 array_insert(b, b->keeps, atomic);
990
991 return atomic;
992 }
993
994 /* TODO handle actual indirect/dynamic case.. which is going to be weird
995 * to handle with the image_mapping table..
996 */
997 static struct ir3_instruction *
998 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
999 {
1000 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1001 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1002 struct ir3_instruction *texture, *sampler;
1003
1004 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1005 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1006
1007 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1008 sampler,
1009 texture,
1010 }, 2);
1011 }
1012
1013 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1014 static void
1015 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1016 struct ir3_instruction **dst)
1017 {
1018 struct ir3_block *b = ctx->block;
1019 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1020 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1021 struct ir3_instruction *sam;
1022 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1023 struct ir3_instruction *coords[4];
1024 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1025 type_t type = ir3_get_image_type(var);
1026
1027 /* hmm, this seems a bit odd, but it is what blob does and (at least
1028 * a5xx) just faults on bogus addresses otherwise:
1029 */
1030 if (flags & IR3_INSTR_3D) {
1031 flags &= ~IR3_INSTR_3D;
1032 flags |= IR3_INSTR_A;
1033 }
1034
1035 for (unsigned i = 0; i < ncoords; i++)
1036 coords[i] = src0[i];
1037
1038 if (ncoords == 1)
1039 coords[ncoords++] = create_immed(b, 0);
1040
1041 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1042 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1043
1044 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1045 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1046
1047 ir3_split_dest(b, dst, sam, 0, 4);
1048 }
1049
1050 static void
1051 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1052 struct ir3_instruction **dst)
1053 {
1054 struct ir3_block *b = ctx->block;
1055 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1056 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1057 struct ir3_instruction *sam, *lod;
1058 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1059
1060 lod = create_immed(b, 0);
1061 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1062 samp_tex, lod, NULL);
1063
1064 /* Array size actually ends up in .w rather than .z. This doesn't
1065 * matter for miplevel 0, but for higher mips the value in z is
1066 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1067 * returned, which means that we have to add 1 to it for arrays for
1068 * a3xx.
1069 *
1070 * Note use a temporary dst and then copy, since the size of the dst
1071 * array that is passed in is based on nir's understanding of the
1072 * result size, not the hardware's
1073 */
1074 struct ir3_instruction *tmp[4];
1075
1076 ir3_split_dest(b, tmp, sam, 0, 4);
1077
1078 /* get_size instruction returns size in bytes instead of texels
1079 * for imageBuffer, so we need to divide it by the pixel size
1080 * of the image format.
1081 *
1082 * TODO: This is at least true on a5xx. Check other gens.
1083 */
1084 enum glsl_sampler_dim dim =
1085 glsl_get_sampler_dim(glsl_without_array(var->type));
1086 if (dim == GLSL_SAMPLER_DIM_BUF) {
1087 /* Since all the possible values the divisor can take are
1088 * power-of-two (4, 8, or 16), the division is implemented
1089 * as a shift-right.
1090 * During shader setup, the log2 of the image format's
1091 * bytes-per-pixel should have been emitted in 2nd slot of
1092 * image_dims. See ir3_shader::emit_image_dims().
1093 */
1094 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1095 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1096 const_state->image_dims.off[var->data.driver_location];
1097 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1098
1099 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1100 }
1101
1102 for (unsigned i = 0; i < ncoords; i++)
1103 dst[i] = tmp[i];
1104
1105 if (flags & IR3_INSTR_A) {
1106 if (ctx->compiler->levels_add_one) {
1107 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1108 } else {
1109 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1110 }
1111 }
1112 }
1113
1114 static void
1115 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1116 {
1117 struct ir3_block *b = ctx->block;
1118 struct ir3_instruction *barrier;
1119
1120 switch (intr->intrinsic) {
1121 case nir_intrinsic_barrier:
1122 barrier = ir3_BAR(b);
1123 barrier->cat7.g = true;
1124 barrier->cat7.l = true;
1125 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1126 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1127 break;
1128 case nir_intrinsic_memory_barrier:
1129 barrier = ir3_FENCE(b);
1130 barrier->cat7.g = true;
1131 barrier->cat7.r = true;
1132 barrier->cat7.w = true;
1133 barrier->cat7.l = true;
1134 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1135 IR3_BARRIER_BUFFER_W;
1136 barrier->barrier_conflict =
1137 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1138 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1139 break;
1140 case nir_intrinsic_memory_barrier_atomic_counter:
1141 case nir_intrinsic_memory_barrier_buffer:
1142 barrier = ir3_FENCE(b);
1143 barrier->cat7.g = true;
1144 barrier->cat7.r = true;
1145 barrier->cat7.w = true;
1146 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1147 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1148 IR3_BARRIER_BUFFER_W;
1149 break;
1150 case nir_intrinsic_memory_barrier_image:
1151 // TODO double check if this should have .g set
1152 barrier = ir3_FENCE(b);
1153 barrier->cat7.g = true;
1154 barrier->cat7.r = true;
1155 barrier->cat7.w = true;
1156 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1157 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1158 IR3_BARRIER_IMAGE_W;
1159 break;
1160 case nir_intrinsic_memory_barrier_shared:
1161 barrier = ir3_FENCE(b);
1162 barrier->cat7.g = true;
1163 barrier->cat7.l = true;
1164 barrier->cat7.r = true;
1165 barrier->cat7.w = true;
1166 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1167 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1168 IR3_BARRIER_SHARED_W;
1169 break;
1170 case nir_intrinsic_group_memory_barrier:
1171 barrier = ir3_FENCE(b);
1172 barrier->cat7.g = true;
1173 barrier->cat7.l = true;
1174 barrier->cat7.r = true;
1175 barrier->cat7.w = true;
1176 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1177 IR3_BARRIER_IMAGE_W |
1178 IR3_BARRIER_BUFFER_W;
1179 barrier->barrier_conflict =
1180 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1181 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1182 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1183 break;
1184 default:
1185 unreachable("boo");
1186 }
1187
1188 /* make sure barrier doesn't get DCE'd */
1189 array_insert(b, b->keeps, barrier);
1190 }
1191
1192 static void add_sysval_input_compmask(struct ir3_context *ctx,
1193 gl_system_value slot, unsigned compmask,
1194 struct ir3_instruction *instr)
1195 {
1196 struct ir3_shader_variant *so = ctx->so;
1197 unsigned n = so->inputs_count++;
1198
1199 assert(instr->opc == OPC_META_INPUT);
1200 instr->input.inidx = n;
1201 instr->input.sysval = slot;
1202
1203 so->inputs[n].sysval = true;
1204 so->inputs[n].slot = slot;
1205 so->inputs[n].compmask = compmask;
1206 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1207 so->total_in++;
1208 }
1209
1210 static struct ir3_instruction *
1211 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1212 unsigned compmask)
1213 {
1214 assert(compmask);
1215 struct ir3_instruction *sysval = create_input_compmask(ctx, 0, compmask);
1216 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1217 return sysval;
1218 }
1219
1220 static struct ir3_instruction *
1221 get_barycentric_centroid(struct ir3_context *ctx)
1222 {
1223 if (!ctx->ij_centroid) {
1224 struct ir3_instruction *xy[2];
1225 struct ir3_instruction *ij;
1226
1227 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1228 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1229
1230 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1231 }
1232
1233 return ctx->ij_centroid;
1234 }
1235
1236 static struct ir3_instruction *
1237 get_barycentric_sample(struct ir3_context *ctx)
1238 {
1239 if (!ctx->ij_sample) {
1240 struct ir3_instruction *xy[2];
1241 struct ir3_instruction *ij;
1242
1243 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1244 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1245
1246 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1247 }
1248
1249 return ctx->ij_sample;
1250 }
1251
1252 static struct ir3_instruction *
1253 get_barycentric_pixel(struct ir3_context *ctx)
1254 {
1255 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1256 * this to create ij_pixel only on demand:
1257 */
1258 return ctx->ij_pixel;
1259 }
1260
1261 static struct ir3_instruction *
1262 get_frag_coord(struct ir3_context *ctx)
1263 {
1264 if (!ctx->frag_coord) {
1265 struct ir3_block *b = ctx->block;
1266 struct ir3_instruction *xyzw[4];
1267 struct ir3_instruction *hw_frag_coord;
1268
1269 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1270 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1271
1272 /* for frag_coord.xy, we get unsigned values.. we need
1273 * to subtract (integer) 8 and divide by 16 (right-
1274 * shift by 4) then convert to float:
1275 *
1276 * sub.s tmp, src, 8
1277 * shr.b tmp, tmp, 4
1278 * mov.u32f32 dst, tmp
1279 *
1280 */
1281 for (int i = 0; i < 2; i++) {
1282 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1283 create_immed(b, 8), 0);
1284 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1285 create_immed(b, 4), 0);
1286 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1287 }
1288
1289 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1290 ctx->so->frag_coord = true;
1291 }
1292
1293 return ctx->frag_coord;
1294 }
1295
1296 static void
1297 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1298 {
1299 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1300 struct ir3_instruction **dst;
1301 struct ir3_instruction * const *src;
1302 struct ir3_block *b = ctx->block;
1303 int idx, comp;
1304
1305 if (info->has_dest) {
1306 unsigned n = nir_intrinsic_dest_components(intr);
1307 dst = ir3_get_dst(ctx, &intr->dest, n);
1308 } else {
1309 dst = NULL;
1310 }
1311
1312 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1313 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1314
1315 switch (intr->intrinsic) {
1316 case nir_intrinsic_load_uniform:
1317 idx = nir_intrinsic_base(intr);
1318 if (nir_src_is_const(intr->src[0])) {
1319 idx += nir_src_as_uint(intr->src[0]);
1320 for (int i = 0; i < intr->num_components; i++) {
1321 dst[i] = create_uniform_typed(b, idx + i,
1322 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1323 }
1324 } else {
1325 src = ir3_get_src(ctx, &intr->src[0]);
1326 for (int i = 0; i < intr->num_components; i++) {
1327 dst[i] = create_uniform_indirect(b, idx + i,
1328 ir3_get_addr(ctx, src[0], 1));
1329 }
1330 /* NOTE: if relative addressing is used, we set
1331 * constlen in the compiler (to worst-case value)
1332 * since we don't know in the assembler what the max
1333 * addr reg value can be:
1334 */
1335 ctx->so->constlen = MAX2(ctx->so->constlen,
1336 ctx->so->shader->ubo_state.size / 16);
1337 }
1338 break;
1339
1340 case nir_intrinsic_load_vs_primitive_stride_ir3:
1341 dst[0] = create_uniform(b, primitive_param + 0);
1342 break;
1343 case nir_intrinsic_load_vs_vertex_stride_ir3:
1344 dst[0] = create_uniform(b, primitive_param + 1);
1345 break;
1346 case nir_intrinsic_load_hs_patch_stride_ir3:
1347 dst[0] = create_uniform(b, primitive_param + 2);
1348 break;
1349 case nir_intrinsic_load_patch_vertices_in:
1350 dst[0] = create_uniform(b, primitive_param + 3);
1351 break;
1352 case nir_intrinsic_load_tess_param_base_ir3:
1353 dst[0] = create_uniform(b, primitive_param + 4);
1354 dst[1] = create_uniform(b, primitive_param + 5);
1355 break;
1356 case nir_intrinsic_load_tess_factor_base_ir3:
1357 dst[0] = create_uniform(b, primitive_param + 6);
1358 dst[1] = create_uniform(b, primitive_param + 7);
1359 break;
1360
1361 case nir_intrinsic_load_primitive_location_ir3:
1362 idx = nir_intrinsic_driver_location(intr);
1363 dst[0] = create_uniform(b, primitive_map + idx);
1364 break;
1365
1366 case nir_intrinsic_load_gs_header_ir3:
1367 dst[0] = ctx->gs_header;
1368 break;
1369 case nir_intrinsic_load_tcs_header_ir3:
1370 dst[0] = ctx->tcs_header;
1371 break;
1372
1373 case nir_intrinsic_load_primitive_id:
1374 dst[0] = ctx->primitive_id;
1375 break;
1376
1377 case nir_intrinsic_load_tess_coord:
1378 if (!ctx->tess_coord) {
1379 ctx->tess_coord =
1380 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1381 }
1382 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1383
1384 /* Unused, but ir3_put_dst() below wants to free something */
1385 dst[2] = create_immed(b, 0);
1386 break;
1387
1388 case nir_intrinsic_end_patch_ir3:
1389 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1390 struct ir3_instruction *end = ir3_ENDPATCH(b);
1391 array_insert(b, b->keeps, end);
1392
1393 end->barrier_class = IR3_BARRIER_EVERYTHING;
1394 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1395 break;
1396
1397 case nir_intrinsic_store_global_ir3: {
1398 struct ir3_instruction *value, *addr, *offset;
1399
1400 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1401 ir3_get_src(ctx, &intr->src[1])[0],
1402 ir3_get_src(ctx, &intr->src[1])[1]
1403 }, 2);
1404
1405 offset = ir3_get_src(ctx, &intr->src[2])[0];
1406
1407 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1408 intr->num_components);
1409
1410 struct ir3_instruction *stg =
1411 ir3_STG_G(ctx->block, addr, 0, value, 0,
1412 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1413 stg->cat6.type = TYPE_U32;
1414 stg->cat6.iim_val = 1;
1415
1416 array_insert(b, b->keeps, stg);
1417
1418 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1419 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1420 break;
1421 }
1422
1423 case nir_intrinsic_load_global_ir3: {
1424 struct ir3_instruction *addr, *offset;
1425
1426 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1427 ir3_get_src(ctx, &intr->src[0])[0],
1428 ir3_get_src(ctx, &intr->src[0])[1]
1429 }, 2);
1430
1431 offset = ir3_get_src(ctx, &intr->src[1])[0];
1432
1433 struct ir3_instruction *load =
1434 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1435 0, offset, 0);
1436 load->cat6.type = TYPE_U32;
1437 load->regs[0]->wrmask = MASK(intr->num_components);
1438
1439 load->barrier_class = IR3_BARRIER_BUFFER_R;
1440 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1441
1442 ir3_split_dest(b, dst, load, 0, intr->num_components);
1443 break;
1444 }
1445
1446 case nir_intrinsic_load_ubo:
1447 emit_intrinsic_load_ubo(ctx, intr, dst);
1448 break;
1449 case nir_intrinsic_load_frag_coord:
1450 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1451 break;
1452 case nir_intrinsic_load_sample_pos_from_id: {
1453 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1454 * but that doesn't seem necessary.
1455 */
1456 struct ir3_instruction *offset =
1457 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1458 offset->regs[0]->wrmask = 0x3;
1459 offset->cat5.type = TYPE_F32;
1460
1461 ir3_split_dest(b, dst, offset, 0, 2);
1462
1463 break;
1464 }
1465 case nir_intrinsic_load_size_ir3:
1466 if (!ctx->ij_size) {
1467 ctx->ij_size =
1468 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1469 }
1470 dst[0] = ctx->ij_size;
1471 break;
1472 case nir_intrinsic_load_barycentric_centroid:
1473 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1474 break;
1475 case nir_intrinsic_load_barycentric_sample:
1476 if (ctx->so->key.msaa) {
1477 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1478 } else {
1479 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1480 }
1481 break;
1482 case nir_intrinsic_load_barycentric_pixel:
1483 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1484 break;
1485 case nir_intrinsic_load_interpolated_input:
1486 idx = nir_intrinsic_base(intr);
1487 comp = nir_intrinsic_component(intr);
1488 src = ir3_get_src(ctx, &intr->src[0]);
1489 if (nir_src_is_const(intr->src[1])) {
1490 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1491 idx += nir_src_as_uint(intr->src[1]);
1492 for (int i = 0; i < intr->num_components; i++) {
1493 unsigned inloc = idx * 4 + i + comp;
1494 if (ctx->so->inputs[idx].bary &&
1495 !ctx->so->inputs[idx].use_ldlv) {
1496 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1497 } else {
1498 /* for non-varyings use the pre-setup input, since
1499 * that is easier than mapping things back to a
1500 * nir_variable to figure out what it is.
1501 */
1502 dst[i] = ctx->ir->inputs[inloc];
1503 }
1504 }
1505 } else {
1506 ir3_context_error(ctx, "unhandled");
1507 }
1508 break;
1509 case nir_intrinsic_load_input:
1510 idx = nir_intrinsic_base(intr);
1511 comp = nir_intrinsic_component(intr);
1512 if (nir_src_is_const(intr->src[0])) {
1513 idx += nir_src_as_uint(intr->src[0]);
1514 for (int i = 0; i < intr->num_components; i++) {
1515 unsigned n = idx * 4 + i + comp;
1516 dst[i] = ctx->inputs[n];
1517 compile_assert(ctx, ctx->inputs[n]);
1518 }
1519 } else {
1520 src = ir3_get_src(ctx, &intr->src[0]);
1521 struct ir3_instruction *collect =
1522 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1523 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1524 for (int i = 0; i < intr->num_components; i++) {
1525 unsigned n = idx * 4 + i + comp;
1526 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1527 n, addr, collect);
1528 }
1529 }
1530 break;
1531 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1532 * pass and replaced by an ir3-specifc version that adds the
1533 * dword-offset in the last source.
1534 */
1535 case nir_intrinsic_load_ssbo_ir3:
1536 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1537 break;
1538 case nir_intrinsic_store_ssbo_ir3:
1539 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1540 !ctx->s->info.fs.early_fragment_tests)
1541 ctx->so->no_earlyz = true;
1542 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1543 break;
1544 case nir_intrinsic_get_buffer_size:
1545 emit_intrinsic_ssbo_size(ctx, intr, dst);
1546 break;
1547 case nir_intrinsic_ssbo_atomic_add_ir3:
1548 case nir_intrinsic_ssbo_atomic_imin_ir3:
1549 case nir_intrinsic_ssbo_atomic_umin_ir3:
1550 case nir_intrinsic_ssbo_atomic_imax_ir3:
1551 case nir_intrinsic_ssbo_atomic_umax_ir3:
1552 case nir_intrinsic_ssbo_atomic_and_ir3:
1553 case nir_intrinsic_ssbo_atomic_or_ir3:
1554 case nir_intrinsic_ssbo_atomic_xor_ir3:
1555 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1556 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1557 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1558 !ctx->s->info.fs.early_fragment_tests)
1559 ctx->so->no_earlyz = true;
1560 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1561 break;
1562 case nir_intrinsic_load_shared:
1563 emit_intrinsic_load_shared(ctx, intr, dst);
1564 break;
1565 case nir_intrinsic_store_shared:
1566 emit_intrinsic_store_shared(ctx, intr);
1567 break;
1568 case nir_intrinsic_shared_atomic_add:
1569 case nir_intrinsic_shared_atomic_imin:
1570 case nir_intrinsic_shared_atomic_umin:
1571 case nir_intrinsic_shared_atomic_imax:
1572 case nir_intrinsic_shared_atomic_umax:
1573 case nir_intrinsic_shared_atomic_and:
1574 case nir_intrinsic_shared_atomic_or:
1575 case nir_intrinsic_shared_atomic_xor:
1576 case nir_intrinsic_shared_atomic_exchange:
1577 case nir_intrinsic_shared_atomic_comp_swap:
1578 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1579 break;
1580 case nir_intrinsic_image_deref_load:
1581 emit_intrinsic_load_image(ctx, intr, dst);
1582 break;
1583 case nir_intrinsic_image_deref_store:
1584 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1585 !ctx->s->info.fs.early_fragment_tests)
1586 ctx->so->no_earlyz = true;
1587 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1588 break;
1589 case nir_intrinsic_image_deref_size:
1590 emit_intrinsic_image_size(ctx, intr, dst);
1591 break;
1592 case nir_intrinsic_image_deref_atomic_add:
1593 case nir_intrinsic_image_deref_atomic_imin:
1594 case nir_intrinsic_image_deref_atomic_umin:
1595 case nir_intrinsic_image_deref_atomic_imax:
1596 case nir_intrinsic_image_deref_atomic_umax:
1597 case nir_intrinsic_image_deref_atomic_and:
1598 case nir_intrinsic_image_deref_atomic_or:
1599 case nir_intrinsic_image_deref_atomic_xor:
1600 case nir_intrinsic_image_deref_atomic_exchange:
1601 case nir_intrinsic_image_deref_atomic_comp_swap:
1602 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1603 !ctx->s->info.fs.early_fragment_tests)
1604 ctx->so->no_earlyz = true;
1605 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1606 break;
1607 case nir_intrinsic_barrier:
1608 case nir_intrinsic_memory_barrier:
1609 case nir_intrinsic_group_memory_barrier:
1610 case nir_intrinsic_memory_barrier_atomic_counter:
1611 case nir_intrinsic_memory_barrier_buffer:
1612 case nir_intrinsic_memory_barrier_image:
1613 case nir_intrinsic_memory_barrier_shared:
1614 emit_intrinsic_barrier(ctx, intr);
1615 /* note that blk ptr no longer valid, make that obvious: */
1616 b = NULL;
1617 break;
1618 case nir_intrinsic_store_output:
1619 idx = nir_intrinsic_base(intr);
1620 comp = nir_intrinsic_component(intr);
1621 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1622 idx += nir_src_as_uint(intr->src[1]);
1623
1624 src = ir3_get_src(ctx, &intr->src[0]);
1625 for (int i = 0; i < intr->num_components; i++) {
1626 unsigned n = idx * 4 + i + comp;
1627 ctx->outputs[n] = src[i];
1628 }
1629 break;
1630 case nir_intrinsic_load_base_vertex:
1631 case nir_intrinsic_load_first_vertex:
1632 if (!ctx->basevertex) {
1633 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1634 }
1635 dst[0] = ctx->basevertex;
1636 break;
1637 case nir_intrinsic_load_vertex_id_zero_base:
1638 case nir_intrinsic_load_vertex_id:
1639 if (!ctx->vertex_id) {
1640 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1641 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1642 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1643 }
1644 dst[0] = ctx->vertex_id;
1645 break;
1646 case nir_intrinsic_load_instance_id:
1647 if (!ctx->instance_id) {
1648 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1649 }
1650 dst[0] = ctx->instance_id;
1651 break;
1652 case nir_intrinsic_load_sample_id:
1653 ctx->so->per_samp = true;
1654 /* fall-thru */
1655 case nir_intrinsic_load_sample_id_no_per_sample:
1656 if (!ctx->samp_id) {
1657 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1658 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1659 }
1660 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1661 break;
1662 case nir_intrinsic_load_sample_mask_in:
1663 if (!ctx->samp_mask_in) {
1664 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1665 }
1666 dst[0] = ctx->samp_mask_in;
1667 break;
1668 case nir_intrinsic_load_user_clip_plane:
1669 idx = nir_intrinsic_ucp_id(intr);
1670 for (int i = 0; i < intr->num_components; i++) {
1671 unsigned n = idx * 4 + i;
1672 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1673 }
1674 break;
1675 case nir_intrinsic_load_front_face:
1676 if (!ctx->frag_face) {
1677 ctx->so->frag_face = true;
1678 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1679 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1680 }
1681 /* for fragface, we get -1 for back and 0 for front. However this is
1682 * the inverse of what nir expects (where ~0 is true).
1683 */
1684 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1685 dst[0] = ir3_NOT_B(b, dst[0], 0);
1686 break;
1687 case nir_intrinsic_load_local_invocation_id:
1688 if (!ctx->local_invocation_id) {
1689 ctx->local_invocation_id =
1690 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1691 }
1692 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1693 break;
1694 case nir_intrinsic_load_work_group_id:
1695 if (!ctx->work_group_id) {
1696 ctx->work_group_id =
1697 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1698 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1699 }
1700 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1701 break;
1702 case nir_intrinsic_load_num_work_groups:
1703 for (int i = 0; i < intr->num_components; i++) {
1704 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1705 }
1706 break;
1707 case nir_intrinsic_load_local_group_size:
1708 for (int i = 0; i < intr->num_components; i++) {
1709 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1710 }
1711 break;
1712 case nir_intrinsic_discard_if:
1713 case nir_intrinsic_discard: {
1714 struct ir3_instruction *cond, *kill;
1715
1716 if (intr->intrinsic == nir_intrinsic_discard_if) {
1717 /* conditional discard: */
1718 src = ir3_get_src(ctx, &intr->src[0]);
1719 cond = ir3_b2n(b, src[0]);
1720 } else {
1721 /* unconditional discard: */
1722 cond = create_immed(b, 1);
1723 }
1724
1725 /* NOTE: only cmps.*.* can write p0.x: */
1726 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1727 cond->cat2.condition = IR3_COND_NE;
1728
1729 /* condition always goes in predicate register: */
1730 cond->regs[0]->num = regid(REG_P0, 0);
1731 cond->regs[0]->flags &= ~IR3_REG_SSA;
1732
1733 kill = ir3_KILL(b, cond, 0);
1734 array_insert(ctx->ir, ctx->ir->predicates, kill);
1735
1736 array_insert(b, b->keeps, kill);
1737 ctx->so->no_earlyz = true;
1738
1739 break;
1740 }
1741
1742 case nir_intrinsic_cond_end_ir3: {
1743 struct ir3_instruction *cond, *kill;
1744
1745 src = ir3_get_src(ctx, &intr->src[0]);
1746 cond = ir3_b2n(b, src[0]);
1747
1748 /* NOTE: only cmps.*.* can write p0.x: */
1749 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1750 cond->cat2.condition = IR3_COND_NE;
1751
1752 /* condition always goes in predicate register: */
1753 cond->regs[0]->num = regid(REG_P0, 0);
1754
1755 kill = ir3_CONDEND(b, cond, 0);
1756
1757 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1758 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1759
1760 array_insert(ctx->ir, ctx->ir->predicates, kill);
1761 array_insert(b, b->keeps, kill);
1762 break;
1763 }
1764
1765 case nir_intrinsic_load_shared_ir3:
1766 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1767 break;
1768 case nir_intrinsic_store_shared_ir3:
1769 emit_intrinsic_store_shared_ir3(ctx, intr);
1770 break;
1771 default:
1772 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1773 nir_intrinsic_infos[intr->intrinsic].name);
1774 break;
1775 }
1776
1777 if (info->has_dest)
1778 ir3_put_dst(ctx, &intr->dest);
1779 }
1780
1781 static void
1782 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1783 {
1784 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1785 instr->def.num_components);
1786
1787 if (instr->def.bit_size < 32) {
1788 for (int i = 0; i < instr->def.num_components; i++)
1789 dst[i] = create_immed_typed(ctx->block,
1790 instr->value[i].u16,
1791 TYPE_U16);
1792 } else {
1793 for (int i = 0; i < instr->def.num_components; i++)
1794 dst[i] = create_immed_typed(ctx->block,
1795 instr->value[i].u32,
1796 TYPE_U32);
1797 }
1798
1799 }
1800
1801 static void
1802 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1803 {
1804 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1805 undef->def.num_components);
1806 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1807
1808 /* backend doesn't want undefined instructions, so just plug
1809 * in 0.0..
1810 */
1811 for (int i = 0; i < undef->def.num_components; i++)
1812 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1813 }
1814
1815 /*
1816 * texture fetch/sample instructions:
1817 */
1818
1819 static void
1820 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1821 {
1822 unsigned coords, flags = 0;
1823
1824 /* note: would use tex->coord_components.. except txs.. also,
1825 * since array index goes after shadow ref, we don't want to
1826 * count it:
1827 */
1828 switch (tex->sampler_dim) {
1829 case GLSL_SAMPLER_DIM_1D:
1830 case GLSL_SAMPLER_DIM_BUF:
1831 coords = 1;
1832 break;
1833 case GLSL_SAMPLER_DIM_2D:
1834 case GLSL_SAMPLER_DIM_RECT:
1835 case GLSL_SAMPLER_DIM_EXTERNAL:
1836 case GLSL_SAMPLER_DIM_MS:
1837 coords = 2;
1838 break;
1839 case GLSL_SAMPLER_DIM_3D:
1840 case GLSL_SAMPLER_DIM_CUBE:
1841 coords = 3;
1842 flags |= IR3_INSTR_3D;
1843 break;
1844 default:
1845 unreachable("bad sampler_dim");
1846 }
1847
1848 if (tex->is_shadow && tex->op != nir_texop_lod)
1849 flags |= IR3_INSTR_S;
1850
1851 if (tex->is_array && tex->op != nir_texop_lod)
1852 flags |= IR3_INSTR_A;
1853
1854 *flagsp = flags;
1855 *coordsp = coords;
1856 }
1857
1858 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1859 * or immediate (in which case it will get lowered later to a non .s2en
1860 * version of the tex instruction which encode tex/samp as immediates:
1861 */
1862 static struct ir3_instruction *
1863 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1864 {
1865 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1866 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1867 struct ir3_instruction *texture, *sampler;
1868
1869 if (texture_idx >= 0) {
1870 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1871 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1872 } else {
1873 /* TODO what to do for dynamic case? I guess we only need the
1874 * max index for astc srgb workaround so maybe not a problem
1875 * to worry about if we don't enable indirect samplers for
1876 * a4xx?
1877 */
1878 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1879 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1880 }
1881
1882 if (sampler_idx >= 0) {
1883 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1884 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1885 } else {
1886 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1887 }
1888
1889 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1890 sampler,
1891 texture,
1892 }, 2);
1893 }
1894
1895 static void
1896 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1897 {
1898 struct ir3_block *b = ctx->block;
1899 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1900 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1901 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1902 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1903 unsigned i, coords, flags, ncomp;
1904 unsigned nsrc0 = 0, nsrc1 = 0;
1905 type_t type;
1906 opc_t opc = 0;
1907
1908 ncomp = nir_dest_num_components(tex->dest);
1909
1910 coord = off = ddx = ddy = NULL;
1911 lod = proj = compare = sample_index = NULL;
1912
1913 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1914
1915 for (unsigned i = 0; i < tex->num_srcs; i++) {
1916 switch (tex->src[i].src_type) {
1917 case nir_tex_src_coord:
1918 coord = ir3_get_src(ctx, &tex->src[i].src);
1919 break;
1920 case nir_tex_src_bias:
1921 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1922 has_bias = true;
1923 break;
1924 case nir_tex_src_lod:
1925 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1926 has_lod = true;
1927 break;
1928 case nir_tex_src_comparator: /* shadow comparator */
1929 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1930 break;
1931 case nir_tex_src_projector:
1932 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1933 has_proj = true;
1934 break;
1935 case nir_tex_src_offset:
1936 off = ir3_get_src(ctx, &tex->src[i].src);
1937 has_off = true;
1938 break;
1939 case nir_tex_src_ddx:
1940 ddx = ir3_get_src(ctx, &tex->src[i].src);
1941 break;
1942 case nir_tex_src_ddy:
1943 ddy = ir3_get_src(ctx, &tex->src[i].src);
1944 break;
1945 case nir_tex_src_ms_index:
1946 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1947 break;
1948 case nir_tex_src_texture_offset:
1949 case nir_tex_src_sampler_offset:
1950 /* handled in get_tex_samp_src() */
1951 break;
1952 default:
1953 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1954 tex->src[i].src_type);
1955 return;
1956 }
1957 }
1958
1959 switch (tex->op) {
1960 case nir_texop_tex_prefetch:
1961 compile_assert(ctx, !has_bias);
1962 compile_assert(ctx, !has_lod);
1963 compile_assert(ctx, !compare);
1964 compile_assert(ctx, !has_proj);
1965 compile_assert(ctx, !has_off);
1966 compile_assert(ctx, !ddx);
1967 compile_assert(ctx, !ddy);
1968 compile_assert(ctx, !sample_index);
1969 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
1970 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
1971
1972 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
1973 opc = OPC_META_TEX_PREFETCH;
1974 ctx->so->num_sampler_prefetch++;
1975 break;
1976 }
1977 /* fallthru */
1978 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1979 case nir_texop_txb: opc = OPC_SAMB; break;
1980 case nir_texop_txl: opc = OPC_SAML; break;
1981 case nir_texop_txd: opc = OPC_SAMGQ; break;
1982 case nir_texop_txf: opc = OPC_ISAML; break;
1983 case nir_texop_lod: opc = OPC_GETLOD; break;
1984 case nir_texop_tg4:
1985 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1986 * what blob does, seems gather is broken?), and a3xx did
1987 * not support it (but probably could also emulate).
1988 */
1989 switch (tex->component) {
1990 case 0: opc = OPC_GATHER4R; break;
1991 case 1: opc = OPC_GATHER4G; break;
1992 case 2: opc = OPC_GATHER4B; break;
1993 case 3: opc = OPC_GATHER4A; break;
1994 }
1995 break;
1996 case nir_texop_txf_ms_fb:
1997 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1998 default:
1999 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2000 return;
2001 }
2002
2003 tex_info(tex, &flags, &coords);
2004
2005 /*
2006 * lay out the first argument in the proper order:
2007 * - actual coordinates first
2008 * - shadow reference
2009 * - array index
2010 * - projection w
2011 * - starting at offset 4, dpdx.xy, dpdy.xy
2012 *
2013 * bias/lod go into the second arg
2014 */
2015
2016 /* insert tex coords: */
2017 for (i = 0; i < coords; i++)
2018 src0[i] = coord[i];
2019
2020 nsrc0 = i;
2021
2022 /* scale up integer coords for TXF based on the LOD */
2023 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2024 assert(has_lod);
2025 for (i = 0; i < coords; i++)
2026 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2027 }
2028
2029 if (coords == 1) {
2030 /* hw doesn't do 1d, so we treat it as 2d with
2031 * height of 1, and patch up the y coord.
2032 */
2033 if (is_isam(opc)) {
2034 src0[nsrc0++] = create_immed(b, 0);
2035 } else {
2036 src0[nsrc0++] = create_immed(b, fui(0.5));
2037 }
2038 }
2039
2040 if (tex->is_shadow && tex->op != nir_texop_lod)
2041 src0[nsrc0++] = compare;
2042
2043 if (tex->is_array && tex->op != nir_texop_lod) {
2044 struct ir3_instruction *idx = coord[coords];
2045
2046 /* the array coord for cube arrays needs 0.5 added to it */
2047 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2048 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2049
2050 src0[nsrc0++] = idx;
2051 }
2052
2053 if (has_proj) {
2054 src0[nsrc0++] = proj;
2055 flags |= IR3_INSTR_P;
2056 }
2057
2058 /* pad to 4, then ddx/ddy: */
2059 if (tex->op == nir_texop_txd) {
2060 while (nsrc0 < 4)
2061 src0[nsrc0++] = create_immed(b, fui(0.0));
2062 for (i = 0; i < coords; i++)
2063 src0[nsrc0++] = ddx[i];
2064 if (coords < 2)
2065 src0[nsrc0++] = create_immed(b, fui(0.0));
2066 for (i = 0; i < coords; i++)
2067 src0[nsrc0++] = ddy[i];
2068 if (coords < 2)
2069 src0[nsrc0++] = create_immed(b, fui(0.0));
2070 }
2071
2072 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2073 * with scaled x coord according to requested sample:
2074 */
2075 if (opc == OPC_ISAMM) {
2076 if (ctx->compiler->txf_ms_with_isaml) {
2077 /* the samples are laid out in x dimension as
2078 * 0 1 2 3
2079 * x_ms = (x << ms) + sample_index;
2080 */
2081 struct ir3_instruction *ms;
2082 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2083
2084 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2085 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2086
2087 opc = OPC_ISAML;
2088 } else {
2089 src0[nsrc0++] = sample_index;
2090 }
2091 }
2092
2093 /*
2094 * second argument (if applicable):
2095 * - offsets
2096 * - lod
2097 * - bias
2098 */
2099 if (has_off | has_lod | has_bias) {
2100 if (has_off) {
2101 unsigned off_coords = coords;
2102 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2103 off_coords--;
2104 for (i = 0; i < off_coords; i++)
2105 src1[nsrc1++] = off[i];
2106 if (off_coords < 2)
2107 src1[nsrc1++] = create_immed(b, fui(0.0));
2108 flags |= IR3_INSTR_O;
2109 }
2110
2111 if (has_lod | has_bias)
2112 src1[nsrc1++] = lod;
2113 }
2114
2115 switch (tex->dest_type) {
2116 case nir_type_invalid:
2117 case nir_type_float:
2118 type = TYPE_F32;
2119 break;
2120 case nir_type_int:
2121 type = TYPE_S32;
2122 break;
2123 case nir_type_uint:
2124 case nir_type_bool:
2125 type = TYPE_U32;
2126 break;
2127 default:
2128 unreachable("bad dest_type");
2129 }
2130
2131 if (opc == OPC_GETLOD)
2132 type = TYPE_S32;
2133
2134 struct ir3_instruction *samp_tex;
2135
2136 if (tex->op == nir_texop_txf_ms_fb) {
2137 /* only expect a single txf_ms_fb per shader: */
2138 compile_assert(ctx, !ctx->so->fb_read);
2139 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2140
2141 ctx->so->fb_read = true;
2142 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2143 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2144 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2145 }, 2);
2146
2147 ctx->so->num_samp++;
2148 } else {
2149 samp_tex = get_tex_samp_tex_src(ctx, tex);
2150 }
2151
2152 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2153 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2154
2155 if (opc == OPC_META_TEX_PREFETCH) {
2156 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2157
2158 compile_assert(ctx, tex->src[idx].src.is_ssa);
2159
2160 sam = ir3_META_TEX_PREFETCH(b);
2161 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2162 sam->prefetch.input_offset =
2163 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2164 sam->prefetch.tex = tex->texture_index;
2165 sam->prefetch.samp = tex->sampler_index;
2166 } else {
2167 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2168 samp_tex, col0, col1);
2169 }
2170
2171 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2172 assert(opc != OPC_META_TEX_PREFETCH);
2173
2174 /* only need first 3 components: */
2175 sam->regs[0]->wrmask = 0x7;
2176 ir3_split_dest(b, dst, sam, 0, 3);
2177
2178 /* we need to sample the alpha separately with a non-ASTC
2179 * texture state:
2180 */
2181 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2182 samp_tex, col0, col1);
2183
2184 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2185
2186 /* fixup .w component: */
2187 ir3_split_dest(b, &dst[3], sam, 3, 1);
2188 } else {
2189 /* normal (non-workaround) case: */
2190 ir3_split_dest(b, dst, sam, 0, ncomp);
2191 }
2192
2193 /* GETLOD returns results in 4.8 fixed point */
2194 if (opc == OPC_GETLOD) {
2195 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2196
2197 compile_assert(ctx, tex->dest_type == nir_type_float);
2198 for (i = 0; i < 2; i++) {
2199 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2200 factor, 0);
2201 }
2202 }
2203
2204 ir3_put_dst(ctx, &tex->dest);
2205 }
2206
2207 static void
2208 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2209 {
2210 struct ir3_block *b = ctx->block;
2211 struct ir3_instruction **dst, *sam;
2212
2213 dst = ir3_get_dst(ctx, &tex->dest, 1);
2214
2215 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2216 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2217
2218 /* even though there is only one component, since it ends
2219 * up in .y/.z/.w rather than .x, we need a split_dest()
2220 */
2221 if (idx)
2222 ir3_split_dest(b, dst, sam, 0, idx + 1);
2223
2224 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2225 * the value in TEX_CONST_0 is zero-based.
2226 */
2227 if (ctx->compiler->levels_add_one)
2228 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2229
2230 ir3_put_dst(ctx, &tex->dest);
2231 }
2232
2233 static void
2234 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2235 {
2236 struct ir3_block *b = ctx->block;
2237 struct ir3_instruction **dst, *sam;
2238 struct ir3_instruction *lod;
2239 unsigned flags, coords;
2240
2241 tex_info(tex, &flags, &coords);
2242
2243 /* Actually we want the number of dimensions, not coordinates. This
2244 * distinction only matters for cubes.
2245 */
2246 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2247 coords = 2;
2248
2249 dst = ir3_get_dst(ctx, &tex->dest, 4);
2250
2251 compile_assert(ctx, tex->num_srcs == 1);
2252 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2253
2254 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2255
2256 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2257 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2258
2259 ir3_split_dest(b, dst, sam, 0, 4);
2260
2261 /* Array size actually ends up in .w rather than .z. This doesn't
2262 * matter for miplevel 0, but for higher mips the value in z is
2263 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2264 * returned, which means that we have to add 1 to it for arrays.
2265 */
2266 if (tex->is_array) {
2267 if (ctx->compiler->levels_add_one) {
2268 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2269 } else {
2270 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2271 }
2272 }
2273
2274 ir3_put_dst(ctx, &tex->dest);
2275 }
2276
2277 static void
2278 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2279 {
2280 switch (jump->type) {
2281 case nir_jump_break:
2282 case nir_jump_continue:
2283 case nir_jump_return:
2284 /* I *think* we can simply just ignore this, and use the
2285 * successor block link to figure out where we need to
2286 * jump to for break/continue
2287 */
2288 break;
2289 default:
2290 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2291 break;
2292 }
2293 }
2294
2295 static void
2296 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2297 {
2298 switch (instr->type) {
2299 case nir_instr_type_alu:
2300 emit_alu(ctx, nir_instr_as_alu(instr));
2301 break;
2302 case nir_instr_type_deref:
2303 /* ignored, handled as part of the intrinsic they are src to */
2304 break;
2305 case nir_instr_type_intrinsic:
2306 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2307 break;
2308 case nir_instr_type_load_const:
2309 emit_load_const(ctx, nir_instr_as_load_const(instr));
2310 break;
2311 case nir_instr_type_ssa_undef:
2312 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2313 break;
2314 case nir_instr_type_tex: {
2315 nir_tex_instr *tex = nir_instr_as_tex(instr);
2316 /* couple tex instructions get special-cased:
2317 */
2318 switch (tex->op) {
2319 case nir_texop_txs:
2320 emit_tex_txs(ctx, tex);
2321 break;
2322 case nir_texop_query_levels:
2323 emit_tex_info(ctx, tex, 2);
2324 break;
2325 case nir_texop_texture_samples:
2326 emit_tex_info(ctx, tex, 3);
2327 break;
2328 default:
2329 emit_tex(ctx, tex);
2330 break;
2331 }
2332 break;
2333 }
2334 case nir_instr_type_jump:
2335 emit_jump(ctx, nir_instr_as_jump(instr));
2336 break;
2337 case nir_instr_type_phi:
2338 /* we have converted phi webs to regs in NIR by now */
2339 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2340 break;
2341 case nir_instr_type_call:
2342 case nir_instr_type_parallel_copy:
2343 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2344 break;
2345 }
2346 }
2347
2348 static struct ir3_block *
2349 get_block(struct ir3_context *ctx, const nir_block *nblock)
2350 {
2351 struct ir3_block *block;
2352 struct hash_entry *hentry;
2353
2354 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2355 if (hentry)
2356 return hentry->data;
2357
2358 block = ir3_block_create(ctx->ir);
2359 block->nblock = nblock;
2360 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2361
2362 block->predecessors = _mesa_pointer_set_create(block);
2363 set_foreach(nblock->predecessors, sentry) {
2364 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2365 }
2366
2367 return block;
2368 }
2369
2370 static void
2371 emit_block(struct ir3_context *ctx, nir_block *nblock)
2372 {
2373 struct ir3_block *block = get_block(ctx, nblock);
2374
2375 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2376 if (nblock->successors[i]) {
2377 block->successors[i] =
2378 get_block(ctx, nblock->successors[i]);
2379 }
2380 }
2381
2382 ctx->block = block;
2383 list_addtail(&block->node, &ctx->ir->block_list);
2384
2385 /* re-emit addr register in each block if needed: */
2386 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2387 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2388 ctx->addr_ht[i] = NULL;
2389 }
2390
2391 nir_foreach_instr(instr, nblock) {
2392 ctx->cur_instr = instr;
2393 emit_instr(ctx, instr);
2394 ctx->cur_instr = NULL;
2395 if (ctx->error)
2396 return;
2397 }
2398 }
2399
2400 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2401
2402 static void
2403 emit_if(struct ir3_context *ctx, nir_if *nif)
2404 {
2405 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2406
2407 ctx->block->condition =
2408 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2409
2410 emit_cf_list(ctx, &nif->then_list);
2411 emit_cf_list(ctx, &nif->else_list);
2412 }
2413
2414 static void
2415 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2416 {
2417 emit_cf_list(ctx, &nloop->body);
2418 ctx->so->loops++;
2419 }
2420
2421 static void
2422 stack_push(struct ir3_context *ctx)
2423 {
2424 ctx->stack++;
2425 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2426 }
2427
2428 static void
2429 stack_pop(struct ir3_context *ctx)
2430 {
2431 compile_assert(ctx, ctx->stack > 0);
2432 ctx->stack--;
2433 }
2434
2435 static void
2436 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2437 {
2438 foreach_list_typed(nir_cf_node, node, node, list) {
2439 switch (node->type) {
2440 case nir_cf_node_block:
2441 emit_block(ctx, nir_cf_node_as_block(node));
2442 break;
2443 case nir_cf_node_if:
2444 stack_push(ctx);
2445 emit_if(ctx, nir_cf_node_as_if(node));
2446 stack_pop(ctx);
2447 break;
2448 case nir_cf_node_loop:
2449 stack_push(ctx);
2450 emit_loop(ctx, nir_cf_node_as_loop(node));
2451 stack_pop(ctx);
2452 break;
2453 case nir_cf_node_function:
2454 ir3_context_error(ctx, "TODO\n");
2455 break;
2456 }
2457 }
2458 }
2459
2460 /* emit stream-out code. At this point, the current block is the original
2461 * (nir) end block, and nir ensures that all flow control paths terminate
2462 * into the end block. We re-purpose the original end block to generate
2463 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2464 * block holding stream-out write instructions, followed by the new end
2465 * block:
2466 *
2467 * blockOrigEnd {
2468 * p0.x = (vtxcnt < maxvtxcnt)
2469 * // succs: blockStreamOut, blockNewEnd
2470 * }
2471 * blockStreamOut {
2472 * ... stream-out instructions ...
2473 * // succs: blockNewEnd
2474 * }
2475 * blockNewEnd {
2476 * }
2477 */
2478 static void
2479 emit_stream_out(struct ir3_context *ctx)
2480 {
2481 struct ir3 *ir = ctx->ir;
2482 struct ir3_stream_output_info *strmout =
2483 &ctx->so->shader->stream_output;
2484 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2485 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2486 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2487
2488 /* create vtxcnt input in input block at top of shader,
2489 * so that it is seen as live over the entire duration
2490 * of the shader:
2491 */
2492 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2493 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2494
2495 /* at this point, we are at the original 'end' block,
2496 * re-purpose this block to stream-out condition, then
2497 * append stream-out block and new-end block
2498 */
2499 orig_end_block = ctx->block;
2500
2501 // TODO these blocks need to update predecessors..
2502 // maybe w/ store_global intrinsic, we could do this
2503 // stuff in nir->nir pass
2504
2505 stream_out_block = ir3_block_create(ir);
2506 list_addtail(&stream_out_block->node, &ir->block_list);
2507
2508 new_end_block = ir3_block_create(ir);
2509 list_addtail(&new_end_block->node, &ir->block_list);
2510
2511 orig_end_block->successors[0] = stream_out_block;
2512 orig_end_block->successors[1] = new_end_block;
2513 stream_out_block->successors[0] = new_end_block;
2514
2515 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2516 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2517 cond->regs[0]->num = regid(REG_P0, 0);
2518 cond->regs[0]->flags &= ~IR3_REG_SSA;
2519 cond->cat2.condition = IR3_COND_LT;
2520
2521 /* condition goes on previous block to the conditional,
2522 * since it is used to pick which of the two successor
2523 * paths to take:
2524 */
2525 orig_end_block->condition = cond;
2526
2527 /* switch to stream_out_block to generate the stream-out
2528 * instructions:
2529 */
2530 ctx->block = stream_out_block;
2531
2532 /* Calculate base addresses based on vtxcnt. Instructions
2533 * generated for bases not used in following loop will be
2534 * stripped out in the backend.
2535 */
2536 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2537 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2538 unsigned stride = strmout->stride[i];
2539 struct ir3_instruction *base, *off;
2540
2541 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2542
2543 /* 24-bit should be enough: */
2544 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2545 create_immed(ctx->block, stride * 4), 0);
2546
2547 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2548 }
2549
2550 /* Generate the per-output store instructions: */
2551 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2552 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2553 unsigned c = j + strmout->output[i].start_component;
2554 struct ir3_instruction *base, *out, *stg;
2555
2556 base = bases[strmout->output[i].output_buffer];
2557 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2558
2559 stg = ir3_STG(ctx->block, base, 0, out, 0,
2560 create_immed(ctx->block, 1), 0);
2561 stg->cat6.type = TYPE_U32;
2562 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2563
2564 array_insert(ctx->block, ctx->block->keeps, stg);
2565 }
2566 }
2567
2568 /* and finally switch to the new_end_block: */
2569 ctx->block = new_end_block;
2570 }
2571
2572 static void
2573 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2574 {
2575 nir_metadata_require(impl, nir_metadata_block_index);
2576
2577 compile_assert(ctx, ctx->stack == 0);
2578
2579 emit_cf_list(ctx, &impl->body);
2580 emit_block(ctx, impl->end_block);
2581
2582 compile_assert(ctx, ctx->stack == 0);
2583
2584 /* at this point, we should have a single empty block,
2585 * into which we emit the 'end' instruction.
2586 */
2587 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2588
2589 /* If stream-out (aka transform-feedback) enabled, emit the
2590 * stream-out instructions, followed by a new empty block (into
2591 * which the 'end' instruction lands).
2592 *
2593 * NOTE: it is done in this order, rather than inserting before
2594 * we emit end_block, because NIR guarantees that all blocks
2595 * flow into end_block, and that end_block has no successors.
2596 * So by re-purposing end_block as the first block of stream-
2597 * out, we guarantee that all exit paths flow into the stream-
2598 * out instructions.
2599 */
2600 if ((ctx->compiler->gpu_id < 500) &&
2601 (ctx->so->shader->stream_output.num_outputs > 0) &&
2602 !ctx->so->binning_pass) {
2603 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2604 emit_stream_out(ctx);
2605 }
2606
2607 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2608 * NOP and has an epilogue that writes the VS outputs to local storage, to
2609 * be read by the HS. Then it resets execution mask (chmask) and chains
2610 * to the next shader (chsh).
2611 */
2612 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2613 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2614 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2615 struct ir3_instruction *chmask =
2616 ir3_CHMASK(ctx->block);
2617 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2618 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2619
2620 struct ir3_instruction *chsh =
2621 ir3_CHSH(ctx->block);
2622 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2623 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2624 } else {
2625 ir3_END(ctx->block);
2626 }
2627 }
2628
2629 static void
2630 setup_input(struct ir3_context *ctx, nir_variable *in)
2631 {
2632 struct ir3_shader_variant *so = ctx->so;
2633 unsigned ncomp = glsl_get_components(in->type);
2634 unsigned n = in->data.driver_location;
2635 unsigned frac = in->data.location_frac;
2636 unsigned slot = in->data.location;
2637
2638 /* Inputs are loaded using ldlw or ldg for these stages. */
2639 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2640 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2641 ctx->so->type == MESA_SHADER_GEOMETRY)
2642 return;
2643
2644 /* skip unread inputs, we could end up with (for example), unsplit
2645 * matrix/etc inputs in the case they are not read, so just silently
2646 * skip these.
2647 */
2648 if (ncomp > 4)
2649 return;
2650
2651 so->inputs[n].slot = slot;
2652 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2653 so->inputs_count = MAX2(so->inputs_count, n + 1);
2654 so->inputs[n].interpolate = in->data.interpolation;
2655
2656 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2657
2658 /* if any varyings have 'sample' qualifer, that triggers us
2659 * to run in per-sample mode:
2660 */
2661 so->per_samp |= in->data.sample;
2662
2663 for (int i = 0; i < ncomp; i++) {
2664 struct ir3_instruction *instr = NULL;
2665 unsigned idx = (n * 4) + i + frac;
2666
2667 if (slot == VARYING_SLOT_POS) {
2668 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2669 } else if (slot == VARYING_SLOT_PNTC) {
2670 /* see for example st_nir_fixup_varying_slots().. this is
2671 * maybe a bit mesa/st specific. But we need things to line
2672 * up for this in fdN_program:
2673 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2674 * if (emit->sprite_coord_enable & texmask) {
2675 * ...
2676 * }
2677 */
2678 so->inputs[n].slot = VARYING_SLOT_VAR8;
2679 so->inputs[n].bary = true;
2680 instr = create_frag_input(ctx, false, idx);
2681 } else {
2682 /* detect the special case for front/back colors where
2683 * we need to do flat vs smooth shading depending on
2684 * rast state:
2685 */
2686 if (in->data.interpolation == INTERP_MODE_NONE) {
2687 switch (slot) {
2688 case VARYING_SLOT_COL0:
2689 case VARYING_SLOT_COL1:
2690 case VARYING_SLOT_BFC0:
2691 case VARYING_SLOT_BFC1:
2692 so->inputs[n].rasterflat = true;
2693 break;
2694 default:
2695 break;
2696 }
2697 }
2698
2699 if (ctx->compiler->flat_bypass) {
2700 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2701 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2702 so->inputs[n].use_ldlv = true;
2703 }
2704
2705 so->inputs[n].bary = true;
2706
2707 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2708 }
2709
2710 compile_assert(ctx, idx < ctx->ninputs);
2711
2712 ctx->inputs[idx] = instr;
2713 }
2714 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2715 /* We shouldn't have fractional input for VS input.. that only shows
2716 * up with varying packing
2717 */
2718 assert(frac == 0);
2719
2720 struct ir3_instruction *input = create_input_compmask(ctx, 0, (1 << ncomp) - 1);
2721 struct ir3_instruction *components[ncomp];
2722
2723 input->input.inidx = n;
2724
2725 ir3_split_dest(ctx->block, components, input, 0, ncomp);
2726
2727 for (int i = 0; i < ncomp; i++) {
2728 unsigned idx = (n * 4) + i + frac;
2729 compile_assert(ctx, idx < ctx->ninputs);
2730 ctx->inputs[idx] = components[i];
2731 }
2732 } else {
2733 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2734 }
2735
2736 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2737 so->total_in += ncomp;
2738 }
2739 }
2740
2741 /* Initially we assign non-packed inloc's for varyings, as we don't really
2742 * know up-front which components will be unused. After all the compilation
2743 * stages we scan the shader to see which components are actually used, and
2744 * re-pack the inlocs to eliminate unneeded varyings.
2745 */
2746 static void
2747 pack_inlocs(struct ir3_context *ctx)
2748 {
2749 struct ir3_shader_variant *so = ctx->so;
2750 uint8_t used_components[so->inputs_count];
2751
2752 memset(used_components, 0, sizeof(used_components));
2753
2754 /*
2755 * First Step: scan shader to find which bary.f/ldlv remain:
2756 */
2757
2758 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2759 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2760 if (is_input(instr)) {
2761 unsigned inloc = instr->regs[1]->iim_val;
2762 unsigned i = inloc / 4;
2763 unsigned j = inloc % 4;
2764
2765 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2766 compile_assert(ctx, i < so->inputs_count);
2767
2768 used_components[i] |= 1 << j;
2769 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2770 for (int n = 0; n < 2; n++) {
2771 unsigned inloc = instr->prefetch.input_offset + n;
2772 unsigned i = inloc / 4;
2773 unsigned j = inloc % 4;
2774
2775 compile_assert(ctx, i < so->inputs_count);
2776
2777 used_components[i] |= 1 << j;
2778 }
2779 }
2780 }
2781 }
2782
2783 /*
2784 * Second Step: reassign varying inloc/slots:
2785 */
2786
2787 unsigned actual_in = 0;
2788 unsigned inloc = 0;
2789
2790 for (unsigned i = 0; i < so->inputs_count; i++) {
2791 unsigned compmask = 0, maxcomp = 0;
2792
2793 so->inputs[i].inloc = inloc;
2794 so->inputs[i].bary = false;
2795
2796 for (unsigned j = 0; j < 4; j++) {
2797 if (!(used_components[i] & (1 << j)))
2798 continue;
2799
2800 compmask |= (1 << j);
2801 actual_in++;
2802 maxcomp = j + 1;
2803
2804 /* at this point, since used_components[i] mask is only
2805 * considering varyings (ie. not sysvals) we know this
2806 * is a varying:
2807 */
2808 so->inputs[i].bary = true;
2809 }
2810
2811 if (so->inputs[i].bary) {
2812 so->varying_in++;
2813 so->inputs[i].compmask = (1 << maxcomp) - 1;
2814 inloc += maxcomp;
2815 }
2816 }
2817
2818 /*
2819 * Third Step: reassign packed inloc's:
2820 */
2821
2822 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2823 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2824 if (is_input(instr)) {
2825 unsigned inloc = instr->regs[1]->iim_val;
2826 unsigned i = inloc / 4;
2827 unsigned j = inloc % 4;
2828
2829 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2830 }
2831 }
2832 }
2833 }
2834
2835 static void
2836 setup_output(struct ir3_context *ctx, nir_variable *out)
2837 {
2838 struct ir3_shader_variant *so = ctx->so;
2839 unsigned ncomp = glsl_get_components(out->type);
2840 unsigned n = out->data.driver_location;
2841 unsigned frac = out->data.location_frac;
2842 unsigned slot = out->data.location;
2843 unsigned comp = 0;
2844
2845 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2846 switch (slot) {
2847 case FRAG_RESULT_DEPTH:
2848 comp = 2; /* tgsi will write to .z component */
2849 so->writes_pos = true;
2850 break;
2851 case FRAG_RESULT_COLOR:
2852 so->color0_mrt = 1;
2853 break;
2854 case FRAG_RESULT_SAMPLE_MASK:
2855 so->writes_smask = true;
2856 break;
2857 default:
2858 if (slot >= FRAG_RESULT_DATA0)
2859 break;
2860 ir3_context_error(ctx, "unknown FS output name: %s\n",
2861 gl_frag_result_name(slot));
2862 }
2863 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2864 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2865 ctx->so->type == MESA_SHADER_GEOMETRY) {
2866 switch (slot) {
2867 case VARYING_SLOT_POS:
2868 so->writes_pos = true;
2869 break;
2870 case VARYING_SLOT_PSIZ:
2871 so->writes_psize = true;
2872 break;
2873 case VARYING_SLOT_PRIMITIVE_ID:
2874 case VARYING_SLOT_LAYER:
2875 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2876 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2877 /* fall through */
2878 case VARYING_SLOT_COL0:
2879 case VARYING_SLOT_COL1:
2880 case VARYING_SLOT_BFC0:
2881 case VARYING_SLOT_BFC1:
2882 case VARYING_SLOT_FOGC:
2883 case VARYING_SLOT_CLIP_DIST0:
2884 case VARYING_SLOT_CLIP_DIST1:
2885 case VARYING_SLOT_CLIP_VERTEX:
2886 break;
2887 default:
2888 if (slot >= VARYING_SLOT_VAR0)
2889 break;
2890 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2891 break;
2892 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2893 _mesa_shader_stage_to_string(ctx->so->type),
2894 gl_varying_slot_name(slot));
2895 }
2896 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2897 /* output lowered to buffer writes. */
2898 return;
2899 } else {
2900 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2901 }
2902
2903 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2904
2905 so->outputs[n].slot = slot;
2906 so->outputs[n].regid = regid(n, comp);
2907 so->outputs_count = MAX2(so->outputs_count, n + 1);
2908
2909 for (int i = 0; i < ncomp; i++) {
2910 unsigned idx = (n * 4) + i + frac;
2911 compile_assert(ctx, idx < ctx->noutputs);
2912 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2913 }
2914
2915 /* if varying packing doesn't happen, we could end up in a situation
2916 * with "holes" in the output, and since the per-generation code that
2917 * sets up varying linkage registers doesn't expect to have more than
2918 * one varying per vec4 slot, pad the holes.
2919 *
2920 * Note that this should probably generate a performance warning of
2921 * some sort.
2922 */
2923 for (int i = 0; i < frac; i++) {
2924 unsigned idx = (n * 4) + i;
2925 if (!ctx->outputs[idx]) {
2926 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2927 }
2928 }
2929 }
2930
2931 static int
2932 max_drvloc(struct exec_list *vars)
2933 {
2934 int drvloc = -1;
2935 nir_foreach_variable(var, vars) {
2936 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2937 }
2938 return drvloc;
2939 }
2940
2941 static void
2942 emit_instructions(struct ir3_context *ctx)
2943 {
2944 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2945
2946 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2947 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2948
2949 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
2950 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
2951
2952 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
2953
2954 /* Create inputs in first block: */
2955 ctx->block = get_block(ctx, nir_start_block(fxn));
2956 ctx->in_block = ctx->block;
2957 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2958
2959 /* for fragment shader, the vcoord input register is used as the
2960 * base for bary.f varying fetch instrs:
2961 *
2962 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2963 * until emit_intrinsic when we know they are actually needed.
2964 * For now, we defer creating ctx->ij_centroid, etc, since we
2965 * only need ij_pixel for "old style" varying inputs (ie.
2966 * tgsi_to_nir)
2967 */
2968 struct ir3_instruction *vcoord = NULL;
2969 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2970 struct ir3_instruction *xy[2];
2971
2972 vcoord = create_input_compmask(ctx, 0, 0x3);
2973 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2974
2975 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2976 }
2977
2978 /* Setup inputs: */
2979 nir_foreach_variable(var, &ctx->s->inputs) {
2980 setup_input(ctx, var);
2981 }
2982
2983 /* Defer add_sysval_input() stuff until after setup_inputs(),
2984 * because sysvals need to be appended after varyings:
2985 */
2986 if (vcoord) {
2987 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2988 0x3, vcoord);
2989 }
2990
2991
2992 /* Tesselation shaders always need primitive ID for indexing the
2993 * BO. Geometry shaders don't always need it but when they do it has be
2994 * delivered and unclobbered in the VS. To make things easy, we always
2995 * make room for it in VS/DS.
2996 */
2997 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
2998 bool has_gs = ctx->so->key.has_gs;
2999 switch (ctx->so->type) {
3000 case MESA_SHADER_VERTEX:
3001 if (has_tess) {
3002 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3003 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3004 } else if (has_gs) {
3005 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3006 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3007 }
3008 break;
3009 case MESA_SHADER_TESS_CTRL:
3010 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3011 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3012 break;
3013 case MESA_SHADER_TESS_EVAL:
3014 if (has_gs)
3015 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3016 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3017 break;
3018 case MESA_SHADER_GEOMETRY:
3019 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3020 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3021 break;
3022 default:
3023 break;
3024 }
3025
3026 /* Setup outputs: */
3027 nir_foreach_variable(var, &ctx->s->outputs) {
3028 setup_output(ctx, var);
3029 }
3030
3031 /* Find # of samplers: */
3032 nir_foreach_variable(var, &ctx->s->uniforms) {
3033 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3034 /* just assume that we'll be reading from images.. if it
3035 * is write-only we don't have to count it, but not sure
3036 * if there is a good way to know?
3037 */
3038 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3039 }
3040
3041 /* NOTE: need to do something more clever when we support >1 fxn */
3042 nir_foreach_register(reg, &fxn->registers) {
3043 ir3_declare_array(ctx, reg);
3044 }
3045 /* And emit the body: */
3046 ctx->impl = fxn;
3047 emit_function(ctx, fxn);
3048 }
3049
3050 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3051 * need to assign the tex state indexes for these after we know the
3052 * max tex index.
3053 */
3054 static void
3055 fixup_astc_srgb(struct ir3_context *ctx)
3056 {
3057 struct ir3_shader_variant *so = ctx->so;
3058 /* indexed by original tex idx, value is newly assigned alpha sampler
3059 * state tex idx. Zero is invalid since there is at least one sampler
3060 * if we get here.
3061 */
3062 unsigned alt_tex_state[16] = {0};
3063 unsigned tex_idx = ctx->max_texture_index + 1;
3064 unsigned idx = 0;
3065
3066 so->astc_srgb.base = tex_idx;
3067
3068 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3069 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3070
3071 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3072
3073 if (alt_tex_state[sam->cat5.tex] == 0) {
3074 /* assign new alternate/alpha tex state slot: */
3075 alt_tex_state[sam->cat5.tex] = tex_idx++;
3076 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3077 so->astc_srgb.count++;
3078 }
3079
3080 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3081 }
3082 }
3083
3084 static void
3085 fixup_binning_pass(struct ir3_context *ctx)
3086 {
3087 struct ir3_shader_variant *so = ctx->so;
3088 struct ir3 *ir = ctx->ir;
3089 unsigned i, j;
3090
3091 /* first pass, remove unused outputs from the IR level outputs: */
3092 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3093 struct ir3_instruction *out = ir->outputs[i];
3094 assert(out->opc == OPC_META_COLLECT);
3095 unsigned outidx = out->collect.outidx;
3096 unsigned slot = so->outputs[outidx].slot;
3097
3098 /* throw away everything but first position/psize */
3099 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3100 ir->outputs[j] = ir->outputs[i];
3101 j++;
3102 }
3103 }
3104 ir->outputs_count = j;
3105
3106 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3107 * table:
3108 */
3109 for (i = 0, j = 0; i < so->outputs_count; i++) {
3110 unsigned slot = so->outputs[i].slot;
3111
3112 /* throw away everything but first position/psize */
3113 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3114 so->outputs[j] = so->outputs[i];
3115
3116 /* fixup outidx to point to new output table entry: */
3117 struct ir3_instruction *out;
3118 foreach_output(out, ir) {
3119 if (out->collect.outidx == i) {
3120 out->collect.outidx = j;
3121 break;
3122 }
3123 }
3124
3125 j++;
3126 }
3127 }
3128 so->outputs_count = j;
3129 }
3130
3131 static void
3132 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3133 {
3134 unsigned idx = 0;
3135
3136 /* Collect sampling instructions eligible for pre-dispatch. */
3137 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3138 list_for_each_entry_safe(struct ir3_instruction, instr,
3139 &block->instr_list, node) {
3140 if (instr->opc == OPC_META_TEX_PREFETCH) {
3141 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3142 struct ir3_sampler_prefetch *fetch =
3143 &ctx->so->sampler_prefetch[idx];
3144 idx++;
3145
3146 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3147 fetch->wrmask = instr->regs[0]->wrmask;
3148 fetch->tex_id = instr->prefetch.tex;
3149 fetch->samp_id = instr->prefetch.samp;
3150 fetch->dst = instr->regs[0]->num;
3151 fetch->src = instr->prefetch.input_offset;
3152
3153 ctx->so->total_in =
3154 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3155
3156 /* Disable half precision until supported. */
3157 fetch->half_precision = 0x0;
3158
3159 /* Remove the prefetch placeholder instruction: */
3160 list_delinit(&instr->node);
3161 }
3162 }
3163 }
3164 }
3165
3166 int
3167 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3168 struct ir3_shader_variant *so)
3169 {
3170 struct ir3_context *ctx;
3171 struct ir3 *ir;
3172 int ret = 0, max_bary;
3173
3174 assert(!so->ir);
3175
3176 ctx = ir3_context_init(compiler, so);
3177 if (!ctx) {
3178 DBG("INIT failed!");
3179 ret = -1;
3180 goto out;
3181 }
3182
3183 emit_instructions(ctx);
3184
3185 if (ctx->error) {
3186 DBG("EMIT failed!");
3187 ret = -1;
3188 goto out;
3189 }
3190
3191 ir = so->ir = ctx->ir;
3192
3193 assert((ctx->noutputs % 4) == 0);
3194
3195 /* Setup IR level outputs, which are "collects" that gather
3196 * the scalar components of outputs.
3197 */
3198 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3199 unsigned ncomp = 0;
3200 /* figure out the # of components written:
3201 *
3202 * TODO do we need to handle holes, ie. if .x and .z
3203 * components written, but .y component not written?
3204 */
3205 for (unsigned j = 0; j < 4; j++) {
3206 if (!ctx->outputs[i + j])
3207 break;
3208 ncomp++;
3209 }
3210
3211 /* Note that in some stages, like TCS, store_output is
3212 * lowered to memory writes, so no components of the
3213 * are "written" from the PoV of traditional store-
3214 * output instructions:
3215 */
3216 if (!ncomp)
3217 continue;
3218
3219 struct ir3_instruction *out =
3220 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3221
3222 int outidx = i / 4;
3223 assert(outidx < so->outputs_count);
3224
3225 /* stash index into so->outputs[] so we can map the
3226 * output back to slot/etc later:
3227 */
3228 out->collect.outidx = outidx;
3229
3230 array_insert(ir, ir->outputs, out);
3231 }
3232
3233 /* Set up the gs header as an output for the vertex shader so it won't
3234 * clobber it for the tess ctrl shader.
3235 *
3236 * TODO this could probably be done more cleanly in a nir pass.
3237 */
3238 if (ctx->so->type == MESA_SHADER_VERTEX ||
3239 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3240 if (ctx->primitive_id) {
3241 unsigned n = so->outputs_count++;
3242 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3243
3244 struct ir3_instruction *out =
3245 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3246 out->collect.outidx = n;
3247 array_insert(ir, ir->outputs, out);
3248 }
3249
3250 if (ctx->gs_header) {
3251 unsigned n = so->outputs_count++;
3252 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3253 struct ir3_instruction *out =
3254 ir3_create_collect(ctx, &ctx->gs_header, 1);
3255 out->collect.outidx = n;
3256 array_insert(ir, ir->outputs, out);
3257 }
3258
3259 if (ctx->tcs_header) {
3260 unsigned n = so->outputs_count++;
3261 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3262 struct ir3_instruction *out =
3263 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3264 out->collect.outidx = n;
3265 array_insert(ir, ir->outputs, out);
3266 }
3267 }
3268
3269 /* at this point, for binning pass, throw away unneeded outputs: */
3270 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3271 fixup_binning_pass(ctx);
3272
3273 ir3_debug_print(ir, "BEFORE CP");
3274
3275 ir3_cp(ir, so);
3276
3277 /* at this point, for binning pass, throw away unneeded outputs:
3278 * Note that for a6xx and later, we do this after ir3_cp to ensure
3279 * that the uniform/constant layout for BS and VS matches, so that
3280 * we can re-use same VS_CONST state group.
3281 */
3282 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3283 fixup_binning_pass(ctx);
3284
3285 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3286 * need to make sure not to remove any inputs that are used by
3287 * the nonbinning VS.
3288 */
3289 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3290 so->type == MESA_SHADER_VERTEX) {
3291 for (int i = 0; i < ctx->ninputs; i++) {
3292 struct ir3_instruction *in = ctx->inputs[i];
3293
3294 if (!in)
3295 continue;
3296
3297 unsigned n = i / 4;
3298 unsigned c = i % 4;
3299
3300 debug_assert(n < so->nonbinning->inputs_count);
3301
3302 if (so->nonbinning->inputs[n].sysval)
3303 continue;
3304
3305 /* be sure to keep inputs, even if only used in VS */
3306 if (so->nonbinning->inputs[n].compmask & (1 << c))
3307 array_insert(in->block, in->block->keeps, in);
3308 }
3309 }
3310
3311 ir3_debug_print(ir, "BEFORE GROUPING");
3312
3313 ir3_sched_add_deps(ir);
3314
3315 /* Group left/right neighbors, inserting mov's where needed to
3316 * solve conflicts:
3317 */
3318 ir3_group(ir);
3319
3320 ir3_debug_print(ir, "AFTER GROUPING");
3321
3322 ir3_depth(ir, so);
3323
3324 ir3_debug_print(ir, "AFTER DEPTH");
3325
3326 /* do Sethi–Ullman numbering before scheduling: */
3327 ir3_sun(ir);
3328
3329 ret = ir3_sched(ir);
3330 if (ret) {
3331 DBG("SCHED failed!");
3332 goto out;
3333 }
3334
3335 if (compiler->gpu_id >= 600) {
3336 ir3_a6xx_fixup_atomic_dests(ir, so);
3337 }
3338
3339 ir3_debug_print(ir, "AFTER SCHED");
3340
3341 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3342 * with draw pass VS, so binning and draw pass can both use the
3343 * same VBO state.
3344 *
3345 * Note that VS inputs are expected to be full precision.
3346 */
3347 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3348 (ir->type == MESA_SHADER_VERTEX) &&
3349 so->binning_pass;
3350
3351 if (pre_assign_inputs) {
3352 for (unsigned i = 0; i < ctx->ninputs; i++) {
3353 struct ir3_instruction *instr = ctx->inputs[i];
3354
3355 if (!instr)
3356 continue;
3357
3358 unsigned n = i / 4;
3359 unsigned c = i % 4;
3360 unsigned regid = so->nonbinning->inputs[n].regid + c;
3361
3362 instr->regs[0]->num = regid;
3363 }
3364
3365 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3366 } else if (ctx->tcs_header) {
3367 /* We need to have these values in the same registers between VS and TCS
3368 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3369 */
3370
3371 ctx->tcs_header->regs[0]->num = regid(0, 0);
3372 ctx->primitive_id->regs[0]->num = regid(0, 1);
3373 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3374 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3375 } else if (ctx->gs_header) {
3376 /* We need to have these values in the same registers between producer
3377 * (VS or DS) and GS since the producer chains to GS and doesn't get
3378 * the sysvals redelivered.
3379 */
3380
3381 ctx->gs_header->regs[0]->num = regid(0, 0);
3382 ctx->primitive_id->regs[0]->num = regid(0, 1);
3383 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3384 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3385 } else if (so->num_sampler_prefetch) {
3386 assert(so->type == MESA_SHADER_FRAGMENT);
3387 struct ir3_instruction *instr, *precolor[2];
3388 int idx = 0;
3389
3390 foreach_input(instr, ir) {
3391 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3392 continue;
3393
3394 assert(idx < ARRAY_SIZE(precolor));
3395
3396 precolor[idx] = instr;
3397 instr->regs[0]->num = idx;
3398
3399 idx++;
3400 }
3401 ret = ir3_ra(so, precolor, idx);
3402 } else {
3403 ret = ir3_ra(so, NULL, 0);
3404 }
3405
3406 if (ret) {
3407 DBG("RA failed!");
3408 goto out;
3409 }
3410
3411 ir3_debug_print(ir, "AFTER RA");
3412
3413 if (so->type == MESA_SHADER_FRAGMENT)
3414 pack_inlocs(ctx);
3415
3416 /*
3417 * Fixup inputs/outputs to point to the actual registers assigned:
3418 *
3419 * 1) initialize to r63.x (invalid/unused)
3420 * 2) iterate IR level inputs/outputs and update the variants
3421 * inputs/outputs table based on the assigned registers for
3422 * the remaining inputs/outputs.
3423 */
3424
3425 for (unsigned i = 0; i < so->inputs_count; i++)
3426 so->inputs[i].regid = regid(63, 0);
3427 for (unsigned i = 0; i < so->outputs_count; i++)
3428 so->outputs[i].regid = regid(63, 0);
3429
3430 struct ir3_instruction *out;
3431 foreach_output(out, ir) {
3432 assert(out->opc == OPC_META_COLLECT);
3433 unsigned outidx = out->collect.outidx;
3434
3435 so->outputs[outidx].regid = out->regs[0]->num;
3436 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3437 }
3438
3439 struct ir3_instruction *in;
3440 foreach_input(in, ir) {
3441 assert(in->opc == OPC_META_INPUT);
3442 unsigned inidx = in->input.inidx;
3443
3444 so->inputs[inidx].regid = in->regs[0]->num;
3445 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3446 }
3447
3448 if (ctx->astc_srgb)
3449 fixup_astc_srgb(ctx);
3450
3451 /* We need to do legalize after (for frag shader's) the "bary.f"
3452 * offsets (inloc) have been assigned.
3453 */
3454 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3455
3456 ir3_debug_print(ir, "AFTER LEGALIZE");
3457
3458 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3459 * know what we might have to wait on when coming in from VS chsh.
3460 */
3461 if (so->type == MESA_SHADER_TESS_CTRL ||
3462 so->type == MESA_SHADER_GEOMETRY ) {
3463 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3464 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3465 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3466 break;
3467 }
3468 }
3469 }
3470
3471 so->branchstack = ctx->max_stack;
3472
3473 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3474 if (so->type == MESA_SHADER_FRAGMENT)
3475 so->total_in = max_bary + 1;
3476
3477 so->max_sun = ir->max_sun;
3478
3479 /* Collect sampling instructions eligible for pre-dispatch. */
3480 collect_tex_prefetches(ctx, ir);
3481
3482 out:
3483 if (ret) {
3484 if (so->ir)
3485 ir3_destroy(so->ir);
3486 so->ir = NULL;
3487 }
3488 ir3_context_free(ctx);
3489
3490 return ret;
3491 }