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freedreno/ir3: fixes for half reg in/out
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count: {
620 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
621 // double check on earlier gen's. Once half-precision support is
622 // in place, this should probably move to a NIR lowering pass:
623 struct ir3_instruction *hi, *lo;
624
625 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
626 TYPE_U32, TYPE_U16);
627 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
628
629 hi = ir3_CBITS_B(b, hi, 0);
630 lo = ir3_CBITS_B(b, lo, 0);
631
632 // TODO maybe the builders should default to making dst half-precision
633 // if the src's were half precision, to make this less awkward.. otoh
634 // we should probably just do this lowering in NIR.
635 hi->regs[0]->flags |= IR3_REG_HALF;
636 lo->regs[0]->flags |= IR3_REG_HALF;
637
638 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
639 dst[0]->regs[0]->flags |= IR3_REG_HALF;
640 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
641 break;
642 }
643 case nir_op_ifind_msb: {
644 struct ir3_instruction *cmp;
645 dst[0] = ir3_CLZ_S(b, src[0], 0);
646 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
647 cmp->cat2.condition = IR3_COND_GE;
648 dst[0] = ir3_SEL_B32(b,
649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
650 cmp, 0, dst[0], 0);
651 break;
652 }
653 case nir_op_ufind_msb:
654 dst[0] = ir3_CLZ_B(b, src[0], 0);
655 dst[0] = ir3_SEL_B32(b,
656 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
657 src[0], 0, dst[0], 0);
658 break;
659 case nir_op_find_lsb:
660 dst[0] = ir3_BFREV_B(b, src[0], 0);
661 dst[0] = ir3_CLZ_B(b, dst[0], 0);
662 break;
663 case nir_op_bitfield_reverse:
664 dst[0] = ir3_BFREV_B(b, src[0], 0);
665 break;
666
667 default:
668 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
669 nir_op_infos[alu->op].name);
670 break;
671 }
672
673 ir3_put_dst(ctx, &alu->dest.dest);
674 }
675
676 /* handles direct/indirect UBO reads: */
677 static void
678 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
679 struct ir3_instruction **dst)
680 {
681 struct ir3_block *b = ctx->block;
682 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
683 /* UBO addresses are the first driver params, but subtract 2 here to
684 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
685 * is the uniforms: */
686 unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2;
687 const unsigned ptrsz = ir3_pointer_size(ctx);
688
689 int off = 0;
690
691 /* First src is ubo index, which could either be an immed or not: */
692 src0 = ir3_get_src(ctx, &intr->src[0])[0];
693 if (is_same_type_mov(src0) &&
694 (src0->regs[1]->flags & IR3_REG_IMMED)) {
695 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
696 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
697 } else {
698 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
699 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
700 }
701
702 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
703 addr = base_lo;
704
705 if (nir_src_is_const(intr->src[1])) {
706 off += nir_src_as_uint(intr->src[1]);
707 } else {
708 /* For load_ubo_indirect, second src is indirect offset: */
709 src1 = ir3_get_src(ctx, &intr->src[1])[0];
710
711 /* and add offset to addr: */
712 addr = ir3_ADD_S(b, addr, 0, src1, 0);
713 }
714
715 /* if offset is to large to encode in the ldg, split it out: */
716 if ((off + (intr->num_components * 4)) > 1024) {
717 /* split out the minimal amount to improve the odds that
718 * cp can fit the immediate in the add.s instruction:
719 */
720 unsigned off2 = off + (intr->num_components * 4) - 1024;
721 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
722 off -= off2;
723 }
724
725 if (ptrsz == 2) {
726 struct ir3_instruction *carry;
727
728 /* handle 32b rollover, ie:
729 * if (addr < base_lo)
730 * base_hi++
731 */
732 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
733 carry->cat2.condition = IR3_COND_LT;
734 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
735
736 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
737 }
738
739 for (int i = 0; i < intr->num_components; i++) {
740 struct ir3_instruction *load =
741 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
742 load->cat6.type = TYPE_U32;
743 load->cat6.src_offset = off + i * 4; /* byte offset */
744 dst[i] = load;
745 }
746 }
747
748 /* src[] = { block_index } */
749 static void
750 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
751 struct ir3_instruction **dst)
752 {
753 /* SSBO size stored as a const starting at ssbo_sizes: */
754 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
755 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
756 ctx->so->const_layout.ssbo_size.off[blk_idx];
757
758 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
759
760 dst[0] = create_uniform(ctx->block, idx);
761 }
762
763 /* src[] = { offset }. const_index[] = { base } */
764 static void
765 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
766 struct ir3_instruction **dst)
767 {
768 struct ir3_block *b = ctx->block;
769 struct ir3_instruction *ldl, *offset;
770 unsigned base;
771
772 offset = ir3_get_src(ctx, &intr->src[0])[0];
773 base = nir_intrinsic_base(intr);
774
775 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
776 ldl->cat6.src_offset = base;
777 ldl->cat6.type = utype_dst(intr->dest);
778 ldl->regs[0]->wrmask = MASK(intr->num_components);
779
780 ldl->barrier_class = IR3_BARRIER_SHARED_R;
781 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
782
783 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
784 }
785
786 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
787 static void
788 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
789 {
790 struct ir3_block *b = ctx->block;
791 struct ir3_instruction *stl, *offset;
792 struct ir3_instruction * const *value;
793 unsigned base, wrmask;
794
795 value = ir3_get_src(ctx, &intr->src[0]);
796 offset = ir3_get_src(ctx, &intr->src[1])[0];
797
798 base = nir_intrinsic_base(intr);
799 wrmask = nir_intrinsic_write_mask(intr);
800
801 /* Combine groups of consecutive enabled channels in one write
802 * message. We use ffs to find the first enabled channel and then ffs on
803 * the bit-inverse, down-shifted writemask to determine the length of
804 * the block of enabled bits.
805 *
806 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
807 */
808 while (wrmask) {
809 unsigned first_component = ffs(wrmask) - 1;
810 unsigned length = ffs(~(wrmask >> first_component)) - 1;
811
812 stl = ir3_STL(b, offset, 0,
813 ir3_create_collect(ctx, &value[first_component], length), 0,
814 create_immed(b, length), 0);
815 stl->cat6.dst_offset = first_component + base;
816 stl->cat6.type = utype_src(intr->src[0]);
817 stl->barrier_class = IR3_BARRIER_SHARED_W;
818 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
819
820 array_insert(b, b->keeps, stl);
821
822 /* Clear the bits in the writemask that we just wrote, then try
823 * again to see if more channels are left.
824 */
825 wrmask &= (15 << (first_component + length));
826 }
827 }
828
829 /*
830 * CS shared variable atomic intrinsics
831 *
832 * All of the shared variable atomic memory operations read a value from
833 * memory, compute a new value using one of the operations below, write the
834 * new value to memory, and return the original value read.
835 *
836 * All operations take 2 sources except CompSwap that takes 3. These
837 * sources represent:
838 *
839 * 0: The offset into the shared variable storage region that the atomic
840 * operation will operate on.
841 * 1: The data parameter to the atomic function (i.e. the value to add
842 * in shared_atomic_add, etc).
843 * 2: For CompSwap only: the second data parameter.
844 */
845 static struct ir3_instruction *
846 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
847 {
848 struct ir3_block *b = ctx->block;
849 struct ir3_instruction *atomic, *src0, *src1;
850 type_t type = TYPE_U32;
851
852 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
853 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
854
855 switch (intr->intrinsic) {
856 case nir_intrinsic_shared_atomic_add:
857 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
858 break;
859 case nir_intrinsic_shared_atomic_imin:
860 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
861 type = TYPE_S32;
862 break;
863 case nir_intrinsic_shared_atomic_umin:
864 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
865 break;
866 case nir_intrinsic_shared_atomic_imax:
867 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
868 type = TYPE_S32;
869 break;
870 case nir_intrinsic_shared_atomic_umax:
871 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
872 break;
873 case nir_intrinsic_shared_atomic_and:
874 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_or:
877 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
878 break;
879 case nir_intrinsic_shared_atomic_xor:
880 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
881 break;
882 case nir_intrinsic_shared_atomic_exchange:
883 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
884 break;
885 case nir_intrinsic_shared_atomic_comp_swap:
886 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
887 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
888 ir3_get_src(ctx, &intr->src[2])[0],
889 src1,
890 }, 2);
891 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
892 break;
893 default:
894 unreachable("boo");
895 }
896
897 atomic->cat6.iim_val = 1;
898 atomic->cat6.d = 1;
899 atomic->cat6.type = type;
900 atomic->barrier_class = IR3_BARRIER_SHARED_W;
901 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
902
903 /* even if nothing consume the result, we can't DCE the instruction: */
904 array_insert(b, b->keeps, atomic);
905
906 return atomic;
907 }
908
909 /* TODO handle actual indirect/dynamic case.. which is going to be weird
910 * to handle with the image_mapping table..
911 */
912 static struct ir3_instruction *
913 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
914 {
915 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
916 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
917 struct ir3_instruction *texture, *sampler;
918
919 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
920 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
921
922 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
923 sampler,
924 texture,
925 }, 2);
926 }
927
928 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
929 static void
930 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
931 struct ir3_instruction **dst)
932 {
933 struct ir3_block *b = ctx->block;
934 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
935 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
936 struct ir3_instruction *sam;
937 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
938 struct ir3_instruction *coords[4];
939 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
940 type_t type = ir3_get_image_type(var);
941
942 /* hmm, this seems a bit odd, but it is what blob does and (at least
943 * a5xx) just faults on bogus addresses otherwise:
944 */
945 if (flags & IR3_INSTR_3D) {
946 flags &= ~IR3_INSTR_3D;
947 flags |= IR3_INSTR_A;
948 }
949
950 for (unsigned i = 0; i < ncoords; i++)
951 coords[i] = src0[i];
952
953 if (ncoords == 1)
954 coords[ncoords++] = create_immed(b, 0);
955
956 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
957 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
958
959 sam->barrier_class = IR3_BARRIER_IMAGE_R;
960 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
961
962 ir3_split_dest(b, dst, sam, 0, 4);
963 }
964
965 static void
966 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
967 struct ir3_instruction **dst)
968 {
969 struct ir3_block *b = ctx->block;
970 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
971 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
972 struct ir3_instruction *sam, *lod;
973 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
974
975 lod = create_immed(b, 0);
976 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
977 samp_tex, lod, NULL);
978
979 /* Array size actually ends up in .w rather than .z. This doesn't
980 * matter for miplevel 0, but for higher mips the value in z is
981 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
982 * returned, which means that we have to add 1 to it for arrays for
983 * a3xx.
984 *
985 * Note use a temporary dst and then copy, since the size of the dst
986 * array that is passed in is based on nir's understanding of the
987 * result size, not the hardware's
988 */
989 struct ir3_instruction *tmp[4];
990
991 ir3_split_dest(b, tmp, sam, 0, 4);
992
993 /* get_size instruction returns size in bytes instead of texels
994 * for imageBuffer, so we need to divide it by the pixel size
995 * of the image format.
996 *
997 * TODO: This is at least true on a5xx. Check other gens.
998 */
999 enum glsl_sampler_dim dim =
1000 glsl_get_sampler_dim(glsl_without_array(var->type));
1001 if (dim == GLSL_SAMPLER_DIM_BUF) {
1002 /* Since all the possible values the divisor can take are
1003 * power-of-two (4, 8, or 16), the division is implemented
1004 * as a shift-right.
1005 * During shader setup, the log2 of the image format's
1006 * bytes-per-pixel should have been emitted in 2nd slot of
1007 * image_dims. See ir3_shader::emit_image_dims().
1008 */
1009 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1010 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1011 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1012
1013 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1014 }
1015
1016 for (unsigned i = 0; i < ncoords; i++)
1017 dst[i] = tmp[i];
1018
1019 if (flags & IR3_INSTR_A) {
1020 if (ctx->compiler->levels_add_one) {
1021 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1022 } else {
1023 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1024 }
1025 }
1026 }
1027
1028 static void
1029 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1030 {
1031 struct ir3_block *b = ctx->block;
1032 struct ir3_instruction *barrier;
1033
1034 switch (intr->intrinsic) {
1035 case nir_intrinsic_barrier:
1036 barrier = ir3_BAR(b);
1037 barrier->cat7.g = true;
1038 barrier->cat7.l = true;
1039 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1040 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1041 break;
1042 case nir_intrinsic_memory_barrier:
1043 barrier = ir3_FENCE(b);
1044 barrier->cat7.g = true;
1045 barrier->cat7.r = true;
1046 barrier->cat7.w = true;
1047 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1048 IR3_BARRIER_BUFFER_W;
1049 barrier->barrier_conflict =
1050 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1051 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1052 break;
1053 case nir_intrinsic_memory_barrier_atomic_counter:
1054 case nir_intrinsic_memory_barrier_buffer:
1055 barrier = ir3_FENCE(b);
1056 barrier->cat7.g = true;
1057 barrier->cat7.r = true;
1058 barrier->cat7.w = true;
1059 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1060 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1061 IR3_BARRIER_BUFFER_W;
1062 break;
1063 case nir_intrinsic_memory_barrier_image:
1064 // TODO double check if this should have .g set
1065 barrier = ir3_FENCE(b);
1066 barrier->cat7.g = true;
1067 barrier->cat7.r = true;
1068 barrier->cat7.w = true;
1069 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1070 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1071 IR3_BARRIER_IMAGE_W;
1072 break;
1073 case nir_intrinsic_memory_barrier_shared:
1074 barrier = ir3_FENCE(b);
1075 barrier->cat7.g = true;
1076 barrier->cat7.l = true;
1077 barrier->cat7.r = true;
1078 barrier->cat7.w = true;
1079 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1080 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1081 IR3_BARRIER_SHARED_W;
1082 break;
1083 case nir_intrinsic_group_memory_barrier:
1084 barrier = ir3_FENCE(b);
1085 barrier->cat7.g = true;
1086 barrier->cat7.l = true;
1087 barrier->cat7.r = true;
1088 barrier->cat7.w = true;
1089 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1090 IR3_BARRIER_IMAGE_W |
1091 IR3_BARRIER_BUFFER_W;
1092 barrier->barrier_conflict =
1093 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1094 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1095 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1096 break;
1097 default:
1098 unreachable("boo");
1099 }
1100
1101 /* make sure barrier doesn't get DCE'd */
1102 array_insert(b, b->keeps, barrier);
1103 }
1104
1105 static void add_sysval_input_compmask(struct ir3_context *ctx,
1106 gl_system_value slot, unsigned compmask,
1107 struct ir3_instruction *instr)
1108 {
1109 struct ir3_shader_variant *so = ctx->so;
1110 unsigned r = regid(so->inputs_count, 0);
1111 unsigned n = so->inputs_count++;
1112
1113 so->inputs[n].sysval = true;
1114 so->inputs[n].slot = slot;
1115 so->inputs[n].compmask = compmask;
1116 so->inputs[n].regid = r;
1117 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1118 so->total_in++;
1119
1120 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1121 ctx->ir->inputs[r] = instr;
1122 }
1123
1124 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1125 struct ir3_instruction *instr)
1126 {
1127 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1128 }
1129
1130 static struct ir3_instruction *
1131 get_barycentric_centroid(struct ir3_context *ctx)
1132 {
1133 if (!ctx->ij_centroid) {
1134 struct ir3_instruction *xy[2];
1135 struct ir3_instruction *ij;
1136
1137 ij = create_input_compmask(ctx, 0, 0x3);
1138 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1139
1140 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1141
1142 add_sysval_input_compmask(ctx,
1143 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1144 0x3, ij);
1145 }
1146
1147 return ctx->ij_centroid;
1148 }
1149
1150 static struct ir3_instruction *
1151 get_barycentric_sample(struct ir3_context *ctx)
1152 {
1153 if (!ctx->ij_sample) {
1154 struct ir3_instruction *xy[2];
1155 struct ir3_instruction *ij;
1156
1157 ij = create_input_compmask(ctx, 0, 0x3);
1158 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1159
1160 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1161
1162 add_sysval_input_compmask(ctx,
1163 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1164 0x3, ij);
1165 }
1166
1167 return ctx->ij_sample;
1168 }
1169
1170 static struct ir3_instruction *
1171 get_barycentric_pixel(struct ir3_context *ctx)
1172 {
1173 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1174 * this to create ij_pixel only on demand:
1175 */
1176 return ctx->ij_pixel;
1177 }
1178
1179 static struct ir3_instruction *
1180 get_frag_coord(struct ir3_context *ctx)
1181 {
1182 if (!ctx->frag_coord) {
1183 struct ir3_block *b = ctx->block;
1184 struct ir3_instruction *xyzw[4];
1185 struct ir3_instruction *hw_frag_coord;
1186
1187 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1188 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1189
1190 /* for frag_coord.xy, we get unsigned values.. we need
1191 * to subtract (integer) 8 and divide by 16 (right-
1192 * shift by 4) then convert to float:
1193 *
1194 * sub.s tmp, src, 8
1195 * shr.b tmp, tmp, 4
1196 * mov.u32f32 dst, tmp
1197 *
1198 */
1199 for (int i = 0; i < 2; i++) {
1200 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1201 create_immed(b, 8), 0);
1202 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1203 create_immed(b, 4), 0);
1204 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1205 }
1206
1207 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1208
1209 add_sysval_input_compmask(ctx,
1210 SYSTEM_VALUE_FRAG_COORD,
1211 0xf, hw_frag_coord);
1212
1213 ctx->so->frag_coord = true;
1214 }
1215
1216 return ctx->frag_coord;
1217 }
1218
1219 static void
1220 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1221 {
1222 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1223 struct ir3_instruction **dst;
1224 struct ir3_instruction * const *src;
1225 struct ir3_block *b = ctx->block;
1226 int idx, comp;
1227
1228 if (info->has_dest) {
1229 unsigned n = nir_intrinsic_dest_components(intr);
1230 dst = ir3_get_dst(ctx, &intr->dest, n);
1231 } else {
1232 dst = NULL;
1233 }
1234
1235 switch (intr->intrinsic) {
1236 case nir_intrinsic_load_uniform:
1237 idx = nir_intrinsic_base(intr);
1238 if (nir_src_is_const(intr->src[0])) {
1239 idx += nir_src_as_uint(intr->src[0]);
1240 for (int i = 0; i < intr->num_components; i++) {
1241 dst[i] = create_uniform(b, idx + i);
1242 }
1243 } else {
1244 src = ir3_get_src(ctx, &intr->src[0]);
1245 for (int i = 0; i < intr->num_components; i++) {
1246 dst[i] = create_uniform_indirect(b, idx + i,
1247 ir3_get_addr(ctx, src[0], 1));
1248 }
1249 /* NOTE: if relative addressing is used, we set
1250 * constlen in the compiler (to worst-case value)
1251 * since we don't know in the assembler what the max
1252 * addr reg value can be:
1253 */
1254 ctx->so->constlen = ctx->s->num_uniforms;
1255 }
1256 break;
1257 case nir_intrinsic_load_ubo:
1258 emit_intrinsic_load_ubo(ctx, intr, dst);
1259 break;
1260 case nir_intrinsic_load_frag_coord:
1261 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1262 break;
1263 case nir_intrinsic_load_sample_pos_from_id: {
1264 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1265 * but that doesn't seem necessary.
1266 */
1267 struct ir3_instruction *offset =
1268 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1269 offset->regs[0]->wrmask = 0x3;
1270 offset->cat5.type = TYPE_F32;
1271
1272 ir3_split_dest(b, dst, offset, 0, 2);
1273
1274 break;
1275 }
1276 case nir_intrinsic_load_size_ir3:
1277 if (!ctx->ij_size) {
1278 ctx->ij_size = create_input(ctx, 0);
1279
1280 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1281 ctx->ij_size);
1282 }
1283 dst[0] = ctx->ij_size;
1284 break;
1285 case nir_intrinsic_load_barycentric_centroid:
1286 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1287 break;
1288 case nir_intrinsic_load_barycentric_sample:
1289 if (ctx->so->key.msaa) {
1290 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1291 } else {
1292 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1293 }
1294 break;
1295 case nir_intrinsic_load_barycentric_pixel:
1296 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1297 break;
1298 case nir_intrinsic_load_interpolated_input:
1299 idx = nir_intrinsic_base(intr);
1300 comp = nir_intrinsic_component(intr);
1301 src = ir3_get_src(ctx, &intr->src[0]);
1302 if (nir_src_is_const(intr->src[1])) {
1303 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1304 idx += nir_src_as_uint(intr->src[1]);
1305 for (int i = 0; i < intr->num_components; i++) {
1306 unsigned inloc = idx * 4 + i + comp;
1307 if (ctx->so->inputs[idx].bary) {
1308 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1309 } else {
1310 /* for non-varyings use the pre-setup input, since
1311 * that is easier than mapping things back to a
1312 * nir_variable to figure out what it is.
1313 */
1314 dst[i] = ctx->ir->inputs[inloc];
1315 }
1316 }
1317 } else {
1318 ir3_context_error(ctx, "unhandled");
1319 }
1320 break;
1321 case nir_intrinsic_load_input:
1322 idx = nir_intrinsic_base(intr);
1323 comp = nir_intrinsic_component(intr);
1324 if (nir_src_is_const(intr->src[0])) {
1325 idx += nir_src_as_uint(intr->src[0]);
1326 for (int i = 0; i < intr->num_components; i++) {
1327 unsigned n = idx * 4 + i + comp;
1328 dst[i] = ctx->ir->inputs[n];
1329 compile_assert(ctx, ctx->ir->inputs[n]);
1330 }
1331 } else {
1332 src = ir3_get_src(ctx, &intr->src[0]);
1333 struct ir3_instruction *collect =
1334 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1335 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1336 for (int i = 0; i < intr->num_components; i++) {
1337 unsigned n = idx * 4 + i + comp;
1338 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1339 n, addr, collect);
1340 }
1341 }
1342 break;
1343 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1344 * pass and replaced by an ir3-specifc version that adds the
1345 * dword-offset in the last source.
1346 */
1347 case nir_intrinsic_load_ssbo_ir3:
1348 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1349 break;
1350 case nir_intrinsic_store_ssbo_ir3:
1351 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1352 !ctx->s->info.fs.early_fragment_tests)
1353 ctx->so->no_earlyz = true;
1354 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1355 break;
1356 case nir_intrinsic_get_buffer_size:
1357 emit_intrinsic_ssbo_size(ctx, intr, dst);
1358 break;
1359 case nir_intrinsic_ssbo_atomic_add_ir3:
1360 case nir_intrinsic_ssbo_atomic_imin_ir3:
1361 case nir_intrinsic_ssbo_atomic_umin_ir3:
1362 case nir_intrinsic_ssbo_atomic_imax_ir3:
1363 case nir_intrinsic_ssbo_atomic_umax_ir3:
1364 case nir_intrinsic_ssbo_atomic_and_ir3:
1365 case nir_intrinsic_ssbo_atomic_or_ir3:
1366 case nir_intrinsic_ssbo_atomic_xor_ir3:
1367 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1368 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1369 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1370 !ctx->s->info.fs.early_fragment_tests)
1371 ctx->so->no_earlyz = true;
1372 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1373 break;
1374 case nir_intrinsic_load_shared:
1375 emit_intrinsic_load_shared(ctx, intr, dst);
1376 break;
1377 case nir_intrinsic_store_shared:
1378 emit_intrinsic_store_shared(ctx, intr);
1379 break;
1380 case nir_intrinsic_shared_atomic_add:
1381 case nir_intrinsic_shared_atomic_imin:
1382 case nir_intrinsic_shared_atomic_umin:
1383 case nir_intrinsic_shared_atomic_imax:
1384 case nir_intrinsic_shared_atomic_umax:
1385 case nir_intrinsic_shared_atomic_and:
1386 case nir_intrinsic_shared_atomic_or:
1387 case nir_intrinsic_shared_atomic_xor:
1388 case nir_intrinsic_shared_atomic_exchange:
1389 case nir_intrinsic_shared_atomic_comp_swap:
1390 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1391 break;
1392 case nir_intrinsic_image_deref_load:
1393 emit_intrinsic_load_image(ctx, intr, dst);
1394 break;
1395 case nir_intrinsic_image_deref_store:
1396 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1397 !ctx->s->info.fs.early_fragment_tests)
1398 ctx->so->no_earlyz = true;
1399 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1400 break;
1401 case nir_intrinsic_image_deref_size:
1402 emit_intrinsic_image_size(ctx, intr, dst);
1403 break;
1404 case nir_intrinsic_image_deref_atomic_add:
1405 case nir_intrinsic_image_deref_atomic_min:
1406 case nir_intrinsic_image_deref_atomic_max:
1407 case nir_intrinsic_image_deref_atomic_and:
1408 case nir_intrinsic_image_deref_atomic_or:
1409 case nir_intrinsic_image_deref_atomic_xor:
1410 case nir_intrinsic_image_deref_atomic_exchange:
1411 case nir_intrinsic_image_deref_atomic_comp_swap:
1412 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1413 !ctx->s->info.fs.early_fragment_tests)
1414 ctx->so->no_earlyz = true;
1415 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1416 break;
1417 case nir_intrinsic_barrier:
1418 case nir_intrinsic_memory_barrier:
1419 case nir_intrinsic_group_memory_barrier:
1420 case nir_intrinsic_memory_barrier_atomic_counter:
1421 case nir_intrinsic_memory_barrier_buffer:
1422 case nir_intrinsic_memory_barrier_image:
1423 case nir_intrinsic_memory_barrier_shared:
1424 emit_intrinsic_barrier(ctx, intr);
1425 /* note that blk ptr no longer valid, make that obvious: */
1426 b = NULL;
1427 break;
1428 case nir_intrinsic_store_output:
1429 idx = nir_intrinsic_base(intr);
1430 comp = nir_intrinsic_component(intr);
1431 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1432 idx += nir_src_as_uint(intr->src[1]);
1433
1434 src = ir3_get_src(ctx, &intr->src[0]);
1435 for (int i = 0; i < intr->num_components; i++) {
1436 unsigned n = idx * 4 + i + comp;
1437 ctx->ir->outputs[n] = src[i];
1438 }
1439 break;
1440 case nir_intrinsic_load_base_vertex:
1441 case nir_intrinsic_load_first_vertex:
1442 if (!ctx->basevertex) {
1443 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1444 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1445 }
1446 dst[0] = ctx->basevertex;
1447 break;
1448 case nir_intrinsic_load_vertex_id_zero_base:
1449 case nir_intrinsic_load_vertex_id:
1450 if (!ctx->vertex_id) {
1451 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1452 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1453 ctx->vertex_id = create_input(ctx, 0);
1454 add_sysval_input(ctx, sv, ctx->vertex_id);
1455 }
1456 dst[0] = ctx->vertex_id;
1457 break;
1458 case nir_intrinsic_load_instance_id:
1459 if (!ctx->instance_id) {
1460 ctx->instance_id = create_input(ctx, 0);
1461 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1462 ctx->instance_id);
1463 }
1464 dst[0] = ctx->instance_id;
1465 break;
1466 case nir_intrinsic_load_sample_id:
1467 ctx->so->per_samp = true;
1468 /* fall-thru */
1469 case nir_intrinsic_load_sample_id_no_per_sample:
1470 if (!ctx->samp_id) {
1471 ctx->samp_id = create_input(ctx, 0);
1472 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1473 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1474 ctx->samp_id);
1475 }
1476 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1477 break;
1478 case nir_intrinsic_load_sample_mask_in:
1479 if (!ctx->samp_mask_in) {
1480 ctx->samp_mask_in = create_input(ctx, 0);
1481 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1482 ctx->samp_mask_in);
1483 }
1484 dst[0] = ctx->samp_mask_in;
1485 break;
1486 case nir_intrinsic_load_user_clip_plane:
1487 idx = nir_intrinsic_ucp_id(intr);
1488 for (int i = 0; i < intr->num_components; i++) {
1489 unsigned n = idx * 4 + i;
1490 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1491 }
1492 break;
1493 case nir_intrinsic_load_front_face:
1494 if (!ctx->frag_face) {
1495 ctx->so->frag_face = true;
1496 ctx->frag_face = create_input(ctx, 0);
1497 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1498 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1499 }
1500 /* for fragface, we get -1 for back and 0 for front. However this is
1501 * the inverse of what nir expects (where ~0 is true).
1502 */
1503 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1504 dst[0] = ir3_NOT_B(b, dst[0], 0);
1505 break;
1506 case nir_intrinsic_load_local_invocation_id:
1507 if (!ctx->local_invocation_id) {
1508 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1509 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1510 0x7, ctx->local_invocation_id);
1511 }
1512 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1513 break;
1514 case nir_intrinsic_load_work_group_id:
1515 if (!ctx->work_group_id) {
1516 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1517 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1518 0x7, ctx->work_group_id);
1519 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1520 }
1521 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1522 break;
1523 case nir_intrinsic_load_num_work_groups:
1524 for (int i = 0; i < intr->num_components; i++) {
1525 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1526 }
1527 break;
1528 case nir_intrinsic_load_local_group_size:
1529 for (int i = 0; i < intr->num_components; i++) {
1530 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1531 }
1532 break;
1533 case nir_intrinsic_discard_if:
1534 case nir_intrinsic_discard: {
1535 struct ir3_instruction *cond, *kill;
1536
1537 if (intr->intrinsic == nir_intrinsic_discard_if) {
1538 /* conditional discard: */
1539 src = ir3_get_src(ctx, &intr->src[0]);
1540 cond = ir3_b2n(b, src[0]);
1541 } else {
1542 /* unconditional discard: */
1543 cond = create_immed(b, 1);
1544 }
1545
1546 /* NOTE: only cmps.*.* can write p0.x: */
1547 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1548 cond->cat2.condition = IR3_COND_NE;
1549
1550 /* condition always goes in predicate register: */
1551 cond->regs[0]->num = regid(REG_P0, 0);
1552
1553 kill = ir3_KILL(b, cond, 0);
1554 array_insert(ctx->ir, ctx->ir->predicates, kill);
1555
1556 array_insert(b, b->keeps, kill);
1557 ctx->so->no_earlyz = true;
1558
1559 break;
1560 }
1561 default:
1562 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1563 nir_intrinsic_infos[intr->intrinsic].name);
1564 break;
1565 }
1566
1567 if (info->has_dest)
1568 ir3_put_dst(ctx, &intr->dest);
1569 }
1570
1571 static void
1572 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1573 {
1574 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1575 instr->def.num_components);
1576 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1577
1578 for (int i = 0; i < instr->def.num_components; i++)
1579 dst[i] = create_immed_typed(ctx->block, instr->value[i].u32, type);
1580 }
1581
1582 static void
1583 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1584 {
1585 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1586 undef->def.num_components);
1587 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1588
1589 /* backend doesn't want undefined instructions, so just plug
1590 * in 0.0..
1591 */
1592 for (int i = 0; i < undef->def.num_components; i++)
1593 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1594 }
1595
1596 /*
1597 * texture fetch/sample instructions:
1598 */
1599
1600 static void
1601 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1602 {
1603 unsigned coords, flags = 0;
1604
1605 /* note: would use tex->coord_components.. except txs.. also,
1606 * since array index goes after shadow ref, we don't want to
1607 * count it:
1608 */
1609 switch (tex->sampler_dim) {
1610 case GLSL_SAMPLER_DIM_1D:
1611 case GLSL_SAMPLER_DIM_BUF:
1612 coords = 1;
1613 break;
1614 case GLSL_SAMPLER_DIM_2D:
1615 case GLSL_SAMPLER_DIM_RECT:
1616 case GLSL_SAMPLER_DIM_EXTERNAL:
1617 case GLSL_SAMPLER_DIM_MS:
1618 coords = 2;
1619 break;
1620 case GLSL_SAMPLER_DIM_3D:
1621 case GLSL_SAMPLER_DIM_CUBE:
1622 coords = 3;
1623 flags |= IR3_INSTR_3D;
1624 break;
1625 default:
1626 unreachable("bad sampler_dim");
1627 }
1628
1629 if (tex->is_shadow && tex->op != nir_texop_lod)
1630 flags |= IR3_INSTR_S;
1631
1632 if (tex->is_array && tex->op != nir_texop_lod)
1633 flags |= IR3_INSTR_A;
1634
1635 *flagsp = flags;
1636 *coordsp = coords;
1637 }
1638
1639 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1640 * or immediate (in which case it will get lowered later to a non .s2en
1641 * version of the tex instruction which encode tex/samp as immediates:
1642 */
1643 static struct ir3_instruction *
1644 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1645 {
1646 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1647 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1648 struct ir3_instruction *texture, *sampler;
1649
1650 if (texture_idx >= 0) {
1651 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1652 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1653 } else {
1654 /* TODO what to do for dynamic case? I guess we only need the
1655 * max index for astc srgb workaround so maybe not a problem
1656 * to worry about if we don't enable indirect samplers for
1657 * a4xx?
1658 */
1659 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1660 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1661 }
1662
1663 if (sampler_idx >= 0) {
1664 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1665 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1666 } else {
1667 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1668 }
1669
1670 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1671 sampler,
1672 texture,
1673 }, 2);
1674 }
1675
1676 static void
1677 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1678 {
1679 struct ir3_block *b = ctx->block;
1680 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1681 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1682 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1683 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1684 unsigned i, coords, flags, ncomp;
1685 unsigned nsrc0 = 0, nsrc1 = 0;
1686 type_t type;
1687 opc_t opc = 0;
1688
1689 ncomp = nir_dest_num_components(tex->dest);
1690
1691 coord = off = ddx = ddy = NULL;
1692 lod = proj = compare = sample_index = NULL;
1693
1694 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1695
1696 for (unsigned i = 0; i < tex->num_srcs; i++) {
1697 switch (tex->src[i].src_type) {
1698 case nir_tex_src_coord:
1699 coord = ir3_get_src(ctx, &tex->src[i].src);
1700 break;
1701 case nir_tex_src_bias:
1702 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1703 has_bias = true;
1704 break;
1705 case nir_tex_src_lod:
1706 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1707 has_lod = true;
1708 break;
1709 case nir_tex_src_comparator: /* shadow comparator */
1710 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1711 break;
1712 case nir_tex_src_projector:
1713 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1714 has_proj = true;
1715 break;
1716 case nir_tex_src_offset:
1717 off = ir3_get_src(ctx, &tex->src[i].src);
1718 has_off = true;
1719 break;
1720 case nir_tex_src_ddx:
1721 ddx = ir3_get_src(ctx, &tex->src[i].src);
1722 break;
1723 case nir_tex_src_ddy:
1724 ddy = ir3_get_src(ctx, &tex->src[i].src);
1725 break;
1726 case nir_tex_src_ms_index:
1727 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1728 break;
1729 case nir_tex_src_texture_offset:
1730 case nir_tex_src_sampler_offset:
1731 /* handled in get_tex_samp_src() */
1732 break;
1733 default:
1734 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1735 tex->src[i].src_type);
1736 return;
1737 }
1738 }
1739
1740 switch (tex->op) {
1741 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1742 case nir_texop_txb: opc = OPC_SAMB; break;
1743 case nir_texop_txl: opc = OPC_SAML; break;
1744 case nir_texop_txd: opc = OPC_SAMGQ; break;
1745 case nir_texop_txf: opc = OPC_ISAML; break;
1746 case nir_texop_lod: opc = OPC_GETLOD; break;
1747 case nir_texop_tg4:
1748 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1749 * what blob does, seems gather is broken?), and a3xx did
1750 * not support it (but probably could also emulate).
1751 */
1752 switch (tex->component) {
1753 case 0: opc = OPC_GATHER4R; break;
1754 case 1: opc = OPC_GATHER4G; break;
1755 case 2: opc = OPC_GATHER4B; break;
1756 case 3: opc = OPC_GATHER4A; break;
1757 }
1758 break;
1759 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1760 case nir_texop_txs:
1761 case nir_texop_query_levels:
1762 case nir_texop_texture_samples:
1763 case nir_texop_samples_identical:
1764 case nir_texop_txf_ms_mcs:
1765 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1766 return;
1767 }
1768
1769 tex_info(tex, &flags, &coords);
1770
1771 /*
1772 * lay out the first argument in the proper order:
1773 * - actual coordinates first
1774 * - shadow reference
1775 * - array index
1776 * - projection w
1777 * - starting at offset 4, dpdx.xy, dpdy.xy
1778 *
1779 * bias/lod go into the second arg
1780 */
1781
1782 /* insert tex coords: */
1783 for (i = 0; i < coords; i++)
1784 src0[i] = coord[i];
1785
1786 nsrc0 = i;
1787
1788 /* scale up integer coords for TXF based on the LOD */
1789 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1790 assert(has_lod);
1791 for (i = 0; i < coords; i++)
1792 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1793 }
1794
1795 if (coords == 1) {
1796 /* hw doesn't do 1d, so we treat it as 2d with
1797 * height of 1, and patch up the y coord.
1798 */
1799 if (is_isam(opc)) {
1800 src0[nsrc0++] = create_immed(b, 0);
1801 } else {
1802 src0[nsrc0++] = create_immed(b, fui(0.5));
1803 }
1804 }
1805
1806 if (tex->is_shadow && tex->op != nir_texop_lod)
1807 src0[nsrc0++] = compare;
1808
1809 if (tex->is_array && tex->op != nir_texop_lod) {
1810 struct ir3_instruction *idx = coord[coords];
1811
1812 /* the array coord for cube arrays needs 0.5 added to it */
1813 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1814 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1815
1816 src0[nsrc0++] = idx;
1817 }
1818
1819 if (has_proj) {
1820 src0[nsrc0++] = proj;
1821 flags |= IR3_INSTR_P;
1822 }
1823
1824 /* pad to 4, then ddx/ddy: */
1825 if (tex->op == nir_texop_txd) {
1826 while (nsrc0 < 4)
1827 src0[nsrc0++] = create_immed(b, fui(0.0));
1828 for (i = 0; i < coords; i++)
1829 src0[nsrc0++] = ddx[i];
1830 if (coords < 2)
1831 src0[nsrc0++] = create_immed(b, fui(0.0));
1832 for (i = 0; i < coords; i++)
1833 src0[nsrc0++] = ddy[i];
1834 if (coords < 2)
1835 src0[nsrc0++] = create_immed(b, fui(0.0));
1836 }
1837
1838 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1839 * with scaled x coord according to requested sample:
1840 */
1841 if (tex->op == nir_texop_txf_ms) {
1842 if (ctx->compiler->txf_ms_with_isaml) {
1843 /* the samples are laid out in x dimension as
1844 * 0 1 2 3
1845 * x_ms = (x << ms) + sample_index;
1846 */
1847 struct ir3_instruction *ms;
1848 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1849
1850 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1851 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1852
1853 opc = OPC_ISAML;
1854 } else {
1855 src0[nsrc0++] = sample_index;
1856 }
1857 }
1858
1859 /*
1860 * second argument (if applicable):
1861 * - offsets
1862 * - lod
1863 * - bias
1864 */
1865 if (has_off | has_lod | has_bias) {
1866 if (has_off) {
1867 unsigned off_coords = coords;
1868 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1869 off_coords--;
1870 for (i = 0; i < off_coords; i++)
1871 src1[nsrc1++] = off[i];
1872 if (off_coords < 2)
1873 src1[nsrc1++] = create_immed(b, fui(0.0));
1874 flags |= IR3_INSTR_O;
1875 }
1876
1877 if (has_lod | has_bias)
1878 src1[nsrc1++] = lod;
1879 }
1880
1881 switch (tex->dest_type) {
1882 case nir_type_invalid:
1883 case nir_type_float:
1884 type = TYPE_F32;
1885 break;
1886 case nir_type_int:
1887 type = TYPE_S32;
1888 break;
1889 case nir_type_uint:
1890 case nir_type_bool:
1891 type = TYPE_U32;
1892 break;
1893 default:
1894 unreachable("bad dest_type");
1895 }
1896
1897 if (opc == OPC_GETLOD)
1898 type = TYPE_U32;
1899
1900 struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
1901 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1902 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1903
1904 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1905 samp_tex, col0, col1);
1906
1907 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1908 /* only need first 3 components: */
1909 sam->regs[0]->wrmask = 0x7;
1910 ir3_split_dest(b, dst, sam, 0, 3);
1911
1912 /* we need to sample the alpha separately with a non-ASTC
1913 * texture state:
1914 */
1915 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1916 samp_tex, col0, col1);
1917
1918 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1919
1920 /* fixup .w component: */
1921 ir3_split_dest(b, &dst[3], sam, 3, 1);
1922 } else {
1923 /* normal (non-workaround) case: */
1924 ir3_split_dest(b, dst, sam, 0, ncomp);
1925 }
1926
1927 /* GETLOD returns results in 4.8 fixed point */
1928 if (opc == OPC_GETLOD) {
1929 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1930
1931 compile_assert(ctx, tex->dest_type == nir_type_float);
1932 for (i = 0; i < 2; i++) {
1933 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1934 factor, 0);
1935 }
1936 }
1937
1938 ir3_put_dst(ctx, &tex->dest);
1939 }
1940
1941 static void
1942 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1943 {
1944 struct ir3_block *b = ctx->block;
1945 struct ir3_instruction **dst, *sam;
1946
1947 dst = ir3_get_dst(ctx, &tex->dest, 1);
1948
1949 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1950 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1951
1952 /* even though there is only one component, since it ends
1953 * up in .z rather than .x, we need a split_dest()
1954 */
1955 ir3_split_dest(b, dst, sam, 0, 3);
1956
1957 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1958 * the value in TEX_CONST_0 is zero-based.
1959 */
1960 if (ctx->compiler->levels_add_one)
1961 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1962
1963 ir3_put_dst(ctx, &tex->dest);
1964 }
1965
1966 static void
1967 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1968 {
1969 struct ir3_block *b = ctx->block;
1970 struct ir3_instruction **dst, *sam;
1971 struct ir3_instruction *lod;
1972 unsigned flags, coords;
1973
1974 tex_info(tex, &flags, &coords);
1975
1976 /* Actually we want the number of dimensions, not coordinates. This
1977 * distinction only matters for cubes.
1978 */
1979 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1980 coords = 2;
1981
1982 dst = ir3_get_dst(ctx, &tex->dest, 4);
1983
1984 compile_assert(ctx, tex->num_srcs == 1);
1985 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1986
1987 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
1988
1989 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1990 get_tex_samp_tex_src(ctx, tex), lod, NULL);
1991
1992 ir3_split_dest(b, dst, sam, 0, 4);
1993
1994 /* Array size actually ends up in .w rather than .z. This doesn't
1995 * matter for miplevel 0, but for higher mips the value in z is
1996 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1997 * returned, which means that we have to add 1 to it for arrays.
1998 */
1999 if (tex->is_array) {
2000 if (ctx->compiler->levels_add_one) {
2001 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2002 } else {
2003 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2004 }
2005 }
2006
2007 ir3_put_dst(ctx, &tex->dest);
2008 }
2009
2010 static void
2011 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2012 {
2013 switch (jump->type) {
2014 case nir_jump_break:
2015 case nir_jump_continue:
2016 case nir_jump_return:
2017 /* I *think* we can simply just ignore this, and use the
2018 * successor block link to figure out where we need to
2019 * jump to for break/continue
2020 */
2021 break;
2022 default:
2023 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2024 break;
2025 }
2026 }
2027
2028 static void
2029 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2030 {
2031 switch (instr->type) {
2032 case nir_instr_type_alu:
2033 emit_alu(ctx, nir_instr_as_alu(instr));
2034 break;
2035 case nir_instr_type_deref:
2036 /* ignored, handled as part of the intrinsic they are src to */
2037 break;
2038 case nir_instr_type_intrinsic:
2039 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2040 break;
2041 case nir_instr_type_load_const:
2042 emit_load_const(ctx, nir_instr_as_load_const(instr));
2043 break;
2044 case nir_instr_type_ssa_undef:
2045 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2046 break;
2047 case nir_instr_type_tex: {
2048 nir_tex_instr *tex = nir_instr_as_tex(instr);
2049 /* couple tex instructions get special-cased:
2050 */
2051 switch (tex->op) {
2052 case nir_texop_txs:
2053 emit_tex_txs(ctx, tex);
2054 break;
2055 case nir_texop_query_levels:
2056 emit_tex_query_levels(ctx, tex);
2057 break;
2058 default:
2059 emit_tex(ctx, tex);
2060 break;
2061 }
2062 break;
2063 }
2064 case nir_instr_type_jump:
2065 emit_jump(ctx, nir_instr_as_jump(instr));
2066 break;
2067 case nir_instr_type_phi:
2068 /* we have converted phi webs to regs in NIR by now */
2069 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2070 break;
2071 case nir_instr_type_call:
2072 case nir_instr_type_parallel_copy:
2073 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2074 break;
2075 }
2076 }
2077
2078 static struct ir3_block *
2079 get_block(struct ir3_context *ctx, const nir_block *nblock)
2080 {
2081 struct ir3_block *block;
2082 struct hash_entry *hentry;
2083 unsigned i;
2084
2085 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2086 if (hentry)
2087 return hentry->data;
2088
2089 block = ir3_block_create(ctx->ir);
2090 block->nblock = nblock;
2091 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2092
2093 block->predecessors_count = nblock->predecessors->entries;
2094 block->predecessors = ralloc_array_size(block,
2095 sizeof(block->predecessors[0]), block->predecessors_count);
2096 i = 0;
2097 set_foreach(nblock->predecessors, sentry) {
2098 block->predecessors[i++] = get_block(ctx, sentry->key);
2099 }
2100
2101 return block;
2102 }
2103
2104 static void
2105 emit_block(struct ir3_context *ctx, nir_block *nblock)
2106 {
2107 struct ir3_block *block = get_block(ctx, nblock);
2108
2109 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2110 if (nblock->successors[i]) {
2111 block->successors[i] =
2112 get_block(ctx, nblock->successors[i]);
2113 }
2114 }
2115
2116 ctx->block = block;
2117 list_addtail(&block->node, &ctx->ir->block_list);
2118
2119 /* re-emit addr register in each block if needed: */
2120 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2121 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2122 ctx->addr_ht[i] = NULL;
2123 }
2124
2125 nir_foreach_instr(instr, nblock) {
2126 ctx->cur_instr = instr;
2127 emit_instr(ctx, instr);
2128 ctx->cur_instr = NULL;
2129 if (ctx->error)
2130 return;
2131 }
2132 }
2133
2134 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2135
2136 static void
2137 emit_if(struct ir3_context *ctx, nir_if *nif)
2138 {
2139 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2140
2141 ctx->block->condition =
2142 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2143
2144 emit_cf_list(ctx, &nif->then_list);
2145 emit_cf_list(ctx, &nif->else_list);
2146 }
2147
2148 static void
2149 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2150 {
2151 emit_cf_list(ctx, &nloop->body);
2152 }
2153
2154 static void
2155 stack_push(struct ir3_context *ctx)
2156 {
2157 ctx->stack++;
2158 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2159 }
2160
2161 static void
2162 stack_pop(struct ir3_context *ctx)
2163 {
2164 compile_assert(ctx, ctx->stack > 0);
2165 ctx->stack--;
2166 }
2167
2168 static void
2169 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2170 {
2171 foreach_list_typed(nir_cf_node, node, node, list) {
2172 switch (node->type) {
2173 case nir_cf_node_block:
2174 emit_block(ctx, nir_cf_node_as_block(node));
2175 break;
2176 case nir_cf_node_if:
2177 stack_push(ctx);
2178 emit_if(ctx, nir_cf_node_as_if(node));
2179 stack_pop(ctx);
2180 break;
2181 case nir_cf_node_loop:
2182 stack_push(ctx);
2183 emit_loop(ctx, nir_cf_node_as_loop(node));
2184 stack_pop(ctx);
2185 break;
2186 case nir_cf_node_function:
2187 ir3_context_error(ctx, "TODO\n");
2188 break;
2189 }
2190 }
2191 }
2192
2193 /* emit stream-out code. At this point, the current block is the original
2194 * (nir) end block, and nir ensures that all flow control paths terminate
2195 * into the end block. We re-purpose the original end block to generate
2196 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2197 * block holding stream-out write instructions, followed by the new end
2198 * block:
2199 *
2200 * blockOrigEnd {
2201 * p0.x = (vtxcnt < maxvtxcnt)
2202 * // succs: blockStreamOut, blockNewEnd
2203 * }
2204 * blockStreamOut {
2205 * ... stream-out instructions ...
2206 * // succs: blockNewEnd
2207 * }
2208 * blockNewEnd {
2209 * }
2210 */
2211 static void
2212 emit_stream_out(struct ir3_context *ctx)
2213 {
2214 struct ir3_shader_variant *v = ctx->so;
2215 struct ir3 *ir = ctx->ir;
2216 struct ir3_stream_output_info *strmout =
2217 &ctx->so->shader->stream_output;
2218 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2219 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2220 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2221
2222 /* create vtxcnt input in input block at top of shader,
2223 * so that it is seen as live over the entire duration
2224 * of the shader:
2225 */
2226 vtxcnt = create_input(ctx, 0);
2227 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2228
2229 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2230
2231 /* at this point, we are at the original 'end' block,
2232 * re-purpose this block to stream-out condition, then
2233 * append stream-out block and new-end block
2234 */
2235 orig_end_block = ctx->block;
2236
2237 // TODO these blocks need to update predecessors..
2238 // maybe w/ store_global intrinsic, we could do this
2239 // stuff in nir->nir pass
2240
2241 stream_out_block = ir3_block_create(ir);
2242 list_addtail(&stream_out_block->node, &ir->block_list);
2243
2244 new_end_block = ir3_block_create(ir);
2245 list_addtail(&new_end_block->node, &ir->block_list);
2246
2247 orig_end_block->successors[0] = stream_out_block;
2248 orig_end_block->successors[1] = new_end_block;
2249 stream_out_block->successors[0] = new_end_block;
2250
2251 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2252 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2253 cond->regs[0]->num = regid(REG_P0, 0);
2254 cond->cat2.condition = IR3_COND_LT;
2255
2256 /* condition goes on previous block to the conditional,
2257 * since it is used to pick which of the two successor
2258 * paths to take:
2259 */
2260 orig_end_block->condition = cond;
2261
2262 /* switch to stream_out_block to generate the stream-out
2263 * instructions:
2264 */
2265 ctx->block = stream_out_block;
2266
2267 /* Calculate base addresses based on vtxcnt. Instructions
2268 * generated for bases not used in following loop will be
2269 * stripped out in the backend.
2270 */
2271 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2272 unsigned stride = strmout->stride[i];
2273 struct ir3_instruction *base, *off;
2274
2275 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2276
2277 /* 24-bit should be enough: */
2278 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2279 create_immed(ctx->block, stride * 4), 0);
2280
2281 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2282 }
2283
2284 /* Generate the per-output store instructions: */
2285 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2286 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2287 unsigned c = j + strmout->output[i].start_component;
2288 struct ir3_instruction *base, *out, *stg;
2289
2290 base = bases[strmout->output[i].output_buffer];
2291 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2292
2293 stg = ir3_STG(ctx->block, base, 0, out, 0,
2294 create_immed(ctx->block, 1), 0);
2295 stg->cat6.type = TYPE_U32;
2296 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2297
2298 array_insert(ctx->block, ctx->block->keeps, stg);
2299 }
2300 }
2301
2302 /* and finally switch to the new_end_block: */
2303 ctx->block = new_end_block;
2304 }
2305
2306 static void
2307 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2308 {
2309 nir_metadata_require(impl, nir_metadata_block_index);
2310
2311 compile_assert(ctx, ctx->stack == 0);
2312
2313 emit_cf_list(ctx, &impl->body);
2314 emit_block(ctx, impl->end_block);
2315
2316 compile_assert(ctx, ctx->stack == 0);
2317
2318 /* at this point, we should have a single empty block,
2319 * into which we emit the 'end' instruction.
2320 */
2321 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2322
2323 /* If stream-out (aka transform-feedback) enabled, emit the
2324 * stream-out instructions, followed by a new empty block (into
2325 * which the 'end' instruction lands).
2326 *
2327 * NOTE: it is done in this order, rather than inserting before
2328 * we emit end_block, because NIR guarantees that all blocks
2329 * flow into end_block, and that end_block has no successors.
2330 * So by re-purposing end_block as the first block of stream-
2331 * out, we guarantee that all exit paths flow into the stream-
2332 * out instructions.
2333 */
2334 if ((ctx->compiler->gpu_id < 500) &&
2335 (ctx->so->shader->stream_output.num_outputs > 0) &&
2336 !ctx->so->binning_pass) {
2337 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2338 emit_stream_out(ctx);
2339 }
2340
2341 ir3_END(ctx->block);
2342 }
2343
2344 static void
2345 setup_input(struct ir3_context *ctx, nir_variable *in)
2346 {
2347 struct ir3_shader_variant *so = ctx->so;
2348 unsigned ncomp = glsl_get_components(in->type);
2349 unsigned n = in->data.driver_location;
2350 unsigned frac = in->data.location_frac;
2351 unsigned slot = in->data.location;
2352
2353 /* skip unread inputs, we could end up with (for example), unsplit
2354 * matrix/etc inputs in the case they are not read, so just silently
2355 * skip these.
2356 */
2357 if (ncomp > 4)
2358 return;
2359
2360 so->inputs[n].slot = slot;
2361 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2362 so->inputs_count = MAX2(so->inputs_count, n + 1);
2363 so->inputs[n].interpolate = in->data.interpolation;
2364
2365 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2366
2367 /* if any varyings have 'sample' qualifer, that triggers us
2368 * to run in per-sample mode:
2369 */
2370 so->per_samp |= in->data.sample;
2371
2372 for (int i = 0; i < ncomp; i++) {
2373 struct ir3_instruction *instr = NULL;
2374 unsigned idx = (n * 4) + i + frac;
2375
2376 if (slot == VARYING_SLOT_POS) {
2377 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2378 } else if (slot == VARYING_SLOT_PNTC) {
2379 /* see for example st_nir_fixup_varying_slots().. this is
2380 * maybe a bit mesa/st specific. But we need things to line
2381 * up for this in fdN_program:
2382 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2383 * if (emit->sprite_coord_enable & texmask) {
2384 * ...
2385 * }
2386 */
2387 so->inputs[n].slot = VARYING_SLOT_VAR8;
2388 so->inputs[n].bary = true;
2389 instr = create_frag_input(ctx, false, idx);
2390 } else {
2391 bool use_ldlv = false;
2392
2393 /* detect the special case for front/back colors where
2394 * we need to do flat vs smooth shading depending on
2395 * rast state:
2396 */
2397 if (in->data.interpolation == INTERP_MODE_NONE) {
2398 switch (slot) {
2399 case VARYING_SLOT_COL0:
2400 case VARYING_SLOT_COL1:
2401 case VARYING_SLOT_BFC0:
2402 case VARYING_SLOT_BFC1:
2403 so->inputs[n].rasterflat = true;
2404 break;
2405 default:
2406 break;
2407 }
2408 }
2409
2410 if (ctx->compiler->flat_bypass) {
2411 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2412 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2413 use_ldlv = true;
2414 }
2415
2416 so->inputs[n].bary = true;
2417
2418 instr = create_frag_input(ctx, use_ldlv, idx);
2419 }
2420
2421 compile_assert(ctx, idx < ctx->ir->ninputs);
2422
2423 ctx->ir->inputs[idx] = instr;
2424 }
2425 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2426 for (int i = 0; i < ncomp; i++) {
2427 unsigned idx = (n * 4) + i + frac;
2428 compile_assert(ctx, idx < ctx->ir->ninputs);
2429 ctx->ir->inputs[idx] = create_input(ctx, idx);
2430 }
2431 } else {
2432 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2433 }
2434
2435 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2436 so->total_in += ncomp;
2437 }
2438 }
2439
2440 /* Initially we assign non-packed inloc's for varyings, as we don't really
2441 * know up-front which components will be unused. After all the compilation
2442 * stages we scan the shader to see which components are actually used, and
2443 * re-pack the inlocs to eliminate unneeded varyings.
2444 */
2445 static void
2446 pack_inlocs(struct ir3_context *ctx)
2447 {
2448 struct ir3_shader_variant *so = ctx->so;
2449 uint8_t used_components[so->inputs_count];
2450
2451 memset(used_components, 0, sizeof(used_components));
2452
2453 /*
2454 * First Step: scan shader to find which bary.f/ldlv remain:
2455 */
2456
2457 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2458 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2459 if (is_input(instr)) {
2460 unsigned inloc = instr->regs[1]->iim_val;
2461 unsigned i = inloc / 4;
2462 unsigned j = inloc % 4;
2463
2464 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2465 compile_assert(ctx, i < so->inputs_count);
2466
2467 used_components[i] |= 1 << j;
2468 }
2469 }
2470 }
2471
2472 /*
2473 * Second Step: reassign varying inloc/slots:
2474 */
2475
2476 unsigned actual_in = 0;
2477 unsigned inloc = 0;
2478
2479 for (unsigned i = 0; i < so->inputs_count; i++) {
2480 unsigned compmask = 0, maxcomp = 0;
2481
2482 so->inputs[i].ncomp = 0;
2483 so->inputs[i].inloc = inloc;
2484 so->inputs[i].bary = false;
2485
2486 for (unsigned j = 0; j < 4; j++) {
2487 if (!(used_components[i] & (1 << j)))
2488 continue;
2489
2490 compmask |= (1 << j);
2491 actual_in++;
2492 so->inputs[i].ncomp++;
2493 maxcomp = j + 1;
2494
2495 /* at this point, since used_components[i] mask is only
2496 * considering varyings (ie. not sysvals) we know this
2497 * is a varying:
2498 */
2499 so->inputs[i].bary = true;
2500 }
2501
2502 if (so->inputs[i].bary) {
2503 so->varying_in++;
2504 so->inputs[i].compmask = (1 << maxcomp) - 1;
2505 inloc += maxcomp;
2506 }
2507 }
2508
2509 /*
2510 * Third Step: reassign packed inloc's:
2511 */
2512
2513 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2514 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2515 if (is_input(instr)) {
2516 unsigned inloc = instr->regs[1]->iim_val;
2517 unsigned i = inloc / 4;
2518 unsigned j = inloc % 4;
2519
2520 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2521 }
2522 }
2523 }
2524 }
2525
2526 static void
2527 setup_output(struct ir3_context *ctx, nir_variable *out)
2528 {
2529 struct ir3_shader_variant *so = ctx->so;
2530 unsigned ncomp = glsl_get_components(out->type);
2531 unsigned n = out->data.driver_location;
2532 unsigned frac = out->data.location_frac;
2533 unsigned slot = out->data.location;
2534 unsigned comp = 0;
2535
2536 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2537 switch (slot) {
2538 case FRAG_RESULT_DEPTH:
2539 comp = 2; /* tgsi will write to .z component */
2540 so->writes_pos = true;
2541 break;
2542 case FRAG_RESULT_COLOR:
2543 so->color0_mrt = 1;
2544 break;
2545 case FRAG_RESULT_SAMPLE_MASK:
2546 so->writes_smask = true;
2547 break;
2548 default:
2549 if (slot >= FRAG_RESULT_DATA0)
2550 break;
2551 ir3_context_error(ctx, "unknown FS output name: %s\n",
2552 gl_frag_result_name(slot));
2553 }
2554 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2555 switch (slot) {
2556 case VARYING_SLOT_POS:
2557 so->writes_pos = true;
2558 break;
2559 case VARYING_SLOT_PSIZ:
2560 so->writes_psize = true;
2561 break;
2562 case VARYING_SLOT_COL0:
2563 case VARYING_SLOT_COL1:
2564 case VARYING_SLOT_BFC0:
2565 case VARYING_SLOT_BFC1:
2566 case VARYING_SLOT_FOGC:
2567 case VARYING_SLOT_CLIP_DIST0:
2568 case VARYING_SLOT_CLIP_DIST1:
2569 case VARYING_SLOT_CLIP_VERTEX:
2570 break;
2571 default:
2572 if (slot >= VARYING_SLOT_VAR0)
2573 break;
2574 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2575 break;
2576 ir3_context_error(ctx, "unknown VS output name: %s\n",
2577 gl_varying_slot_name(slot));
2578 }
2579 } else {
2580 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2581 }
2582
2583 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2584
2585 so->outputs[n].slot = slot;
2586 so->outputs[n].regid = regid(n, comp);
2587 so->outputs_count = MAX2(so->outputs_count, n + 1);
2588
2589 for (int i = 0; i < ncomp; i++) {
2590 unsigned idx = (n * 4) + i + frac;
2591 compile_assert(ctx, idx < ctx->ir->noutputs);
2592 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2593 }
2594
2595 /* if varying packing doesn't happen, we could end up in a situation
2596 * with "holes" in the output, and since the per-generation code that
2597 * sets up varying linkage registers doesn't expect to have more than
2598 * one varying per vec4 slot, pad the holes.
2599 *
2600 * Note that this should probably generate a performance warning of
2601 * some sort.
2602 */
2603 for (int i = 0; i < frac; i++) {
2604 unsigned idx = (n * 4) + i;
2605 if (!ctx->ir->outputs[idx]) {
2606 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2607 }
2608 }
2609 }
2610
2611 static int
2612 max_drvloc(struct exec_list *vars)
2613 {
2614 int drvloc = -1;
2615 nir_foreach_variable(var, vars) {
2616 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2617 }
2618 return drvloc;
2619 }
2620
2621 static const unsigned max_sysvals[] = {
2622 [MESA_SHADER_FRAGMENT] = 24, // TODO
2623 [MESA_SHADER_VERTEX] = 16,
2624 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2625 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2626 };
2627
2628 static void
2629 emit_instructions(struct ir3_context *ctx)
2630 {
2631 unsigned ninputs, noutputs;
2632 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2633
2634 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2635 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2636
2637 /* we need to leave room for sysvals:
2638 */
2639 ninputs += max_sysvals[ctx->so->type];
2640
2641 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2642
2643 /* Create inputs in first block: */
2644 ctx->block = get_block(ctx, nir_start_block(fxn));
2645 ctx->in_block = ctx->block;
2646 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2647
2648 ninputs -= max_sysvals[ctx->so->type];
2649
2650 /* for fragment shader, the vcoord input register is used as the
2651 * base for bary.f varying fetch instrs:
2652 *
2653 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2654 * until emit_intrinsic when we know they are actually needed.
2655 * For now, we defer creating ctx->ij_centroid, etc, since we
2656 * only need ij_pixel for "old style" varying inputs (ie.
2657 * tgsi_to_nir)
2658 */
2659 struct ir3_instruction *vcoord = NULL;
2660 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2661 struct ir3_instruction *xy[2];
2662
2663 vcoord = create_input_compmask(ctx, 0, 0x3);
2664 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2665
2666 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2667 }
2668
2669 /* Setup inputs: */
2670 nir_foreach_variable(var, &ctx->s->inputs) {
2671 setup_input(ctx, var);
2672 }
2673
2674 /* Defer add_sysval_input() stuff until after setup_inputs(),
2675 * because sysvals need to be appended after varyings:
2676 */
2677 if (vcoord) {
2678 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2679 0x3, vcoord);
2680 }
2681
2682 /* Setup outputs: */
2683 nir_foreach_variable(var, &ctx->s->outputs) {
2684 setup_output(ctx, var);
2685 }
2686
2687 /* Find # of samplers: */
2688 nir_foreach_variable(var, &ctx->s->uniforms) {
2689 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2690 /* just assume that we'll be reading from images.. if it
2691 * is write-only we don't have to count it, but not sure
2692 * if there is a good way to know?
2693 */
2694 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2695 }
2696
2697 /* NOTE: need to do something more clever when we support >1 fxn */
2698 nir_foreach_register(reg, &fxn->registers) {
2699 ir3_declare_array(ctx, reg);
2700 }
2701 /* And emit the body: */
2702 ctx->impl = fxn;
2703 emit_function(ctx, fxn);
2704 }
2705
2706 /* from NIR perspective, we actually have varying inputs. But the varying
2707 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2708 * only actual inputs are the sysvals.
2709 */
2710 static void
2711 fixup_frag_inputs(struct ir3_context *ctx)
2712 {
2713 struct ir3_shader_variant *so = ctx->so;
2714 struct ir3 *ir = ctx->ir;
2715 unsigned i = 0;
2716
2717 /* sysvals should appear at the end of the inputs, drop everything else: */
2718 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2719 i++;
2720
2721 /* at IR level, inputs are always blocks of 4 scalars: */
2722 i *= 4;
2723
2724 ir->inputs = &ir->inputs[i];
2725 ir->ninputs -= i;
2726 }
2727
2728 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2729 * need to assign the tex state indexes for these after we know the
2730 * max tex index.
2731 */
2732 static void
2733 fixup_astc_srgb(struct ir3_context *ctx)
2734 {
2735 struct ir3_shader_variant *so = ctx->so;
2736 /* indexed by original tex idx, value is newly assigned alpha sampler
2737 * state tex idx. Zero is invalid since there is at least one sampler
2738 * if we get here.
2739 */
2740 unsigned alt_tex_state[16] = {0};
2741 unsigned tex_idx = ctx->max_texture_index + 1;
2742 unsigned idx = 0;
2743
2744 so->astc_srgb.base = tex_idx;
2745
2746 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2747 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2748
2749 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2750
2751 if (alt_tex_state[sam->cat5.tex] == 0) {
2752 /* assign new alternate/alpha tex state slot: */
2753 alt_tex_state[sam->cat5.tex] = tex_idx++;
2754 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2755 so->astc_srgb.count++;
2756 }
2757
2758 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2759 }
2760 }
2761
2762 static void
2763 fixup_binning_pass(struct ir3_context *ctx)
2764 {
2765 struct ir3_shader_variant *so = ctx->so;
2766 struct ir3 *ir = ctx->ir;
2767 unsigned i, j;
2768
2769 for (i = 0, j = 0; i < so->outputs_count; i++) {
2770 unsigned slot = so->outputs[i].slot;
2771
2772 /* throw away everything but first position/psize */
2773 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2774 if (i != j) {
2775 so->outputs[j] = so->outputs[i];
2776 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2777 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2778 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2779 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2780 }
2781 j++;
2782 }
2783 }
2784 so->outputs_count = j;
2785 ir->noutputs = j * 4;
2786 }
2787
2788 int
2789 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2790 struct ir3_shader_variant *so)
2791 {
2792 struct ir3_context *ctx;
2793 struct ir3 *ir;
2794 struct ir3_instruction **inputs;
2795 unsigned i;
2796 int ret = 0, max_bary;
2797
2798 assert(!so->ir);
2799
2800 ctx = ir3_context_init(compiler, so);
2801 if (!ctx) {
2802 DBG("INIT failed!");
2803 ret = -1;
2804 goto out;
2805 }
2806
2807 emit_instructions(ctx);
2808
2809 if (ctx->error) {
2810 DBG("EMIT failed!");
2811 ret = -1;
2812 goto out;
2813 }
2814
2815 ir = so->ir = ctx->ir;
2816
2817 /* keep track of the inputs from TGSI perspective.. */
2818 inputs = ir->inputs;
2819
2820 /* but fixup actual inputs for frag shader: */
2821 if (so->type == MESA_SHADER_FRAGMENT)
2822 fixup_frag_inputs(ctx);
2823
2824 /* at this point, for binning pass, throw away unneeded outputs: */
2825 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2826 fixup_binning_pass(ctx);
2827
2828 /* if we want half-precision outputs, mark the output registers
2829 * as half:
2830 */
2831 if (so->key.half_precision) {
2832 for (i = 0; i < ir->noutputs; i++) {
2833 struct ir3_instruction *out = ir->outputs[i];
2834
2835 if (!out)
2836 continue;
2837
2838 /* if frag shader writes z, that needs to be full precision: */
2839 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2840 continue;
2841
2842 out->regs[0]->flags |= IR3_REG_HALF;
2843 /* output could be a fanout (ie. texture fetch output)
2844 * in which case we need to propagate the half-reg flag
2845 * up to the definer so that RA sees it:
2846 */
2847 if (out->opc == OPC_META_FO) {
2848 out = out->regs[1]->instr;
2849 out->regs[0]->flags |= IR3_REG_HALF;
2850 }
2851
2852 if (out->opc == OPC_MOV) {
2853 out->cat1.dst_type = half_type(out->cat1.dst_type);
2854 }
2855 }
2856 }
2857
2858 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2859 printf("BEFORE CP:\n");
2860 ir3_print(ir);
2861 }
2862
2863 ir3_cp(ir, so);
2864
2865 /* at this point, for binning pass, throw away unneeded outputs:
2866 * Note that for a6xx and later, we do this after ir3_cp to ensure
2867 * that the uniform/constant layout for BS and VS matches, so that
2868 * we can re-use same VS_CONST state group.
2869 */
2870 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2871 fixup_binning_pass(ctx);
2872
2873 /* Insert mov if there's same instruction for each output.
2874 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2875 */
2876 for (int i = ir->noutputs - 1; i >= 0; i--) {
2877 if (!ir->outputs[i])
2878 continue;
2879 for (unsigned j = 0; j < i; j++) {
2880 if (ir->outputs[i] == ir->outputs[j]) {
2881 ir->outputs[i] =
2882 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2883 }
2884 }
2885 }
2886
2887 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2888 printf("BEFORE GROUPING:\n");
2889 ir3_print(ir);
2890 }
2891
2892 ir3_sched_add_deps(ir);
2893
2894 /* Group left/right neighbors, inserting mov's where needed to
2895 * solve conflicts:
2896 */
2897 ir3_group(ir);
2898
2899 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2900 printf("AFTER GROUPING:\n");
2901 ir3_print(ir);
2902 }
2903
2904 ir3_depth(ir);
2905
2906 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2907 printf("AFTER DEPTH:\n");
2908 ir3_print(ir);
2909 }
2910
2911 /* do Sethi–Ullman numbering before scheduling: */
2912 ir3_sun(ir);
2913
2914 ret = ir3_sched(ir);
2915 if (ret) {
2916 DBG("SCHED failed!");
2917 goto out;
2918 }
2919
2920 if (compiler->gpu_id >= 600) {
2921 ir3_a6xx_fixup_atomic_dests(ir, so);
2922 }
2923
2924 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2925 printf("AFTER SCHED:\n");
2926 ir3_print(ir);
2927 }
2928
2929 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2930 if (ret) {
2931 DBG("RA failed!");
2932 goto out;
2933 }
2934
2935 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2936 printf("AFTER RA:\n");
2937 ir3_print(ir);
2938 }
2939
2940 if (so->type == MESA_SHADER_FRAGMENT)
2941 pack_inlocs(ctx);
2942
2943 /* fixup input/outputs: */
2944 for (i = 0; i < so->outputs_count; i++) {
2945 /* sometimes we get outputs that don't write the .x coord, like:
2946 *
2947 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2948 *
2949 * Presumably the result of varying packing and then eliminating
2950 * some unneeded varyings? Just skip head to the first valid
2951 * component of the output.
2952 */
2953 for (unsigned j = 0; j < 4; j++) {
2954 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2955 if (instr) {
2956 so->outputs[i].regid = instr->regs[0]->num;
2957 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
2958 break;
2959 }
2960 }
2961 }
2962
2963 /* Note that some or all channels of an input may be unused: */
2964 for (i = 0; i < so->inputs_count; i++) {
2965 unsigned j, reg = regid(63,0);
2966 bool half = false;
2967 for (j = 0; j < 4; j++) {
2968 struct ir3_instruction *in = inputs[(i*4) + j];
2969
2970 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2971 reg = in->regs[0]->num - j;
2972 if (half) {
2973 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
2974 } else {
2975 half = !!(in->regs[0]->flags & IR3_REG_HALF);
2976 }
2977 }
2978 }
2979 so->inputs[i].regid = reg;
2980 so->inputs[i].half = half;
2981 }
2982
2983 if (ctx->astc_srgb)
2984 fixup_astc_srgb(ctx);
2985
2986 /* We need to do legalize after (for frag shader's) the "bary.f"
2987 * offsets (inloc) have been assigned.
2988 */
2989 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
2990
2991 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2992 printf("AFTER LEGALIZE:\n");
2993 ir3_print(ir);
2994 }
2995
2996 so->branchstack = ctx->max_stack;
2997
2998 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2999 if (so->type == MESA_SHADER_FRAGMENT)
3000 so->total_in = max_bary + 1;
3001
3002 so->max_sun = ir->max_sun;
3003
3004 out:
3005 if (ret) {
3006 if (so->ir)
3007 ir3_destroy(so->ir);
3008 so->ir = NULL;
3009 }
3010 ir3_context_free(ctx);
3011
3012 return ret;
3013 }