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freedreno/ir3: Support 16-bit comparison instructions
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 break;
392 case nir_op_b2f16:
393 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
394 break;
395 case nir_op_b2f32:
396 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
397 break;
398 case nir_op_b2i8:
399 case nir_op_b2i16:
400 case nir_op_b2i32:
401 dst[0] = ir3_b2n(b, src[0]);
402 break;
403 case nir_op_i2b32:
404 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
405 dst[0]->cat2.condition = IR3_COND_NE;
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], dst_type);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 case nir_op_fddx_coarse:
455 dst[0] = ir3_DSX(b, src[0], 0);
456 dst[0]->cat5.type = TYPE_F32;
457 break;
458 case nir_op_fddy:
459 case nir_op_fddy_coarse:
460 dst[0] = ir3_DSY(b, src[0], 0);
461 dst[0]->cat5.type = TYPE_F32;
462 break;
463 break;
464 case nir_op_flt16:
465 case nir_op_flt32:
466 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
467 dst[0]->cat2.condition = IR3_COND_LT;
468 break;
469 case nir_op_fge16:
470 case nir_op_fge32:
471 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
472 dst[0]->cat2.condition = IR3_COND_GE;
473 break;
474 case nir_op_feq16:
475 case nir_op_feq32:
476 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
477 dst[0]->cat2.condition = IR3_COND_EQ;
478 break;
479 case nir_op_fne16:
480 case nir_op_fne32:
481 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
482 dst[0]->cat2.condition = IR3_COND_NE;
483 break;
484 case nir_op_fceil:
485 dst[0] = ir3_CEIL_F(b, src[0], 0);
486 break;
487 case nir_op_ffloor:
488 dst[0] = ir3_FLOOR_F(b, src[0], 0);
489 break;
490 case nir_op_ftrunc:
491 dst[0] = ir3_TRUNC_F(b, src[0], 0);
492 break;
493 case nir_op_fround_even:
494 dst[0] = ir3_RNDNE_F(b, src[0], 0);
495 break;
496 case nir_op_fsign:
497 dst[0] = ir3_SIGN_F(b, src[0], 0);
498 break;
499
500 case nir_op_fsin:
501 dst[0] = ir3_SIN(b, src[0], 0);
502 break;
503 case nir_op_fcos:
504 dst[0] = ir3_COS(b, src[0], 0);
505 break;
506 case nir_op_frsq:
507 dst[0] = ir3_RSQ(b, src[0], 0);
508 break;
509 case nir_op_frcp:
510 dst[0] = ir3_RCP(b, src[0], 0);
511 break;
512 case nir_op_flog2:
513 dst[0] = ir3_LOG2(b, src[0], 0);
514 break;
515 case nir_op_fexp2:
516 dst[0] = ir3_EXP2(b, src[0], 0);
517 break;
518 case nir_op_fsqrt:
519 dst[0] = ir3_SQRT(b, src[0], 0);
520 break;
521
522 case nir_op_iabs:
523 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
524 break;
525 case nir_op_iadd:
526 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
527 break;
528 case nir_op_iand:
529 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
530 break;
531 case nir_op_imax:
532 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_umax:
535 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_imin:
538 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_umin:
541 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_umul_low:
544 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_imadsh_mix16:
547 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
548 break;
549 case nir_op_imad24_ir3:
550 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
551 break;
552 case nir_op_imul24:
553 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_ineg:
556 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
557 break;
558 case nir_op_inot:
559 dst[0] = ir3_NOT_B(b, src[0], 0);
560 break;
561 case nir_op_ior:
562 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishl:
565 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ishr:
568 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_isub:
571 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ixor:
574 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ushr:
577 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ilt16:
580 case nir_op_ilt32:
581 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
582 dst[0]->cat2.condition = IR3_COND_LT;
583 break;
584 case nir_op_ige16:
585 case nir_op_ige32:
586 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
587 dst[0]->cat2.condition = IR3_COND_GE;
588 break;
589 case nir_op_ieq16:
590 case nir_op_ieq32:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_EQ;
593 break;
594 case nir_op_ine16:
595 case nir_op_ine32:
596 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_NE;
598 break;
599 case nir_op_ult16:
600 case nir_op_ult32:
601 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_uge16:
605 case nir_op_uge32:
606 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609
610 case nir_op_b32csel: {
611 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
612 compile_assert(ctx, bs[1] == bs[2]);
613 /* the boolean condition is 32b even if src[1] and src[2] are
614 * half-precision, but sel.b16 wants all three src's to be the
615 * same type.
616 */
617 if (bs[1] < 32)
618 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
619 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
620 break;
621 }
622 case nir_op_bit_count: {
623 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
624 // double check on earlier gen's. Once half-precision support is
625 // in place, this should probably move to a NIR lowering pass:
626 struct ir3_instruction *hi, *lo;
627
628 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
629 TYPE_U32, TYPE_U16);
630 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
631
632 hi = ir3_CBITS_B(b, hi, 0);
633 lo = ir3_CBITS_B(b, lo, 0);
634
635 // TODO maybe the builders should default to making dst half-precision
636 // if the src's were half precision, to make this less awkward.. otoh
637 // we should probably just do this lowering in NIR.
638 hi->regs[0]->flags |= IR3_REG_HALF;
639 lo->regs[0]->flags |= IR3_REG_HALF;
640
641 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
642 dst[0]->regs[0]->flags |= IR3_REG_HALF;
643 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
644 break;
645 }
646 case nir_op_ifind_msb: {
647 struct ir3_instruction *cmp;
648 dst[0] = ir3_CLZ_S(b, src[0], 0);
649 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
650 cmp->cat2.condition = IR3_COND_GE;
651 dst[0] = ir3_SEL_B32(b,
652 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
653 cmp, 0, dst[0], 0);
654 break;
655 }
656 case nir_op_ufind_msb:
657 dst[0] = ir3_CLZ_B(b, src[0], 0);
658 dst[0] = ir3_SEL_B32(b,
659 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
660 src[0], 0, dst[0], 0);
661 break;
662 case nir_op_find_lsb:
663 dst[0] = ir3_BFREV_B(b, src[0], 0);
664 dst[0] = ir3_CLZ_B(b, dst[0], 0);
665 break;
666 case nir_op_bitfield_reverse:
667 dst[0] = ir3_BFREV_B(b, src[0], 0);
668 break;
669
670 default:
671 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
672 nir_op_infos[alu->op].name);
673 break;
674 }
675
676 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
677 assert(dst_sz == 1);
678
679 if (nir_dest_bit_size(alu->dest.dest) < 32)
680 dst[0]->regs[0]->flags |= IR3_REG_HALF;
681
682 dst[0] = ir3_n2b(b, dst[0]);
683 }
684
685 if (nir_dest_bit_size(alu->dest.dest) < 32) {
686 for (unsigned i = 0; i < dst_sz; i++) {
687 dst[i]->regs[0]->flags |= IR3_REG_HALF;
688 }
689 }
690
691 ir3_put_dst(ctx, &alu->dest.dest);
692 }
693
694 /* handles direct/indirect UBO reads: */
695 static void
696 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
697 struct ir3_instruction **dst)
698 {
699 struct ir3_block *b = ctx->block;
700 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
701 /* UBO addresses are the first driver params, but subtract 2 here to
702 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
703 * is the uniforms: */
704 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
705 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
706 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
707
708 int off = 0;
709
710 /* First src is ubo index, which could either be an immed or not: */
711 src0 = ir3_get_src(ctx, &intr->src[0])[0];
712 if (is_same_type_mov(src0) &&
713 (src0->regs[1]->flags & IR3_REG_IMMED)) {
714 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
715 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
716 } else {
717 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
718 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
719
720 /* NOTE: since relative addressing is used, make sure constlen is
721 * at least big enough to cover all the UBO addresses, since the
722 * assembler won't know what the max address reg is.
723 */
724 ctx->so->constlen = MAX2(ctx->so->constlen,
725 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
726 }
727
728 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
729 addr = base_lo;
730
731 if (nir_src_is_const(intr->src[1])) {
732 off += nir_src_as_uint(intr->src[1]);
733 } else {
734 /* For load_ubo_indirect, second src is indirect offset: */
735 src1 = ir3_get_src(ctx, &intr->src[1])[0];
736
737 /* and add offset to addr: */
738 addr = ir3_ADD_S(b, addr, 0, src1, 0);
739 }
740
741 /* if offset is to large to encode in the ldg, split it out: */
742 if ((off + (intr->num_components * 4)) > 1024) {
743 /* split out the minimal amount to improve the odds that
744 * cp can fit the immediate in the add.s instruction:
745 */
746 unsigned off2 = off + (intr->num_components * 4) - 1024;
747 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
748 off -= off2;
749 }
750
751 if (ptrsz == 2) {
752 struct ir3_instruction *carry;
753
754 /* handle 32b rollover, ie:
755 * if (addr < base_lo)
756 * base_hi++
757 */
758 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
759 carry->cat2.condition = IR3_COND_LT;
760 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
761
762 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
763 }
764
765 for (int i = 0; i < intr->num_components; i++) {
766 struct ir3_instruction *load =
767 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
768 create_immed(b, off + i * 4), 0);
769 load->cat6.type = TYPE_U32;
770 dst[i] = load;
771 }
772 }
773
774 /* src[] = { block_index } */
775 static void
776 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
777 struct ir3_instruction **dst)
778 {
779 /* SSBO size stored as a const starting at ssbo_sizes: */
780 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
781 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
782 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
783 const_state->ssbo_size.off[blk_idx];
784
785 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
786
787 dst[0] = create_uniform(ctx->block, idx);
788 }
789
790 /* src[] = { offset }. const_index[] = { base } */
791 static void
792 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
793 struct ir3_instruction **dst)
794 {
795 struct ir3_block *b = ctx->block;
796 struct ir3_instruction *ldl, *offset;
797 unsigned base;
798
799 offset = ir3_get_src(ctx, &intr->src[0])[0];
800 base = nir_intrinsic_base(intr);
801
802 ldl = ir3_LDL(b, offset, 0,
803 create_immed(b, intr->num_components), 0,
804 create_immed(b, base), 0);
805
806 ldl->cat6.type = utype_dst(intr->dest);
807 ldl->regs[0]->wrmask = MASK(intr->num_components);
808
809 ldl->barrier_class = IR3_BARRIER_SHARED_R;
810 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
811
812 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
813 }
814
815 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
816 static void
817 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
818 {
819 struct ir3_block *b = ctx->block;
820 struct ir3_instruction *stl, *offset;
821 struct ir3_instruction * const *value;
822 unsigned base, wrmask;
823
824 value = ir3_get_src(ctx, &intr->src[0]);
825 offset = ir3_get_src(ctx, &intr->src[1])[0];
826
827 base = nir_intrinsic_base(intr);
828 wrmask = nir_intrinsic_write_mask(intr);
829
830 /* Combine groups of consecutive enabled channels in one write
831 * message. We use ffs to find the first enabled channel and then ffs on
832 * the bit-inverse, down-shifted writemask to determine the length of
833 * the block of enabled bits.
834 *
835 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
836 */
837 while (wrmask) {
838 unsigned first_component = ffs(wrmask) - 1;
839 unsigned length = ffs(~(wrmask >> first_component)) - 1;
840
841 stl = ir3_STL(b, offset, 0,
842 ir3_create_collect(ctx, &value[first_component], length), 0,
843 create_immed(b, length), 0);
844 stl->cat6.dst_offset = first_component + base;
845 stl->cat6.type = utype_src(intr->src[0]);
846 stl->barrier_class = IR3_BARRIER_SHARED_W;
847 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
848
849 array_insert(b, b->keeps, stl);
850
851 /* Clear the bits in the writemask that we just wrote, then try
852 * again to see if more channels are left.
853 */
854 wrmask &= (15 << (first_component + length));
855 }
856 }
857
858 /* src[] = { offset }. const_index[] = { base } */
859 static void
860 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
861 struct ir3_instruction **dst)
862 {
863 struct ir3_block *b = ctx->block;
864 struct ir3_instruction *load, *offset;
865 unsigned base;
866
867 offset = ir3_get_src(ctx, &intr->src[0])[0];
868 base = nir_intrinsic_base(intr);
869
870 load = ir3_LDLW(b, offset, 0,
871 create_immed(b, intr->num_components), 0,
872 create_immed(b, base), 0);
873
874 load->cat6.type = utype_dst(intr->dest);
875 load->regs[0]->wrmask = MASK(intr->num_components);
876
877 load->barrier_class = IR3_BARRIER_SHARED_R;
878 load->barrier_conflict = IR3_BARRIER_SHARED_W;
879
880 ir3_split_dest(b, dst, load, 0, intr->num_components);
881 }
882
883 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
884 static void
885 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
886 {
887 struct ir3_block *b = ctx->block;
888 struct ir3_instruction *store, *offset;
889 struct ir3_instruction * const *value;
890 unsigned base, wrmask;
891
892 value = ir3_get_src(ctx, &intr->src[0]);
893 offset = ir3_get_src(ctx, &intr->src[1])[0];
894
895 base = nir_intrinsic_base(intr);
896 wrmask = nir_intrinsic_write_mask(intr);
897
898 /* Combine groups of consecutive enabled channels in one write
899 * message. We use ffs to find the first enabled channel and then ffs on
900 * the bit-inverse, down-shifted writemask to determine the length of
901 * the block of enabled bits.
902 *
903 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
904 */
905 while (wrmask) {
906 unsigned first_component = ffs(wrmask) - 1;
907 unsigned length = ffs(~(wrmask >> first_component)) - 1;
908
909 store = ir3_STLW(b, offset, 0,
910 ir3_create_collect(ctx, &value[first_component], length), 0,
911 create_immed(b, length), 0);
912
913 store->cat6.dst_offset = first_component + base;
914 store->cat6.type = utype_src(intr->src[0]);
915 store->barrier_class = IR3_BARRIER_SHARED_W;
916 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
917
918 array_insert(b, b->keeps, store);
919
920 /* Clear the bits in the writemask that we just wrote, then try
921 * again to see if more channels are left.
922 */
923 wrmask &= (15 << (first_component + length));
924 }
925 }
926
927 /*
928 * CS shared variable atomic intrinsics
929 *
930 * All of the shared variable atomic memory operations read a value from
931 * memory, compute a new value using one of the operations below, write the
932 * new value to memory, and return the original value read.
933 *
934 * All operations take 2 sources except CompSwap that takes 3. These
935 * sources represent:
936 *
937 * 0: The offset into the shared variable storage region that the atomic
938 * operation will operate on.
939 * 1: The data parameter to the atomic function (i.e. the value to add
940 * in shared_atomic_add, etc).
941 * 2: For CompSwap only: the second data parameter.
942 */
943 static struct ir3_instruction *
944 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
945 {
946 struct ir3_block *b = ctx->block;
947 struct ir3_instruction *atomic, *src0, *src1;
948 type_t type = TYPE_U32;
949
950 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
951 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
952
953 switch (intr->intrinsic) {
954 case nir_intrinsic_shared_atomic_add:
955 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
956 break;
957 case nir_intrinsic_shared_atomic_imin:
958 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
959 type = TYPE_S32;
960 break;
961 case nir_intrinsic_shared_atomic_umin:
962 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
963 break;
964 case nir_intrinsic_shared_atomic_imax:
965 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
966 type = TYPE_S32;
967 break;
968 case nir_intrinsic_shared_atomic_umax:
969 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
970 break;
971 case nir_intrinsic_shared_atomic_and:
972 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
973 break;
974 case nir_intrinsic_shared_atomic_or:
975 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
976 break;
977 case nir_intrinsic_shared_atomic_xor:
978 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
979 break;
980 case nir_intrinsic_shared_atomic_exchange:
981 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
982 break;
983 case nir_intrinsic_shared_atomic_comp_swap:
984 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
985 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
986 ir3_get_src(ctx, &intr->src[2])[0],
987 src1,
988 }, 2);
989 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
990 break;
991 default:
992 unreachable("boo");
993 }
994
995 atomic->cat6.iim_val = 1;
996 atomic->cat6.d = 1;
997 atomic->cat6.type = type;
998 atomic->barrier_class = IR3_BARRIER_SHARED_W;
999 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1000
1001 /* even if nothing consume the result, we can't DCE the instruction: */
1002 array_insert(b, b->keeps, atomic);
1003
1004 return atomic;
1005 }
1006
1007 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1008 * to handle with the image_mapping table..
1009 */
1010 static struct ir3_instruction *
1011 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1012 {
1013 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1014 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1015 struct ir3_instruction *texture, *sampler;
1016
1017 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1018 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1019
1020 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1021 sampler,
1022 texture,
1023 }, 2);
1024 }
1025
1026 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1027 static void
1028 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1029 struct ir3_instruction **dst)
1030 {
1031 struct ir3_block *b = ctx->block;
1032 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1033 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1034 struct ir3_instruction *sam;
1035 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1036 struct ir3_instruction *coords[4];
1037 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1038 type_t type = ir3_get_image_type(var);
1039
1040 /* hmm, this seems a bit odd, but it is what blob does and (at least
1041 * a5xx) just faults on bogus addresses otherwise:
1042 */
1043 if (flags & IR3_INSTR_3D) {
1044 flags &= ~IR3_INSTR_3D;
1045 flags |= IR3_INSTR_A;
1046 }
1047
1048 for (unsigned i = 0; i < ncoords; i++)
1049 coords[i] = src0[i];
1050
1051 if (ncoords == 1)
1052 coords[ncoords++] = create_immed(b, 0);
1053
1054 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1055 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1056
1057 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1058 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1059
1060 ir3_split_dest(b, dst, sam, 0, 4);
1061 }
1062
1063 static void
1064 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1065 struct ir3_instruction **dst)
1066 {
1067 struct ir3_block *b = ctx->block;
1068 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1069 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1070 struct ir3_instruction *sam, *lod;
1071 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1072
1073 lod = create_immed(b, 0);
1074 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1075 samp_tex, lod, NULL);
1076
1077 /* Array size actually ends up in .w rather than .z. This doesn't
1078 * matter for miplevel 0, but for higher mips the value in z is
1079 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1080 * returned, which means that we have to add 1 to it for arrays for
1081 * a3xx.
1082 *
1083 * Note use a temporary dst and then copy, since the size of the dst
1084 * array that is passed in is based on nir's understanding of the
1085 * result size, not the hardware's
1086 */
1087 struct ir3_instruction *tmp[4];
1088
1089 ir3_split_dest(b, tmp, sam, 0, 4);
1090
1091 /* get_size instruction returns size in bytes instead of texels
1092 * for imageBuffer, so we need to divide it by the pixel size
1093 * of the image format.
1094 *
1095 * TODO: This is at least true on a5xx. Check other gens.
1096 */
1097 enum glsl_sampler_dim dim =
1098 glsl_get_sampler_dim(glsl_without_array(var->type));
1099 if (dim == GLSL_SAMPLER_DIM_BUF) {
1100 /* Since all the possible values the divisor can take are
1101 * power-of-two (4, 8, or 16), the division is implemented
1102 * as a shift-right.
1103 * During shader setup, the log2 of the image format's
1104 * bytes-per-pixel should have been emitted in 2nd slot of
1105 * image_dims. See ir3_shader::emit_image_dims().
1106 */
1107 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1108 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1109 const_state->image_dims.off[var->data.driver_location];
1110 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1111
1112 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1113 }
1114
1115 for (unsigned i = 0; i < ncoords; i++)
1116 dst[i] = tmp[i];
1117
1118 if (flags & IR3_INSTR_A) {
1119 if (ctx->compiler->levels_add_one) {
1120 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1121 } else {
1122 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1123 }
1124 }
1125 }
1126
1127 static void
1128 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1129 {
1130 struct ir3_block *b = ctx->block;
1131 struct ir3_instruction *barrier;
1132
1133 switch (intr->intrinsic) {
1134 case nir_intrinsic_barrier:
1135 barrier = ir3_BAR(b);
1136 barrier->cat7.g = true;
1137 barrier->cat7.l = true;
1138 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1139 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1140 break;
1141 case nir_intrinsic_memory_barrier:
1142 barrier = ir3_FENCE(b);
1143 barrier->cat7.g = true;
1144 barrier->cat7.r = true;
1145 barrier->cat7.w = true;
1146 barrier->cat7.l = true;
1147 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1148 IR3_BARRIER_BUFFER_W;
1149 barrier->barrier_conflict =
1150 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1151 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1152 break;
1153 case nir_intrinsic_memory_barrier_atomic_counter:
1154 case nir_intrinsic_memory_barrier_buffer:
1155 barrier = ir3_FENCE(b);
1156 barrier->cat7.g = true;
1157 barrier->cat7.r = true;
1158 barrier->cat7.w = true;
1159 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1160 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1161 IR3_BARRIER_BUFFER_W;
1162 break;
1163 case nir_intrinsic_memory_barrier_image:
1164 // TODO double check if this should have .g set
1165 barrier = ir3_FENCE(b);
1166 barrier->cat7.g = true;
1167 barrier->cat7.r = true;
1168 barrier->cat7.w = true;
1169 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1170 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1171 IR3_BARRIER_IMAGE_W;
1172 break;
1173 case nir_intrinsic_memory_barrier_shared:
1174 barrier = ir3_FENCE(b);
1175 barrier->cat7.g = true;
1176 barrier->cat7.l = true;
1177 barrier->cat7.r = true;
1178 barrier->cat7.w = true;
1179 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1180 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1181 IR3_BARRIER_SHARED_W;
1182 break;
1183 case nir_intrinsic_group_memory_barrier:
1184 barrier = ir3_FENCE(b);
1185 barrier->cat7.g = true;
1186 barrier->cat7.l = true;
1187 barrier->cat7.r = true;
1188 barrier->cat7.w = true;
1189 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1190 IR3_BARRIER_IMAGE_W |
1191 IR3_BARRIER_BUFFER_W;
1192 barrier->barrier_conflict =
1193 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1194 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1195 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1196 break;
1197 default:
1198 unreachable("boo");
1199 }
1200
1201 /* make sure barrier doesn't get DCE'd */
1202 array_insert(b, b->keeps, barrier);
1203 }
1204
1205 static void add_sysval_input_compmask(struct ir3_context *ctx,
1206 gl_system_value slot, unsigned compmask,
1207 struct ir3_instruction *instr)
1208 {
1209 struct ir3_shader_variant *so = ctx->so;
1210 unsigned n = so->inputs_count++;
1211
1212 assert(instr->opc == OPC_META_INPUT);
1213 instr->input.inidx = n;
1214 instr->input.sysval = slot;
1215
1216 so->inputs[n].sysval = true;
1217 so->inputs[n].slot = slot;
1218 so->inputs[n].compmask = compmask;
1219 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1220 so->total_in++;
1221 }
1222
1223 static struct ir3_instruction *
1224 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1225 unsigned compmask)
1226 {
1227 assert(compmask);
1228 struct ir3_instruction *sysval = create_input(ctx, compmask);
1229 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1230 return sysval;
1231 }
1232
1233 static struct ir3_instruction *
1234 get_barycentric_centroid(struct ir3_context *ctx)
1235 {
1236 if (!ctx->ij_centroid) {
1237 struct ir3_instruction *xy[2];
1238 struct ir3_instruction *ij;
1239
1240 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1241 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1242
1243 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1244 }
1245
1246 return ctx->ij_centroid;
1247 }
1248
1249 static struct ir3_instruction *
1250 get_barycentric_sample(struct ir3_context *ctx)
1251 {
1252 if (!ctx->ij_sample) {
1253 struct ir3_instruction *xy[2];
1254 struct ir3_instruction *ij;
1255
1256 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1257 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1258
1259 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1260 }
1261
1262 return ctx->ij_sample;
1263 }
1264
1265 static struct ir3_instruction *
1266 get_barycentric_pixel(struct ir3_context *ctx)
1267 {
1268 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1269 * this to create ij_pixel only on demand:
1270 */
1271 return ctx->ij_pixel;
1272 }
1273
1274 static struct ir3_instruction *
1275 get_frag_coord(struct ir3_context *ctx)
1276 {
1277 if (!ctx->frag_coord) {
1278 struct ir3_block *b = ctx->block;
1279 struct ir3_instruction *xyzw[4];
1280 struct ir3_instruction *hw_frag_coord;
1281
1282 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1283 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1284
1285 /* for frag_coord.xy, we get unsigned values.. we need
1286 * to subtract (integer) 8 and divide by 16 (right-
1287 * shift by 4) then convert to float:
1288 *
1289 * sub.s tmp, src, 8
1290 * shr.b tmp, tmp, 4
1291 * mov.u32f32 dst, tmp
1292 *
1293 */
1294 for (int i = 0; i < 2; i++) {
1295 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1296 create_immed(b, 8), 0);
1297 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1298 create_immed(b, 4), 0);
1299 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1300 }
1301
1302 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1303 ctx->so->frag_coord = true;
1304 }
1305
1306 return ctx->frag_coord;
1307 }
1308
1309 static void
1310 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1311 {
1312 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1313 struct ir3_instruction **dst;
1314 struct ir3_instruction * const *src;
1315 struct ir3_block *b = ctx->block;
1316 int idx, comp;
1317
1318 if (info->has_dest) {
1319 unsigned n = nir_intrinsic_dest_components(intr);
1320 dst = ir3_get_dst(ctx, &intr->dest, n);
1321 } else {
1322 dst = NULL;
1323 }
1324
1325 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1326 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1327
1328 switch (intr->intrinsic) {
1329 case nir_intrinsic_load_uniform:
1330 idx = nir_intrinsic_base(intr);
1331 if (nir_src_is_const(intr->src[0])) {
1332 idx += nir_src_as_uint(intr->src[0]);
1333 for (int i = 0; i < intr->num_components; i++) {
1334 dst[i] = create_uniform_typed(b, idx + i,
1335 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1336 }
1337 } else {
1338 src = ir3_get_src(ctx, &intr->src[0]);
1339 for (int i = 0; i < intr->num_components; i++) {
1340 dst[i] = create_uniform_indirect(b, idx + i,
1341 ir3_get_addr(ctx, src[0], 1));
1342 }
1343 /* NOTE: if relative addressing is used, we set
1344 * constlen in the compiler (to worst-case value)
1345 * since we don't know in the assembler what the max
1346 * addr reg value can be:
1347 */
1348 ctx->so->constlen = MAX2(ctx->so->constlen,
1349 ctx->so->shader->ubo_state.size / 16);
1350 }
1351 break;
1352
1353 case nir_intrinsic_load_vs_primitive_stride_ir3:
1354 dst[0] = create_uniform(b, primitive_param + 0);
1355 break;
1356 case nir_intrinsic_load_vs_vertex_stride_ir3:
1357 dst[0] = create_uniform(b, primitive_param + 1);
1358 break;
1359 case nir_intrinsic_load_hs_patch_stride_ir3:
1360 dst[0] = create_uniform(b, primitive_param + 2);
1361 break;
1362 case nir_intrinsic_load_patch_vertices_in:
1363 dst[0] = create_uniform(b, primitive_param + 3);
1364 break;
1365 case nir_intrinsic_load_tess_param_base_ir3:
1366 dst[0] = create_uniform(b, primitive_param + 4);
1367 dst[1] = create_uniform(b, primitive_param + 5);
1368 break;
1369 case nir_intrinsic_load_tess_factor_base_ir3:
1370 dst[0] = create_uniform(b, primitive_param + 6);
1371 dst[1] = create_uniform(b, primitive_param + 7);
1372 break;
1373
1374 case nir_intrinsic_load_primitive_location_ir3:
1375 idx = nir_intrinsic_driver_location(intr);
1376 dst[0] = create_uniform(b, primitive_map + idx);
1377 break;
1378
1379 case nir_intrinsic_load_gs_header_ir3:
1380 dst[0] = ctx->gs_header;
1381 break;
1382 case nir_intrinsic_load_tcs_header_ir3:
1383 dst[0] = ctx->tcs_header;
1384 break;
1385
1386 case nir_intrinsic_load_primitive_id:
1387 dst[0] = ctx->primitive_id;
1388 break;
1389
1390 case nir_intrinsic_load_tess_coord:
1391 if (!ctx->tess_coord) {
1392 ctx->tess_coord =
1393 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1394 }
1395 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1396
1397 /* Unused, but ir3_put_dst() below wants to free something */
1398 dst[2] = create_immed(b, 0);
1399 break;
1400
1401 case nir_intrinsic_end_patch_ir3:
1402 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1403 struct ir3_instruction *end = ir3_ENDPATCH(b);
1404 array_insert(b, b->keeps, end);
1405
1406 end->barrier_class = IR3_BARRIER_EVERYTHING;
1407 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1408 break;
1409
1410 case nir_intrinsic_store_global_ir3: {
1411 struct ir3_instruction *value, *addr, *offset;
1412
1413 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1414 ir3_get_src(ctx, &intr->src[1])[0],
1415 ir3_get_src(ctx, &intr->src[1])[1]
1416 }, 2);
1417
1418 offset = ir3_get_src(ctx, &intr->src[2])[0];
1419
1420 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1421 intr->num_components);
1422
1423 struct ir3_instruction *stg =
1424 ir3_STG_G(ctx->block, addr, 0, value, 0,
1425 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1426 stg->cat6.type = TYPE_U32;
1427 stg->cat6.iim_val = 1;
1428
1429 array_insert(b, b->keeps, stg);
1430
1431 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1432 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1433 break;
1434 }
1435
1436 case nir_intrinsic_load_global_ir3: {
1437 struct ir3_instruction *addr, *offset;
1438
1439 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1440 ir3_get_src(ctx, &intr->src[0])[0],
1441 ir3_get_src(ctx, &intr->src[0])[1]
1442 }, 2);
1443
1444 offset = ir3_get_src(ctx, &intr->src[1])[0];
1445
1446 struct ir3_instruction *load =
1447 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1448 0, offset, 0);
1449 load->cat6.type = TYPE_U32;
1450 load->regs[0]->wrmask = MASK(intr->num_components);
1451
1452 load->barrier_class = IR3_BARRIER_BUFFER_R;
1453 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1454
1455 ir3_split_dest(b, dst, load, 0, intr->num_components);
1456 break;
1457 }
1458
1459 case nir_intrinsic_load_ubo:
1460 emit_intrinsic_load_ubo(ctx, intr, dst);
1461 break;
1462 case nir_intrinsic_load_frag_coord:
1463 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1464 break;
1465 case nir_intrinsic_load_sample_pos_from_id: {
1466 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1467 * but that doesn't seem necessary.
1468 */
1469 struct ir3_instruction *offset =
1470 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1471 offset->regs[0]->wrmask = 0x3;
1472 offset->cat5.type = TYPE_F32;
1473
1474 ir3_split_dest(b, dst, offset, 0, 2);
1475
1476 break;
1477 }
1478 case nir_intrinsic_load_size_ir3:
1479 if (!ctx->ij_size) {
1480 ctx->ij_size =
1481 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1482 }
1483 dst[0] = ctx->ij_size;
1484 break;
1485 case nir_intrinsic_load_barycentric_centroid:
1486 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1487 break;
1488 case nir_intrinsic_load_barycentric_sample:
1489 if (ctx->so->key.msaa) {
1490 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1491 } else {
1492 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1493 }
1494 break;
1495 case nir_intrinsic_load_barycentric_pixel:
1496 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1497 break;
1498 case nir_intrinsic_load_interpolated_input:
1499 idx = nir_intrinsic_base(intr);
1500 comp = nir_intrinsic_component(intr);
1501 src = ir3_get_src(ctx, &intr->src[0]);
1502 if (nir_src_is_const(intr->src[1])) {
1503 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1504 idx += nir_src_as_uint(intr->src[1]);
1505 for (int i = 0; i < intr->num_components; i++) {
1506 unsigned inloc = idx * 4 + i + comp;
1507 if (ctx->so->inputs[idx].bary &&
1508 !ctx->so->inputs[idx].use_ldlv) {
1509 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1510 } else {
1511 /* for non-varyings use the pre-setup input, since
1512 * that is easier than mapping things back to a
1513 * nir_variable to figure out what it is.
1514 */
1515 dst[i] = ctx->ir->inputs[inloc];
1516 }
1517 }
1518 } else {
1519 ir3_context_error(ctx, "unhandled");
1520 }
1521 break;
1522 case nir_intrinsic_load_input:
1523 idx = nir_intrinsic_base(intr);
1524 comp = nir_intrinsic_component(intr);
1525 if (nir_src_is_const(intr->src[0])) {
1526 idx += nir_src_as_uint(intr->src[0]);
1527 for (int i = 0; i < intr->num_components; i++) {
1528 unsigned n = idx * 4 + i + comp;
1529 dst[i] = ctx->inputs[n];
1530 compile_assert(ctx, ctx->inputs[n]);
1531 }
1532 } else {
1533 src = ir3_get_src(ctx, &intr->src[0]);
1534 struct ir3_instruction *collect =
1535 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1536 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1537 for (int i = 0; i < intr->num_components; i++) {
1538 unsigned n = idx * 4 + i + comp;
1539 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1540 n, addr, collect);
1541 }
1542 }
1543 break;
1544 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1545 * pass and replaced by an ir3-specifc version that adds the
1546 * dword-offset in the last source.
1547 */
1548 case nir_intrinsic_load_ssbo_ir3:
1549 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1550 break;
1551 case nir_intrinsic_store_ssbo_ir3:
1552 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1553 !ctx->s->info.fs.early_fragment_tests)
1554 ctx->so->no_earlyz = true;
1555 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1556 break;
1557 case nir_intrinsic_get_buffer_size:
1558 emit_intrinsic_ssbo_size(ctx, intr, dst);
1559 break;
1560 case nir_intrinsic_ssbo_atomic_add_ir3:
1561 case nir_intrinsic_ssbo_atomic_imin_ir3:
1562 case nir_intrinsic_ssbo_atomic_umin_ir3:
1563 case nir_intrinsic_ssbo_atomic_imax_ir3:
1564 case nir_intrinsic_ssbo_atomic_umax_ir3:
1565 case nir_intrinsic_ssbo_atomic_and_ir3:
1566 case nir_intrinsic_ssbo_atomic_or_ir3:
1567 case nir_intrinsic_ssbo_atomic_xor_ir3:
1568 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1569 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1570 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1571 !ctx->s->info.fs.early_fragment_tests)
1572 ctx->so->no_earlyz = true;
1573 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1574 break;
1575 case nir_intrinsic_load_shared:
1576 emit_intrinsic_load_shared(ctx, intr, dst);
1577 break;
1578 case nir_intrinsic_store_shared:
1579 emit_intrinsic_store_shared(ctx, intr);
1580 break;
1581 case nir_intrinsic_shared_atomic_add:
1582 case nir_intrinsic_shared_atomic_imin:
1583 case nir_intrinsic_shared_atomic_umin:
1584 case nir_intrinsic_shared_atomic_imax:
1585 case nir_intrinsic_shared_atomic_umax:
1586 case nir_intrinsic_shared_atomic_and:
1587 case nir_intrinsic_shared_atomic_or:
1588 case nir_intrinsic_shared_atomic_xor:
1589 case nir_intrinsic_shared_atomic_exchange:
1590 case nir_intrinsic_shared_atomic_comp_swap:
1591 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1592 break;
1593 case nir_intrinsic_image_deref_load:
1594 emit_intrinsic_load_image(ctx, intr, dst);
1595 break;
1596 case nir_intrinsic_image_deref_store:
1597 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1598 !ctx->s->info.fs.early_fragment_tests)
1599 ctx->so->no_earlyz = true;
1600 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1601 break;
1602 case nir_intrinsic_image_deref_size:
1603 emit_intrinsic_image_size(ctx, intr, dst);
1604 break;
1605 case nir_intrinsic_image_deref_atomic_add:
1606 case nir_intrinsic_image_deref_atomic_imin:
1607 case nir_intrinsic_image_deref_atomic_umin:
1608 case nir_intrinsic_image_deref_atomic_imax:
1609 case nir_intrinsic_image_deref_atomic_umax:
1610 case nir_intrinsic_image_deref_atomic_and:
1611 case nir_intrinsic_image_deref_atomic_or:
1612 case nir_intrinsic_image_deref_atomic_xor:
1613 case nir_intrinsic_image_deref_atomic_exchange:
1614 case nir_intrinsic_image_deref_atomic_comp_swap:
1615 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1616 !ctx->s->info.fs.early_fragment_tests)
1617 ctx->so->no_earlyz = true;
1618 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1619 break;
1620 case nir_intrinsic_barrier:
1621 case nir_intrinsic_memory_barrier:
1622 case nir_intrinsic_group_memory_barrier:
1623 case nir_intrinsic_memory_barrier_atomic_counter:
1624 case nir_intrinsic_memory_barrier_buffer:
1625 case nir_intrinsic_memory_barrier_image:
1626 case nir_intrinsic_memory_barrier_shared:
1627 emit_intrinsic_barrier(ctx, intr);
1628 /* note that blk ptr no longer valid, make that obvious: */
1629 b = NULL;
1630 break;
1631 case nir_intrinsic_store_output:
1632 idx = nir_intrinsic_base(intr);
1633 comp = nir_intrinsic_component(intr);
1634 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1635 idx += nir_src_as_uint(intr->src[1]);
1636
1637 src = ir3_get_src(ctx, &intr->src[0]);
1638 for (int i = 0; i < intr->num_components; i++) {
1639 unsigned n = idx * 4 + i + comp;
1640 ctx->outputs[n] = src[i];
1641 }
1642 break;
1643 case nir_intrinsic_load_base_vertex:
1644 case nir_intrinsic_load_first_vertex:
1645 if (!ctx->basevertex) {
1646 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1647 }
1648 dst[0] = ctx->basevertex;
1649 break;
1650 case nir_intrinsic_load_vertex_id_zero_base:
1651 case nir_intrinsic_load_vertex_id:
1652 if (!ctx->vertex_id) {
1653 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1654 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1655 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1656 }
1657 dst[0] = ctx->vertex_id;
1658 break;
1659 case nir_intrinsic_load_instance_id:
1660 if (!ctx->instance_id) {
1661 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1662 }
1663 dst[0] = ctx->instance_id;
1664 break;
1665 case nir_intrinsic_load_sample_id:
1666 ctx->so->per_samp = true;
1667 /* fall-thru */
1668 case nir_intrinsic_load_sample_id_no_per_sample:
1669 if (!ctx->samp_id) {
1670 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1671 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1672 }
1673 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1674 break;
1675 case nir_intrinsic_load_sample_mask_in:
1676 if (!ctx->samp_mask_in) {
1677 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1678 }
1679 dst[0] = ctx->samp_mask_in;
1680 break;
1681 case nir_intrinsic_load_user_clip_plane:
1682 idx = nir_intrinsic_ucp_id(intr);
1683 for (int i = 0; i < intr->num_components; i++) {
1684 unsigned n = idx * 4 + i;
1685 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1686 }
1687 break;
1688 case nir_intrinsic_load_front_face:
1689 if (!ctx->frag_face) {
1690 ctx->so->frag_face = true;
1691 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1692 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1693 }
1694 /* for fragface, we get -1 for back and 0 for front. However this is
1695 * the inverse of what nir expects (where ~0 is true).
1696 */
1697 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1698 dst[0] = ir3_NOT_B(b, dst[0], 0);
1699 break;
1700 case nir_intrinsic_load_local_invocation_id:
1701 if (!ctx->local_invocation_id) {
1702 ctx->local_invocation_id =
1703 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1704 }
1705 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1706 break;
1707 case nir_intrinsic_load_work_group_id:
1708 if (!ctx->work_group_id) {
1709 ctx->work_group_id =
1710 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1711 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1712 }
1713 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1714 break;
1715 case nir_intrinsic_load_num_work_groups:
1716 for (int i = 0; i < intr->num_components; i++) {
1717 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1718 }
1719 break;
1720 case nir_intrinsic_load_local_group_size:
1721 for (int i = 0; i < intr->num_components; i++) {
1722 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1723 }
1724 break;
1725 case nir_intrinsic_discard_if:
1726 case nir_intrinsic_discard: {
1727 struct ir3_instruction *cond, *kill;
1728
1729 if (intr->intrinsic == nir_intrinsic_discard_if) {
1730 /* conditional discard: */
1731 src = ir3_get_src(ctx, &intr->src[0]);
1732 cond = ir3_b2n(b, src[0]);
1733 } else {
1734 /* unconditional discard: */
1735 cond = create_immed(b, 1);
1736 }
1737
1738 /* NOTE: only cmps.*.* can write p0.x: */
1739 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1740 cond->cat2.condition = IR3_COND_NE;
1741
1742 /* condition always goes in predicate register: */
1743 cond->regs[0]->num = regid(REG_P0, 0);
1744 cond->regs[0]->flags &= ~IR3_REG_SSA;
1745
1746 kill = ir3_KILL(b, cond, 0);
1747 array_insert(ctx->ir, ctx->ir->predicates, kill);
1748
1749 array_insert(b, b->keeps, kill);
1750 ctx->so->no_earlyz = true;
1751
1752 break;
1753 }
1754
1755 case nir_intrinsic_cond_end_ir3: {
1756 struct ir3_instruction *cond, *kill;
1757
1758 src = ir3_get_src(ctx, &intr->src[0]);
1759 cond = ir3_b2n(b, src[0]);
1760
1761 /* NOTE: only cmps.*.* can write p0.x: */
1762 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1763 cond->cat2.condition = IR3_COND_NE;
1764
1765 /* condition always goes in predicate register: */
1766 cond->regs[0]->num = regid(REG_P0, 0);
1767
1768 kill = ir3_CONDEND(b, cond, 0);
1769
1770 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1771 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1772
1773 array_insert(ctx->ir, ctx->ir->predicates, kill);
1774 array_insert(b, b->keeps, kill);
1775 break;
1776 }
1777
1778 case nir_intrinsic_load_shared_ir3:
1779 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1780 break;
1781 case nir_intrinsic_store_shared_ir3:
1782 emit_intrinsic_store_shared_ir3(ctx, intr);
1783 break;
1784 default:
1785 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1786 nir_intrinsic_infos[intr->intrinsic].name);
1787 break;
1788 }
1789
1790 if (info->has_dest)
1791 ir3_put_dst(ctx, &intr->dest);
1792 }
1793
1794 static void
1795 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1796 {
1797 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1798 instr->def.num_components);
1799
1800 if (instr->def.bit_size < 32) {
1801 for (int i = 0; i < instr->def.num_components; i++)
1802 dst[i] = create_immed_typed(ctx->block,
1803 instr->value[i].u16,
1804 TYPE_U16);
1805 } else {
1806 for (int i = 0; i < instr->def.num_components; i++)
1807 dst[i] = create_immed_typed(ctx->block,
1808 instr->value[i].u32,
1809 TYPE_U32);
1810 }
1811
1812 }
1813
1814 static void
1815 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1816 {
1817 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1818 undef->def.num_components);
1819 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1820
1821 /* backend doesn't want undefined instructions, so just plug
1822 * in 0.0..
1823 */
1824 for (int i = 0; i < undef->def.num_components; i++)
1825 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1826 }
1827
1828 /*
1829 * texture fetch/sample instructions:
1830 */
1831
1832 static void
1833 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1834 {
1835 unsigned coords, flags = 0;
1836
1837 /* note: would use tex->coord_components.. except txs.. also,
1838 * since array index goes after shadow ref, we don't want to
1839 * count it:
1840 */
1841 switch (tex->sampler_dim) {
1842 case GLSL_SAMPLER_DIM_1D:
1843 case GLSL_SAMPLER_DIM_BUF:
1844 coords = 1;
1845 break;
1846 case GLSL_SAMPLER_DIM_2D:
1847 case GLSL_SAMPLER_DIM_RECT:
1848 case GLSL_SAMPLER_DIM_EXTERNAL:
1849 case GLSL_SAMPLER_DIM_MS:
1850 coords = 2;
1851 break;
1852 case GLSL_SAMPLER_DIM_3D:
1853 case GLSL_SAMPLER_DIM_CUBE:
1854 coords = 3;
1855 flags |= IR3_INSTR_3D;
1856 break;
1857 default:
1858 unreachable("bad sampler_dim");
1859 }
1860
1861 if (tex->is_shadow && tex->op != nir_texop_lod)
1862 flags |= IR3_INSTR_S;
1863
1864 if (tex->is_array && tex->op != nir_texop_lod)
1865 flags |= IR3_INSTR_A;
1866
1867 *flagsp = flags;
1868 *coordsp = coords;
1869 }
1870
1871 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1872 * or immediate (in which case it will get lowered later to a non .s2en
1873 * version of the tex instruction which encode tex/samp as immediates:
1874 */
1875 static struct ir3_instruction *
1876 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1877 {
1878 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1879 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1880 struct ir3_instruction *texture, *sampler;
1881
1882 if (texture_idx >= 0) {
1883 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1884 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1885 } else {
1886 /* TODO what to do for dynamic case? I guess we only need the
1887 * max index for astc srgb workaround so maybe not a problem
1888 * to worry about if we don't enable indirect samplers for
1889 * a4xx?
1890 */
1891 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1892 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1893 }
1894
1895 if (sampler_idx >= 0) {
1896 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1897 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1898 } else {
1899 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1900 }
1901
1902 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1903 sampler,
1904 texture,
1905 }, 2);
1906 }
1907
1908 static void
1909 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1910 {
1911 struct ir3_block *b = ctx->block;
1912 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1913 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1914 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1915 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1916 unsigned i, coords, flags, ncomp;
1917 unsigned nsrc0 = 0, nsrc1 = 0;
1918 type_t type;
1919 opc_t opc = 0;
1920
1921 ncomp = nir_dest_num_components(tex->dest);
1922
1923 coord = off = ddx = ddy = NULL;
1924 lod = proj = compare = sample_index = NULL;
1925
1926 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1927
1928 for (unsigned i = 0; i < tex->num_srcs; i++) {
1929 switch (tex->src[i].src_type) {
1930 case nir_tex_src_coord:
1931 coord = ir3_get_src(ctx, &tex->src[i].src);
1932 break;
1933 case nir_tex_src_bias:
1934 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1935 has_bias = true;
1936 break;
1937 case nir_tex_src_lod:
1938 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1939 has_lod = true;
1940 break;
1941 case nir_tex_src_comparator: /* shadow comparator */
1942 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1943 break;
1944 case nir_tex_src_projector:
1945 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1946 has_proj = true;
1947 break;
1948 case nir_tex_src_offset:
1949 off = ir3_get_src(ctx, &tex->src[i].src);
1950 has_off = true;
1951 break;
1952 case nir_tex_src_ddx:
1953 ddx = ir3_get_src(ctx, &tex->src[i].src);
1954 break;
1955 case nir_tex_src_ddy:
1956 ddy = ir3_get_src(ctx, &tex->src[i].src);
1957 break;
1958 case nir_tex_src_ms_index:
1959 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1960 break;
1961 case nir_tex_src_texture_offset:
1962 case nir_tex_src_sampler_offset:
1963 /* handled in get_tex_samp_src() */
1964 break;
1965 default:
1966 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1967 tex->src[i].src_type);
1968 return;
1969 }
1970 }
1971
1972 switch (tex->op) {
1973 case nir_texop_tex_prefetch:
1974 compile_assert(ctx, !has_bias);
1975 compile_assert(ctx, !has_lod);
1976 compile_assert(ctx, !compare);
1977 compile_assert(ctx, !has_proj);
1978 compile_assert(ctx, !has_off);
1979 compile_assert(ctx, !ddx);
1980 compile_assert(ctx, !ddy);
1981 compile_assert(ctx, !sample_index);
1982 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
1983 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
1984
1985 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
1986 opc = OPC_META_TEX_PREFETCH;
1987 ctx->so->num_sampler_prefetch++;
1988 break;
1989 }
1990 /* fallthru */
1991 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1992 case nir_texop_txb: opc = OPC_SAMB; break;
1993 case nir_texop_txl: opc = OPC_SAML; break;
1994 case nir_texop_txd: opc = OPC_SAMGQ; break;
1995 case nir_texop_txf: opc = OPC_ISAML; break;
1996 case nir_texop_lod: opc = OPC_GETLOD; break;
1997 case nir_texop_tg4:
1998 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1999 * what blob does, seems gather is broken?), and a3xx did
2000 * not support it (but probably could also emulate).
2001 */
2002 switch (tex->component) {
2003 case 0: opc = OPC_GATHER4R; break;
2004 case 1: opc = OPC_GATHER4G; break;
2005 case 2: opc = OPC_GATHER4B; break;
2006 case 3: opc = OPC_GATHER4A; break;
2007 }
2008 break;
2009 case nir_texop_txf_ms_fb:
2010 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2011 default:
2012 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2013 return;
2014 }
2015
2016 tex_info(tex, &flags, &coords);
2017
2018 /*
2019 * lay out the first argument in the proper order:
2020 * - actual coordinates first
2021 * - shadow reference
2022 * - array index
2023 * - projection w
2024 * - starting at offset 4, dpdx.xy, dpdy.xy
2025 *
2026 * bias/lod go into the second arg
2027 */
2028
2029 /* insert tex coords: */
2030 for (i = 0; i < coords; i++)
2031 src0[i] = coord[i];
2032
2033 nsrc0 = i;
2034
2035 /* scale up integer coords for TXF based on the LOD */
2036 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2037 assert(has_lod);
2038 for (i = 0; i < coords; i++)
2039 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2040 }
2041
2042 if (coords == 1) {
2043 /* hw doesn't do 1d, so we treat it as 2d with
2044 * height of 1, and patch up the y coord.
2045 */
2046 if (is_isam(opc)) {
2047 src0[nsrc0++] = create_immed(b, 0);
2048 } else {
2049 src0[nsrc0++] = create_immed(b, fui(0.5));
2050 }
2051 }
2052
2053 if (tex->is_shadow && tex->op != nir_texop_lod)
2054 src0[nsrc0++] = compare;
2055
2056 if (tex->is_array && tex->op != nir_texop_lod) {
2057 struct ir3_instruction *idx = coord[coords];
2058
2059 /* the array coord for cube arrays needs 0.5 added to it */
2060 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2061 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2062
2063 src0[nsrc0++] = idx;
2064 }
2065
2066 if (has_proj) {
2067 src0[nsrc0++] = proj;
2068 flags |= IR3_INSTR_P;
2069 }
2070
2071 /* pad to 4, then ddx/ddy: */
2072 if (tex->op == nir_texop_txd) {
2073 while (nsrc0 < 4)
2074 src0[nsrc0++] = create_immed(b, fui(0.0));
2075 for (i = 0; i < coords; i++)
2076 src0[nsrc0++] = ddx[i];
2077 if (coords < 2)
2078 src0[nsrc0++] = create_immed(b, fui(0.0));
2079 for (i = 0; i < coords; i++)
2080 src0[nsrc0++] = ddy[i];
2081 if (coords < 2)
2082 src0[nsrc0++] = create_immed(b, fui(0.0));
2083 }
2084
2085 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2086 * with scaled x coord according to requested sample:
2087 */
2088 if (opc == OPC_ISAMM) {
2089 if (ctx->compiler->txf_ms_with_isaml) {
2090 /* the samples are laid out in x dimension as
2091 * 0 1 2 3
2092 * x_ms = (x << ms) + sample_index;
2093 */
2094 struct ir3_instruction *ms;
2095 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2096
2097 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2098 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2099
2100 opc = OPC_ISAML;
2101 } else {
2102 src0[nsrc0++] = sample_index;
2103 }
2104 }
2105
2106 /*
2107 * second argument (if applicable):
2108 * - offsets
2109 * - lod
2110 * - bias
2111 */
2112 if (has_off | has_lod | has_bias) {
2113 if (has_off) {
2114 unsigned off_coords = coords;
2115 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2116 off_coords--;
2117 for (i = 0; i < off_coords; i++)
2118 src1[nsrc1++] = off[i];
2119 if (off_coords < 2)
2120 src1[nsrc1++] = create_immed(b, fui(0.0));
2121 flags |= IR3_INSTR_O;
2122 }
2123
2124 if (has_lod | has_bias)
2125 src1[nsrc1++] = lod;
2126 }
2127
2128 switch (tex->dest_type) {
2129 case nir_type_invalid:
2130 case nir_type_float:
2131 type = TYPE_F32;
2132 break;
2133 case nir_type_int:
2134 type = TYPE_S32;
2135 break;
2136 case nir_type_uint:
2137 case nir_type_bool:
2138 type = TYPE_U32;
2139 break;
2140 default:
2141 unreachable("bad dest_type");
2142 }
2143
2144 if (opc == OPC_GETLOD)
2145 type = TYPE_S32;
2146
2147 struct ir3_instruction *samp_tex;
2148
2149 if (tex->op == nir_texop_txf_ms_fb) {
2150 /* only expect a single txf_ms_fb per shader: */
2151 compile_assert(ctx, !ctx->so->fb_read);
2152 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2153
2154 ctx->so->fb_read = true;
2155 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2156 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2157 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2158 }, 2);
2159
2160 ctx->so->num_samp++;
2161 } else {
2162 samp_tex = get_tex_samp_tex_src(ctx, tex);
2163 }
2164
2165 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2166 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2167
2168 if (opc == OPC_META_TEX_PREFETCH) {
2169 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2170
2171 compile_assert(ctx, tex->src[idx].src.is_ssa);
2172
2173 sam = ir3_META_TEX_PREFETCH(b);
2174 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2175 sam->prefetch.input_offset =
2176 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2177 sam->prefetch.tex = tex->texture_index;
2178 sam->prefetch.samp = tex->sampler_index;
2179 } else {
2180 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2181 samp_tex, col0, col1);
2182 }
2183
2184 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2185 assert(opc != OPC_META_TEX_PREFETCH);
2186
2187 /* only need first 3 components: */
2188 sam->regs[0]->wrmask = 0x7;
2189 ir3_split_dest(b, dst, sam, 0, 3);
2190
2191 /* we need to sample the alpha separately with a non-ASTC
2192 * texture state:
2193 */
2194 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2195 samp_tex, col0, col1);
2196
2197 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2198
2199 /* fixup .w component: */
2200 ir3_split_dest(b, &dst[3], sam, 3, 1);
2201 } else {
2202 /* normal (non-workaround) case: */
2203 ir3_split_dest(b, dst, sam, 0, ncomp);
2204 }
2205
2206 /* GETLOD returns results in 4.8 fixed point */
2207 if (opc == OPC_GETLOD) {
2208 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2209
2210 compile_assert(ctx, tex->dest_type == nir_type_float);
2211 for (i = 0; i < 2; i++) {
2212 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2213 factor, 0);
2214 }
2215 }
2216
2217 ir3_put_dst(ctx, &tex->dest);
2218 }
2219
2220 static void
2221 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2222 {
2223 struct ir3_block *b = ctx->block;
2224 struct ir3_instruction **dst, *sam;
2225
2226 dst = ir3_get_dst(ctx, &tex->dest, 1);
2227
2228 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2229 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2230
2231 /* even though there is only one component, since it ends
2232 * up in .y/.z/.w rather than .x, we need a split_dest()
2233 */
2234 if (idx)
2235 ir3_split_dest(b, dst, sam, 0, idx + 1);
2236
2237 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2238 * the value in TEX_CONST_0 is zero-based.
2239 */
2240 if (ctx->compiler->levels_add_one)
2241 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2242
2243 ir3_put_dst(ctx, &tex->dest);
2244 }
2245
2246 static void
2247 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2248 {
2249 struct ir3_block *b = ctx->block;
2250 struct ir3_instruction **dst, *sam;
2251 struct ir3_instruction *lod;
2252 unsigned flags, coords;
2253
2254 tex_info(tex, &flags, &coords);
2255
2256 /* Actually we want the number of dimensions, not coordinates. This
2257 * distinction only matters for cubes.
2258 */
2259 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2260 coords = 2;
2261
2262 dst = ir3_get_dst(ctx, &tex->dest, 4);
2263
2264 compile_assert(ctx, tex->num_srcs == 1);
2265 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2266
2267 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2268
2269 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2270 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2271
2272 ir3_split_dest(b, dst, sam, 0, 4);
2273
2274 /* Array size actually ends up in .w rather than .z. This doesn't
2275 * matter for miplevel 0, but for higher mips the value in z is
2276 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2277 * returned, which means that we have to add 1 to it for arrays.
2278 */
2279 if (tex->is_array) {
2280 if (ctx->compiler->levels_add_one) {
2281 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2282 } else {
2283 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2284 }
2285 }
2286
2287 ir3_put_dst(ctx, &tex->dest);
2288 }
2289
2290 static void
2291 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2292 {
2293 switch (jump->type) {
2294 case nir_jump_break:
2295 case nir_jump_continue:
2296 case nir_jump_return:
2297 /* I *think* we can simply just ignore this, and use the
2298 * successor block link to figure out where we need to
2299 * jump to for break/continue
2300 */
2301 break;
2302 default:
2303 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2304 break;
2305 }
2306 }
2307
2308 static void
2309 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2310 {
2311 switch (instr->type) {
2312 case nir_instr_type_alu:
2313 emit_alu(ctx, nir_instr_as_alu(instr));
2314 break;
2315 case nir_instr_type_deref:
2316 /* ignored, handled as part of the intrinsic they are src to */
2317 break;
2318 case nir_instr_type_intrinsic:
2319 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2320 break;
2321 case nir_instr_type_load_const:
2322 emit_load_const(ctx, nir_instr_as_load_const(instr));
2323 break;
2324 case nir_instr_type_ssa_undef:
2325 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2326 break;
2327 case nir_instr_type_tex: {
2328 nir_tex_instr *tex = nir_instr_as_tex(instr);
2329 /* couple tex instructions get special-cased:
2330 */
2331 switch (tex->op) {
2332 case nir_texop_txs:
2333 emit_tex_txs(ctx, tex);
2334 break;
2335 case nir_texop_query_levels:
2336 emit_tex_info(ctx, tex, 2);
2337 break;
2338 case nir_texop_texture_samples:
2339 emit_tex_info(ctx, tex, 3);
2340 break;
2341 default:
2342 emit_tex(ctx, tex);
2343 break;
2344 }
2345 break;
2346 }
2347 case nir_instr_type_jump:
2348 emit_jump(ctx, nir_instr_as_jump(instr));
2349 break;
2350 case nir_instr_type_phi:
2351 /* we have converted phi webs to regs in NIR by now */
2352 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2353 break;
2354 case nir_instr_type_call:
2355 case nir_instr_type_parallel_copy:
2356 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2357 break;
2358 }
2359 }
2360
2361 static struct ir3_block *
2362 get_block(struct ir3_context *ctx, const nir_block *nblock)
2363 {
2364 struct ir3_block *block;
2365 struct hash_entry *hentry;
2366
2367 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2368 if (hentry)
2369 return hentry->data;
2370
2371 block = ir3_block_create(ctx->ir);
2372 block->nblock = nblock;
2373 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2374
2375 block->predecessors = _mesa_pointer_set_create(block);
2376 set_foreach(nblock->predecessors, sentry) {
2377 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2378 }
2379
2380 return block;
2381 }
2382
2383 static void
2384 emit_block(struct ir3_context *ctx, nir_block *nblock)
2385 {
2386 struct ir3_block *block = get_block(ctx, nblock);
2387
2388 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2389 if (nblock->successors[i]) {
2390 block->successors[i] =
2391 get_block(ctx, nblock->successors[i]);
2392 }
2393 }
2394
2395 ctx->block = block;
2396 list_addtail(&block->node, &ctx->ir->block_list);
2397
2398 /* re-emit addr register in each block if needed: */
2399 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2400 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2401 ctx->addr_ht[i] = NULL;
2402 }
2403
2404 nir_foreach_instr(instr, nblock) {
2405 ctx->cur_instr = instr;
2406 emit_instr(ctx, instr);
2407 ctx->cur_instr = NULL;
2408 if (ctx->error)
2409 return;
2410 }
2411 }
2412
2413 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2414
2415 static void
2416 emit_if(struct ir3_context *ctx, nir_if *nif)
2417 {
2418 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2419
2420 ctx->block->condition =
2421 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2422
2423 emit_cf_list(ctx, &nif->then_list);
2424 emit_cf_list(ctx, &nif->else_list);
2425 }
2426
2427 static void
2428 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2429 {
2430 emit_cf_list(ctx, &nloop->body);
2431 ctx->so->loops++;
2432 }
2433
2434 static void
2435 stack_push(struct ir3_context *ctx)
2436 {
2437 ctx->stack++;
2438 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2439 }
2440
2441 static void
2442 stack_pop(struct ir3_context *ctx)
2443 {
2444 compile_assert(ctx, ctx->stack > 0);
2445 ctx->stack--;
2446 }
2447
2448 static void
2449 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2450 {
2451 foreach_list_typed(nir_cf_node, node, node, list) {
2452 switch (node->type) {
2453 case nir_cf_node_block:
2454 emit_block(ctx, nir_cf_node_as_block(node));
2455 break;
2456 case nir_cf_node_if:
2457 stack_push(ctx);
2458 emit_if(ctx, nir_cf_node_as_if(node));
2459 stack_pop(ctx);
2460 break;
2461 case nir_cf_node_loop:
2462 stack_push(ctx);
2463 emit_loop(ctx, nir_cf_node_as_loop(node));
2464 stack_pop(ctx);
2465 break;
2466 case nir_cf_node_function:
2467 ir3_context_error(ctx, "TODO\n");
2468 break;
2469 }
2470 }
2471 }
2472
2473 /* emit stream-out code. At this point, the current block is the original
2474 * (nir) end block, and nir ensures that all flow control paths terminate
2475 * into the end block. We re-purpose the original end block to generate
2476 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2477 * block holding stream-out write instructions, followed by the new end
2478 * block:
2479 *
2480 * blockOrigEnd {
2481 * p0.x = (vtxcnt < maxvtxcnt)
2482 * // succs: blockStreamOut, blockNewEnd
2483 * }
2484 * blockStreamOut {
2485 * ... stream-out instructions ...
2486 * // succs: blockNewEnd
2487 * }
2488 * blockNewEnd {
2489 * }
2490 */
2491 static void
2492 emit_stream_out(struct ir3_context *ctx)
2493 {
2494 struct ir3 *ir = ctx->ir;
2495 struct ir3_stream_output_info *strmout =
2496 &ctx->so->shader->stream_output;
2497 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2498 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2499 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2500
2501 /* create vtxcnt input in input block at top of shader,
2502 * so that it is seen as live over the entire duration
2503 * of the shader:
2504 */
2505 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2506 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2507
2508 /* at this point, we are at the original 'end' block,
2509 * re-purpose this block to stream-out condition, then
2510 * append stream-out block and new-end block
2511 */
2512 orig_end_block = ctx->block;
2513
2514 // TODO these blocks need to update predecessors..
2515 // maybe w/ store_global intrinsic, we could do this
2516 // stuff in nir->nir pass
2517
2518 stream_out_block = ir3_block_create(ir);
2519 list_addtail(&stream_out_block->node, &ir->block_list);
2520
2521 new_end_block = ir3_block_create(ir);
2522 list_addtail(&new_end_block->node, &ir->block_list);
2523
2524 orig_end_block->successors[0] = stream_out_block;
2525 orig_end_block->successors[1] = new_end_block;
2526 stream_out_block->successors[0] = new_end_block;
2527
2528 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2529 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2530 cond->regs[0]->num = regid(REG_P0, 0);
2531 cond->regs[0]->flags &= ~IR3_REG_SSA;
2532 cond->cat2.condition = IR3_COND_LT;
2533
2534 /* condition goes on previous block to the conditional,
2535 * since it is used to pick which of the two successor
2536 * paths to take:
2537 */
2538 orig_end_block->condition = cond;
2539
2540 /* switch to stream_out_block to generate the stream-out
2541 * instructions:
2542 */
2543 ctx->block = stream_out_block;
2544
2545 /* Calculate base addresses based on vtxcnt. Instructions
2546 * generated for bases not used in following loop will be
2547 * stripped out in the backend.
2548 */
2549 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2550 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2551 unsigned stride = strmout->stride[i];
2552 struct ir3_instruction *base, *off;
2553
2554 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2555
2556 /* 24-bit should be enough: */
2557 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2558 create_immed(ctx->block, stride * 4), 0);
2559
2560 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2561 }
2562
2563 /* Generate the per-output store instructions: */
2564 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2565 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2566 unsigned c = j + strmout->output[i].start_component;
2567 struct ir3_instruction *base, *out, *stg;
2568
2569 base = bases[strmout->output[i].output_buffer];
2570 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2571
2572 stg = ir3_STG(ctx->block, base, 0, out, 0,
2573 create_immed(ctx->block, 1), 0);
2574 stg->cat6.type = TYPE_U32;
2575 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2576
2577 array_insert(ctx->block, ctx->block->keeps, stg);
2578 }
2579 }
2580
2581 /* and finally switch to the new_end_block: */
2582 ctx->block = new_end_block;
2583 }
2584
2585 static void
2586 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2587 {
2588 nir_metadata_require(impl, nir_metadata_block_index);
2589
2590 compile_assert(ctx, ctx->stack == 0);
2591
2592 emit_cf_list(ctx, &impl->body);
2593 emit_block(ctx, impl->end_block);
2594
2595 compile_assert(ctx, ctx->stack == 0);
2596
2597 /* at this point, we should have a single empty block,
2598 * into which we emit the 'end' instruction.
2599 */
2600 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2601
2602 /* If stream-out (aka transform-feedback) enabled, emit the
2603 * stream-out instructions, followed by a new empty block (into
2604 * which the 'end' instruction lands).
2605 *
2606 * NOTE: it is done in this order, rather than inserting before
2607 * we emit end_block, because NIR guarantees that all blocks
2608 * flow into end_block, and that end_block has no successors.
2609 * So by re-purposing end_block as the first block of stream-
2610 * out, we guarantee that all exit paths flow into the stream-
2611 * out instructions.
2612 */
2613 if ((ctx->compiler->gpu_id < 500) &&
2614 (ctx->so->shader->stream_output.num_outputs > 0) &&
2615 !ctx->so->binning_pass) {
2616 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2617 emit_stream_out(ctx);
2618 }
2619
2620 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2621 * NOP and has an epilogue that writes the VS outputs to local storage, to
2622 * be read by the HS. Then it resets execution mask (chmask) and chains
2623 * to the next shader (chsh).
2624 */
2625 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2626 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2627 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2628 struct ir3_instruction *chmask =
2629 ir3_CHMASK(ctx->block);
2630 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2631 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2632
2633 struct ir3_instruction *chsh =
2634 ir3_CHSH(ctx->block);
2635 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2636 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2637 } else {
2638 ir3_END(ctx->block);
2639 }
2640 }
2641
2642 static void
2643 setup_input(struct ir3_context *ctx, nir_variable *in)
2644 {
2645 struct ir3_shader_variant *so = ctx->so;
2646 unsigned ncomp = glsl_get_components(in->type);
2647 unsigned n = in->data.driver_location;
2648 unsigned frac = in->data.location_frac;
2649 unsigned slot = in->data.location;
2650
2651 /* Inputs are loaded using ldlw or ldg for these stages. */
2652 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2653 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2654 ctx->so->type == MESA_SHADER_GEOMETRY)
2655 return;
2656
2657 /* skip unread inputs, we could end up with (for example), unsplit
2658 * matrix/etc inputs in the case they are not read, so just silently
2659 * skip these.
2660 */
2661 if (ncomp > 4)
2662 return;
2663
2664 so->inputs[n].slot = slot;
2665 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2666 so->inputs_count = MAX2(so->inputs_count, n + 1);
2667 so->inputs[n].interpolate = in->data.interpolation;
2668
2669 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2670
2671 /* if any varyings have 'sample' qualifer, that triggers us
2672 * to run in per-sample mode:
2673 */
2674 so->per_samp |= in->data.sample;
2675
2676 for (int i = 0; i < ncomp; i++) {
2677 struct ir3_instruction *instr = NULL;
2678 unsigned idx = (n * 4) + i + frac;
2679
2680 if (slot == VARYING_SLOT_POS) {
2681 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2682 } else if (slot == VARYING_SLOT_PNTC) {
2683 /* see for example st_nir_fixup_varying_slots().. this is
2684 * maybe a bit mesa/st specific. But we need things to line
2685 * up for this in fdN_program:
2686 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2687 * if (emit->sprite_coord_enable & texmask) {
2688 * ...
2689 * }
2690 */
2691 so->inputs[n].slot = VARYING_SLOT_VAR8;
2692 so->inputs[n].bary = true;
2693 instr = create_frag_input(ctx, false, idx);
2694 } else {
2695 /* detect the special case for front/back colors where
2696 * we need to do flat vs smooth shading depending on
2697 * rast state:
2698 */
2699 if (in->data.interpolation == INTERP_MODE_NONE) {
2700 switch (slot) {
2701 case VARYING_SLOT_COL0:
2702 case VARYING_SLOT_COL1:
2703 case VARYING_SLOT_BFC0:
2704 case VARYING_SLOT_BFC1:
2705 so->inputs[n].rasterflat = true;
2706 break;
2707 default:
2708 break;
2709 }
2710 }
2711
2712 if (ctx->compiler->flat_bypass) {
2713 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2714 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2715 so->inputs[n].use_ldlv = true;
2716 }
2717
2718 so->inputs[n].bary = true;
2719
2720 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2721 }
2722
2723 compile_assert(ctx, idx < ctx->ninputs);
2724
2725 ctx->inputs[idx] = instr;
2726 }
2727 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2728 /* We shouldn't have fractional input for VS input.. that only shows
2729 * up with varying packing
2730 */
2731 assert(frac == 0);
2732
2733 struct ir3_instruction *input = create_input(ctx, (1 << ncomp) - 1);
2734 struct ir3_instruction *components[ncomp];
2735
2736 input->input.inidx = n;
2737
2738 ir3_split_dest(ctx->block, components, input, 0, ncomp);
2739
2740 for (int i = 0; i < ncomp; i++) {
2741 unsigned idx = (n * 4) + i + frac;
2742 compile_assert(ctx, idx < ctx->ninputs);
2743 ctx->inputs[idx] = components[i];
2744 }
2745 } else {
2746 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2747 }
2748
2749 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2750 so->total_in += ncomp;
2751 }
2752 }
2753
2754 /* Initially we assign non-packed inloc's for varyings, as we don't really
2755 * know up-front which components will be unused. After all the compilation
2756 * stages we scan the shader to see which components are actually used, and
2757 * re-pack the inlocs to eliminate unneeded varyings.
2758 */
2759 static void
2760 pack_inlocs(struct ir3_context *ctx)
2761 {
2762 struct ir3_shader_variant *so = ctx->so;
2763 uint8_t used_components[so->inputs_count];
2764
2765 memset(used_components, 0, sizeof(used_components));
2766
2767 /*
2768 * First Step: scan shader to find which bary.f/ldlv remain:
2769 */
2770
2771 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2772 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2773 if (is_input(instr)) {
2774 unsigned inloc = instr->regs[1]->iim_val;
2775 unsigned i = inloc / 4;
2776 unsigned j = inloc % 4;
2777
2778 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2779 compile_assert(ctx, i < so->inputs_count);
2780
2781 used_components[i] |= 1 << j;
2782 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2783 for (int n = 0; n < 2; n++) {
2784 unsigned inloc = instr->prefetch.input_offset + n;
2785 unsigned i = inloc / 4;
2786 unsigned j = inloc % 4;
2787
2788 compile_assert(ctx, i < so->inputs_count);
2789
2790 used_components[i] |= 1 << j;
2791 }
2792 }
2793 }
2794 }
2795
2796 /*
2797 * Second Step: reassign varying inloc/slots:
2798 */
2799
2800 unsigned actual_in = 0;
2801 unsigned inloc = 0;
2802
2803 for (unsigned i = 0; i < so->inputs_count; i++) {
2804 unsigned compmask = 0, maxcomp = 0;
2805
2806 so->inputs[i].inloc = inloc;
2807 so->inputs[i].bary = false;
2808
2809 for (unsigned j = 0; j < 4; j++) {
2810 if (!(used_components[i] & (1 << j)))
2811 continue;
2812
2813 compmask |= (1 << j);
2814 actual_in++;
2815 maxcomp = j + 1;
2816
2817 /* at this point, since used_components[i] mask is only
2818 * considering varyings (ie. not sysvals) we know this
2819 * is a varying:
2820 */
2821 so->inputs[i].bary = true;
2822 }
2823
2824 if (so->inputs[i].bary) {
2825 so->varying_in++;
2826 so->inputs[i].compmask = (1 << maxcomp) - 1;
2827 inloc += maxcomp;
2828 }
2829 }
2830
2831 /*
2832 * Third Step: reassign packed inloc's:
2833 */
2834
2835 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2836 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2837 if (is_input(instr)) {
2838 unsigned inloc = instr->regs[1]->iim_val;
2839 unsigned i = inloc / 4;
2840 unsigned j = inloc % 4;
2841
2842 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2843 }
2844 }
2845 }
2846 }
2847
2848 static void
2849 setup_output(struct ir3_context *ctx, nir_variable *out)
2850 {
2851 struct ir3_shader_variant *so = ctx->so;
2852 unsigned ncomp = glsl_get_components(out->type);
2853 unsigned n = out->data.driver_location;
2854 unsigned frac = out->data.location_frac;
2855 unsigned slot = out->data.location;
2856 unsigned comp = 0;
2857
2858 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2859 switch (slot) {
2860 case FRAG_RESULT_DEPTH:
2861 comp = 2; /* tgsi will write to .z component */
2862 so->writes_pos = true;
2863 break;
2864 case FRAG_RESULT_COLOR:
2865 so->color0_mrt = 1;
2866 break;
2867 case FRAG_RESULT_SAMPLE_MASK:
2868 so->writes_smask = true;
2869 break;
2870 default:
2871 if (slot >= FRAG_RESULT_DATA0)
2872 break;
2873 ir3_context_error(ctx, "unknown FS output name: %s\n",
2874 gl_frag_result_name(slot));
2875 }
2876 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2877 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2878 ctx->so->type == MESA_SHADER_GEOMETRY) {
2879 switch (slot) {
2880 case VARYING_SLOT_POS:
2881 so->writes_pos = true;
2882 break;
2883 case VARYING_SLOT_PSIZ:
2884 so->writes_psize = true;
2885 break;
2886 case VARYING_SLOT_PRIMITIVE_ID:
2887 case VARYING_SLOT_LAYER:
2888 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2889 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2890 /* fall through */
2891 case VARYING_SLOT_COL0:
2892 case VARYING_SLOT_COL1:
2893 case VARYING_SLOT_BFC0:
2894 case VARYING_SLOT_BFC1:
2895 case VARYING_SLOT_FOGC:
2896 case VARYING_SLOT_CLIP_DIST0:
2897 case VARYING_SLOT_CLIP_DIST1:
2898 case VARYING_SLOT_CLIP_VERTEX:
2899 break;
2900 default:
2901 if (slot >= VARYING_SLOT_VAR0)
2902 break;
2903 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2904 break;
2905 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2906 _mesa_shader_stage_to_string(ctx->so->type),
2907 gl_varying_slot_name(slot));
2908 }
2909 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2910 /* output lowered to buffer writes. */
2911 return;
2912 } else {
2913 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2914 }
2915
2916 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2917
2918 so->outputs[n].slot = slot;
2919 so->outputs[n].regid = regid(n, comp);
2920 so->outputs_count = MAX2(so->outputs_count, n + 1);
2921
2922 for (int i = 0; i < ncomp; i++) {
2923 unsigned idx = (n * 4) + i + frac;
2924 compile_assert(ctx, idx < ctx->noutputs);
2925 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2926 }
2927
2928 /* if varying packing doesn't happen, we could end up in a situation
2929 * with "holes" in the output, and since the per-generation code that
2930 * sets up varying linkage registers doesn't expect to have more than
2931 * one varying per vec4 slot, pad the holes.
2932 *
2933 * Note that this should probably generate a performance warning of
2934 * some sort.
2935 */
2936 for (int i = 0; i < frac; i++) {
2937 unsigned idx = (n * 4) + i;
2938 if (!ctx->outputs[idx]) {
2939 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2940 }
2941 }
2942 }
2943
2944 static int
2945 max_drvloc(struct exec_list *vars)
2946 {
2947 int drvloc = -1;
2948 nir_foreach_variable(var, vars) {
2949 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2950 }
2951 return drvloc;
2952 }
2953
2954 static void
2955 emit_instructions(struct ir3_context *ctx)
2956 {
2957 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2958
2959 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2960 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2961
2962 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
2963 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
2964
2965 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
2966
2967 /* Create inputs in first block: */
2968 ctx->block = get_block(ctx, nir_start_block(fxn));
2969 ctx->in_block = ctx->block;
2970 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2971
2972 /* for fragment shader, the vcoord input register is used as the
2973 * base for bary.f varying fetch instrs:
2974 *
2975 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2976 * until emit_intrinsic when we know they are actually needed.
2977 * For now, we defer creating ctx->ij_centroid, etc, since we
2978 * only need ij_pixel for "old style" varying inputs (ie.
2979 * tgsi_to_nir)
2980 */
2981 struct ir3_instruction *vcoord = NULL;
2982 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2983 struct ir3_instruction *xy[2];
2984
2985 vcoord = create_input(ctx, 0x3);
2986 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2987
2988 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2989 }
2990
2991 /* Setup inputs: */
2992 nir_foreach_variable(var, &ctx->s->inputs) {
2993 setup_input(ctx, var);
2994 }
2995
2996 /* Defer add_sysval_input() stuff until after setup_inputs(),
2997 * because sysvals need to be appended after varyings:
2998 */
2999 if (vcoord) {
3000 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
3001 0x3, vcoord);
3002 }
3003
3004
3005 /* Tesselation shaders always need primitive ID for indexing the
3006 * BO. Geometry shaders don't always need it but when they do it has be
3007 * delivered and unclobbered in the VS. To make things easy, we always
3008 * make room for it in VS/DS.
3009 */
3010 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3011 bool has_gs = ctx->so->key.has_gs;
3012 switch (ctx->so->type) {
3013 case MESA_SHADER_VERTEX:
3014 if (has_tess) {
3015 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3016 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3017 } else if (has_gs) {
3018 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3019 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3020 }
3021 break;
3022 case MESA_SHADER_TESS_CTRL:
3023 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3024 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3025 break;
3026 case MESA_SHADER_TESS_EVAL:
3027 if (has_gs)
3028 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3029 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3030 break;
3031 case MESA_SHADER_GEOMETRY:
3032 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3033 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3034 break;
3035 default:
3036 break;
3037 }
3038
3039 /* Setup outputs: */
3040 nir_foreach_variable(var, &ctx->s->outputs) {
3041 setup_output(ctx, var);
3042 }
3043
3044 /* Find # of samplers: */
3045 nir_foreach_variable(var, &ctx->s->uniforms) {
3046 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3047 /* just assume that we'll be reading from images.. if it
3048 * is write-only we don't have to count it, but not sure
3049 * if there is a good way to know?
3050 */
3051 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3052 }
3053
3054 /* NOTE: need to do something more clever when we support >1 fxn */
3055 nir_foreach_register(reg, &fxn->registers) {
3056 ir3_declare_array(ctx, reg);
3057 }
3058 /* And emit the body: */
3059 ctx->impl = fxn;
3060 emit_function(ctx, fxn);
3061 }
3062
3063 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3064 * need to assign the tex state indexes for these after we know the
3065 * max tex index.
3066 */
3067 static void
3068 fixup_astc_srgb(struct ir3_context *ctx)
3069 {
3070 struct ir3_shader_variant *so = ctx->so;
3071 /* indexed by original tex idx, value is newly assigned alpha sampler
3072 * state tex idx. Zero is invalid since there is at least one sampler
3073 * if we get here.
3074 */
3075 unsigned alt_tex_state[16] = {0};
3076 unsigned tex_idx = ctx->max_texture_index + 1;
3077 unsigned idx = 0;
3078
3079 so->astc_srgb.base = tex_idx;
3080
3081 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3082 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3083
3084 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3085
3086 if (alt_tex_state[sam->cat5.tex] == 0) {
3087 /* assign new alternate/alpha tex state slot: */
3088 alt_tex_state[sam->cat5.tex] = tex_idx++;
3089 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3090 so->astc_srgb.count++;
3091 }
3092
3093 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3094 }
3095 }
3096
3097 static void
3098 fixup_binning_pass(struct ir3_context *ctx)
3099 {
3100 struct ir3_shader_variant *so = ctx->so;
3101 struct ir3 *ir = ctx->ir;
3102 unsigned i, j;
3103
3104 /* first pass, remove unused outputs from the IR level outputs: */
3105 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3106 struct ir3_instruction *out = ir->outputs[i];
3107 assert(out->opc == OPC_META_COLLECT);
3108 unsigned outidx = out->collect.outidx;
3109 unsigned slot = so->outputs[outidx].slot;
3110
3111 /* throw away everything but first position/psize */
3112 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3113 ir->outputs[j] = ir->outputs[i];
3114 j++;
3115 }
3116 }
3117 ir->outputs_count = j;
3118
3119 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3120 * table:
3121 */
3122 for (i = 0, j = 0; i < so->outputs_count; i++) {
3123 unsigned slot = so->outputs[i].slot;
3124
3125 /* throw away everything but first position/psize */
3126 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3127 so->outputs[j] = so->outputs[i];
3128
3129 /* fixup outidx to point to new output table entry: */
3130 struct ir3_instruction *out;
3131 foreach_output(out, ir) {
3132 if (out->collect.outidx == i) {
3133 out->collect.outidx = j;
3134 break;
3135 }
3136 }
3137
3138 j++;
3139 }
3140 }
3141 so->outputs_count = j;
3142 }
3143
3144 static void
3145 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3146 {
3147 unsigned idx = 0;
3148
3149 /* Collect sampling instructions eligible for pre-dispatch. */
3150 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3151 list_for_each_entry_safe(struct ir3_instruction, instr,
3152 &block->instr_list, node) {
3153 if (instr->opc == OPC_META_TEX_PREFETCH) {
3154 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3155 struct ir3_sampler_prefetch *fetch =
3156 &ctx->so->sampler_prefetch[idx];
3157 idx++;
3158
3159 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3160 fetch->wrmask = instr->regs[0]->wrmask;
3161 fetch->tex_id = instr->prefetch.tex;
3162 fetch->samp_id = instr->prefetch.samp;
3163 fetch->dst = instr->regs[0]->num;
3164 fetch->src = instr->prefetch.input_offset;
3165
3166 ctx->so->total_in =
3167 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3168
3169 /* Disable half precision until supported. */
3170 fetch->half_precision = 0x0;
3171
3172 /* Remove the prefetch placeholder instruction: */
3173 list_delinit(&instr->node);
3174 }
3175 }
3176 }
3177 }
3178
3179 int
3180 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3181 struct ir3_shader_variant *so)
3182 {
3183 struct ir3_context *ctx;
3184 struct ir3 *ir;
3185 int ret = 0, max_bary;
3186
3187 assert(!so->ir);
3188
3189 ctx = ir3_context_init(compiler, so);
3190 if (!ctx) {
3191 DBG("INIT failed!");
3192 ret = -1;
3193 goto out;
3194 }
3195
3196 emit_instructions(ctx);
3197
3198 if (ctx->error) {
3199 DBG("EMIT failed!");
3200 ret = -1;
3201 goto out;
3202 }
3203
3204 ir = so->ir = ctx->ir;
3205
3206 assert((ctx->noutputs % 4) == 0);
3207
3208 /* Setup IR level outputs, which are "collects" that gather
3209 * the scalar components of outputs.
3210 */
3211 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3212 unsigned ncomp = 0;
3213 /* figure out the # of components written:
3214 *
3215 * TODO do we need to handle holes, ie. if .x and .z
3216 * components written, but .y component not written?
3217 */
3218 for (unsigned j = 0; j < 4; j++) {
3219 if (!ctx->outputs[i + j])
3220 break;
3221 ncomp++;
3222 }
3223
3224 /* Note that in some stages, like TCS, store_output is
3225 * lowered to memory writes, so no components of the
3226 * are "written" from the PoV of traditional store-
3227 * output instructions:
3228 */
3229 if (!ncomp)
3230 continue;
3231
3232 struct ir3_instruction *out =
3233 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3234
3235 int outidx = i / 4;
3236 assert(outidx < so->outputs_count);
3237
3238 /* stash index into so->outputs[] so we can map the
3239 * output back to slot/etc later:
3240 */
3241 out->collect.outidx = outidx;
3242
3243 array_insert(ir, ir->outputs, out);
3244 }
3245
3246 /* Set up the gs header as an output for the vertex shader so it won't
3247 * clobber it for the tess ctrl shader.
3248 *
3249 * TODO this could probably be done more cleanly in a nir pass.
3250 */
3251 if (ctx->so->type == MESA_SHADER_VERTEX ||
3252 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3253 if (ctx->primitive_id) {
3254 unsigned n = so->outputs_count++;
3255 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3256
3257 struct ir3_instruction *out =
3258 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3259 out->collect.outidx = n;
3260 array_insert(ir, ir->outputs, out);
3261 }
3262
3263 if (ctx->gs_header) {
3264 unsigned n = so->outputs_count++;
3265 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3266 struct ir3_instruction *out =
3267 ir3_create_collect(ctx, &ctx->gs_header, 1);
3268 out->collect.outidx = n;
3269 array_insert(ir, ir->outputs, out);
3270 }
3271
3272 if (ctx->tcs_header) {
3273 unsigned n = so->outputs_count++;
3274 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3275 struct ir3_instruction *out =
3276 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3277 out->collect.outidx = n;
3278 array_insert(ir, ir->outputs, out);
3279 }
3280 }
3281
3282 /* at this point, for binning pass, throw away unneeded outputs: */
3283 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3284 fixup_binning_pass(ctx);
3285
3286 ir3_debug_print(ir, "BEFORE CP");
3287
3288 ir3_cp(ir, so);
3289
3290 /* at this point, for binning pass, throw away unneeded outputs:
3291 * Note that for a6xx and later, we do this after ir3_cp to ensure
3292 * that the uniform/constant layout for BS and VS matches, so that
3293 * we can re-use same VS_CONST state group.
3294 */
3295 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3296 fixup_binning_pass(ctx);
3297
3298 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3299 * need to make sure not to remove any inputs that are used by
3300 * the nonbinning VS.
3301 */
3302 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3303 so->type == MESA_SHADER_VERTEX) {
3304 for (int i = 0; i < ctx->ninputs; i++) {
3305 struct ir3_instruction *in = ctx->inputs[i];
3306
3307 if (!in)
3308 continue;
3309
3310 unsigned n = i / 4;
3311 unsigned c = i % 4;
3312
3313 debug_assert(n < so->nonbinning->inputs_count);
3314
3315 if (so->nonbinning->inputs[n].sysval)
3316 continue;
3317
3318 /* be sure to keep inputs, even if only used in VS */
3319 if (so->nonbinning->inputs[n].compmask & (1 << c))
3320 array_insert(in->block, in->block->keeps, in);
3321 }
3322 }
3323
3324 ir3_debug_print(ir, "BEFORE GROUPING");
3325
3326 ir3_sched_add_deps(ir);
3327
3328 /* Group left/right neighbors, inserting mov's where needed to
3329 * solve conflicts:
3330 */
3331 ir3_group(ir);
3332
3333 ir3_debug_print(ir, "AFTER GROUPING");
3334
3335 ir3_depth(ir, so);
3336
3337 ir3_debug_print(ir, "AFTER DEPTH");
3338
3339 /* do Sethi–Ullman numbering before scheduling: */
3340 ir3_sun(ir);
3341
3342 ret = ir3_sched(ir);
3343 if (ret) {
3344 DBG("SCHED failed!");
3345 goto out;
3346 }
3347
3348 if (compiler->gpu_id >= 600) {
3349 ir3_a6xx_fixup_atomic_dests(ir, so);
3350 }
3351
3352 ir3_debug_print(ir, "AFTER SCHED");
3353
3354 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3355 * with draw pass VS, so binning and draw pass can both use the
3356 * same VBO state.
3357 *
3358 * Note that VS inputs are expected to be full precision.
3359 */
3360 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3361 (ir->type == MESA_SHADER_VERTEX) &&
3362 so->binning_pass;
3363
3364 if (pre_assign_inputs) {
3365 for (unsigned i = 0; i < ctx->ninputs; i++) {
3366 struct ir3_instruction *instr = ctx->inputs[i];
3367
3368 if (!instr)
3369 continue;
3370
3371 unsigned n = i / 4;
3372 unsigned c = i % 4;
3373 unsigned regid = so->nonbinning->inputs[n].regid + c;
3374
3375 instr->regs[0]->num = regid;
3376 }
3377
3378 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3379 } else if (ctx->tcs_header) {
3380 /* We need to have these values in the same registers between VS and TCS
3381 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3382 */
3383
3384 ctx->tcs_header->regs[0]->num = regid(0, 0);
3385 ctx->primitive_id->regs[0]->num = regid(0, 1);
3386 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3387 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3388 } else if (ctx->gs_header) {
3389 /* We need to have these values in the same registers between producer
3390 * (VS or DS) and GS since the producer chains to GS and doesn't get
3391 * the sysvals redelivered.
3392 */
3393
3394 ctx->gs_header->regs[0]->num = regid(0, 0);
3395 ctx->primitive_id->regs[0]->num = regid(0, 1);
3396 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3397 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3398 } else if (so->num_sampler_prefetch) {
3399 assert(so->type == MESA_SHADER_FRAGMENT);
3400 struct ir3_instruction *instr, *precolor[2];
3401 int idx = 0;
3402
3403 foreach_input(instr, ir) {
3404 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3405 continue;
3406
3407 assert(idx < ARRAY_SIZE(precolor));
3408
3409 precolor[idx] = instr;
3410 instr->regs[0]->num = idx;
3411
3412 idx++;
3413 }
3414 ret = ir3_ra(so, precolor, idx);
3415 } else {
3416 ret = ir3_ra(so, NULL, 0);
3417 }
3418
3419 if (ret) {
3420 DBG("RA failed!");
3421 goto out;
3422 }
3423
3424 ir3_debug_print(ir, "AFTER RA");
3425
3426 if (so->type == MESA_SHADER_FRAGMENT)
3427 pack_inlocs(ctx);
3428
3429 /*
3430 * Fixup inputs/outputs to point to the actual registers assigned:
3431 *
3432 * 1) initialize to r63.x (invalid/unused)
3433 * 2) iterate IR level inputs/outputs and update the variants
3434 * inputs/outputs table based on the assigned registers for
3435 * the remaining inputs/outputs.
3436 */
3437
3438 for (unsigned i = 0; i < so->inputs_count; i++)
3439 so->inputs[i].regid = regid(63, 0);
3440 for (unsigned i = 0; i < so->outputs_count; i++)
3441 so->outputs[i].regid = regid(63, 0);
3442
3443 struct ir3_instruction *out;
3444 foreach_output(out, ir) {
3445 assert(out->opc == OPC_META_COLLECT);
3446 unsigned outidx = out->collect.outidx;
3447
3448 so->outputs[outidx].regid = out->regs[0]->num;
3449 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3450 }
3451
3452 struct ir3_instruction *in;
3453 foreach_input(in, ir) {
3454 assert(in->opc == OPC_META_INPUT);
3455 unsigned inidx = in->input.inidx;
3456
3457 so->inputs[inidx].regid = in->regs[0]->num;
3458 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3459 }
3460
3461 if (ctx->astc_srgb)
3462 fixup_astc_srgb(ctx);
3463
3464 /* We need to do legalize after (for frag shader's) the "bary.f"
3465 * offsets (inloc) have been assigned.
3466 */
3467 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3468
3469 ir3_debug_print(ir, "AFTER LEGALIZE");
3470
3471 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3472 * know what we might have to wait on when coming in from VS chsh.
3473 */
3474 if (so->type == MESA_SHADER_TESS_CTRL ||
3475 so->type == MESA_SHADER_GEOMETRY ) {
3476 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3477 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3478 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3479 break;
3480 }
3481 }
3482 }
3483
3484 so->branchstack = ctx->max_stack;
3485
3486 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3487 if (so->type == MESA_SHADER_FRAGMENT)
3488 so->total_in = max_bary + 1;
3489
3490 so->max_sun = ir->max_sun;
3491
3492 /* Collect sampling instructions eligible for pre-dispatch. */
3493 collect_tex_prefetches(ctx, ir);
3494
3495 out:
3496 if (ret) {
3497 if (so->ir)
3498 ir3_destroy(so->ir);
3499 so->ir = NULL;
3500 }
3501 ir3_context_free(ctx);
3502
3503 return ret;
3504 }