src/freedreno/ir3/ir3_context.h

   1 /*
   2  * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_CONTEXT_H_
  28 #define IR3_CONTEXT_H_
  29
  30 #include "ir3_compiler.h"
  31 #include "ir3_nir.h"
  32 #include "ir3.h"
  33
  34 /* for conditionally setting boolean flag(s): */
  35 #define COND(bool, val) ((bool) ? (val) : 0)
  36
  37 #define DBG(fmt, ...) \
  38                 do { debug_printf("%s:%d: "fmt "\n", \
  39                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  40
  41 /**
  42  * The context for compilation of a single shader.
  43  */
  44 struct ir3_context {
  45         struct ir3_compiler *compiler;
  46
  47         struct nir_shader *s;
  48
  49         struct nir_instr *cur_instr;  /* current instruction, just for debug */
  50
  51         struct ir3 *ir;
  52         struct ir3_shader_variant *so;
  53
  54         struct ir3_block *block;      /* the current block */
  55         struct ir3_block *in_block;   /* block created for shader inputs */
  56
  57         nir_function_impl *impl;
  58
  59         /* For fragment shaders, varyings are not actual shader inputs,
  60          * instead the hw passes a varying-coord which is used with
  61          * bary.f.
  62          *
  63          * But NIR doesn't know that, it still declares varyings as
  64          * inputs.  So we do all the input tracking normally and fix
  65          * things up after compile_instructions()
  66          *
  67          * NOTE that frag_vcoord is the hardware position (possibly it
  68          * is actually an index or tag or some such.. it is *not*
  69          * values that can be directly used for gl_FragCoord..)
  70          */
  71         struct ir3_instruction *frag_vcoord;
  72
  73         /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
  74         struct ir3_instruction *frag_face, *frag_coord;
  75
  76         /* For vertex shaders, keep track of the system values sources */
  77         struct ir3_instruction *vertex_id, *basevertex, *instance_id;
  78
  79         /* For fragment shaders: */
  80         struct ir3_instruction *samp_id, *samp_mask_in;
  81
  82         /* Compute shader inputs: */
  83         struct ir3_instruction *local_invocation_id, *work_group_id;
  84
  85         /* mapping from nir_register to defining instruction: */
  86         struct hash_table *def_ht;
  87
  88         unsigned num_arrays;
  89
  90         /* Tracking for max level of flowcontrol (branchstack) needed
  91          * by a5xx+:
  92          */
  93         unsigned stack, max_stack;
  94
  95         /* a common pattern for indirect addressing is to request the
  96          * same address register multiple times.  To avoid generating
  97          * duplicate instruction sequences (which our backend does not
  98          * try to clean up, since that should be done as the NIR stage)
  99          * we cache the address value generated for a given src value:
 100          *
 101          * Note that we have to cache these per alignment, since same
 102          * src used for an array of vec1 cannot be also used for an
 103          * array of vec4.
 104          */
 105         struct hash_table *addr_ht[4];
 106
 107         /* last dst array, for indirect we need to insert a var-store.
 108          */
 109         struct ir3_instruction **last_dst;
 110         unsigned last_dst_n;
 111
 112         /* maps nir_block to ir3_block, mostly for the purposes of
 113          * figuring out the blocks successors
 114          */
 115         struct hash_table *block_ht;
 116
 117         /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
 118         unsigned astc_srgb;
 119
 120         unsigned samples;             /* bitmask of x,y sample shifts */
 121
 122         unsigned max_texture_index;
 123
 124         /* set if we encounter something we can't handle yet, so we
 125          * can bail cleanly and fallback to TGSI compiler f/e
 126          */
 127         bool error;
 128 };
 129
 130 struct ir3_context * ir3_context_init(struct ir3_compiler *compiler,
 131                 struct ir3_shader_variant *so);
 132 void ir3_context_free(struct ir3_context *ctx);
 133
 134 /* gpu pointer size in units of 32bit registers/slots */
 135 static inline
 136 unsigned ir3_pointer_size(struct ir3_context *ctx)
 137 {
 138         return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
 139 }
 140
 141 struct ir3_instruction ** ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n);
 142 struct ir3_instruction ** ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n);
 143 struct ir3_instruction * const * ir3_get_src(struct ir3_context *ctx, nir_src *src);
 144 void put_dst(struct ir3_context *ctx, nir_dest *dst);
 145 struct ir3_instruction * ir3_create_collect(struct ir3_context *ctx,
 146                 struct ir3_instruction *const *arr, unsigned arrsz);
 147 void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
 148                 struct ir3_instruction *src, unsigned base, unsigned n);
 149
 150 void ir3_context_error(struct ir3_context *ctx, const char *format, ...);
 151
 152 #define compile_assert(ctx, cond) do { \
 153                 if (!(cond)) ir3_context_error((ctx), "failed assert: "#cond"\n"); \
 154         } while (0)
 155
 156 struct ir3_instruction * ir3_get_addr(struct ir3_context *ctx,
 157                 struct ir3_instruction *src, int align);
 158 struct ir3_instruction * ir3_get_predicate(struct ir3_context *ctx,
 159                 struct ir3_instruction *src);
 160
 161 void ir3_declare_array(struct ir3_context *ctx, nir_register *reg);
 162 struct ir3_array * ir3_get_array(struct ir3_context *ctx, nir_register *reg);
 163 struct ir3_instruction *ir3_create_array_load(struct ir3_context *ctx,
 164                 struct ir3_array *arr, int n, struct ir3_instruction *address);
 165 void ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
 166                 struct ir3_instruction *src, struct ir3_instruction *address);
 167
 168 static inline type_t utype_for_size(unsigned bit_size)
 169 {
 170         switch (bit_size) {
 171         case 32: return TYPE_U32;
 172         case 16: return TYPE_U16;
 173         case  8: return TYPE_U8;
 174         default: unreachable("bad bitsize"); return ~0;
 175         }
 176 }
 177
 178 static inline type_t utype_src(nir_src src)
 179 { return utype_for_size(nir_src_bit_size(src)); }
 180
 181 static inline type_t utype_dst(nir_dest dst)
 182 { return utype_for_size(nir_dest_bit_size(dst)); }
 183
 184 #endif /* IR3_CONTEXT_H_ */