src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45         bool progress;
  46 };
  47
  48 /* is it a type preserving mov, with ok flags?
  49  *
  50  * @instr: the mov to consider removing
  51  * @dst_instr: the instruction consuming the mov (instr)
  52  *
  53  * TODO maybe drop allow_flags since this is only false when dst is
  54  * NULL (ie. outputs)
  55  */
  56 static bool is_eligible_mov(struct ir3_instruction *instr,
  57                 struct ir3_instruction *dst_instr, bool allow_flags)
  58 {
  59         if (is_same_type_mov(instr)) {
  60                 struct ir3_register *dst = instr->regs[0];
  61                 struct ir3_register *src = instr->regs[1];
  62                 struct ir3_instruction *src_instr = ssa(src);
  63
  64                 /* only if mov src is SSA (not const/immed): */
  65                 if (!src_instr)
  66                         return false;
  67
  68                 /* no indirect: */
  69                 if (dst->flags & IR3_REG_RELATIV)
  70                         return false;
  71                 if (src->flags & IR3_REG_RELATIV)
  72                         return false;
  73
  74                 if (src->flags & IR3_REG_ARRAY)
  75                         return false;
  76
  77                 if (!allow_flags)
  78                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  79                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  80                                 return false;
  81
  82                 /* If src is coming from fanout/split (ie. one component of a
  83                  * texture fetch, etc) and we have constraints on swizzle of
  84                  * destination, then skip it.
  85                  *
  86                  * We could possibly do a bit better, and copy-propagation if
  87                  * we can CP all components that are being fanned out.
  88                  */
  89                 if (src_instr->opc == OPC_META_SPLIT) {
  90                         if (!dst_instr)
  91                                 return false;
  92                         if (dst_instr->opc == OPC_META_COLLECT)
  93                                 return false;
  94                         if (dst_instr->cp.left || dst_instr->cp.right)
  95                                 return false;
  96                 }
  97
  98                 return true;
  99         }
 100         return false;
 101 }
 102
 103 /* propagate register flags from src to dst.. negates need special
 104  * handling to cancel each other out.
 105  */
 106 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 107 {
 108         unsigned srcflags = src->regs[1]->flags;
 109
 110         /* if what we are combining into already has (abs) flags,
 111          * we can drop (neg) from src:
 112          */
 113         if (*dstflags & IR3_REG_FABS)
 114                 srcflags &= ~IR3_REG_FNEG;
 115         if (*dstflags & IR3_REG_SABS)
 116                 srcflags &= ~IR3_REG_SNEG;
 117
 118         if (srcflags & IR3_REG_FABS)
 119                 *dstflags |= IR3_REG_FABS;
 120         if (srcflags & IR3_REG_SABS)
 121                 *dstflags |= IR3_REG_SABS;
 122         if (srcflags & IR3_REG_FNEG)
 123                 *dstflags ^= IR3_REG_FNEG;
 124         if (srcflags & IR3_REG_SNEG)
 125                 *dstflags ^= IR3_REG_SNEG;
 126         if (srcflags & IR3_REG_BNOT)
 127                 *dstflags ^= IR3_REG_BNOT;
 128
 129         *dstflags &= ~IR3_REG_SSA;
 130         *dstflags |= srcflags & IR3_REG_SSA;
 131         *dstflags |= srcflags & IR3_REG_CONST;
 132         *dstflags |= srcflags & IR3_REG_IMMED;
 133         *dstflags |= srcflags & IR3_REG_RELATIV;
 134         *dstflags |= srcflags & IR3_REG_ARRAY;
 135         *dstflags |= srcflags & IR3_REG_HIGH;
 136
 137         /* if src of the src is boolean we can drop the (abs) since we know
 138          * the source value is already a postitive integer.  This cleans
 139          * up the absnegs that get inserted when converting between nir and
 140          * native boolean (see ir3_b2n/n2b)
 141          */
 142         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 143         if (srcsrc && is_bool(srcsrc))
 144                 *dstflags &= ~IR3_REG_SABS;
 145 }
 146
 147 /* Tries lowering an immediate register argument to a const buffer access by
 148  * adding to the list of immediates to be pushed to the const buffer when
 149  * switching to this shader.
 150  */
 151 static bool
 152 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
 153                 struct ir3_register *reg, unsigned new_flags)
 154 {
 155         if (!(new_flags & IR3_REG_IMMED))
 156                 return false;
 157
 158         new_flags &= ~IR3_REG_IMMED;
 159         new_flags |= IR3_REG_CONST;
 160
 161         if (!ir3_valid_flags(instr, n, new_flags))
 162                 return false;
 163
 164         unsigned swiz, idx, i;
 165
 166         reg = ir3_reg_clone(ctx->shader, reg);
 167
 168         /* Half constant registers seems to handle only 32-bit values
 169          * within floating-point opcodes. So convert back to 32-bit values.
 170          */
 171         bool f_opcode = (is_cat2_float(instr->opc) ||
 172                         is_cat3_float(instr->opc)) ? true : false;
 173         if (f_opcode && (new_flags & IR3_REG_HALF))
 174                 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 175
 176         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 177          * so just evaluate those and clear the flags:
 178          */
 179         if (new_flags & IR3_REG_SABS) {
 180                 reg->iim_val = abs(reg->iim_val);
 181                 new_flags &= ~IR3_REG_SABS;
 182         }
 183
 184         if (new_flags & IR3_REG_FABS) {
 185                 reg->fim_val = fabs(reg->fim_val);
 186                 new_flags &= ~IR3_REG_FABS;
 187         }
 188
 189         if (new_flags & IR3_REG_SNEG) {
 190                 reg->iim_val = -reg->iim_val;
 191                 new_flags &= ~IR3_REG_SNEG;
 192         }
 193
 194         if (new_flags & IR3_REG_FNEG) {
 195                 reg->fim_val = -reg->fim_val;
 196                 new_flags &= ~IR3_REG_FNEG;
 197         }
 198
 199         /* Reallocate for 4 more elements whenever it's necessary */
 200         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 201         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 202                 const_state->immediates_size += 4;
 203                 const_state->immediates = realloc (const_state->immediates,
 204                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 205
 206                 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
 207                         const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
 208         }
 209
 210         for (i = 0; i < const_state->immediate_idx; i++) {
 211                 swiz = i % 4;
 212                 idx  = i / 4;
 213
 214                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 215                         break;
 216                 }
 217         }
 218
 219         if (i == const_state->immediate_idx) {
 220                 struct ir3_compiler *compiler = instr->block->shader->compiler;
 221                 /* Add on a new immediate to be pushed, if we have space left in the
 222                  * constbuf.
 223                  */
 224                 if (const_state->offsets.immediate + const_state->immediate_idx / 4 >=
 225                                 compiler->max_const)
 226                         return false;
 227
 228                 swiz = i % 4;
 229                 idx  = i / 4;
 230
 231                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 232                 const_state->immediates_count = idx + 1;
 233                 const_state->immediate_idx++;
 234         }
 235
 236         reg->flags = new_flags;
 237         reg->num = i + (4 * const_state->offsets.immediate);
 238
 239         instr->regs[n + 1] = reg;
 240
 241         return true;
 242 }
 243
 244 static void
 245 unuse(struct ir3_instruction *instr)
 246 {
 247         debug_assert(instr->use_count > 0);
 248
 249         if (--instr->use_count == 0) {
 250                 struct ir3_block *block = instr->block;
 251
 252                 instr->barrier_class = 0;
 253                 instr->barrier_conflict = 0;
 254
 255                 /* we don't want to remove anything in keeps (which could
 256                  * be things like array store's)
 257                  */
 258                 for (unsigned i = 0; i < block->keeps_count; i++) {
 259                         debug_assert(block->keeps[i] != instr);
 260                 }
 261         }
 262 }
 263
 264 /**
 265  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 266  * instructions, which cannot reference a constant.  See if it is
 267  * possible to swap the 1st and 2nd sources.
 268  */
 269 static bool
 270 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 271 {
 272         if (!is_mad(instr->opc))
 273                 return false;
 274
 275         /* NOTE: pre-swap first two src's before valid_flags(),
 276          * which might try to dereference the n'th src:
 277          */
 278         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 279
 280         /* cat3 doesn't encode immediate, but we can lower immediate
 281          * to const if that helps:
 282          */
 283         if (new_flags & IR3_REG_IMMED) {
 284                 new_flags &= ~IR3_REG_IMMED;
 285                 new_flags |=  IR3_REG_CONST;
 286         }
 287
 288         bool valid_swap =
 289                 /* can we propagate mov if we move 2nd src to first? */
 290                 ir3_valid_flags(instr, 0, new_flags) &&
 291                 /* and does first src fit in second slot? */
 292                 ir3_valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 293
 294         if (!valid_swap) {
 295                 /* put things back the way they were: */
 296                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 297         }   /* otherwise leave things swapped */
 298
 299         return valid_swap;
 300 }
 301
 302 /**
 303  * Handle cp for a given src register.  This additionally handles
 304  * the cases of collapsing immedate/const (which replace the src
 305  * register with a non-ssa src) or collapsing mov's from relative
 306  * src (which needs to also fixup the address src reference by the
 307  * instruction).
 308  */
 309 static bool
 310 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 311                 struct ir3_register *reg, unsigned n)
 312 {
 313         struct ir3_instruction *src = ssa(reg);
 314
 315         if (is_eligible_mov(src, instr, true)) {
 316                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 317                 struct ir3_register *src_reg = src->regs[1];
 318                 unsigned new_flags = reg->flags;
 319
 320                 combine_flags(&new_flags, src);
 321
 322                 if (ir3_valid_flags(instr, n, new_flags)) {
 323                         if (new_flags & IR3_REG_ARRAY) {
 324                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 325                                 reg->array = src_reg->array;
 326                         }
 327                         reg->flags = new_flags;
 328                         reg->instr = ssa(src_reg);
 329
 330                         instr->barrier_class |= src->barrier_class;
 331                         instr->barrier_conflict |= src->barrier_conflict;
 332
 333                         unuse(src);
 334                         reg->instr->use_count++;
 335
 336                         return true;
 337                 }
 338         } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
 339                         /* cannot collapse const/immed/etc into meta instrs: */
 340                         !is_meta(instr)) {
 341                 /* immed/const/etc cases, which require some special handling: */
 342                 struct ir3_register *src_reg = src->regs[1];
 343                 unsigned new_flags = reg->flags;
 344
 345                 combine_flags(&new_flags, src);
 346
 347                 if (!ir3_valid_flags(instr, n, new_flags)) {
 348                         /* See if lowering an immediate to const would help. */
 349                         if (lower_immed(ctx, instr, n, src_reg, new_flags))
 350                                 return true;
 351
 352                         /* special case for "normal" mad instructions, we can
 353                          * try swapping the first two args if that fits better.
 354                          *
 355                          * the "plain" MAD's (ie. the ones that don't shift first
 356                          * src prior to multiply) can swap their first two srcs if
 357                          * src[0] is !CONST and src[1] is CONST:
 358                          */
 359                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 360                                 return true;
 361                         } else {
 362                                 return false;
 363                         }
 364                 }
 365
 366                 /* Here we handle the special case of mov from
 367                  * CONST and/or RELATIV.  These need to be handled
 368                  * specially, because in the case of move from CONST
 369                  * there is no src ir3_instruction so we need to
 370                  * replace the ir3_register.  And in the case of
 371                  * RELATIV we need to handle the address register
 372                  * dependency.
 373                  */
 374                 if (src_reg->flags & IR3_REG_CONST) {
 375                         /* an instruction cannot reference two different
 376                          * address registers:
 377                          */
 378                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 379                                         conflicts(instr->address, reg->instr->address))
 380                                 return false;
 381
 382                         /* This seems to be a hw bug, or something where the timings
 383                          * just somehow don't work out.  This restriction may only
 384                          * apply if the first src is also CONST.
 385                          */
 386                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 387                                         (src_reg->flags & IR3_REG_RELATIV) &&
 388                                         (src_reg->array.offset == 0))
 389                                 return false;
 390
 391                         /* When narrowing constant from 32b to 16b, it seems
 392                          * to work only for float. So we should do this only with
 393                          * float opcodes.
 394                          */
 395                         if (src->cat1.dst_type == TYPE_F16) {
 396                                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
 397                                         return false;
 398                                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
 399                                         return false;
 400                         }
 401
 402                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 403                         src_reg->flags = new_flags;
 404                         instr->regs[n+1] = src_reg;
 405
 406                         if (src_reg->flags & IR3_REG_RELATIV)
 407                                 ir3_instr_set_address(instr, reg->instr->address);
 408
 409                         return true;
 410                 }
 411
 412                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 413                                 !conflicts(instr->address, reg->instr->address)) {
 414                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 415                         src_reg->flags = new_flags;
 416                         instr->regs[n+1] = src_reg;
 417                         ir3_instr_set_address(instr, reg->instr->address);
 418
 419                         return true;
 420                 }
 421
 422                 /* NOTE: seems we can only do immed integers, so don't
 423                  * need to care about float.  But we do need to handle
 424                  * abs/neg *before* checking that the immediate requires
 425                  * few enough bits to encode:
 426                  *
 427                  * TODO: do we need to do something to avoid accidentally
 428                  * catching a float immed?
 429                  */
 430                 if (src_reg->flags & IR3_REG_IMMED) {
 431                         int32_t iim_val = src_reg->iim_val;
 432
 433                         debug_assert((opc_cat(instr->opc) == 1) ||
 434                                         (opc_cat(instr->opc) == 6) ||
 435                                         ir3_cat2_int(instr->opc) ||
 436                                         (is_mad(instr->opc) && (n == 0)));
 437
 438                         if (new_flags & IR3_REG_SABS)
 439                                 iim_val = abs(iim_val);
 440
 441                         if (new_flags & IR3_REG_SNEG)
 442                                 iim_val = -iim_val;
 443
 444                         if (new_flags & IR3_REG_BNOT)
 445                                 iim_val = ~iim_val;
 446
 447                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 448                         if (ir3_valid_flags(instr, n, new_flags) &&
 449                                         ((instr->opc == OPC_MOV) ||
 450                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 451                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 452                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 453                                 src_reg->flags = new_flags;
 454                                 src_reg->iim_val = iim_val;
 455                                 instr->regs[n+1] = src_reg;
 456
 457                                 return true;
 458                         } else if (lower_immed(ctx, instr, n, src_reg, new_flags)) {
 459                                 /* Fell back to loading the immediate as a const */
 460                                 return true;
 461                         }
 462                 }
 463         }
 464
 465         return false;
 466 }
 467
 468 /* Handle special case of eliminating output mov, and similar cases where
 469  * there isn't a normal "consuming" instruction.  In this case we cannot
 470  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 471  * be eliminated)
 472  */
 473 static struct ir3_instruction *
 474 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 475 {
 476         if (is_eligible_mov(instr, NULL, false)) {
 477                 struct ir3_register *reg = instr->regs[1];
 478                 if (!(reg->flags & IR3_REG_ARRAY)) {
 479                         struct ir3_instruction *src_instr = ssa(reg);
 480                         debug_assert(src_instr);
 481                         ctx->progress = true;
 482                         return src_instr;
 483                 }
 484         }
 485         return instr;
 486 }
 487
 488 /**
 489  * Find instruction src's which are mov's that can be collapsed, replacing
 490  * the mov dst with the mov src
 491  */
 492 static void
 493 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 494 {
 495         if (instr->regs_count == 0)
 496                 return;
 497
 498         if (ir3_instr_check_mark(instr))
 499                 return;
 500
 501         /* walk down the graph from each src: */
 502         bool progress;
 503         do {
 504                 progress = false;
 505                 foreach_src_n (reg, n, instr) {
 506                         struct ir3_instruction *src = ssa(reg);
 507
 508                         if (!src)
 509                                 continue;
 510
 511                         instr_cp(ctx, src);
 512
 513                         /* TODO non-indirect access we could figure out which register
 514                          * we actually want and allow cp..
 515                          */
 516                         if (reg->flags & IR3_REG_ARRAY)
 517                                 continue;
 518
 519                         /* Don't CP absneg into meta instructions, that won't end well: */
 520                         if (is_meta(instr) && (src->opc != OPC_MOV))
 521                                 continue;
 522
 523                         progress |= reg_cp(ctx, instr, reg, n);
 524                         ctx->progress |= progress;
 525                 }
 526         } while (progress);
 527
 528         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 529                 struct ir3_instruction *src = ssa(instr->regs[0]);
 530                 if (src)
 531                         instr_cp(ctx, src);
 532         }
 533
 534         if (instr->address) {
 535                 instr_cp(ctx, instr->address);
 536                 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
 537         }
 538
 539         /* we can end up with extra cmps.s from frontend, which uses a
 540          *
 541          *    cmps.s p0.x, cond, 0
 542          *
 543          * as a way to mov into the predicate register.  But frequently 'cond'
 544          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 545          * just re-write the instruction writing predicate register to get rid
 546          * of the double cmps.
 547          */
 548         if ((instr->opc == OPC_CMPS_S) &&
 549                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 550                         ssa(instr->regs[1]) &&
 551                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 552                         (instr->regs[2]->iim_val == 0) &&
 553                         (instr->cat2.condition == IR3_COND_NE)) {
 554                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 555                 switch (cond->opc) {
 556                 case OPC_CMPS_S:
 557                 case OPC_CMPS_F:
 558                 case OPC_CMPS_U:
 559                         instr->opc   = cond->opc;
 560                         instr->flags = cond->flags;
 561                         instr->cat2  = cond->cat2;
 562                         ir3_instr_set_address(instr, cond->address);
 563                         instr->regs[1] = cond->regs[1];
 564                         instr->regs[2] = cond->regs[2];
 565                         instr->barrier_class |= cond->barrier_class;
 566                         instr->barrier_conflict |= cond->barrier_conflict;
 567                         unuse(cond);
 568                         ctx->progress = true;
 569                         break;
 570                 default:
 571                         break;
 572                 }
 573         }
 574
 575         /* Handle converting a sam.s2en (taking samp/tex idx params via register)
 576          * into a normal sam (encoding immediate samp/tex idx) if they are
 577          * immediate. This saves some instructions and regs in the common case
 578          * where we know samp/tex at compile time. This needs to be done in the
 579          * frontend for bindless tex, though, so don't replicate it here.
 580          */
 581         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 582                         !(instr->flags & IR3_INSTR_B) &&
 583                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 584                 /* The first src will be a collect, if both of it's
 585                  * two sources are mov from imm, then we can
 586                  */
 587                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 588
 589                 debug_assert(samp_tex->opc == OPC_META_COLLECT);
 590
 591                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 592                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 593
 594                 if ((samp->opc == OPC_MOV) &&
 595                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 596                                 (tex->opc == OPC_MOV) &&
 597                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 598                         instr->flags &= ~IR3_INSTR_S2EN;
 599                         instr->cat5.samp = samp->regs[1]->iim_val;
 600                         instr->cat5.tex  = tex->regs[1]->iim_val;
 601
 602                         /* shuffle around the regs to remove the first src: */
 603                         instr->regs_count--;
 604                         for (unsigned i = 1; i < instr->regs_count; i++) {
 605                                 instr->regs[i] = instr->regs[i + 1];
 606                         }
 607
 608                         ctx->progress = true;
 609                 }
 610         }
 611 }
 612
 613 bool
 614 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 615 {
 616         struct ir3_cp_ctx ctx = {
 617                         .shader = ir,
 618                         .so = so,
 619         };
 620
 621         /* This is a bit annoying, and probably wouldn't be necessary if we
 622          * tracked a reverse link from producing instruction to consumer.
 623          * But we need to know when we've eliminated the last consumer of
 624          * a mov, so we need to do a pass to first count consumers of a
 625          * mov.
 626          */
 627         foreach_block (block, &ir->block_list) {
 628                 foreach_instr (instr, &block->instr_list) {
 629
 630                         /* by the way, we don't account for false-dep's, so the CP
 631                          * pass should always happen before false-dep's are inserted
 632                          */
 633                         debug_assert(instr->deps_count == 0);
 634
 635                         foreach_ssa_src (src, instr) {
 636                                 src->use_count++;
 637                         }
 638                 }
 639         }
 640
 641         ir3_clear_mark(ir);
 642
 643         foreach_output_n (out, n, ir) {
 644                 instr_cp(&ctx, out);
 645                 ir->outputs[n] = eliminate_output_mov(&ctx, out);
 646         }
 647
 648         foreach_block (block, &ir->block_list) {
 649                 if (block->condition) {
 650                         instr_cp(&ctx, block->condition);
 651                         block->condition = eliminate_output_mov(&ctx, block->condition);
 652                 }
 653
 654                 for (unsigned i = 0; i < block->keeps_count; i++) {
 655                         instr_cp(&ctx, block->keeps[i]);
 656                         block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
 657                 }
 658         }
 659
 660         return ctx.progress;
 661 }