src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45         bool progress;
  46 };
  47
  48 /* is it a type preserving mov, with ok flags?
  49  *
  50  * @instr: the mov to consider removing
  51  * @dst_instr: the instruction consuming the mov (instr)
  52  *
  53  * TODO maybe drop allow_flags since this is only false when dst is
  54  * NULL (ie. outputs)
  55  */
  56 static bool is_eligible_mov(struct ir3_instruction *instr,
  57                 struct ir3_instruction *dst_instr, bool allow_flags)
  58 {
  59         if (is_same_type_mov(instr)) {
  60                 struct ir3_register *dst = instr->regs[0];
  61                 struct ir3_register *src = instr->regs[1];
  62                 struct ir3_instruction *src_instr = ssa(src);
  63
  64                 /* only if mov src is SSA (not const/immed): */
  65                 if (!src_instr)
  66                         return false;
  67
  68                 /* no indirect: */
  69                 if (dst->flags & IR3_REG_RELATIV)
  70                         return false;
  71                 if (src->flags & IR3_REG_RELATIV)
  72                         return false;
  73
  74                 if (src->flags & IR3_REG_ARRAY)
  75                         return false;
  76
  77                 if (!allow_flags)
  78                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  79                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  80                                 return false;
  81
  82                 /* If src is coming from fanout/split (ie. one component of a
  83                  * texture fetch, etc) and we have constraints on swizzle of
  84                  * destination, then skip it.
  85                  *
  86                  * We could possibly do a bit better, and copy-propagation if
  87                  * we can CP all components that are being fanned out.
  88                  */
  89                 if (src_instr->opc == OPC_META_SPLIT) {
  90                         if (!dst_instr)
  91                                 return false;
  92                         if (dst_instr->opc == OPC_META_COLLECT)
  93                                 return false;
  94                         if (dst_instr->cp.left || dst_instr->cp.right)
  95                                 return false;
  96                 }
  97
  98                 return true;
  99         }
 100         return false;
 101 }
 102
 103 static unsigned cp_flags(unsigned flags)
 104 {
 105         /* only considering these flags (at least for now): */
 106         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
 107                         IR3_REG_FNEG | IR3_REG_FABS |
 108                         IR3_REG_SNEG | IR3_REG_SABS |
 109                         IR3_REG_BNOT | IR3_REG_RELATIV);
 110         return flags;
 111 }
 112
 113 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 114                 unsigned flags)
 115 {
 116         struct ir3_compiler *compiler = instr->block->shader->compiler;
 117         unsigned valid_flags;
 118
 119         if ((flags & IR3_REG_HIGH) &&
 120                         (opc_cat(instr->opc) > 1) &&
 121                         (compiler->gpu_id >= 600))
 122                 return false;
 123
 124         flags = cp_flags(flags);
 125
 126         /* If destination is indirect, then source cannot be.. at least
 127          * I don't think so..
 128          */
 129         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 130                         (flags & IR3_REG_RELATIV))
 131                 return false;
 132
 133         if (flags & IR3_REG_RELATIV) {
 134                 /* TODO need to test on earlier gens.. pretty sure the earlier
 135                  * problem was just that we didn't check that the src was from
 136                  * same block (since we can't propagate address register values
 137                  * across blocks currently)
 138                  */
 139                 if (compiler->gpu_id < 600)
 140                         return false;
 141
 142                 /* NOTE in the special try_swap_mad_two_srcs() case we can be
 143                  * called on a src that has already had an indirect load folded
 144                  * in, in which case ssa() returns NULL
 145                  */
 146                 struct ir3_instruction *src = ssa(instr->regs[n+1]);
 147                 if (src && src->address->block != instr->block)
 148                         return false;
 149         }
 150
 151         switch (opc_cat(instr->opc)) {
 152         case 1:
 153                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 154                 if (flags & ~valid_flags)
 155                         return false;
 156                 break;
 157         case 2:
 158                 valid_flags = ir3_cat2_absneg(instr->opc) |
 159                                 IR3_REG_CONST | IR3_REG_RELATIV;
 160
 161                 if (ir3_cat2_int(instr->opc))
 162                         valid_flags |= IR3_REG_IMMED;
 163
 164                 if (flags & ~valid_flags)
 165                         return false;
 166
 167                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 168                         unsigned m = (n ^ 1) + 1;
 169                         /* cannot deal w/ const in both srcs:
 170                          * (note that some cat2 actually only have a single src)
 171                          */
 172                         if (m < instr->regs_count) {
 173                                 struct ir3_register *reg = instr->regs[m];
 174                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 175                                         return false;
 176                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 177                                         return false;
 178                         }
 179                 }
 180                 break;
 181         case 3:
 182                 valid_flags = ir3_cat3_absneg(instr->opc) |
 183                                 IR3_REG_CONST | IR3_REG_RELATIV;
 184
 185                 if (flags & ~valid_flags)
 186                         return false;
 187
 188                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 189                         /* cannot deal w/ const/relativ in 2nd src: */
 190                         if (n == 1)
 191                                 return false;
 192                 }
 193
 194                 break;
 195         case 4:
 196                 /* seems like blob compiler avoids const as src.. */
 197                 /* TODO double check if this is still the case on a4xx */
 198                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 199                         return false;
 200                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 201                         return false;
 202                 break;
 203         case 5:
 204                 /* no flags allowed */
 205                 if (flags)
 206                         return false;
 207                 break;
 208         case 6:
 209                 valid_flags = IR3_REG_IMMED;
 210                 if (flags & ~valid_flags)
 211                         return false;
 212
 213                 if (flags & IR3_REG_IMMED) {
 214                         /* doesn't seem like we can have immediate src for store
 215                          * instructions:
 216                          *
 217                          * TODO this restriction could also apply to load instructions,
 218                          * but for load instructions this arg is the address (and not
 219                          * really sure any good way to test a hard-coded immed addr src)
 220                          */
 221                         if (is_store(instr) && (n == 1))
 222                                 return false;
 223
 224                         if ((instr->opc == OPC_LDL) && (n == 0))
 225                                 return false;
 226
 227                         if ((instr->opc == OPC_STL) && (n != 2))
 228                                 return false;
 229
 230                         if (instr->opc == OPC_STLW && n == 0)
 231                                 return false;
 232
 233                         if (instr->opc == OPC_LDLW && n == 0)
 234                                 return false;
 235
 236                         /* disallow immediates in anything but the SSBO slot argument for
 237                          * cat6 instructions:
 238                          */
 239                         if (is_atomic(instr->opc) && (n != 0))
 240                                 return false;
 241
 242                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 243                                 return false;
 244
 245                         if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
 246                                 return false;
 247
 248                         /* as with atomics, these cat6 instrs can only have an immediate
 249                          * for SSBO/IBO slot argument
 250                          */
 251                         switch (instr->opc) {
 252                         case OPC_LDIB:
 253                         case OPC_LDC:
 254                         case OPC_RESINFO:
 255                                 if (n != 0)
 256                                         return false;
 257                                 break;
 258                         default:
 259                                 break;
 260                         }
 261                 }
 262
 263                 break;
 264         }
 265
 266         return true;
 267 }
 268
 269 /* propagate register flags from src to dst.. negates need special
 270  * handling to cancel each other out.
 271  */
 272 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 273 {
 274         unsigned srcflags = src->regs[1]->flags;
 275
 276         /* if what we are combining into already has (abs) flags,
 277          * we can drop (neg) from src:
 278          */
 279         if (*dstflags & IR3_REG_FABS)
 280                 srcflags &= ~IR3_REG_FNEG;
 281         if (*dstflags & IR3_REG_SABS)
 282                 srcflags &= ~IR3_REG_SNEG;
 283
 284         if (srcflags & IR3_REG_FABS)
 285                 *dstflags |= IR3_REG_FABS;
 286         if (srcflags & IR3_REG_SABS)
 287                 *dstflags |= IR3_REG_SABS;
 288         if (srcflags & IR3_REG_FNEG)
 289                 *dstflags ^= IR3_REG_FNEG;
 290         if (srcflags & IR3_REG_SNEG)
 291                 *dstflags ^= IR3_REG_SNEG;
 292         if (srcflags & IR3_REG_BNOT)
 293                 *dstflags ^= IR3_REG_BNOT;
 294
 295         *dstflags &= ~IR3_REG_SSA;
 296         *dstflags |= srcflags & IR3_REG_SSA;
 297         *dstflags |= srcflags & IR3_REG_CONST;
 298         *dstflags |= srcflags & IR3_REG_IMMED;
 299         *dstflags |= srcflags & IR3_REG_RELATIV;
 300         *dstflags |= srcflags & IR3_REG_ARRAY;
 301         *dstflags |= srcflags & IR3_REG_HIGH;
 302
 303         /* if src of the src is boolean we can drop the (abs) since we know
 304          * the source value is already a postitive integer.  This cleans
 305          * up the absnegs that get inserted when converting between nir and
 306          * native boolean (see ir3_b2n/n2b)
 307          */
 308         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 309         if (srcsrc && is_bool(srcsrc))
 310                 *dstflags &= ~IR3_REG_SABS;
 311 }
 312
 313 /* Tries lowering an immediate register argument to a const buffer access by
 314  * adding to the list of immediates to be pushed to the const buffer when
 315  * switching to this shader.
 316  */
 317 static bool
 318 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
 319                 struct ir3_register *reg, unsigned new_flags)
 320 {
 321         if (!(new_flags & IR3_REG_IMMED))
 322                 return false;
 323
 324         new_flags &= ~IR3_REG_IMMED;
 325         new_flags |= IR3_REG_CONST;
 326
 327         if (!valid_flags(instr, n, new_flags))
 328                 return false;
 329
 330         unsigned swiz, idx, i;
 331
 332         reg = ir3_reg_clone(ctx->shader, reg);
 333
 334         /* Half constant registers seems to handle only 32-bit values
 335          * within floating-point opcodes. So convert back to 32-bit values.
 336          */
 337         bool f_opcode = (is_cat2_float(instr->opc) ||
 338                         is_cat3_float(instr->opc)) ? true : false;
 339         if (f_opcode && (new_flags & IR3_REG_HALF))
 340                 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 341
 342         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 343          * so just evaluate those and clear the flags:
 344          */
 345         if (new_flags & IR3_REG_SABS) {
 346                 reg->iim_val = abs(reg->iim_val);
 347                 new_flags &= ~IR3_REG_SABS;
 348         }
 349
 350         if (new_flags & IR3_REG_FABS) {
 351                 reg->fim_val = fabs(reg->fim_val);
 352                 new_flags &= ~IR3_REG_FABS;
 353         }
 354
 355         if (new_flags & IR3_REG_SNEG) {
 356                 reg->iim_val = -reg->iim_val;
 357                 new_flags &= ~IR3_REG_SNEG;
 358         }
 359
 360         if (new_flags & IR3_REG_FNEG) {
 361                 reg->fim_val = -reg->fim_val;
 362                 new_flags &= ~IR3_REG_FNEG;
 363         }
 364
 365         /* Reallocate for 4 more elements whenever it's necessary */
 366         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 367         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 368                 const_state->immediates_size += 4;
 369                 const_state->immediates = realloc (const_state->immediates,
 370                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 371
 372                 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
 373                         const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
 374         }
 375
 376         for (i = 0; i < const_state->immediate_idx; i++) {
 377                 swiz = i % 4;
 378                 idx  = i / 4;
 379
 380                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 381                         break;
 382                 }
 383         }
 384
 385         if (i == const_state->immediate_idx) {
 386                 struct ir3_compiler *compiler = instr->block->shader->compiler;
 387                 /* Add on a new immediate to be pushed, if we have space left in the
 388                  * constbuf.
 389                  */
 390                 if (const_state->offsets.immediate + const_state->immediate_idx / 4 >=
 391                                 compiler->max_const)
 392                         return false;
 393
 394                 swiz = i % 4;
 395                 idx  = i / 4;
 396
 397                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 398                 const_state->immediates_count = idx + 1;
 399                 const_state->immediate_idx++;
 400         }
 401
 402         reg->flags = new_flags;
 403         reg->num = i + (4 * const_state->offsets.immediate);
 404
 405         instr->regs[n + 1] = reg;
 406
 407         return true;
 408 }
 409
 410 static void
 411 unuse(struct ir3_instruction *instr)
 412 {
 413         debug_assert(instr->use_count > 0);
 414
 415         if (--instr->use_count == 0) {
 416                 struct ir3_block *block = instr->block;
 417
 418                 instr->barrier_class = 0;
 419                 instr->barrier_conflict = 0;
 420
 421                 /* we don't want to remove anything in keeps (which could
 422                  * be things like array store's)
 423                  */
 424                 for (unsigned i = 0; i < block->keeps_count; i++) {
 425                         debug_assert(block->keeps[i] != instr);
 426                 }
 427         }
 428 }
 429
 430 /**
 431  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 432  * instructions, which cannot reference a constant.  See if it is
 433  * possible to swap the 1st and 2nd sources.
 434  */
 435 static bool
 436 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 437 {
 438         if (!is_mad(instr->opc))
 439                 return false;
 440
 441         /* NOTE: pre-swap first two src's before valid_flags(),
 442          * which might try to dereference the n'th src:
 443          */
 444         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 445
 446         /* cat3 doesn't encode immediate, but we can lower immediate
 447          * to const if that helps:
 448          */
 449         if (new_flags & IR3_REG_IMMED) {
 450                 new_flags &= ~IR3_REG_IMMED;
 451                 new_flags |=  IR3_REG_CONST;
 452         }
 453
 454         bool valid_swap =
 455                 /* can we propagate mov if we move 2nd src to first? */
 456                 valid_flags(instr, 0, new_flags) &&
 457                 /* and does first src fit in second slot? */
 458                 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 459
 460         if (!valid_swap) {
 461                 /* put things back the way they were: */
 462                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 463         }   /* otherwise leave things swapped */
 464
 465         return valid_swap;
 466 }
 467
 468 /**
 469  * Handle cp for a given src register.  This additionally handles
 470  * the cases of collapsing immedate/const (which replace the src
 471  * register with a non-ssa src) or collapsing mov's from relative
 472  * src (which needs to also fixup the address src reference by the
 473  * instruction).
 474  */
 475 static bool
 476 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 477                 struct ir3_register *reg, unsigned n)
 478 {
 479         struct ir3_instruction *src = ssa(reg);
 480
 481         if (is_eligible_mov(src, instr, true)) {
 482                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 483                 struct ir3_register *src_reg = src->regs[1];
 484                 unsigned new_flags = reg->flags;
 485
 486                 combine_flags(&new_flags, src);
 487
 488                 if (valid_flags(instr, n, new_flags)) {
 489                         if (new_flags & IR3_REG_ARRAY) {
 490                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 491                                 reg->array = src_reg->array;
 492                         }
 493                         reg->flags = new_flags;
 494                         reg->instr = ssa(src_reg);
 495
 496                         instr->barrier_class |= src->barrier_class;
 497                         instr->barrier_conflict |= src->barrier_conflict;
 498
 499                         unuse(src);
 500                         reg->instr->use_count++;
 501
 502                         return true;
 503                 }
 504         } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
 505                         /* cannot collapse const/immed/etc into meta instrs: */
 506                         !is_meta(instr)) {
 507                 /* immed/const/etc cases, which require some special handling: */
 508                 struct ir3_register *src_reg = src->regs[1];
 509                 unsigned new_flags = reg->flags;
 510
 511                 combine_flags(&new_flags, src);
 512
 513                 if (!valid_flags(instr, n, new_flags)) {
 514                         /* See if lowering an immediate to const would help. */
 515                         if (lower_immed(ctx, instr, n, src_reg, new_flags))
 516                                 return true;
 517
 518                         /* special case for "normal" mad instructions, we can
 519                          * try swapping the first two args if that fits better.
 520                          *
 521                          * the "plain" MAD's (ie. the ones that don't shift first
 522                          * src prior to multiply) can swap their first two srcs if
 523                          * src[0] is !CONST and src[1] is CONST:
 524                          */
 525                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 526                                 return true;
 527                         } else {
 528                                 return false;
 529                         }
 530                 }
 531
 532                 /* Here we handle the special case of mov from
 533                  * CONST and/or RELATIV.  These need to be handled
 534                  * specially, because in the case of move from CONST
 535                  * there is no src ir3_instruction so we need to
 536                  * replace the ir3_register.  And in the case of
 537                  * RELATIV we need to handle the address register
 538                  * dependency.
 539                  */
 540                 if (src_reg->flags & IR3_REG_CONST) {
 541                         /* an instruction cannot reference two different
 542                          * address registers:
 543                          */
 544                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 545                                         conflicts(instr->address, reg->instr->address))
 546                                 return false;
 547
 548                         /* This seems to be a hw bug, or something where the timings
 549                          * just somehow don't work out.  This restriction may only
 550                          * apply if the first src is also CONST.
 551                          */
 552                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 553                                         (src_reg->flags & IR3_REG_RELATIV) &&
 554                                         (src_reg->array.offset == 0))
 555                                 return false;
 556
 557                         /* When narrowing constant from 32b to 16b, it seems
 558                          * to work only for float. So we should do this only with
 559                          * float opcodes.
 560                          */
 561                         if (src->cat1.dst_type == TYPE_F16) {
 562                                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
 563                                         return false;
 564                                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
 565                                         return false;
 566                         }
 567
 568                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 569                         src_reg->flags = new_flags;
 570                         instr->regs[n+1] = src_reg;
 571
 572                         if (src_reg->flags & IR3_REG_RELATIV)
 573                                 ir3_instr_set_address(instr, reg->instr->address);
 574
 575                         return true;
 576                 }
 577
 578                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 579                                 !conflicts(instr->address, reg->instr->address)) {
 580                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 581                         src_reg->flags = new_flags;
 582                         instr->regs[n+1] = src_reg;
 583                         ir3_instr_set_address(instr, reg->instr->address);
 584
 585                         return true;
 586                 }
 587
 588                 /* NOTE: seems we can only do immed integers, so don't
 589                  * need to care about float.  But we do need to handle
 590                  * abs/neg *before* checking that the immediate requires
 591                  * few enough bits to encode:
 592                  *
 593                  * TODO: do we need to do something to avoid accidentally
 594                  * catching a float immed?
 595                  */
 596                 if (src_reg->flags & IR3_REG_IMMED) {
 597                         int32_t iim_val = src_reg->iim_val;
 598
 599                         debug_assert((opc_cat(instr->opc) == 1) ||
 600                                         (opc_cat(instr->opc) == 6) ||
 601                                         ir3_cat2_int(instr->opc) ||
 602                                         (is_mad(instr->opc) && (n == 0)));
 603
 604                         if (new_flags & IR3_REG_SABS)
 605                                 iim_val = abs(iim_val);
 606
 607                         if (new_flags & IR3_REG_SNEG)
 608                                 iim_val = -iim_val;
 609
 610                         if (new_flags & IR3_REG_BNOT)
 611                                 iim_val = ~iim_val;
 612
 613                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 614                         if (valid_flags(instr, n, new_flags) &&
 615                                         ((instr->opc == OPC_MOV) ||
 616                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 617                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 618                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 619                                 src_reg->flags = new_flags;
 620                                 src_reg->iim_val = iim_val;
 621                                 instr->regs[n+1] = src_reg;
 622
 623                                 return true;
 624                         } else if (lower_immed(ctx, instr, n, src_reg, new_flags)) {
 625                                 /* Fell back to loading the immediate as a const */
 626                                 return true;
 627                         }
 628                 }
 629         }
 630
 631         return false;
 632 }
 633
 634 /* Handle special case of eliminating output mov, and similar cases where
 635  * there isn't a normal "consuming" instruction.  In this case we cannot
 636  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 637  * be eliminated)
 638  */
 639 static struct ir3_instruction *
 640 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 641 {
 642         if (is_eligible_mov(instr, NULL, false)) {
 643                 struct ir3_register *reg = instr->regs[1];
 644                 if (!(reg->flags & IR3_REG_ARRAY)) {
 645                         struct ir3_instruction *src_instr = ssa(reg);
 646                         debug_assert(src_instr);
 647                         ctx->progress = true;
 648                         return src_instr;
 649                 }
 650         }
 651         return instr;
 652 }
 653
 654 /**
 655  * Find instruction src's which are mov's that can be collapsed, replacing
 656  * the mov dst with the mov src
 657  */
 658 static void
 659 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 660 {
 661         if (instr->regs_count == 0)
 662                 return;
 663
 664         if (ir3_instr_check_mark(instr))
 665                 return;
 666
 667         /* walk down the graph from each src: */
 668         bool progress;
 669         do {
 670                 progress = false;
 671                 foreach_src_n (reg, n, instr) {
 672                         struct ir3_instruction *src = ssa(reg);
 673
 674                         if (!src)
 675                                 continue;
 676
 677                         instr_cp(ctx, src);
 678
 679                         /* TODO non-indirect access we could figure out which register
 680                          * we actually want and allow cp..
 681                          */
 682                         if (reg->flags & IR3_REG_ARRAY)
 683                                 continue;
 684
 685                         /* Don't CP absneg into meta instructions, that won't end well: */
 686                         if (is_meta(instr) && (src->opc != OPC_MOV))
 687                                 continue;
 688
 689                         progress |= reg_cp(ctx, instr, reg, n);
 690                         ctx->progress |= progress;
 691                 }
 692         } while (progress);
 693
 694         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 695                 struct ir3_instruction *src = ssa(instr->regs[0]);
 696                 if (src)
 697                         instr_cp(ctx, src);
 698         }
 699
 700         if (instr->address) {
 701                 instr_cp(ctx, instr->address);
 702                 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
 703         }
 704
 705         /* we can end up with extra cmps.s from frontend, which uses a
 706          *
 707          *    cmps.s p0.x, cond, 0
 708          *
 709          * as a way to mov into the predicate register.  But frequently 'cond'
 710          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 711          * just re-write the instruction writing predicate register to get rid
 712          * of the double cmps.
 713          */
 714         if ((instr->opc == OPC_CMPS_S) &&
 715                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 716                         ssa(instr->regs[1]) &&
 717                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 718                         (instr->regs[2]->iim_val == 0) &&
 719                         (instr->cat2.condition == IR3_COND_NE)) {
 720                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 721                 switch (cond->opc) {
 722                 case OPC_CMPS_S:
 723                 case OPC_CMPS_F:
 724                 case OPC_CMPS_U:
 725                         instr->opc   = cond->opc;
 726                         instr->flags = cond->flags;
 727                         instr->cat2  = cond->cat2;
 728                         ir3_instr_set_address(instr, cond->address);
 729                         instr->regs[1] = cond->regs[1];
 730                         instr->regs[2] = cond->regs[2];
 731                         instr->barrier_class |= cond->barrier_class;
 732                         instr->barrier_conflict |= cond->barrier_conflict;
 733                         unuse(cond);
 734                         ctx->progress = true;
 735                         break;
 736                 default:
 737                         break;
 738                 }
 739         }
 740
 741         /* Handle converting a sam.s2en (taking samp/tex idx params via register)
 742          * into a normal sam (encoding immediate samp/tex idx) if they are
 743          * immediate. This saves some instructions and regs in the common case
 744          * where we know samp/tex at compile time. This needs to be done in the
 745          * frontend for bindless tex, though, so don't replicate it here.
 746          */
 747         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 748                         !(instr->flags & IR3_INSTR_B) &&
 749                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 750                 /* The first src will be a collect, if both of it's
 751                  * two sources are mov from imm, then we can
 752                  */
 753                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 754
 755                 debug_assert(samp_tex->opc == OPC_META_COLLECT);
 756
 757                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 758                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 759
 760                 if ((samp->opc == OPC_MOV) &&
 761                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 762                                 (tex->opc == OPC_MOV) &&
 763                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 764                         instr->flags &= ~IR3_INSTR_S2EN;
 765                         instr->cat5.samp = samp->regs[1]->iim_val;
 766                         instr->cat5.tex  = tex->regs[1]->iim_val;
 767
 768                         /* shuffle around the regs to remove the first src: */
 769                         instr->regs_count--;
 770                         for (unsigned i = 1; i < instr->regs_count; i++) {
 771                                 instr->regs[i] = instr->regs[i + 1];
 772                         }
 773
 774                         ctx->progress = true;
 775                 }
 776         }
 777 }
 778
 779 bool
 780 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 781 {
 782         struct ir3_cp_ctx ctx = {
 783                         .shader = ir,
 784                         .so = so,
 785         };
 786
 787         /* This is a bit annoying, and probably wouldn't be necessary if we
 788          * tracked a reverse link from producing instruction to consumer.
 789          * But we need to know when we've eliminated the last consumer of
 790          * a mov, so we need to do a pass to first count consumers of a
 791          * mov.
 792          */
 793         foreach_block (block, &ir->block_list) {
 794                 foreach_instr (instr, &block->instr_list) {
 795
 796                         /* by the way, we don't account for false-dep's, so the CP
 797                          * pass should always happen before false-dep's are inserted
 798                          */
 799                         debug_assert(instr->deps_count == 0);
 800
 801                         foreach_ssa_src (src, instr) {
 802                                 src->use_count++;
 803                         }
 804                 }
 805         }
 806
 807         ir3_clear_mark(ir);
 808
 809         foreach_output_n (out, n, ir) {
 810                 instr_cp(&ctx, out);
 811                 ir->outputs[n] = eliminate_output_mov(&ctx, out);
 812         }
 813
 814         foreach_block (block, &ir->block_list) {
 815                 if (block->condition) {
 816                         instr_cp(&ctx, block->condition);
 817                         block->condition = eliminate_output_mov(&ctx, block->condition);
 818                 }
 819
 820                 for (unsigned i = 0; i < block->keeps_count; i++) {
 821                         instr_cp(&ctx, block->keeps[i]);
 822                         block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
 823                 }
 824         }
 825
 826         return ctx.progress;
 827 }