2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/ralloc.h"
28 #include "util/u_math.h"
31 #include "ir3_shader.h"
36 * The legalize pass handles ensuring sufficient nop's and sync flags for
39 * 1) Iteratively determine where sync ((sy)/(ss)) flags are needed,
40 * based on state flowing out of predecessor blocks until there is
41 * no further change. In some cases this requires inserting nops.
42 * 2) Mark (ei) on last varying input, and (ul) on last use of a0.x
43 * 3) Final nop scheduling for instruction latency
44 * 4) Resolve jumps and schedule blocks, marking potential convergence
48 struct ir3_legalize_ctx
{
49 struct ir3_compiler
*compiler
;
50 struct ir3_shader_variant
*so
;
55 struct ir3_legalize_state
{
57 regmask_t needs_ss_war
; /* write after read */
61 struct ir3_legalize_block_data
{
63 struct ir3_legalize_state state
;
66 /* We want to evaluate each block from the position of any other
67 * predecessor block, in order that the flags set are the union of
68 * all possible program paths.
70 * To do this, we need to know the output state (needs_ss/ss_war/sy)
71 * of all predecessor blocks. The tricky thing is loops, which mean
72 * that we can't simply recursively process each predecessor block
73 * before legalizing the current block.
75 * How we handle that is by looping over all the blocks until the
76 * results converge. If the output state of a given block changes
77 * in a given pass, this means that all successor blocks are not
78 * yet fully legalized.
82 legalize_block(struct ir3_legalize_ctx
*ctx
, struct ir3_block
*block
)
84 struct ir3_legalize_block_data
*bd
= block
->data
;
89 struct ir3_instruction
*last_input
= NULL
;
90 struct ir3_instruction
*last_rel
= NULL
;
91 struct ir3_instruction
*last_n
= NULL
;
92 struct list_head instr_list
;
93 struct ir3_legalize_state prev_state
= bd
->state
;
94 struct ir3_legalize_state
*state
= &bd
->state
;
95 bool last_input_needs_ss
= false;
96 bool has_tex_prefetch
= false;
97 bool mergedregs
= ctx
->so
->mergedregs
;
99 /* our input state is the OR of all predecessor blocks' state: */
100 set_foreach(block
->predecessors
, entry
) {
101 struct ir3_block
*predecessor
= (struct ir3_block
*)entry
->key
;
102 struct ir3_legalize_block_data
*pbd
= predecessor
->data
;
103 struct ir3_legalize_state
*pstate
= &pbd
->state
;
105 /* Our input (ss)/(sy) state is based on OR'ing the output
106 * state of all our predecessor blocks
108 regmask_or(&state
->needs_ss
,
109 &state
->needs_ss
, &pstate
->needs_ss
);
110 regmask_or(&state
->needs_ss_war
,
111 &state
->needs_ss_war
, &pstate
->needs_ss_war
);
112 regmask_or(&state
->needs_sy
,
113 &state
->needs_sy
, &pstate
->needs_sy
);
116 /* remove all the instructions from the list, we'll be adding
117 * them back in as we go
119 list_replace(&block
->instr_list
, &instr_list
);
120 list_inithead(&block
->instr_list
);
122 foreach_instr_safe (n
, &instr_list
) {
125 n
->flags
&= ~(IR3_INSTR_SS
| IR3_INSTR_SY
);
127 /* _meta::tex_prefetch instructions removed later in
128 * collect_tex_prefetches()
130 if (is_meta(n
) && (n
->opc
!= OPC_META_TEX_PREFETCH
))
134 struct ir3_register
*inloc
= n
->regs
[1];
135 assert(inloc
->flags
& IR3_REG_IMMED
);
136 ctx
->max_bary
= MAX2(ctx
->max_bary
, inloc
->iim_val
);
139 if (last_n
&& is_barrier(last_n
)) {
140 n
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
141 last_input_needs_ss
= false;
142 regmask_init(&state
->needs_ss_war
, mergedregs
);
143 regmask_init(&state
->needs_ss
, mergedregs
);
144 regmask_init(&state
->needs_sy
, mergedregs
);
147 if (last_n
&& (last_n
->opc
== OPC_PREDT
)) {
148 n
->flags
|= IR3_INSTR_SS
;
149 regmask_init(&state
->needs_ss_war
, mergedregs
);
150 regmask_init(&state
->needs_ss
, mergedregs
);
153 /* NOTE: consider dst register too.. it could happen that
154 * texture sample instruction (for example) writes some
155 * components which are unused. A subsequent instruction
156 * that writes the same register can race w/ the sam instr
157 * resulting in undefined results:
159 for (i
= 0; i
< n
->regs_count
; i
++) {
160 struct ir3_register
*reg
= n
->regs
[i
];
164 /* TODO: we probably only need (ss) for alu
165 * instr consuming sfu result.. need to make
166 * some tests for both this and (sy)..
168 if (regmask_get(&state
->needs_ss
, reg
)) {
169 n
->flags
|= IR3_INSTR_SS
;
170 last_input_needs_ss
= false;
171 regmask_init(&state
->needs_ss_war
, mergedregs
);
172 regmask_init(&state
->needs_ss
, mergedregs
);
175 if (regmask_get(&state
->needs_sy
, reg
)) {
176 n
->flags
|= IR3_INSTR_SY
;
177 regmask_init(&state
->needs_sy
, mergedregs
);
181 /* TODO: is it valid to have address reg loaded from a
182 * relative src (ie. mova a0, c<a0.x+4>)? If so, the
183 * last_rel check below should be moved ahead of this:
185 if (reg
->flags
& IR3_REG_RELATIV
)
189 if (n
->regs_count
> 0) {
190 struct ir3_register
*reg
= n
->regs
[0];
191 if (regmask_get(&state
->needs_ss_war
, reg
)) {
192 n
->flags
|= IR3_INSTR_SS
;
193 last_input_needs_ss
= false;
194 regmask_init(&state
->needs_ss_war
, mergedregs
);
195 regmask_init(&state
->needs_ss
, mergedregs
);
198 if (last_rel
&& (reg
->num
== regid(REG_A0
, 0))) {
199 last_rel
->flags
|= IR3_INSTR_UL
;
204 /* cat5+ does not have an (ss) bit, if needed we need to
205 * insert a nop to carry the sync flag. Would be kinda
206 * clever if we were aware of this during scheduling, but
207 * this should be a pretty rare case:
209 if ((n
->flags
& IR3_INSTR_SS
) && (opc_cat(n
->opc
) >= 5)) {
210 struct ir3_instruction
*nop
;
211 nop
= ir3_NOP(block
);
212 nop
->flags
|= IR3_INSTR_SS
;
213 n
->flags
&= ~IR3_INSTR_SS
;
216 /* need to be able to set (ss) on first instruction: */
217 if (list_is_empty(&block
->instr_list
) && (opc_cat(n
->opc
) >= 5))
220 if (ctx
->compiler
->samgq_workaround
&&
221 ctx
->type
== MESA_SHADER_VERTEX
&& n
->opc
== OPC_SAMGQ
) {
222 struct ir3_instruction
*samgp
;
224 list_delinit(&n
->node
);
226 for (i
= 0; i
< 4; i
++) {
227 samgp
= ir3_instr_clone(n
);
228 samgp
->opc
= OPC_SAMGP0
+ i
;
230 samgp
->flags
|= IR3_INSTR_SY
;
233 list_addtail(&n
->node
, &block
->instr_list
);
236 if (n
->opc
== OPC_DSXPP_1
|| n
->opc
== OPC_DSYPP_1
) {
237 struct ir3_instruction
*op_p
= ir3_instr_clone(n
);
238 op_p
->flags
= IR3_INSTR_P
;
240 ctx
->so
->need_fine_derivatives
= true;
244 regmask_set(&state
->needs_ss
, n
->regs
[0]);
246 if (is_tex_or_prefetch(n
)) {
247 regmask_set(&state
->needs_sy
, n
->regs
[0]);
248 if (n
->opc
== OPC_META_TEX_PREFETCH
)
249 has_tex_prefetch
= true;
250 } else if (n
->opc
== OPC_RESINFO
) {
251 regmask_set(&state
->needs_ss
, n
->regs
[0]);
252 ir3_NOP(block
)->flags
|= IR3_INSTR_SS
;
253 last_input_needs_ss
= false;
254 } else if (is_load(n
)) {
255 /* seems like ldlv needs (ss) bit instead?? which is odd but
256 * makes a bunch of flat-varying tests start working on a4xx.
258 if ((n
->opc
== OPC_LDLV
) || (n
->opc
== OPC_LDL
) || (n
->opc
== OPC_LDLW
))
259 regmask_set(&state
->needs_ss
, n
->regs
[0]);
261 regmask_set(&state
->needs_sy
, n
->regs
[0]);
262 } else if (is_atomic(n
->opc
)) {
263 if (n
->flags
& IR3_INSTR_G
) {
264 if (ctx
->compiler
->gpu_id
>= 600) {
265 /* New encoding, returns result via second src: */
266 regmask_set(&state
->needs_sy
, n
->regs
[3]);
268 regmask_set(&state
->needs_sy
, n
->regs
[0]);
271 regmask_set(&state
->needs_ss
, n
->regs
[0]);
275 if (is_ssbo(n
->opc
) || (is_atomic(n
->opc
) && (n
->flags
& IR3_INSTR_G
)))
276 ctx
->so
->has_ssbo
= true;
278 /* both tex/sfu appear to not always immediately consume
279 * their src register(s):
281 if (is_tex(n
) || is_sfu(n
) || is_mem(n
)) {
282 foreach_src (reg
, n
) {
284 regmask_set(&state
->needs_ss_war
, reg
);
290 last_input_needs_ss
|= (n
->opc
== OPC_LDLV
);
297 assert(block
== list_first_entry(&block
->shader
->block_list
,
298 struct ir3_block
, node
));
299 /* special hack.. if using ldlv to bypass interpolation,
300 * we need to insert a dummy bary.f on which we can set
303 if (is_mem(last_input
) && (last_input
->opc
== OPC_LDLV
)) {
304 struct ir3_instruction
*baryf
;
306 /* (ss)bary.f (ei)r63.x, 0, r0.x */
307 baryf
= ir3_instr_create(block
, OPC_BARY_F
);
308 ir3_reg_create(baryf
, regid(63, 0), 0);
309 ir3_reg_create(baryf
, 0, IR3_REG_IMMED
)->iim_val
= 0;
310 ir3_reg_create(baryf
, regid(0, 0), 0);
312 /* insert the dummy bary.f after last_input: */
313 ir3_instr_move_after(baryf
, last_input
);
317 /* by definition, we need (ss) since we are inserting
318 * the dummy bary.f immediately after the ldlv:
320 last_input_needs_ss
= true;
322 last_input
->regs
[0]->flags
|= IR3_REG_EI
;
323 if (last_input_needs_ss
)
324 last_input
->flags
|= IR3_INSTR_SS
;
325 } else if (has_tex_prefetch
) {
326 /* texture prefetch, but *no* inputs.. we need to insert a
327 * dummy bary.f at the top of the shader to unblock varying
330 struct ir3_instruction
*baryf
;
332 /* (ss)bary.f (ei)r63.x, 0, r0.x */
333 baryf
= ir3_instr_create(block
, OPC_BARY_F
);
334 ir3_reg_create(baryf
, regid(63, 0), 0)->flags
|= IR3_REG_EI
;
335 ir3_reg_create(baryf
, 0, IR3_REG_IMMED
)->iim_val
= 0;
336 ir3_reg_create(baryf
, regid(0, 0), 0);
338 /* insert the dummy bary.f at head: */
339 list_delinit(&baryf
->node
);
340 list_add(&baryf
->node
, &block
->instr_list
);
344 last_rel
->flags
|= IR3_INSTR_UL
;
348 if (memcmp(&prev_state
, state
, sizeof(*state
))) {
349 /* our output state changed, this invalidates all of our
352 for (unsigned i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
353 if (!block
->successors
[i
])
355 struct ir3_legalize_block_data
*pbd
= block
->successors
[i
]->data
;
363 /* NOTE: branch instructions are always the last instruction(s)
364 * in the block. We take advantage of this as we resolve the
365 * branches, since "if (foo) break;" constructs turn into
370 * 0029:021: mov.s32s32 r62.x, r1.y
371 * 0082:022: br !p0.x, target=block5
372 * 0083:023: br p0.x, target=block4
373 * // succs: if _[0029:021: mov.s32s32] block4; else block5;
376 * 0084:024: jump, target=block6
380 * 0085:025: jump, target=block7
384 * ie. only instruction in block4/block5 is a jump, so when
385 * resolving branches we can easily detect this by checking
386 * that the first instruction in the target block is itself
387 * a jump, and setup the br directly to the jump's target
388 * (and strip back out the now unreached jump)
390 * TODO sometimes we end up with things like:
394 * add.u r0.y, r0.y, 1
396 * If we swapped the order of the branches, we could drop one.
398 static struct ir3_block
*
399 resolve_dest_block(struct ir3_block
*block
)
401 /* special case for last block: */
402 if (!block
->successors
[0])
405 /* NOTE that we may or may not have inserted the jump
406 * in the target block yet, so conditions to resolve
407 * the dest to the dest block's successor are:
409 * (1) successor[1] == NULL &&
410 * (2) (block-is-empty || only-instr-is-jump)
412 if (block
->successors
[1] == NULL
) {
413 if (list_is_empty(&block
->instr_list
)) {
414 return block
->successors
[0];
415 } else if (list_length(&block
->instr_list
) == 1) {
416 struct ir3_instruction
*instr
= list_first_entry(
417 &block
->instr_list
, struct ir3_instruction
, node
);
418 if (instr
->opc
== OPC_JUMP
)
419 return block
->successors
[0];
426 remove_unused_block(struct ir3_block
*old_target
)
428 list_delinit(&old_target
->node
);
430 /* cleanup dangling predecessors: */
431 for (unsigned i
= 0; i
< ARRAY_SIZE(old_target
->successors
); i
++) {
432 if (old_target
->successors
[i
]) {
433 struct ir3_block
*succ
= old_target
->successors
[i
];
434 _mesa_set_remove_key(succ
->predecessors
, old_target
);
440 retarget_jump(struct ir3_instruction
*instr
, struct ir3_block
*new_target
)
442 struct ir3_block
*old_target
= instr
->cat0
.target
;
443 struct ir3_block
*cur_block
= instr
->block
;
445 /* update current blocks successors to reflect the retargetting: */
446 if (cur_block
->successors
[0] == old_target
) {
447 cur_block
->successors
[0] = new_target
;
449 debug_assert(cur_block
->successors
[1] == old_target
);
450 cur_block
->successors
[1] = new_target
;
453 /* update new target's predecessors: */
454 _mesa_set_add(new_target
->predecessors
, cur_block
);
456 /* and remove old_target's predecessor: */
457 debug_assert(_mesa_set_search(old_target
->predecessors
, cur_block
));
458 _mesa_set_remove_key(old_target
->predecessors
, cur_block
);
460 if (old_target
->predecessors
->entries
== 0)
461 remove_unused_block(old_target
);
463 instr
->cat0
.target
= new_target
;
467 resolve_jump(struct ir3_instruction
*instr
)
469 struct ir3_block
*tblock
=
470 resolve_dest_block(instr
->cat0
.target
);
471 struct ir3_instruction
*target
;
473 if (tblock
!= instr
->cat0
.target
) {
474 retarget_jump(instr
, tblock
);
478 target
= list_first_entry(&tblock
->instr_list
,
479 struct ir3_instruction
, node
);
481 /* TODO maybe a less fragile way to do this. But we are expecting
482 * a pattern from sched_block() that looks like:
484 * br !p0.x, #else-block
487 * if the first branch target is +2, or if 2nd branch target is +1
488 * then we can just drop the jump.
491 if (instr
->cat0
.inv
== true)
496 if (target
->ip
== (instr
->ip
+ next_block
)) {
497 list_delinit(&instr
->node
);
501 (int)target
->ip
- (int)instr
->ip
;
506 /* resolve jumps, removing jumps/branches to immediately following
507 * instruction which we end up with from earlier stages. Since
508 * removing an instruction can invalidate earlier instruction's
509 * branch offsets, we need to do this iteratively until no more
510 * branches are removed.
513 resolve_jumps(struct ir3
*ir
)
515 foreach_block (block
, &ir
->block_list
)
516 foreach_instr (instr
, &block
->instr_list
)
517 if (is_flow(instr
) && instr
->cat0
.target
)
518 if (resolve_jump(instr
))
524 static void mark_jp(struct ir3_block
*block
)
526 struct ir3_instruction
*target
= list_first_entry(&block
->instr_list
,
527 struct ir3_instruction
, node
);
528 target
->flags
|= IR3_INSTR_JP
;
531 /* Mark points where control flow converges or diverges.
533 * Divergence points could actually be re-convergence points where
534 * "parked" threads are recoverged with threads that took the opposite
535 * path last time around. Possibly it is easier to think of (jp) as
536 * "the execution mask might have changed".
539 mark_xvergence_points(struct ir3
*ir
)
541 foreach_block (block
, &ir
->block_list
) {
542 if (block
->predecessors
->entries
> 1) {
543 /* if a block has more than one possible predecessor, then
544 * the first instruction is a convergence point.
547 } else if (block
->predecessors
->entries
== 1) {
548 /* If a block has one predecessor, which has multiple possible
549 * successors, it is a divergence point.
551 set_foreach(block
->predecessors
, entry
) {
552 struct ir3_block
*predecessor
= (struct ir3_block
*)entry
->key
;
553 if (predecessor
->successors
[1]) {
561 /* Insert the branch/jump instructions for flow control between blocks.
562 * Initially this is done naively, without considering if the successor
563 * block immediately follows the current block (ie. so no jump required),
564 * but that is cleaned up in resolve_jumps().
566 * TODO what ensures that the last write to p0.x in a block is the
567 * branch condition? Have we been getting lucky all this time?
570 block_sched(struct ir3
*ir
)
572 foreach_block (block
, &ir
->block_list
) {
573 if (block
->successors
[1]) {
574 /* if/else, conditional branches to "then" or "else": */
575 struct ir3_instruction
*br
;
577 debug_assert(block
->condition
);
579 /* create "else" branch first (since "then" block should
580 * frequently/always end up being a fall-thru):
582 br
= ir3_B(block
, block
->condition
, 0);
584 br
->cat0
.target
= block
->successors
[1];
587 br
= ir3_B(block
, block
->condition
, 0);
588 br
->cat0
.target
= block
->successors
[0];
590 } else if (block
->successors
[0]) {
591 /* otherwise unconditional jump to next block: */
592 struct ir3_instruction
*jmp
;
594 jmp
= ir3_JUMP(block
);
595 jmp
->cat0
.target
= block
->successors
[0];
600 /* Here we workaround the fact that kill doesn't actually kill the thread as
601 * GL expects. The last instruction always needs to be an end instruction,
602 * which means that if we're stuck in a loop where kill is the only way out,
603 * then we may have to jump out to the end. kill may also have the d3d
604 * semantics of converting the thread to a helper thread, rather than setting
605 * the exec mask to 0, in which case the helper thread could get stuck in an
608 * We do this late, both to give the scheduler the opportunity to reschedule
609 * kill instructions earlier and to avoid having to create a separate basic
612 * TODO: Assuming that the wavefront doesn't stop as soon as all threads are
613 * killed, we might benefit by doing this more aggressively when the remaining
614 * part of the program after the kill is large, since that would let us
615 * skip over the instructions when there are no non-killed threads left.
618 kill_sched(struct ir3
*ir
, struct ir3_shader_variant
*so
)
620 /* True if we know that this block will always eventually lead to the end
623 bool always_ends
= true;
625 struct ir3_block
*last_block
=
626 list_last_entry(&ir
->block_list
, struct ir3_block
, node
);
628 foreach_block_rev (block
, &ir
->block_list
) {
629 for (unsigned i
= 0; i
< 2 && block
->successors
[i
]; i
++) {
630 if (block
->successors
[i
]->start_ip
<= block
->end_ip
)
637 foreach_instr_safe (instr
, &block
->instr_list
) {
638 if (instr
->opc
!= OPC_KILL
)
641 struct ir3_instruction
*br
= ir3_instr_create(block
, OPC_B
);
642 br
->regs
[1] = instr
->regs
[1];
644 list_last_entry(&ir
->block_list
, struct ir3_block
, node
);
647 list_add(&br
->node
, &instr
->node
);
654 /* I'm not entirely sure how the branchstack works, but we probably
655 * need to add at least one entry for the divergence which is resolved
660 /* We don't update predecessors/successors, so we have to do this
667 /* Insert nop's required to make this a legal/valid shader program: */
669 nop_sched(struct ir3
*ir
)
671 foreach_block (block
, &ir
->block_list
) {
672 struct ir3_instruction
*last
= NULL
;
673 struct list_head instr_list
;
675 /* remove all the instructions from the list, we'll be adding
676 * them back in as we go
678 list_replace(&block
->instr_list
, &instr_list
);
679 list_inithead(&block
->instr_list
);
681 foreach_instr_safe (instr
, &instr_list
) {
682 unsigned delay
= ir3_delay_calc(block
, instr
, false, true);
684 /* NOTE: I think the nopN encoding works for a5xx and
685 * probably a4xx, but not a3xx. So far only tested on
689 if ((delay
> 0) && (ir
->compiler
->gpu_id
>= 600) && last
&&
690 ((opc_cat(last
->opc
) == 2) || (opc_cat(last
->opc
) == 3)) &&
691 (last
->repeat
== 0)) {
692 /* the previous cat2/cat3 instruction can encode at most 3 nop's: */
693 unsigned transfer
= MIN2(delay
, 3 - last
->nop
);
694 last
->nop
+= transfer
;
698 if ((delay
> 0) && last
&& (last
->opc
== OPC_NOP
)) {
699 /* the previous nop can encode at most 5 repeats: */
700 unsigned transfer
= MIN2(delay
, 5 - last
->repeat
);
701 last
->repeat
+= transfer
;
706 debug_assert(delay
<= 6);
707 ir3_NOP(block
)->repeat
= delay
- 1;
710 list_addtail(&instr
->node
, &block
->instr_list
);
717 ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
)
719 struct ir3_legalize_ctx
*ctx
= rzalloc(ir
, struct ir3_legalize_ctx
);
720 bool mergedregs
= so
->mergedregs
;
725 ctx
->compiler
= ir
->compiler
;
726 ctx
->type
= ir
->type
;
728 /* allocate per-block data: */
729 foreach_block (block
, &ir
->block_list
) {
730 struct ir3_legalize_block_data
*bd
=
731 rzalloc(ctx
, struct ir3_legalize_block_data
);
733 regmask_init(&bd
->state
.needs_ss_war
, mergedregs
);
734 regmask_init(&bd
->state
.needs_ss
, mergedregs
);
735 regmask_init(&bd
->state
.needs_sy
, mergedregs
);
742 /* process each block: */
745 foreach_block (block
, &ir
->block_list
) {
746 progress
|= legalize_block(ctx
, block
);
750 *max_bary
= ctx
->max_bary
;
753 if (so
->type
== MESA_SHADER_FRAGMENT
)
758 ir3_count_instructions(ir
);
759 } while(resolve_jumps(ir
));
761 mark_xvergence_points(ir
);