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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
36
37 static const nir_shader_compiler_options options = {
38 .lower_fpow = true,
39 .lower_scmp = true,
40 .lower_flrp16 = true,
41 .lower_flrp32 = true,
42 .lower_flrp64 = true,
43 .lower_ffract = true,
44 .lower_fmod = true,
45 .lower_fdiv = true,
46 .lower_isign = true,
47 .lower_ldexp = true,
48 .lower_uadd_carry = true,
49 .lower_mul_high = true,
50 .fuse_ffma = true,
51 .vertex_id_zero_based = true,
52 .lower_extract_byte = true,
53 .lower_extract_word = true,
54 .lower_all_io_to_elements = true,
55 .lower_helper_invocation = true,
56 .lower_bitfield_insert_to_shifts = true,
57 .lower_bitfield_extract_to_shifts = true,
58 .use_interpolated_input_intrinsics = true,
59 .lower_rotate = true,
60 .lower_to_scalar = true,
61 .has_imul24 = true,
62 };
63
64 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
65 static const nir_shader_compiler_options options_a6xx = {
66 .lower_fpow = true,
67 .lower_scmp = true,
68 .lower_flrp16 = true,
69 .lower_flrp32 = true,
70 .lower_flrp64 = true,
71 .lower_ffract = true,
72 .lower_fmod = true,
73 .lower_fdiv = true,
74 .lower_isign = true,
75 .lower_ldexp = true,
76 .lower_uadd_carry = true,
77 .lower_mul_high = true,
78 .fuse_ffma = true,
79 .vertex_id_zero_based = false,
80 .lower_extract_byte = true,
81 .lower_extract_word = true,
82 .lower_all_io_to_elements = true,
83 .lower_helper_invocation = true,
84 .lower_bitfield_insert_to_shifts = true,
85 .lower_bitfield_extract_to_shifts = true,
86 .use_interpolated_input_intrinsics = true,
87 .lower_rotate = true,
88 .vectorize_io = true,
89 .lower_to_scalar = true,
90 .has_imul24 = true,
91 };
92
93 const nir_shader_compiler_options *
94 ir3_get_compiler_options(struct ir3_compiler *compiler)
95 {
96 if (compiler->gpu_id >= 600)
97 return &options_a6xx;
98 return &options;
99 }
100
101 /* for given shader key, are any steps handled in nir? */
102 bool
103 ir3_key_lowers_nir(const struct ir3_shader_key *key)
104 {
105 return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
106 key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
107 key->ucp_enables | key->color_two_side |
108 key->fclamp_color | key->vclamp_color |
109 key->tessellation | key->has_gs;
110 }
111
112 #define OPT(nir, pass, ...) ({ \
113 bool this_progress = false; \
114 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
115 this_progress; \
116 })
117
118 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
119
120 static void
121 ir3_optimize_loop(nir_shader *s)
122 {
123 bool progress;
124 unsigned lower_flrp =
125 (s->options->lower_flrp16 ? 16 : 0) |
126 (s->options->lower_flrp32 ? 32 : 0) |
127 (s->options->lower_flrp64 ? 64 : 0);
128
129 do {
130 progress = false;
131
132 OPT_V(s, nir_lower_vars_to_ssa);
133 progress |= OPT(s, nir_opt_copy_prop_vars);
134 progress |= OPT(s, nir_opt_dead_write_vars);
135 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
136 progress |= OPT(s, nir_lower_phis_to_scalar);
137
138 progress |= OPT(s, nir_copy_prop);
139 progress |= OPT(s, nir_opt_dce);
140 progress |= OPT(s, nir_opt_cse);
141 static int gcm = -1;
142 if (gcm == -1)
143 gcm = env_var_as_unsigned("GCM", 0);
144 if (gcm == 1)
145 progress |= OPT(s, nir_opt_gcm, true);
146 else if (gcm == 2)
147 progress |= OPT(s, nir_opt_gcm, false);
148 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
149 progress |= OPT(s, nir_opt_intrinsics);
150 progress |= OPT(s, nir_opt_algebraic);
151 progress |= OPT(s, nir_opt_constant_folding);
152
153 if (lower_flrp != 0) {
154 if (OPT(s, nir_lower_flrp,
155 lower_flrp,
156 false /* always_precise */,
157 s->options->lower_ffma)) {
158 OPT(s, nir_opt_constant_folding);
159 progress = true;
160 }
161
162 /* Nothing should rematerialize any flrps, so we only
163 * need to do this lowering once.
164 */
165 lower_flrp = 0;
166 }
167
168 progress |= OPT(s, nir_opt_dead_cf);
169 if (OPT(s, nir_opt_trivial_continues)) {
170 progress |= true;
171 /* If nir_opt_trivial_continues makes progress, then we need to clean
172 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
173 * to make progress.
174 */
175 OPT(s, nir_copy_prop);
176 OPT(s, nir_opt_dce);
177 }
178 progress |= OPT(s, nir_opt_if, false);
179 progress |= OPT(s, nir_opt_remove_phis);
180 progress |= OPT(s, nir_opt_undef);
181
182 } while (progress);
183 }
184
185 void
186 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
187 const struct ir3_shader_key *key)
188 {
189 struct nir_lower_tex_options tex_options = {
190 .lower_rect = 0,
191 .lower_tg4_offsets = true,
192 };
193
194 if (key && (key->has_gs || key->tessellation)) {
195 switch (shader->type) {
196 case MESA_SHADER_VERTEX:
197 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
198 break;
199 case MESA_SHADER_TESS_CTRL:
200 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, shader, key->tessellation);
201 break;
202 case MESA_SHADER_TESS_EVAL:
203 NIR_PASS_V(s, ir3_nir_lower_tess_eval, key->tessellation);
204 if (key->has_gs)
205 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
206 break;
207 case MESA_SHADER_GEOMETRY:
208 NIR_PASS_V(s, ir3_nir_lower_gs, shader);
209 break;
210 default:
211 break;
212 }
213 }
214
215 if (key) {
216 switch (shader->type) {
217 case MESA_SHADER_FRAGMENT:
218 tex_options.saturate_s = key->fsaturate_s;
219 tex_options.saturate_t = key->fsaturate_t;
220 tex_options.saturate_r = key->fsaturate_r;
221 break;
222 case MESA_SHADER_VERTEX:
223 tex_options.saturate_s = key->vsaturate_s;
224 tex_options.saturate_t = key->vsaturate_t;
225 tex_options.saturate_r = key->vsaturate_r;
226 break;
227 default:
228 /* TODO */
229 break;
230 }
231 }
232
233 if (shader->compiler->gpu_id >= 400) {
234 /* a4xx seems to have *no* sam.p */
235 tex_options.lower_txp = ~0; /* lower all txp */
236 } else {
237 /* a3xx just needs to avoid sam.p for 3d tex */
238 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
239 }
240
241 if (ir3_shader_debug & IR3_DBG_DISASM) {
242 debug_printf("----------------------\n");
243 nir_print_shader(s, stdout);
244 debug_printf("----------------------\n");
245 }
246
247 OPT_V(s, nir_lower_regs_to_ssa);
248 OPT_V(s, ir3_nir_lower_io_offsets);
249
250 if (key) {
251 if (s->info.stage == MESA_SHADER_VERTEX) {
252 OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false, NULL);
253 if (key->vclamp_color)
254 OPT_V(s, nir_lower_clamp_color_outputs);
255 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
256 OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
257 if (key->fclamp_color)
258 OPT_V(s, nir_lower_clamp_color_outputs);
259 }
260 if (key->color_two_side) {
261 OPT_V(s, nir_lower_two_sided_color);
262 }
263 } else {
264 /* only want to do this the first time (when key is null)
265 * and not again on any potential 2nd variant lowering pass:
266 */
267 OPT_V(s, ir3_nir_apply_trig_workarounds);
268
269 /* This wouldn't hurt to run multiple times, but there is
270 * no need to:
271 */
272 if (shader->type == MESA_SHADER_FRAGMENT)
273 OPT_V(s, nir_lower_fb_read);
274 }
275
276 OPT_V(s, nir_lower_tex, &tex_options);
277 OPT_V(s, nir_lower_load_const_to_scalar);
278 if (shader->compiler->gpu_id < 500)
279 OPT_V(s, ir3_nir_lower_tg4_to_tex);
280
281 ir3_optimize_loop(s);
282
283 /* do ubo load and idiv lowering after first opt loop to get a chance to
284 * propagate constants for divide by immed power-of-two and constant ubo
285 * block/offsets:
286 *
287 * NOTE that UBO analysis pass should only be done once, before variants
288 */
289 const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
290 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
291 if (ubo_progress || idiv_progress)
292 ir3_optimize_loop(s);
293
294 /* Do late algebraic optimization to turn add(a, neg(b)) back into
295 * subs, then the mandatory cleanup after algebraic. Note that it may
296 * produce fnegs, and if so then we need to keep running to squash
297 * fneg(fneg(a)).
298 */
299 bool more_late_algebraic = true;
300 while (more_late_algebraic) {
301 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
302 OPT_V(s, nir_opt_constant_folding);
303 OPT_V(s, nir_copy_prop);
304 OPT_V(s, nir_opt_dce);
305 OPT_V(s, nir_opt_cse);
306 }
307
308 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
309
310 OPT_V(s, nir_opt_sink, nir_move_const_undef);
311
312 if (ir3_shader_debug & IR3_DBG_DISASM) {
313 debug_printf("----------------------\n");
314 nir_print_shader(s, stdout);
315 debug_printf("----------------------\n");
316 }
317
318 nir_sweep(s);
319
320 /* The first time thru, when not creating variant, do the one-time
321 * const_state layout setup. This should be done after ubo range
322 * analysis.
323 */
324 if (!key) {
325 ir3_setup_const_state(shader, s);
326 }
327 }
328
329 static void
330 ir3_nir_scan_driver_consts(nir_shader *shader,
331 struct ir3_const_state *layout)
332 {
333 nir_foreach_function(function, shader) {
334 if (!function->impl)
335 continue;
336
337 nir_foreach_block(block, function->impl) {
338 nir_foreach_instr(instr, block) {
339 if (instr->type != nir_instr_type_intrinsic)
340 continue;
341
342 nir_intrinsic_instr *intr =
343 nir_instr_as_intrinsic(instr);
344 unsigned idx;
345
346 switch (intr->intrinsic) {
347 case nir_intrinsic_get_buffer_size:
348 idx = nir_src_as_uint(intr->src[0]);
349 if (layout->ssbo_size.mask & (1 << idx))
350 break;
351 layout->ssbo_size.mask |= (1 << idx);
352 layout->ssbo_size.off[idx] =
353 layout->ssbo_size.count;
354 layout->ssbo_size.count += 1; /* one const per */
355 break;
356 case nir_intrinsic_image_deref_atomic_add:
357 case nir_intrinsic_image_deref_atomic_imin:
358 case nir_intrinsic_image_deref_atomic_umin:
359 case nir_intrinsic_image_deref_atomic_imax:
360 case nir_intrinsic_image_deref_atomic_umax:
361 case nir_intrinsic_image_deref_atomic_and:
362 case nir_intrinsic_image_deref_atomic_or:
363 case nir_intrinsic_image_deref_atomic_xor:
364 case nir_intrinsic_image_deref_atomic_exchange:
365 case nir_intrinsic_image_deref_atomic_comp_swap:
366 case nir_intrinsic_image_deref_store:
367 case nir_intrinsic_image_deref_size:
368 idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
369 if (layout->image_dims.mask & (1 << idx))
370 break;
371 layout->image_dims.mask |= (1 << idx);
372 layout->image_dims.off[idx] =
373 layout->image_dims.count;
374 layout->image_dims.count += 3; /* three const per */
375 break;
376 case nir_intrinsic_load_ubo:
377 if (nir_src_is_const(intr->src[0])) {
378 layout->num_ubos = MAX2(layout->num_ubos,
379 nir_src_as_uint(intr->src[0]) + 1);
380 } else {
381 layout->num_ubos = shader->info.num_ubos;
382 }
383 break;
384 case nir_intrinsic_load_base_vertex:
385 case nir_intrinsic_load_first_vertex:
386 layout->num_driver_params =
387 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
388 break;
389 case nir_intrinsic_load_user_clip_plane:
390 layout->num_driver_params =
391 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
392 break;
393 case nir_intrinsic_load_num_work_groups:
394 layout->num_driver_params =
395 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
396 break;
397 case nir_intrinsic_load_local_group_size:
398 layout->num_driver_params =
399 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
400 break;
401 default:
402 break;
403 }
404 }
405 }
406 }
407 }
408
409 static void
410 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
411 {
412 struct ir3_compiler *compiler = shader->compiler;
413 struct ir3_const_state *const_state = &shader->const_state;
414
415 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
416
417 ir3_nir_scan_driver_consts(nir, const_state);
418
419 if ((compiler->gpu_id < 500) &&
420 (shader->stream_output.num_outputs > 0)) {
421 const_state->num_driver_params =
422 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
423 }
424
425 /* num_driver_params is scalar, align to vec4: */
426 const_state->num_driver_params = align(const_state->num_driver_params, 4);
427
428 debug_assert((shader->ubo_state.size % 16) == 0);
429 unsigned constoff = align(shader->ubo_state.size / 16, 8);
430 unsigned ptrsz = ir3_pointer_size(compiler);
431
432 if (const_state->num_ubos > 0) {
433 const_state->offsets.ubo = constoff;
434 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
435 }
436
437 if (const_state->ssbo_size.count > 0) {
438 unsigned cnt = const_state->ssbo_size.count;
439 const_state->offsets.ssbo_sizes = constoff;
440 constoff += align(cnt, 4) / 4;
441 }
442
443 if (const_state->image_dims.count > 0) {
444 unsigned cnt = const_state->image_dims.count;
445 const_state->offsets.image_dims = constoff;
446 constoff += align(cnt, 4) / 4;
447 }
448
449 if (const_state->num_driver_params > 0)
450 const_state->offsets.driver_param = constoff;
451 constoff += const_state->num_driver_params / 4;
452
453 if ((shader->type == MESA_SHADER_VERTEX) &&
454 (compiler->gpu_id < 500) &&
455 shader->stream_output.num_outputs > 0) {
456 const_state->offsets.tfbo = constoff;
457 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
458 }
459
460 switch (shader->type) {
461 case MESA_SHADER_VERTEX:
462 const_state->offsets.primitive_param = constoff;
463 constoff += 1;
464 break;
465 case MESA_SHADER_TESS_CTRL:
466 case MESA_SHADER_TESS_EVAL:
467 constoff = align(constoff - 1, 4) + 3;
468 const_state->offsets.primitive_param = constoff;
469 const_state->offsets.primitive_map = constoff + 5;
470 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
471 break;
472 case MESA_SHADER_GEOMETRY:
473 const_state->offsets.primitive_param = constoff;
474 const_state->offsets.primitive_map = constoff + 1;
475 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
476 break;
477 default:
478 break;
479 }
480
481 const_state->offsets.immediate = constoff;
482 }