src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/format/u_format.h"
  31
  32 #include "drm/freedreno_drmif.h"
  33
  34 #include "ir3_shader.h"
  35 #include "ir3_compiler.h"
  36 #include "ir3_nir.h"
  37
  38 int
  39 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  40 {
  41         return glsl_count_attribute_slots(type, false);
  42 }
  43
  44 /* for vertex shader, the inputs are loaded into registers before the shader
  45  * is executed, so max_regs from the shader instructions might not properly
  46  * reflect the # of registers actually used, especially in case passthrough
  47  * varyings.
  48  *
  49  * Likewise, for fragment shader, we can have some regs which are passed
  50  * input values but never touched by the resulting shader (ie. as result
  51  * of dead code elimination or simply because we don't know how to turn
  52  * the reg off.
  53  */
  54 static void
  55 fixup_regfootprint(struct ir3_shader_variant *v)
  56 {
  57         unsigned i;
  58
  59         for (i = 0; i < v->inputs_count; i++) {
  60                 /* skip frag inputs fetch via bary.f since their reg's are
  61                  * not written by gpu before shader starts (and in fact the
  62                  * regid's might not even be valid)
  63                  */
  64                 if (v->inputs[i].bary)
  65                         continue;
  66
  67                 /* ignore high regs that are global to all threads in a warp
  68                  * (they exist by default) (a5xx+)
  69                  */
  70                 if (v->inputs[i].regid >= regid(48,0))
  71                         continue;
  72
  73                 if (v->inputs[i].compmask) {
  74                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  75                         int32_t regid = v->inputs[i].regid + n;
  76                         if (v->inputs[i].half) {
  77                                 if (!v->mergedregs) {
  78                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  79                                 } else {
  80                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  81                                 }
  82                         } else {
  83                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  84                         }
  85                 }
  86         }
  87
  88         for (i = 0; i < v->outputs_count; i++) {
  89                 /* for ex, VS shaders with tess don't have normal varying outs: */
  90                 if (!VALIDREG(v->outputs[i].regid))
  91                         continue;
  92                 int32_t regid = v->outputs[i].regid + 3;
  93                 if (v->outputs[i].half) {
  94                         if (!v->mergedregs) {
  95                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  96                         } else {
  97                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  98                         }
  99                 } else {
 100                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 101                 }
 102         }
 103
 104         for (i = 0; i < v->num_sampler_prefetch; i++) {
 105                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 106                 int32_t regid = v->sampler_prefetch[i].dst + n;
 107                 if (v->sampler_prefetch[i].half_precision) {
 108                         if (!v->mergedregs) {
 109                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 110                         } else {
 111                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 112                         }
 113                 } else {
 114                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 115                 }
 116         }
 117 }
 118
 119 /* wrapper for ir3_assemble() which does some info fixup based on
 120  * shader state.  Non-static since used by ir3_cmdline too.
 121  */
 122 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 123 {
 124         unsigned gpu_id = v->shader->compiler->gpu_id;
 125         void *bin;
 126
 127         bin = ir3_assemble(v);
 128         if (!bin)
 129                 return NULL;
 130
 131         if (gpu_id >= 400) {
 132                 v->instrlen = v->info.sizedwords / (2 * 16);
 133         } else {
 134                 v->instrlen = v->info.sizedwords / (2 * 4);
 135         }
 136
 137         /* NOTE: if relative addressing is used, we set constlen in
 138          * the compiler (to worst-case value) since we don't know in
 139          * the assembler what the max addr reg value can be:
 140          */
 141         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 142
 143         fixup_regfootprint(v);
 144
 145         return bin;
 146 }
 147
 148 static void
 149 assemble_variant(struct ir3_shader_variant *v)
 150 {
 151         v->bin = ir3_shader_assemble(v);
 152
 153         if (shader_debug_enabled(v->shader->type)) {
 154                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 155                         ir3_shader_stage(v), v->shader->nir->info.name);
 156                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 157                         fprintf(stdout, "SIMD0\n");
 158                 ir3_shader_disasm(v, v->bin, stdout);
 159         }
 160
 161         /* no need to keep the ir around beyond this point: */
 162         ir3_destroy(v->ir);
 163         v->ir = NULL;
 164 }
 165
 166 /*
 167  * For creating normal shader variants, 'nonbinning' is NULL.  For
 168  * creating binning pass shader, it is link to corresponding normal
 169  * (non-binning) variant.
 170  */
 171 static struct ir3_shader_variant *
 172 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 173                 struct ir3_shader_variant *nonbinning)
 174 {
 175         struct ir3_shader_variant *v = rzalloc_size(shader, sizeof(*v));
 176         int ret;
 177
 178         if (!v)
 179                 return NULL;
 180
 181         v->id = ++shader->variant_count;
 182         v->shader = shader;
 183         v->binning_pass = !!nonbinning;
 184         v->nonbinning = nonbinning;
 185         v->key = *key;
 186         v->type = shader->type;
 187
 188         if (shader->compiler->gpu_id >= 600) {
 189                 switch (v->type) {
 190                 case MESA_SHADER_TESS_CTRL:
 191                 case MESA_SHADER_TESS_EVAL:
 192                         v->mergedregs = false;
 193                         break;
 194                 case MESA_SHADER_VERTEX:
 195                 case MESA_SHADER_GEOMETRY:
 196                         /* For VS/GS, normally do mergedregs, but if there is tess
 197                          * we need to not used MERGEDREGS
 198                          */
 199                         v->mergedregs = !key->tessellation;
 200                         break;
 201                 default:
 202                         v->mergedregs = true;
 203                 }
 204         } else {
 205                 v->mergedregs = false;
 206         }
 207
 208         ret = ir3_compile_shader_nir(shader->compiler, v);
 209         if (ret) {
 210                 debug_error("compile failed!");
 211                 goto fail;
 212         }
 213
 214         assemble_variant(v);
 215         if (!v->bin) {
 216                 debug_error("assemble failed!");
 217                 goto fail;
 218         }
 219
 220         return v;
 221
 222 fail:
 223         ralloc_free(v);
 224         return NULL;
 225 }
 226
 227 static inline struct ir3_shader_variant *
 228 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 229                 bool *created)
 230 {
 231         struct ir3_shader_variant *v;
 232
 233         *created = false;
 234
 235         for (v = shader->variants; v; v = v->next)
 236                 if (ir3_shader_key_equal(key, &v->key))
 237                         return v;
 238
 239         /* compile new variant if it doesn't exist already: */
 240         v = create_variant(shader, key, NULL);
 241         if (v) {
 242                 v->next = shader->variants;
 243                 shader->variants = v;
 244                 *created = true;
 245         }
 246
 247         return v;
 248 }
 249
 250 struct ir3_shader_variant *
 251 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 252                 bool binning_pass, bool *created)
 253 {
 254         mtx_lock(&shader->variants_lock);
 255         struct ir3_shader_variant *v =
 256                         shader_variant(shader, key, created);
 257
 258         if (v && binning_pass) {
 259                 if (!v->binning) {
 260                         v->binning = create_variant(shader, key, v);
 261                         *created = true;
 262                 }
 263                 mtx_unlock(&shader->variants_lock);
 264                 return v->binning;
 265         }
 266         mtx_unlock(&shader->variants_lock);
 267
 268         return v;
 269 }
 270
 271 void
 272 ir3_shader_destroy(struct ir3_shader *shader)
 273 {
 274         free(shader->const_state.immediates);
 275         ralloc_free(shader->nir);
 276         mtx_destroy(&shader->variants_lock);
 277         ralloc_free(shader);
 278 }
 279
 280 /**
 281  * Creates a bitmask of the used bits of the shader key by this particular
 282  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 283  * possible.
 284  */
 285 static void
 286 ir3_setup_used_key(struct ir3_shader *shader)
 287 {
 288         nir_shader *nir = shader->nir;
 289         struct shader_info *info = &nir->info;
 290         struct ir3_shader_key *key = &shader->key_mask;
 291
 292         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 293          * check in the common case.
 294          */
 295         key->has_per_samp = true;
 296
 297         if (info->stage == MESA_SHADER_FRAGMENT) {
 298                 key->fsaturate_s = ~0;
 299                 key->fsaturate_t = ~0;
 300                 key->fsaturate_r = ~0;
 301                 key->fastc_srgb = ~0;
 302                 key->fsamples = ~0;
 303
 304                 if (info->inputs_read & VARYING_BITS_COLOR) {
 305                         key->rasterflat = true;
 306                         key->color_two_side = true;
 307                 }
 308
 309                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 310                                                                 FRAG_RESULT_STENCIL |
 311                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 312                         key->fclamp_color = true;
 313                 }
 314
 315                 /* Only used for deciding on behavior of
 316                  * nir_intrinsic_load_barycentric_sample
 317                  */
 318                 key->msaa = info->fs.uses_sample_qualifier;
 319         } else {
 320                 key->tessellation = ~0;
 321                 key->has_gs = true;
 322
 323                 if (info->outputs_written & VARYING_BITS_COLOR)
 324                         key->vclamp_color = true;
 325
 326                 if (info->stage == MESA_SHADER_VERTEX) {
 327                         key->vsaturate_s = ~0;
 328                         key->vsaturate_t = ~0;
 329                         key->vsaturate_r = ~0;
 330                         key->vastc_srgb = ~0;
 331                         key->vsamples = ~0;
 332                 }
 333         }
 334 }
 335
 336 struct ir3_shader *
 337 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 338                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 339 {
 340         struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
 341
 342         mtx_init(&shader->variants_lock, mtx_plain);
 343         shader->compiler = compiler;
 344         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 345         shader->type = nir->info.stage;
 346         if (stream_output)
 347                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 348         shader->const_state.num_reserved_user_consts = reserved_user_consts;
 349
 350         if (nir->info.stage == MESA_SHADER_GEOMETRY)
 351                 NIR_PASS_V(nir, ir3_nir_lower_gs);
 352
 353         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 354                            (nir_lower_io_options)0);
 355
 356         if (compiler->gpu_id >= 600 &&
 357                         nir->info.stage == MESA_SHADER_FRAGMENT &&
 358                         !(ir3_shader_debug & IR3_DBG_NOFP16))
 359                 NIR_PASS_V(nir, nir_lower_mediump_outputs);
 360
 361         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 362                 /* NOTE: lower load_barycentric_at_sample first, since it
 363                  * produces load_barycentric_at_offset:
 364                  */
 365                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 366                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 367
 368                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 369         }
 370
 371         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 372
 373         NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
 374
 375         /* do first pass optimization, ignoring the key: */
 376         ir3_optimize_nir(shader, nir);
 377
 378         shader->nir = nir;
 379         if (ir3_shader_debug & IR3_DBG_DISASM) {
 380                 printf("dump nir%d: type=%d", shader->id, shader->type);
 381                 nir_print_shader(shader->nir, stdout);
 382         }
 383
 384         ir3_setup_used_key(shader);
 385
 386         return shader;
 387 }
 388
 389 static void dump_reg(FILE *out, const char *name, uint32_t r)
 390 {
 391         if (r != regid(63,0)) {
 392                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 393                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 394                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 395         }
 396 }
 397
 398 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 399                 unsigned slot, const char *name)
 400 {
 401         uint32_t regid;
 402         regid = ir3_find_output_regid(so, slot);
 403         dump_reg(out, name, regid);
 404 }
 405
 406 static const char *
 407 input_name(struct ir3_shader_variant *so, int i)
 408 {
 409         if (so->inputs[i].sysval) {
 410                 return gl_system_value_name(so->inputs[i].slot);
 411         } else if (so->type == MESA_SHADER_VERTEX) {
 412                 return gl_vert_attrib_name(so->inputs[i].slot);
 413         } else {
 414                 return gl_varying_slot_name(so->inputs[i].slot);
 415         }
 416 }
 417
 418 static const char *
 419 output_name(struct ir3_shader_variant *so, int i)
 420 {
 421         if (so->type == MESA_SHADER_FRAGMENT) {
 422                 return gl_frag_result_name(so->outputs[i].slot);
 423         } else {
 424                 switch (so->outputs[i].slot) {
 425                 case VARYING_SLOT_GS_HEADER_IR3:
 426                         return "GS_HEADER";
 427                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 428                         return "GS_VERTEX_FLAGS";
 429                 case VARYING_SLOT_TCS_HEADER_IR3:
 430                         return "TCS_HEADER";
 431                 default:
 432                         return gl_varying_slot_name(so->outputs[i].slot);
 433                 }
 434         }
 435 }
 436
 437 void
 438 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 439 {
 440         struct ir3 *ir = so->ir;
 441         struct ir3_register *reg;
 442         const char *type = ir3_shader_stage(so);
 443         uint8_t regid;
 444         unsigned i;
 445
 446         foreach_input_n (instr, i, ir) {
 447                 reg = instr->regs[0];
 448                 regid = reg->num;
 449                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 450                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 451                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 452
 453                 if (reg->wrmask > 0x1)
 454                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 455                 fprintf(out, "\n");
 456         }
 457
 458         /* print pre-dispatch texture fetches: */
 459         for (i = 0; i < so->num_sampler_prefetch; i++) {
 460                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 461                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 462                                 fetch->half_precision ? "h" : "",
 463                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 464                                 fetch->src, fetch->samp_id, fetch->tex_id,
 465                                 fetch->wrmask, fetch->cmd);
 466         }
 467
 468         foreach_output_n (instr, i, ir) {
 469                 reg = instr->regs[0];
 470                 regid = reg->num;
 471                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 472                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 473                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 474                 if (reg->wrmask > 0x1)
 475                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 476                 fprintf(out, "\n");
 477         }
 478
 479         const struct ir3_const_state *const_state = ir3_const_state(so);
 480         for (i = 0; i < const_state->immediates_count; i++) {
 481                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 482                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 483                                 const_state->immediates[i].val[0],
 484                                 const_state->immediates[i].val[1],
 485                                 const_state->immediates[i].val[2],
 486                                 const_state->immediates[i].val[3]);
 487         }
 488
 489         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 490
 491         fprintf(out, "; %s: outputs:", type);
 492         for (i = 0; i < so->outputs_count; i++) {
 493                 uint8_t regid = so->outputs[i].regid;
 494                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 495                 fprintf(out, " %s%d.%c (%s)",
 496                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 497                                 output_name(so, i));
 498         }
 499         fprintf(out, "\n");
 500
 501         fprintf(out, "; %s: inputs:", type);
 502         for (i = 0; i < so->inputs_count; i++) {
 503                 uint8_t regid = so->inputs[i].regid;
 504                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 505                                 (regid >> 2), "xyzw"[regid & 0x3],
 506                                 input_name(so, i),
 507                                 so->inputs[i].slot,
 508                                 so->inputs[i].compmask,
 509                                 so->inputs[i].inloc,
 510                                 so->inputs[i].bary);
 511         }
 512         fprintf(out, "\n");
 513
 514         /* print generic shader info: */
 515         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 516                         type, so->shader->id, so->id,
 517                         so->info.instrs_count,
 518                         so->info.nops_count,
 519                         so->info.instrs_count - so->info.nops_count,
 520                         so->info.mov_count, so->info.cov_count,
 521                         so->info.sizedwords);
 522
 523         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 524                         type, so->shader->id, so->id,
 525                         so->info.last_baryf,
 526                         so->info.max_half_reg + 1,
 527                         so->info.max_reg + 1,
 528                         so->constlen);
 529
 530         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 531                         type, so->shader->id, so->id,
 532                         so->info.sstall,
 533                         so->info.ss,
 534                         so->info.sy,
 535                         so->max_sun,
 536                         so->loops);
 537
 538         /* print shader type specific info: */
 539         switch (so->type) {
 540         case MESA_SHADER_VERTEX:
 541                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 542                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 543                 break;
 544         case MESA_SHADER_FRAGMENT:
 545                 dump_reg(out, "pos (ij_pixel)",
 546                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 547                 dump_reg(out, "pos (ij_centroid)",
 548                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 549                 dump_reg(out, "pos (ij_size)",
 550                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 551                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 552                 if (so->color0_mrt) {
 553                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 554                 } else {
 555                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 556                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 557                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 558                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 559                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 560                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 561                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 562                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 563                 }
 564                 dump_reg(out, "fragcoord",
 565                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 566                 dump_reg(out, "fragface",
 567                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 568                 break;
 569         default:
 570                 /* TODO */
 571                 break;
 572         }
 573
 574         fprintf(out, "\n");
 575 }
 576
 577 uint64_t
 578 ir3_shader_outputs(const struct ir3_shader *so)
 579 {
 580         return so->nir->info.outputs_written;
 581 }