src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/format/u_format.h"
  31
  32 #include "drm/freedreno_drmif.h"
  33
  34 #include "ir3_shader.h"
  35 #include "ir3_compiler.h"
  36 #include "ir3_nir.h"
  37
  38 int
  39 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  40 {
  41         return glsl_count_attribute_slots(type, false);
  42 }
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         assert(!v->bo);
  50         if (v->binning)
  51                 delete_variant(v->binning);
  52         free(v->bin);
  53         free(v);
  54 }
  55
  56 /* for vertex shader, the inputs are loaded into registers before the shader
  57  * is executed, so max_regs from the shader instructions might not properly
  58  * reflect the # of registers actually used, especially in case passthrough
  59  * varyings.
  60  *
  61  * Likewise, for fragment shader, we can have some regs which are passed
  62  * input values but never touched by the resulting shader (ie. as result
  63  * of dead code elimination or simply because we don't know how to turn
  64  * the reg off.
  65  */
  66 static void
  67 fixup_regfootprint(struct ir3_shader_variant *v)
  68 {
  69         unsigned i;
  70
  71         for (i = 0; i < v->inputs_count; i++) {
  72                 /* skip frag inputs fetch via bary.f since their reg's are
  73                  * not written by gpu before shader starts (and in fact the
  74                  * regid's might not even be valid)
  75                  */
  76                 if (v->inputs[i].bary)
  77                         continue;
  78
  79                 /* ignore high regs that are global to all threads in a warp
  80                  * (they exist by default) (a5xx+)
  81                  */
  82                 if (v->inputs[i].regid >= regid(48,0))
  83                         continue;
  84
  85                 if (v->inputs[i].compmask) {
  86                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  87                         int32_t regid = v->inputs[i].regid + n;
  88                         if (v->inputs[i].half) {
  89                                 if (!v->mergedregs) {
  90                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  91                                 } else {
  92                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  93                                 }
  94                         } else {
  95                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  96                         }
  97                 }
  98         }
  99
 100         for (i = 0; i < v->outputs_count; i++) {
 101                 /* for ex, VS shaders with tess don't have normal varying outs: */
 102                 if (!VALIDREG(v->outputs[i].regid))
 103                         continue;
 104                 int32_t regid = v->outputs[i].regid + 3;
 105                 if (v->outputs[i].half) {
 106                         if (!v->mergedregs) {
 107                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 108                         } else {
 109                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 110                         }
 111                 } else {
 112                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 113                 }
 114         }
 115
 116         for (i = 0; i < v->num_sampler_prefetch; i++) {
 117                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 118                 int32_t regid = v->sampler_prefetch[i].dst + n;
 119                 if (v->sampler_prefetch[i].half_precision) {
 120                         if (!v->mergedregs) {
 121                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 122                         } else {
 123                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 124                         }
 125                 } else {
 126                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 127                 }
 128         }
 129 }
 130
 131 /* wrapper for ir3_assemble() which does some info fixup based on
 132  * shader state.  Non-static since used by ir3_cmdline too.
 133  */
 134 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 135 {
 136         unsigned gpu_id = v->shader->compiler->gpu_id;
 137         void *bin;
 138
 139         bin = ir3_assemble(v);
 140         if (!bin)
 141                 return NULL;
 142
 143         if (gpu_id >= 400) {
 144                 v->instrlen = v->info.sizedwords / (2 * 16);
 145         } else {
 146                 v->instrlen = v->info.sizedwords / (2 * 4);
 147         }
 148
 149         /* NOTE: if relative addressing is used, we set constlen in
 150          * the compiler (to worst-case value) since we don't know in
 151          * the assembler what the max addr reg value can be:
 152          */
 153         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 154
 155         fixup_regfootprint(v);
 156
 157         return bin;
 158 }
 159
 160 static void
 161 assemble_variant(struct ir3_shader_variant *v)
 162 {
 163         v->bin = ir3_shader_assemble(v);
 164
 165         if (shader_debug_enabled(v->shader->type)) {
 166                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 167                         ir3_shader_stage(v), v->shader->nir->info.name);
 168                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 169                         fprintf(stdout, "SIMD0\n");
 170                 ir3_shader_disasm(v, v->bin, stdout);
 171         }
 172
 173         /* no need to keep the ir around beyond this point: */
 174         ir3_destroy(v->ir);
 175         v->ir = NULL;
 176 }
 177
 178 /*
 179  * For creating normal shader variants, 'nonbinning' is NULL.  For
 180  * creating binning pass shader, it is link to corresponding normal
 181  * (non-binning) variant.
 182  */
 183 static struct ir3_shader_variant *
 184 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 185                 struct ir3_shader_variant *nonbinning)
 186 {
 187         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 188         int ret;
 189
 190         if (!v)
 191                 return NULL;
 192
 193         v->id = ++shader->variant_count;
 194         v->shader = shader;
 195         v->binning_pass = !!nonbinning;
 196         v->nonbinning = nonbinning;
 197         v->key = *key;
 198         v->type = shader->type;
 199
 200         if (shader->compiler->gpu_id >= 600) {
 201                 switch (v->type) {
 202                 case MESA_SHADER_TESS_CTRL:
 203                 case MESA_SHADER_TESS_EVAL:
 204                         v->mergedregs = false;
 205                         break;
 206                 case MESA_SHADER_VERTEX:
 207                 case MESA_SHADER_GEOMETRY:
 208                         /* For VS/GS, normally do mergedregs, but if there is tess
 209                          * we need to not used MERGEDREGS
 210                          */
 211                         v->mergedregs = !key->tessellation;
 212                         break;
 213                 default:
 214                         v->mergedregs = true;
 215                 }
 216         } else {
 217                 v->mergedregs = false;
 218         }
 219
 220         ret = ir3_compile_shader_nir(shader->compiler, v);
 221         if (ret) {
 222                 debug_error("compile failed!");
 223                 goto fail;
 224         }
 225
 226         assemble_variant(v);
 227         if (!v->bin) {
 228                 debug_error("assemble failed!");
 229                 goto fail;
 230         }
 231
 232         return v;
 233
 234 fail:
 235         delete_variant(v);
 236         return NULL;
 237 }
 238
 239 static inline struct ir3_shader_variant *
 240 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 241                 bool *created)
 242 {
 243         struct ir3_shader_variant *v;
 244
 245         *created = false;
 246
 247         for (v = shader->variants; v; v = v->next)
 248                 if (ir3_shader_key_equal(key, &v->key))
 249                         return v;
 250
 251         /* compile new variant if it doesn't exist already: */
 252         v = create_variant(shader, key, NULL);
 253         if (v) {
 254                 v->next = shader->variants;
 255                 shader->variants = v;
 256                 *created = true;
 257         }
 258
 259         return v;
 260 }
 261
 262 struct ir3_shader_variant *
 263 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 264                 bool binning_pass, bool *created)
 265 {
 266         mtx_lock(&shader->variants_lock);
 267         struct ir3_shader_variant *v =
 268                         shader_variant(shader, key, created);
 269
 270         if (v && binning_pass) {
 271                 if (!v->binning) {
 272                         v->binning = create_variant(shader, key, v);
 273                         *created = true;
 274                 }
 275                 mtx_unlock(&shader->variants_lock);
 276                 return v->binning;
 277         }
 278         mtx_unlock(&shader->variants_lock);
 279
 280         return v;
 281 }
 282
 283 void
 284 ir3_shader_destroy(struct ir3_shader *shader)
 285 {
 286         struct ir3_shader_variant *v, *t;
 287         for (v = shader->variants; v; ) {
 288                 t = v;
 289                 v = v->next;
 290                 delete_variant(t);
 291         }
 292         free(shader->const_state.immediates);
 293         ralloc_free(shader->nir);
 294         mtx_destroy(&shader->variants_lock);
 295         free(shader);
 296 }
 297
 298 /**
 299  * Creates a bitmask of the used bits of the shader key by this particular
 300  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 301  * possible.
 302  */
 303 static void
 304 ir3_setup_used_key(struct ir3_shader *shader)
 305 {
 306         nir_shader *nir = shader->nir;
 307         struct shader_info *info = &nir->info;
 308         struct ir3_shader_key *key = &shader->key_mask;
 309
 310         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 311          * check in the common case.
 312          */
 313         key->has_per_samp = true;
 314
 315         if (info->stage == MESA_SHADER_FRAGMENT) {
 316                 key->fsaturate_s = ~0;
 317                 key->fsaturate_t = ~0;
 318                 key->fsaturate_r = ~0;
 319                 key->fastc_srgb = ~0;
 320                 key->fsamples = ~0;
 321
 322                 if (info->inputs_read & VARYING_BITS_COLOR) {
 323                         key->rasterflat = true;
 324                         key->color_two_side = true;
 325                 }
 326
 327                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 328                                                                 FRAG_RESULT_STENCIL |
 329                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 330                         key->fclamp_color = true;
 331                 }
 332
 333                 /* Only used for deciding on behavior of
 334                  * nir_intrinsic_load_barycentric_sample
 335                  */
 336                 key->msaa = info->fs.uses_sample_qualifier;
 337         } else {
 338                 key->tessellation = ~0;
 339                 key->has_gs = true;
 340
 341                 if (info->outputs_written & VARYING_BITS_COLOR)
 342                         key->vclamp_color = true;
 343
 344                 if (info->stage == MESA_SHADER_VERTEX) {
 345                         key->vsaturate_s = ~0;
 346                         key->vsaturate_t = ~0;
 347                         key->vsaturate_r = ~0;
 348                         key->vastc_srgb = ~0;
 349                         key->vsamples = ~0;
 350                 }
 351         }
 352 }
 353
 354 struct ir3_shader *
 355 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 356                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 357 {
 358         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 359
 360         mtx_init(&shader->variants_lock, mtx_plain);
 361         shader->compiler = compiler;
 362         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 363         shader->type = nir->info.stage;
 364         if (stream_output)
 365                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 366         shader->const_state.num_reserved_user_consts = reserved_user_consts;
 367
 368         if (nir->info.stage == MESA_SHADER_GEOMETRY)
 369                 NIR_PASS_V(nir, ir3_nir_lower_gs);
 370
 371         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 372                            (nir_lower_io_options)0);
 373
 374         if (compiler->gpu_id >= 600 &&
 375                         nir->info.stage == MESA_SHADER_FRAGMENT &&
 376                         !(ir3_shader_debug & IR3_DBG_NOFP16))
 377                 NIR_PASS_V(nir, nir_lower_mediump_outputs);
 378
 379         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 380                 /* NOTE: lower load_barycentric_at_sample first, since it
 381                  * produces load_barycentric_at_offset:
 382                  */
 383                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 384                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 385
 386                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 387         }
 388
 389         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 390
 391         NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
 392
 393         /* do first pass optimization, ignoring the key: */
 394         ir3_optimize_nir(shader, nir, NULL);
 395
 396         shader->nir = nir;
 397         if (ir3_shader_debug & IR3_DBG_DISASM) {
 398                 printf("dump nir%d: type=%d", shader->id, shader->type);
 399                 nir_print_shader(shader->nir, stdout);
 400         }
 401
 402         ir3_setup_used_key(shader);
 403
 404         return shader;
 405 }
 406
 407 static void dump_reg(FILE *out, const char *name, uint32_t r)
 408 {
 409         if (r != regid(63,0)) {
 410                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 411                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 412                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 413         }
 414 }
 415
 416 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 417                 unsigned slot, const char *name)
 418 {
 419         uint32_t regid;
 420         regid = ir3_find_output_regid(so, slot);
 421         dump_reg(out, name, regid);
 422 }
 423
 424 static const char *
 425 input_name(struct ir3_shader_variant *so, int i)
 426 {
 427         if (so->inputs[i].sysval) {
 428                 return gl_system_value_name(so->inputs[i].slot);
 429         } else if (so->type == MESA_SHADER_VERTEX) {
 430                 return gl_vert_attrib_name(so->inputs[i].slot);
 431         } else {
 432                 return gl_varying_slot_name(so->inputs[i].slot);
 433         }
 434 }
 435
 436 static const char *
 437 output_name(struct ir3_shader_variant *so, int i)
 438 {
 439         if (so->type == MESA_SHADER_FRAGMENT) {
 440                 return gl_frag_result_name(so->outputs[i].slot);
 441         } else {
 442                 switch (so->outputs[i].slot) {
 443                 case VARYING_SLOT_GS_HEADER_IR3:
 444                         return "GS_HEADER";
 445                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 446                         return "GS_VERTEX_FLAGS";
 447                 case VARYING_SLOT_TCS_HEADER_IR3:
 448                         return "TCS_HEADER";
 449                 default:
 450                         return gl_varying_slot_name(so->outputs[i].slot);
 451                 }
 452         }
 453 }
 454
 455 void
 456 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 457 {
 458         struct ir3 *ir = so->ir;
 459         struct ir3_register *reg;
 460         const char *type = ir3_shader_stage(so);
 461         uint8_t regid;
 462         unsigned i;
 463
 464         foreach_input_n (instr, i, ir) {
 465                 reg = instr->regs[0];
 466                 regid = reg->num;
 467                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 468                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 469                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 470
 471                 if (reg->wrmask > 0x1)
 472                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 473                 fprintf(out, "\n");
 474         }
 475
 476         /* print pre-dispatch texture fetches: */
 477         for (i = 0; i < so->num_sampler_prefetch; i++) {
 478                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 479                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 480                                 fetch->half_precision ? "h" : "",
 481                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 482                                 fetch->src, fetch->samp_id, fetch->tex_id,
 483                                 fetch->wrmask, fetch->cmd);
 484         }
 485
 486         foreach_output_n (instr, i, ir) {
 487                 reg = instr->regs[0];
 488                 regid = reg->num;
 489                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 490                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 491                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 492                 if (reg->wrmask > 0x1)
 493                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 494                 fprintf(out, "\n");
 495         }
 496
 497         const struct ir3_const_state *const_state = ir3_const_state(so);
 498         for (i = 0; i < const_state->immediates_count; i++) {
 499                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 500                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 501                                 const_state->immediates[i].val[0],
 502                                 const_state->immediates[i].val[1],
 503                                 const_state->immediates[i].val[2],
 504                                 const_state->immediates[i].val[3]);
 505         }
 506
 507         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 508
 509         fprintf(out, "; %s: outputs:", type);
 510         for (i = 0; i < so->outputs_count; i++) {
 511                 uint8_t regid = so->outputs[i].regid;
 512                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 513                 fprintf(out, " %s%d.%c (%s)",
 514                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 515                                 output_name(so, i));
 516         }
 517         fprintf(out, "\n");
 518
 519         fprintf(out, "; %s: inputs:", type);
 520         for (i = 0; i < so->inputs_count; i++) {
 521                 uint8_t regid = so->inputs[i].regid;
 522                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 523                                 (regid >> 2), "xyzw"[regid & 0x3],
 524                                 input_name(so, i),
 525                                 so->inputs[i].slot,
 526                                 so->inputs[i].compmask,
 527                                 so->inputs[i].inloc,
 528                                 so->inputs[i].bary);
 529         }
 530         fprintf(out, "\n");
 531
 532         /* print generic shader info: */
 533         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 534                         type, so->shader->id, so->id,
 535                         so->info.instrs_count,
 536                         so->info.nops_count,
 537                         so->info.instrs_count - so->info.nops_count,
 538                         so->info.mov_count, so->info.cov_count,
 539                         so->info.sizedwords);
 540
 541         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 542                         type, so->shader->id, so->id,
 543                         so->info.last_baryf,
 544                         so->info.max_half_reg + 1,
 545                         so->info.max_reg + 1,
 546                         so->constlen);
 547
 548         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 549                         type, so->shader->id, so->id,
 550                         so->info.sstall,
 551                         so->info.ss,
 552                         so->info.sy,
 553                         so->max_sun,
 554                         so->loops);
 555
 556         /* print shader type specific info: */
 557         switch (so->type) {
 558         case MESA_SHADER_VERTEX:
 559                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 560                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 561                 break;
 562         case MESA_SHADER_FRAGMENT:
 563                 dump_reg(out, "pos (ij_pixel)",
 564                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 565                 dump_reg(out, "pos (ij_centroid)",
 566                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 567                 dump_reg(out, "pos (ij_size)",
 568                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 569                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 570                 if (so->color0_mrt) {
 571                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 572                 } else {
 573                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 574                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 575                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 576                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 577                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 578                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 579                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 580                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 581                 }
 582                 dump_reg(out, "fragcoord",
 583                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 584                 dump_reg(out, "fragface",
 585                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 586                 break;
 587         default:
 588                 /* TODO */
 589                 break;
 590         }
 591
 592         fprintf(out, "\n");
 593 }
 594
 595 uint64_t
 596 ir3_shader_outputs(const struct ir3_shader *so)
 597 {
 598         return so->nir->info.outputs_written;
 599 }